Sensing device applied to nonvolatile memory

Abstract

The invention discloses a sensing device applied to a nonvolatile memory. The sensing device comprises two current mirrors, three switches, a voltage control circuit and a judgment circuit, the input end of the first current mirror receives a reference current, and the mirroring end of the first current mirror is connected to the data line. The first switch is connected between the data line and the voltage control circuit. The second switch is connected between the data line and the ground voltage. The third switch is connected between the voltage control circuit and the supply voltage. The input end of the second current mirror receives bias current, and the mirroring end of the second current mirror is connected to the judgment node. The voltage control circuit and the judgment circuit are connected to the judgment node.

Description

Technical Field

[0001] The present invention relates to a sensing device, and more particularly to a sensing device used in non-volatile memory. Background Art

[0002] As we all know, non-volatile memory has been widely used in various electronic products. For example, SD cards, solid state drives (SSDs), etc. Basically, the memory array in the non-volatile memory includes multiple memory cells. And each memory cell has a floating gate transistor. Among them, the floating gate in the floating gate transistor can store hot carriers, and the storage state of the floating gate transistor can be determined by the amount of hot carrier storage. Furthermore, the floating gate transistor can also be called a storage transistor.

[0003] Generally speaking, when hot carriers are injected into a floating gate transistor, the threshold voltage (V T ) will change according to the amount of hot carrier injection. Therefore, a floating gate transistor with a higher threshold voltage requires a higher gate voltage to turn on the floating gate transistor; conversely, a floating gate transistor with a lower threshold voltage can use a lower gate voltage to turn on the floating gate transistor.

[0004] During the programming cycle of non-volatile memory, the amount of hot carriers injected into the floating gate can be controlled to change the threshold voltage of the floating gate transistor. During the sense cycle, a read voltage is provided to the floating gate transistor to generate a cell current, or read current. Based on the size of the cell current, it can be known whether the storage state of the floating gate transistor (i.e., the memory cell) is on or off.

[0005] For example, when a read voltage is applied to a floating gate transistor with a low threshold voltage, the floating gate transistor will be turned on, thereby generating a higher cell current. Conversely, when a read voltage is applied to a floating gate transistor with a high threshold voltage, the floating gate transistor will not be turned on and will be turned off, thereby generating a cell current close to zero. In other words, during a sensing cycle, a cell in the turned-on state generates a higher cell current, while a cell in the turned-off state generates a lower cell current.

[0006] Of course, a sensing device is further required in the non-volatile memory to receive the memory cell current generated by the memory cell and determine the storage state in the memory cell. Summary of the invention

[0007] The present invention relates to a sensing device used in a non-volatile memory, wherein the non-volatile memory includes a storage unit, which is coupled to a data line during a sensing cycle, and the sensing device includes: a first current mirror, an input end of the first current mirror is connected to the first node to receive a reference current, a mirror end of the current mirror is connected to a second node, and the second node is connected to the data line; a first switch, a first end of the first switch is connected to the second node, a second end of the first switch is connected to a third node, and a control end of the first switch is used to receive an inverted reset pulse; a second switch, a first end of the second switch is connected to the second node, a second end of the second switch receives a ground voltage, and the second switch A control end of the switch is used to receive a reset pulse; a voltage control circuit, which receives a clamping voltage and is connected to the third node, a fourth node and a judgment node; a third switch, a first end of the third switch is connected to the fourth node, a second end of the third switch receives the supply voltage, and a control end of the third switch is used to receive a control signal; a second current mirror, an input end of the second current mirror is connected to a fifth node to receive a first bias current, and a mirror end of the second current mirror is connected to the judgment node; and a judgment circuit, an input end of the judgment circuit is connected to the judgment node, and an output end of the judgment circuit is used to generate an output data according to a judgment voltage on the judgment node.

[0008] The present invention relates to a sensing device used in a non-volatile memory, wherein the non-volatile memory includes a storage unit, which is coupled to a data line during a sensing cycle, and the sensing device includes: a first current mirror connected to a first node and a second node, used to control a first current from the second node according to a reference current flowing through the first node, wherein the second node is connected to a data line; a first switch connected to the second node and a third node, and a control end of the first switch is used to receive an inverted reset pulse; a second switch connected to the second node and a ground end, A control end of the second switch is used to receive a reset pulse; a voltage control circuit is connected to the third node and a judgment node, and is used to conduct a current from the judgment node to the third node in a unidirectional manner according to the relationship between the reference current and the current of a storage unit on the data line during a sensing phase of the sensing cycle; a second current mirror is connected to the judgment node and a fourth node, and is used to control a second current flowing to the judgment node according to a first bias current flowing through the fourth node; and a judgment circuit is connected to the judgment node, and is used to generate an output data according to a judgment voltage on the judgment node.

[0009] In order to better understand the above and other aspects of the present invention, the following is a detailed description of preferred embodiments with reference to the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a sensing device;

[0011] Figure 2 is a schematic diagram of another sensing device;

[0012] Figure 3 This is a first embodiment of the sensing device of the present invention;

[0013] FIG. 4A to FIG. 4D It is a schematic diagram of the operation of the sensing device in the sensing cycle according to the first embodiment of the present invention;

[0014] Figure 4E and Figure 4F A schematic diagram of related signals of the sensing device in a sensing period according to the first embodiment of the present invention;

[0015] Figure 5 The second embodiment of the sensing device of the present invention;

[0016] Fig. 6A and Figure 6B It is a schematic diagram of the operation of the sensing device in the sensing cycle according to the second embodiment of the present invention;

[0017] Figure 6C and Fig.6DA schematic diagram of related signals of a sensing device in a sensing period according to a second embodiment of the present invention;

[0018] Figure 7 The third embodiment of the sensing device of the present invention;

[0019] Figure 8 This is a fourth embodiment of the sensing device of the present invention;

[0020] Fig. 9A and Fig. 9B It is a schematic diagram of the operation of the sensing device in the sensing phase of the sensing cycle according to the fourth embodiment of the present invention;

[0021] Fig. 9C and Fig.9D A schematic diagram of related signals of a sensing device in a sensing period according to a fourth embodiment of the present invention;

[0022] Fig. 10A A first example of a voltage clamping circuit used in a sensing device according to an embodiment of the present invention; and

[0023] Fig. 10B This is a second example of the voltage clamping circuit used in the sensing device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0024] Please refer to Figure 1 , which is a schematic diagram of a sensing device 100 . The sensing device 100 includes a transistor M1 , a transistor M2 , a current source 110 , an operational amplifier 120 , and a determination circuit 130 .

[0025] The transistor M1 is connected to the operational amplifier 120 to form a voltage clamping circuit, wherein the drain of the transistor M1 is connected to the data line (DL) to receive the storage cell current Icell output by the storage cell. The gate of the transistor M1 is connected to the output terminal of the operational amplifier 120. The source of the transistor M1 is connected to the ground terminal to receive the ground voltage GND. Furthermore, the inverting input terminal of the operational amplifier 120 receives a clamping voltage V CLP The non-inverting input terminal of the operational amplifier 120 is connected to the drain of the transistor M1. Therefore, when the voltage clamp circuit is in normal operation, the data line voltage V DL Equal to the clamping voltage V CLP .

[0026] The current source 110 is connected between the supply voltage Vdd and a judging node (s). The current source 110 can generate a reference current I REFThe drain of transistor M2 is connected to the determination node s, and the drain of transistor M2 receives the reference current I REF , the gate of transistor M2 is connected to the gate of transistor M1, and the source of transistor M2 is connected to the ground terminal to receive the ground voltage GND. Wherein, the supply voltage Vdd is greater than the clamping voltage V CLP , clamping voltage V CLP Greater than the ground voltage GND. For example, the supply voltage Vdd is 3.3V to 5V, the clamping voltage V CLP It is 0.2V~0.4V.

[0027] The input terminal of the judging circuit 130 is connected to the judging node s for receiving a judging voltage V JUDGE , the output terminal of the judgment circuit 130 generates output data Dout. For example, the judgment circuit 130 includes two NOT gates 132 and 134, which are connected in series between the input terminal and the output terminal of the judgment circuit 130. Therefore, during the sensing cycle, the storage unit can be judged to be in an open state or a closed state according to the output data Dout of the judgment circuit 130.

[0028] During the sensing period, the data line DL is connected to the memory cell and receives the memory cell current Icell. IREF When the voltage V JUDGE will be pulled down to the ground voltage GND. Therefore, the determination circuit 130 outputs the output data Dout of the logic low level, indicating that the memory cell is in the on state. On the contrary, when the memory cell current Icell on the data line DL is less than the reference current I REF When the voltage V JUDGE It will be pulled up to the supply voltage Vdd, so the determination circuit 130 outputs the output data Dout of a logic high level, indicating that the memory cell is in an off state.

[0029] Of course, the determination circuit 130 in this example can have various variations. For example, the determination circuit 130 can be composed of a single NOT gate or more than two NOT gates connected between the input terminal and the output terminal of the determination circuit 130 .

[0030] From the above description, it can be known that the sensing device 100 can determine the storage state of the memory cell according to the memory cell current Icell generated by the memory cell.

[0031] As described above, the operational amplifier 120 of the sensing device 100 is connected to the data line DL. Since the operational amplifier 120 is connected as a negative feedback amplifier, the high gain of the amplifier will also amplify the noise and affect the determination voltage V of the determination node s. JUDGE For example, the amplifier amplifies the ground noise, causing the determination voltage V JUDGE Unstable, causing the judgment circuit 130 to make a wrong judgment.

[0032] Please refer to Figure 2 , which is a schematic diagram of another sensing device 200 . The sensing device 200 can be applied to a non-volatile memory (not shown). The sensing device 200 includes a transistor M1 , a transistor M2 , a transistor M3 , a current source 210 , a switch SW and a determination circuit 230 .

[0033] The source of the transistor M1 is connected to the data line DL to receive the memory cell current Icell output by the memory cell, and the gate of the transistor M1 receives a clamping voltage V CLP , the drain of transistor M1 is connected to a determination node s. During the sensing period, the memory cell is connected to the data line DL, and the data line voltage V DL is (V CLP -V T ). Among them, V T is the threshold voltage of the transistor M1.

[0034] The current source 210 is connected between the supply voltage Vdd and the node a. The current source 210 can generate a reference current I REF . Furthermore, transistor M2 and transistor M3 form a current mirror. The drain of transistor M2 is connected to the determination node s, the gate of transistor M2 is connected to the node a, and the source of transistor M2 is connected to the ground terminal to receive the ground voltage GND. The drain of transistor M3 is connected to the node a, the gate of transistor M3 is connected to the node a, and the source of transistor M3 is connected to the ground terminal to receive the ground voltage GND.

[0035] In addition, a first terminal of the switch SW is connected to the determination node s, a second terminal of the switch SW is connected to the ground terminal to receive the ground voltage GND, and a control terminal of the switch SW receives a reset pulse Rst.

[0036] Furthermore, the input terminal of the determination circuit 230 is connected to the determination node s for receiving the determination voltage V JUDGE, the output end of the judgment circuit 230 generates output data Dout.

[0037] For example, the determination circuit 230 includes a comparator 232. The inverting input terminal of the comparator 232 is connected to the determination node s to receive the determination voltage V JUDGE The non-inverting input terminal of the comparator 232 receives a comparison voltage V CMP , the output terminal of the comparator 232 generates output data Dout. Among them, the comparison voltage V CMP is greater than the ground voltage GND, and the comparison voltage V CMP is less than the supply voltage Vdd.

[0038] At the beginning of the sensing cycle, the switch SW receives the reset pulse Rst, which makes the switch SW closed, and the determination voltage V on the determination node s JUDGE After the reset pulse Rst, the switch SW becomes an open state, and the determination voltage V JUDGE According to the size of the memory cell current Icell, the determination circuit 230 determines the voltage V JUDGE To determine the storage status of the storage unit.

[0039] For example, when the memory cell current Icell on the data line DL is greater than the reference current I REF When the voltage V JUDGE It will be charged to a higher voltage, such as the supply voltage Vdd. Since the supply voltage Vdd is greater than the determination voltage V CMP Therefore, the determination circuit 230 generates the output data Dout of the logic low level, which indicates that the memory cell is in the on state. On the contrary, when the memory cell current Icell on the data line DL is less than the reference current I REF When the voltage V JUDGE The voltage is maintained at the ground voltage GND. Therefore, the determination circuit 230 generates the output data Dout of the logic high level, which indicates that the memory cell is in the off state.

[0040] Of course, the judgment circuit 230 in this example can have various variations. For example, in the judgment circuit 230, the non-inverting input terminal of the comparator 232 is connected to the judgment node s, and the inverting input terminal of the comparator 232 receives the comparison voltage V CMPAt this time, the judgment circuit 230 generates a logic high level output data Dout, which indicates that the storage unit is in an on state. The judgment circuit 230 generates a logic low level output data Dout, which indicates that the storage unit is in an off state.

[0041] exist Figure 2 In the present invention, there is no operational amplifier in the sensing device 200. Therefore, the sensing device 200 is relatively insensitive to noise. However, since the transistor M1 is connected between the data line DL and the determination node s, the gate-source voltage of the transistor M1 will affect the read speed of the sensing device 200. For example, assume that the gate-source voltage of the transistor M1 is -1V. During the sensing cycle, assume that the clamping voltage V CLP is the ground voltage GND (i.e. 0V), then the data line voltage V DL is 1V. That is, V DL =V CLP -V gs =[0V-(-1V)]=1V, V gs is the gate-source voltage of transistor M1. And the 1V data line voltage V DL If the value is too high, the reading speed of the sensing device 200 will be affected. In addition, the change of the pulse width of the reset pulse Rst will also affect the output data Dout of the sensing device 200.

[0042] Please refer to Figure 3 , which illustrates a first embodiment of the sensing device 300 of the present invention. The sensing device 300 includes two current sources 320 and 330 , three switches SW1 , SW2 and SW3 , a voltage control circuit 340 and a determination circuit 360 .

[0043] The data line DL is connected to the node b to provide a memory cell current Icell generated by the memory cell in the nonvolatile memory. That is, during the sensing cycle, the memory cell of the nonvolatile memory is coupled to the data line DL, so that the sensing device 300 can determine the storage state of the memory cell.

[0044] The current mirror 320 has an input terminal and a mirroring terminal. The input terminal of the current mirror 320 is connected to the node a. The input terminal of the current mirror 320 receives a reference current I REF, the mirror end of the current mirror 320 is connected to the node b. Furthermore, the current source 310 is connected between the supply voltage Vdd and the node a, that is, the current source 310 is connected to the input end of the current mirror 320 via the node a. The current source 310 generates a reference current I REF The current mirror 320 includes transistors M1 and M2. The drain of transistor M1 is the input terminal of the current mirror, the drain of transistor M1 is connected to node a, the gate of transistor M1 is connected to node a, and the source of transistor M1 is connected to the ground terminal to receive the ground voltage GND. The drain of transistor M2 is the mirror terminal of the current mirror, the drain of transistor M2 is connected to node b, the gate of transistor M2 is connected to node a, and the source of transistor M2 is connected to the ground terminal to receive the ground voltage GND.

[0045] In the first embodiment of the present invention, the reference current I REF The size of is about 4μA to 5μA, and transistors M1 and M2 have the same size. In the current mirror 320, the current on the mirror end flows from node b to transistor M2. Of course, in other embodiments, transistors M1 and M2 may also have different sizes. At this time, the reference current I received by the input end of the current mirror 320 REF The ratio of the current flowing through the mirror terminal is substantially the same as the size ratio of the transistors M1 and M2.

[0046] The first end of the switch SW1 is connected to the node b, the second end of the switch SW1 is connected to the node c, and the control end of the switch SW1 receives an inverted reset pulse Rstb. The first end of the switch SW2 is connected to the node b, the second end of the switch SW2 is connected to the ground end to receive the ground voltage GND, and the control end of the switch SW2 receives a reset pulse Rst. The reset pulse Rst and the inverted reset pulse Rstb are complementary. Furthermore, the first end of the switch SW3 receives the supply voltage Vdd, the second end of the switch SW3 is connected to the node d, and the control end of the switch SW3 receives a control signal Ctrl.

[0047] The current mirror 330 has an input terminal and a mirror terminal. The input terminal of the current mirror 330 is connected to the node e. The input terminal of the current mirror 330 receives a bias current I BIAS1 ) The mirror end of the current mirror 330 is connected to the determination node s. Furthermore, the current sink 350 is connected between the node e and the ground. That is, the current sink 350 is connected to the input end of the current mirror 330 via the node e. The current sink 350 generates a bias current I BIAS1The current mirror 330 includes transistors M3 and M4. The drain of transistor M3 serves as the mirror end of the current mirror 330, the drain of transistor M3 is connected to the determination node s, the gate of transistor M3 is connected to the node e, and the source of transistor M3 receives the supply voltage Vdd. The drain of transistor M4 serves as the input end of the current mirror, the drain of transistor M4 is connected to the node e, the gate of transistor M4 is connected to the node e, and the source of transistor M4 receives the supply voltage Vdd.

[0048] In the first embodiment of the present invention, the bias current I BIAS1 The size of is about 1μA, and transistors M3 and M4 have the same size. In the current mirror 330, the current on the mirror end flows from transistor M3 to the determination node s. Of course, in other embodiments, transistors M3 and M4 may also have different sizes. At this time, the bias current I received by the input end of the current mirror 330 BIAS1 The ratio of the current flowing through the mirror terminal is substantially the same as the size ratio of the transistors M3 and M4.

[0049] The input terminal of the judging circuit 360 is connected to the judging node s to receive a judging voltage V JUDGE , the output end of the judgment circuit 360 generates output data Dout. For example, the judgment circuit 360 includes a NOT gate 362 connected between the input end and the output end of the judgment circuit 360. Therefore, during the sensing cycle, the storage unit can be judged to be in an on state or a off state according to the output data Dout of the judgment circuit 360. Of course, the present invention does not limit the number of NOT gates in the judgment circuit 360. In other embodiments, the judgment circuit 360 may also include more NOT gates connected in series between the input end and the output end of the judgment circuit 360.

[0050] The voltage control circuit 340 includes a plurality of voltage control devices M. X 、M Y . Voltage control component M X The control terminal receives the clamping voltage V CLP , voltage control component M X The first end of the voltage control component M is connected to the node d. X The second end of the voltage control component M is connected to the node c. Y The control terminal receives the clamping voltage V CLP , voltage control component M Y The first end of the voltage control component M is connected to the judgment node s. Y The second end of is connected to the node c. Wherein, the voltage control component MX The threshold voltage is less than the voltage control component M Y The threshold voltage.

[0051] In one embodiment, the voltage control component M X 、M Y They are all composed of a single transistor, and the size ratio of the two transistors is X:Y. Where X>Y, X and Y are positive numbers. Voltage control element M X The drain of the voltage control component M is connected to the node d. X The source of the voltage control component M is connected to the node c. X The gate receives the clamping voltage V CLP . Voltage control component M Y The drain of the voltage control component M is connected to the judgment node s. Y The source of the voltage control component M is connected to the node c. Y The gate receives the clamping voltage V CLP That is, design the voltage control component M X The size is larger than the voltage control component M Y The size of the voltage control component M X The threshold voltage is less than the voltage control component M Y The threshold voltage.

[0052] In another embodiment, the voltage control component M X 、M Y Each is composed of multiple transistors. For example, the voltage control element M X It includes J transistors, a voltage control component M Y The voltage control component M X In the embodiment, the drains of J transistors are connected to node d, the sources of J transistors are connected to node c, and the gates of J transistors receive the clamping voltage V CLP . In the voltage control component M Y In the embodiment, the drains of the K transistors are connected to the judgment node s, the sources of the K transistors are connected to the node c, and the gates of the K transistors receive the clamping voltage V CLP Furthermore, the voltage control component M X 、M Y The sizes of the (J+K) transistors in the circuit are exactly the same, J>K, and J and K are positive integers. X The number of transistors is greater than the voltage control component M Y The number of transistors, so the voltage control component M X The threshold voltage is less than the voltage control component M Y The threshold voltage.

[0053] Of course, the present invention may not limit the voltage control component M X 、M Y For example, the voltage control element M Y Composed of a single transistor, the voltage control element M X Furthermore, the size or number of the transistors is appropriately designed so that the voltage control element M X The threshold voltage is less than the voltage control component M Y The threshold voltage.

[0054] Please refer to 4A to 4D , which is a schematic diagram showing the operation of the sensing device 300 in the first embodiment of the present invention during a sense cycle. Figure 4E and Figure 4F FIG. 1 is a schematic diagram of related signals of the sensing device 300 during a sensing period according to the first embodiment of the present invention.

[0055] When the memory cell connected to the data line DL is in an off state, the operation of the sensing device 300 is as follows: Figure 4A , Figure 4B , Figure 4C and Figure 4E As shown. Basically, a sensing cycle includes a reset phase P1, a voltage control phase P2 and a sense phase P3. In a sensing cycle, the sensing device 300 can determine the storage state of a memory cell. The sensing device 300 can determine the storage state of multiple memory cells in multiple consecutive sensing cycles.

[0056] First, if Figure 4A and Figure 4E As shown, between time point ta and time point tb is the reset phase P1 of the sensing cycle, switch SW2 receives the reset pulse Rst, so that switch SW2 becomes closed, which can be regarded as a conducted state. Switch SW1 receives the reverse reset pulse Rstb, so that switch SW1 becomes disconnected, which can be regarded as a turned-off state. In addition, switch SW3 receives the control signal Ctrl, so that switch SW3 becomes a closed state.

[0057] like Figure 4E As shown, in the reset phase P1 of the sensing cycle, the voltage V DL is reset to the ground voltage GND, that is, V DL=0V. Furthermore, since the switch SW1 is in the open state, the voltage V JUDGE is pulled up to the supply voltage Vdd. In addition, according to the supply voltage Vdd, the voltage of the node c is reset to (V CLP -V gsx ), where V gsx M is the voltage control component X The gate-source voltage.

[0058] like Figure 4B and Figure 4E As shown, the period between time point tb and time point tc is the voltage control phase P2 of the sensing cycle. Switch SW1 becomes closed, switch SW2 becomes open, and switch SW3 is still closed. At this time, the voltage control component M X Turn on, the supply voltage Vdd is connected through the switch SW3 and the voltage control element M X The current path of the switch SW1 can charge the data line DL. X Receive clamp voltage V CLP , so the voltage V on the data line DL (that is, node b) DL It will be charged from the ground voltage (0V) to (V CLP -V gsx ). Among them, V gsx M is the voltage control component X The gate-source voltage of the voltage control component M X The gate-source voltage V gsx Approximately equal to the voltage control component M X The threshold voltage.

[0059] In addition, due to the voltage control component M Y The gate-source voltage is also equal to the voltage control component M X The gate-source voltage V gsx , and V gsx Less than the voltage control component M Y The threshold voltage, so the voltage control component M Y That is, in the voltage control phase P2 of the sensing cycle, the voltage control element M X Turn on and the voltage control element M Y Turn off. Therefore, if Figure 4E As shown, in the voltage control phase P2 of the sensing cycle, the voltage V on the data line DL (ie, node b) and the node c is DL is charged to (VCLP -V gsx ), and the voltage V JUDGE Maintained at supply voltage Vdd.

[0060] like Figure 4C and Figure 4E As shown, the period between time point tc and time point tf is the sensing phase P3 of the sensing cycle. Switch SW1 is maintained in a closed state, switch SW2 is maintained in an open state, and switch SW3 is in an open state. At this time, the voltage control component M X Turn off, the voltage V on the data line DL (that is, node b) DL The voltage at the node c varies according to the size of the memory cell current Icell.

[0061] exist Figure 4E In the embodiment of the present invention, the storage state of the memory cell is off during the sensing phase P3 of the sensing cycle, so the memory cell current Icell on the data line DL is very small, almost zero (Icell=0), and the reference current I REF Greater than the storage cell current Icell(I REF >Icell). Therefore, at time point tc, after switch SW3 is switched to the off state, the voltage V on node b DL Drop, voltage control component M Y The gate-source voltage increases. When the voltage control component M Y The gate-source voltage is added to the voltage control component M Y When the threshold voltage is reached, the voltage control component M Y Turn on, so that the bias current I BIAS1 The mirror terminal of the current mirror 330 is connected to the voltage control element M X Flows into the mirror terminal of the current mirror 320.

[0062] Furthermore, the bias current I BIAS1 Flows through the voltage control component M Y , so that the voltage control component M Y It operates in the saturation region and becomes a common-gate amplifier, and the data line voltage V DL The voltage of node c decreases, resulting in a judgment voltage V on the judgment node s. JUDGE Decline. Figure 4E As shown, at time point td, the voltage V on the judgment node s is JUDGE is lower than the transition voltage (V Q), the judgment circuit 360 switches from the second logic level (e.g., logic low level "Lo") to the first logic level (e.g., logic high level "Hi"). Therefore, at the time point tf at the end of the sensing cycle, the judgment circuit 360 generates output data Dout of the first logic level (e.g., logic high level "Hi"), indicating that the storage unit is in the off state.

[0063] When the memory cell connected to the data line DL is in an on state, the operation of the sensing device 300 is as follows: Figure 4A , Figure 4B , Figure 4D and Figure 4F Basically, in the reset phase P1 (i.e. Figure 4A The situation) and the voltage control stage P2 (that is Figure 4B ), Figure 4F The signal waveform is the same as Figure 4E That is, the sensing device 300 Figure 4F and Figure 4E The operations of the reset phase P1 and the voltage control phase P2 are similar.

[0064] like Figure 4D and Figure 4F As shown, the period between time point tc and time point tf is the sensing phase P3 of the sensing cycle. Switch SW1 is maintained in a closed state, switch SW2 is maintained in an open state, and switch SW3 is in an open state. At this time, the voltage control component M X Turn off, the voltage V on the data line DL (that is, node b) DL And the voltage of the node c will change according to the size of the memory cell current Icell.

[0065] exist Figure 4D and Figure 4F In the case of , the storage state of the memory cell is in the on state during the sensing phase P3 of the sensing cycle, so the reference current I REF is smaller than the storage cell current Icell (I REF <Icell)。

[0066] Therefore, at time tc, after the switch SW3 is switched to the off state, the voltage V DL Rise, control component M Y The gate-source voltage of the voltage control component M YThe voltage on the judgment node s is maintained at the supply voltage Vdd. Since the voltage on the judgment node s is greater than the transition voltage (V Q ), the judgment circuit 360 generates output data Dout of a second logic level (eg, a logic low level “Lo”). Figure 4F As shown, at the time point tf at the end of the sensing cycle, the determination circuit 360 outputs the output data Dout of the second logic level (e.g., the logic low level "Lo", indicating that the storage unit is in the on state. That is, in the sensing phase P3 of the sensing cycle, according to the reference current I REF In relation to the magnitude of the memory cell current Icell, the voltage control circuit 340 is designed to conduct current in one direction (i.e., from the determination node s to the node c). In the sensing phase P3 of the sensing cycle, when the memory cell current Icell on the data line DL is lower than the reference current I REF When the voltage control circuit 340 conducts a current from the determination node s to the node c in one direction. In the sensing phase P3 of the sensing cycle, when the storage cell current Icell on the data line DL is greater than the reference current I REF When , the voltage control circuit 340 electrically isolates the determination node s from the node c.

[0067] In the above-mentioned sensing device 300, in (I REF -Icell)≈I BIAS1 In the case of JUDGE It is not a full voltage swing. In other words, the voltage V JUDGE The supply voltage Vdd and the ground voltage GND may not be switched, so that the NOT gate 362 in the determination circuit 360 may generate leakage current, resulting in additional power consumption.

[0068] Please refer to Figure 5 , which illustrates a second embodiment of the sensing device 500 of the present invention. Compared with the sensing device 300 of the first embodiment, the sensing device 500 of the second embodiment further includes a switch SW4, a transistor M5 and a delay circuit 510. The following only introduces the connection relationship between a switch SW4, a transistor M5 and a delay circuit 510, and the rest is not repeated. Among them, the delay circuit 500 can be implemented by a Schmitt trigger or by a plurality of buffers connected in series.

[0069] The first end of the switch SW4 is connected to the node b, the second end of the switch SW4 is connected to the node f, and the control end of the switch SW4 receives an inverted control signal Ctrlb, wherein the control signal Ctrll and the inverted control signal Ctrlb are complementary.

[0070] The input end of the delay circuit 510 is connected to the output end of the determination circuit 360 to receive the output data Dout. The delay circuit 510 can delay the output data Dout by a specific delay time and generate a delay signal Dd at the output end of the delay circuit 510. According to the second embodiment of the present invention, the specific delay time of the delay circuit 510 is about 2ns.

[0071] The drain of the transistor M5 is connected to the node f, the source of the transistor M5 is connected to the ground terminal to receive the ground voltage GND, and the gate of the transistor M5 is connected to the output terminal of the delay circuit 510 to receive the delay signal Dd. Basically, the transistor M5 can be regarded as a pull-down device, and when the delay signal Dd is activated, the pull-down device is activated.

[0072] Basically, the switch SW4, a transistor M5 and a delay circuit 510 added to the sensing device 500 of the second embodiment can be used to control the determination voltage V JUDGE , so that the judgment voltage V JUDGE is a full voltage swing signal. In other embodiments, the delay circuit 510 may also be omitted. That is, when the delay circuit 510 is not provided in the sensing device 500, the gate of the transistor M5 receives the output data Dout.

[0073] Furthermore, the operations of the sensing device 500 in the reset phase P1 and the voltage control phase P2 are similar to those of the sensing device 300 in the first embodiment, and are not described in detail here. The following only describes the operations of the sensing device 500 in the sensing phase P3.

[0074] Please refer to Fig. 6A and Figure 6B , which is a schematic diagram showing the operation of the sensing device 500 in the sensing cycle according to the second embodiment of the present invention. Figure 6C and Fig.6D FIG. 5 is a schematic diagram of related signals of the sensing device 500 during a sensing period according to the second embodiment of the present invention.

[0075] When the memory cell connected to the data line DL is in the off state, the sensing device 500 operates in the sense phase P3 as follows: Fig. 6A and Figure 6CAs shown. The period between time point tc and time point tf is the sensing phase P3 of the sensing cycle. Switch SW1 is maintained in a closed state, switch SW2 is maintained in an open state, switch SW3 is in an open state, and switch SW4 is in a closed state. At this time, the voltage control component M X Close, the voltage V on the data line DL (that is, node b) DL The voltage at the node c varies according to the size of the memory cell current Icell.

[0076] Since the storage state of the memory cell is the off state, the memory cell current Icell on the data line DL is very small, almost zero (Icell=0). REF Greater than the storage cell current Icell(I REF >Icell). Therefore, at time point tc, after switch SW3 is switched to the off state, the voltage V on node b DL The voltage control component M Y Turn on, bias current I BIAS1 The mirror terminal of the current mirror 330 is connected to the voltage control element M Y Flows into the mirror terminal of the current mirror 320.

[0077] Furthermore, when the bias current I BIAS1 Flows through the voltage control component M Y , so that the voltage control component M Y It operates in the saturation range and becomes a common gate amplifier, and the data line voltage V on node b DL The voltage of node c decreases, resulting in a judgment voltage V on the judgment node s. JUDGE Decline. Figure 6C As shown, at time point td, the voltage V on the judgment node s is JUDGE is lower than the transition voltage V of the judgment circuit 360 Q , the determination circuit 360 switches the output data Dout to a first logic level (eg, a logic high level “Hi”).

[0078] Furthermore, at time te (i.e., after a specific delay time has passed since time point td), the delay circuit 510 operates to delay the signal Dd and switches it to a logic high level. Therefore, the transistor M5 is turned on, and the voltage V DL is pulled down to the ground voltage GND, causing the voltage control component M Y Enter the linear region and set the judgment voltage V on the judgment node s JUDGE is also pulled to the ground voltage GND. That is, when the delay signal Dd is activated, the pull-down element is activated and the voltage V on the node b is DL And the judgment voltage V on the judgment node sJUDGE Pulled down to the ground voltage GND. Therefore, at the time point tf when the sensing period ends, the output data Dout at which the determination circuit 360 generates a first logic level (e.g., logic high level “Hi”) represents that the memory cell is in the off state.

[0079] In addition, when the memory cell connected to the data line DL is in the on state, the operation of the sensing device 500 in the sensing phase P3 is as Figure 6B shown in Fig.6D and X shown in DL From the time point tc to the time point tf is the sensing phase P3 of the sensing period. The switch SW1 remains in the closed state, the switch SW2 remains in the open state, the switch SW3 is in the open state, and the switch SW4 is in the closed state. At this time, the voltage control component M

[0080] shown in Figure 6B and Fig.6D shown in REF is turned off, and the voltage V REF on the data line DL (i.e., node b) and the voltage of node c change according to the magnitude of the memory cell current Icell. DL rises, causing the voltage control component M Y to remain turned off, and it is determined that the voltage on node s remains at the supply voltage Vdd.

[0081] Since the voltage on the determination node s is greater than the transition voltage V Q of the determination circuit 360, the determination circuit 360 generates output data Dout at a second logic level (e.g., logic low level “Lo”). In addition, the delay circuit 510 does not act on the delay signal Dd, and the delay signal Dd remains at the logic low level. Therefore, the transistor M5 is turned off and the pull-down component does not act. Therefore, as Fig.6D shown in

[0082] shown in JUDGE at the time point tf when the sensing period ends, the determination circuit 360 generates output data Dout at a second logic level (e.g., logic low level “Lo”), representing that the memory cell is in the on state. JUDGE can be switched between the supply voltage Vdd and the ground voltage GND.

[0083] In the sensing devices 300 and 500 of the first embodiment and the second embodiment, the determination circuit 360 is implemented by using a NOT gate 362. Of course, the invention does not limit the composition of the determination circuit 360.

[0084] For example, in other embodiments, the determination circuit 360 may be Figure 2 The comparator 232 in the judgment circuit 230 is used to implement the judgment. The inverting input terminal of the comparator 232 is connected to the judgment node s to receive the judgment voltage V JUDGE The non-inverting input terminal of the comparator 232 receives a comparison voltage V CMP The output terminal of the comparator 232 generates output data Dout. The comparison voltage V CMP Same as Figure 4E and Figure 4F The transition voltage V Q Therefore, when the storage unit is in the off state, the comparator 232 outputs the output data Dout of the first logic level (eg, logic high level “Hi”). When the storage unit is in the on state, the comparator 232 outputs the output data Dout of the second logic level (eg, logic low level “Lo”).

[0085] Generally speaking, the sensing device will not operate during the programming cycle of the non-volatile memory. The sensing device will only operate during the sensing cycle of the non-volatile memory. In some embodiments, the sensing device of the non-volatile memory can receive an enable signal. When the enable signal is activated, it means that the sensing cycle begins. In other words, the sensing device can operate according to the enable signal.

[0086] Please refer to Figure 7 , which illustrates a third embodiment of the sensing device 700 of the present invention. Compared with the sensing device 500 of the second embodiment, the determination circuit 760 of the sensing device 700 of the third embodiment receives an enable signal EN. For example, in the determination circuit 760, the input terminal of the NOT gate 762 is connected to the determination node s, the output terminal of the NOT gate 762 generates the output data Dout, and the enable terminal of the NOT gate 762 receives the enable signal EN.

[0087] When the enable signal EN is not activated, it means that the sensing cycle has not started, and the sensing device 700 does not operate. When the enable signal EN is activated, it means that the sensing cycle has started, and the sensing device 700 can operate normally. For example, when the enable signal EN is at a logic high level, it means that the sensing cycle has started. The sensing device 700 can distinguish multiple sensing cycles during the period when the enable signal EN is at a logic high level to determine the storage status of multiple memory cells. Basically, the operation of the sensing device 700 of the third embodiment is similar to that of the sensing device 500 of the second embodiment, and will not be repeated here.

[0088] In addition, in the third embodiment, the determination circuit 760 in the sensing device 700 may also be composed of other circuits, such as the comparator 232 , in a manner similar to the above description of the determination circuit 360 .

[0089] Please refer to Figure 8 , which illustrates a fourth embodiment of the sensing device 800 of the present invention. Compared with the sensing device 700 of the third embodiment, the sensing device 800 of the fourth embodiment has a judgment circuit 860 with a different structure. The following only introduces the connection relationship of the judgment circuit 860, and the rest is not repeated.

[0090] The judgment circuit 860 includes two NAND gates 862 and 864. The first input terminal of the NAND gate 862 is connected to the judgment node s, the second input terminal of the NAND gate 862 receives the enable signal EN, and the output terminal of the NAND gate 862 generates the output data Dout. Furthermore, the first input terminal of the NAND gate 864 is connected to the judgment node s, the second input terminal of the NAND gate 864 receives the enable signal EN, and the output terminal of the NAND gate 864 generates the notification signal Dx. The input terminal of the delay circuit 510 receives the notification signal Dx, and the output terminal of the delay circuit 510 generates the delay signal Dd. According to an embodiment of the present invention, the two NAND gates 862 and 864 have different transition voltages. The transition voltage of the NAND gate 862 is V Q1 , the transition voltage of NAND gate 864 is V Q2 , and V Q1 >V Q2 .

[0091] During the sensing cycle, the enable signal EN is at a first logic level (e.g., a logic high level). In addition, the operation of the sensing device 800 of the fourth embodiment in the reset phase P1 and the voltage control phase P2 is similar to that of the sensing device 300 of the first embodiment, and will not be described in detail here. The following only introduces the operation of the sensing device 800 in the sensing phase P3.

[0092] Please refer to Fig. 9A and Fig. 9B , which is a schematic diagram showing the operation of the sensing device 800 according to the fourth embodiment of the present invention during the sensing phase of the sensing cycle. Fig. 9C and Fig.9D It is a schematic diagram of related signals of the sensing device in a sensing period according to the fourth embodiment of the present invention.

[0093] When the memory cell connected to the data line DL is in the off state, the operation of the sensing device 800 in the sensing phase P3 is as follows: Fig. 9A and Fig. 9CAs shown. The period between time point tc and time point tf is the sensing phase P3 of the sensing cycle. Switch SW1 is maintained in a closed state, switch SW2 is maintained in an open state, switch SW3 is in an open state, and switch SW4 is in a closed state. At this time, the voltage control component M X Close, the voltage V on the data line DL (that is, node b) DL The voltage at the node c varies according to the size of the memory cell current Icell.

[0094] Since the storage state of the memory cell is the off state, the memory cell current Icell on the data line DL is very small, almost zero (Icell=0). REF Greater than the storage cell current Icell(I REF >Icell). Therefore, at time point tc, after switch SW3 is switched to the off state, the voltage V on node b DL The voltage control component M Y Turn on, bias current I BIAS1 The mirror terminal of the current mirror 330 is connected to the voltage control element M X Flows into the mirror terminal of the current mirror 320.

[0095] Furthermore, when the bias current I BIAS1 Flows through the voltage control component M Y , so that the voltage control component M Y It operates in the saturation range and becomes a common gate amplifier, and the data line voltage V on node b DL The voltage of node c decreases, resulting in a judgment voltage V on the judgment node s. JUDGE Decline. Fig. 9C As shown, at time point td, the voltage V on the judgment node s is JUDGE Lower than the transition voltage V of the NAND gate 862 Q1 , the determination circuit 860 switches the output data Dout from the second logic level (eg, logic low level “Lo”) to the first logic level (eg, logic high level “Hi”).

[0096] Furthermore, at time te, the voltage V on the judgment node s is determined. JUDGE Lower than the transition voltage V of NAND gate 864 Q2 , the judgment circuit 860 switches the notification signal Dx from the second logic level (e.g., logic low level "Lo") to the first logic level (e.g., logic high level "Hi"). Furthermore, at time point tg (i.e., after a specific delay time has passed after time point te), the delay circuit 510 activates the delay signal Dd and switches it to a logic high level. Therefore, the transistor M5 is turned on, and the voltage V on the node b is DLand determining the determination voltage V on node s JUDGE are both pulled down to the ground voltage GND. That is, when the delay signal Dd operates, the pull-down component operates and pulls down the voltage V on node b DL and the determination voltage V on the determination node s JUDGE to the ground voltage GND. Therefore, at the time point tf when the sensing period ends, the determination circuit 860 outputs output data Dout of the first logic level (e.g., logic high level “Hi”), indicating that the memory cell is in the off state.

[0097] When the memory cell connected to the data line DL is in the on state, the operation of the sensing device 800 in the sensing phase P3 is as Fig. 9B shown in Fig.9D . The time period between the time point tc and the time point tf is the sensing phase P3 of the sensing period. The switch SW1 remains in the closed state, the switch SW2 remains in the open state, the switch SW3 is in the open state, and the switch SW4 is in the closed state. At this time, the voltage control component M X is turned off, and the voltage V on the data line DL (i.e., node b) DL and the voltage of node c change according to the magnitude of the memory cell current Icell.

[0098] In the sensing phase P3 of the sensing period, since the storage state of the memory cell is in the on state, the reference current I REF is less than the memory cell current Icell on the data line DL, (i.e., I REF < Icell). Therefore, at the time point tc, after the switch SW3 is switched to the open state, the voltage V on node b DL rises, causing the voltage control component M Y to remain off, and the voltage on the determination node s is maintained at the supply voltage Vdd.

[0099] Since the voltage on the determination node s is greater than the switching voltage V Q1 of the NAND gate 862 and greater than the switching voltage V Q2 of the NAND gate 864, the determination circuit 860 generates output data Dout of the second logic level (e.g., logic low level “Lo”) and the notification signal Dx. In addition, the delay circuit 510 does not operate the delay signal Dd, and the delay signal Dd remains at the logic low level. Therefore, the transistor M5 is turned off and the pull-down component does not operate. Therefore, as Fig.9D shown, at the time point tf when the sensing period ends, the determination circuit 860 outputs output data Dout of the second logic level (e.g., logic low level “Lo”), indicating that the memory cell is in the on state.

[0100] Please refer to Fig. 10A, which illustrates a first example of a voltage clamping circuit 910 used in a sensing device according to an embodiment of the present invention. The voltage clamping circuit 910 can provide a clamping voltage V CLP The voltage control circuit 340 in the sensing devices 300, 500, 700, and 800 of the four embodiments of the present invention is shown in FIG. Fig. 10A As shown, the voltage clamping circuit 910 includes a current source 912 , a transistor Ma and an operational amplifier 914 .

[0101] The current source 912 is connected between the supply voltage Vdd and the node g. The current source 912 can generate a bias current I BIAS2 The drain of transistor Ma is connected to node g, the gate of transistor Ma is connected to the output terminal of operational amplifier 914, and the source of transistor Ma is connected to the ground terminal to receive the ground voltage GND. Furthermore, the first input terminal (e.g., the inverting input terminal) of operational amplifier 914 receives a set voltage Vset, and the second input terminal (e.g., the non-inverting positive input terminal) of operational amplifier 914 is connected to node g, and the voltage on node g is the clamping voltage V CLP Therefore, when the voltage clamp circuit 910 operates normally, the voltage on the node g is equal to the set voltage Vset. In other words, the clamp voltage V output by the voltage clamp circuit 910 is CLP is equal to the set voltage Vset. For example, when the set voltage Vset is 1V, the clamping voltage V received by the voltage control circuit 340 is CLP Also 1V.

[0102] Please refer to Fig. 10B , which is a second example of a voltage clamping circuit 920 used in the sensing device according to an embodiment of the present invention. Similarly, the voltage clamping circuit 920 can provide a clamping voltage V CLP The voltage control circuit 340 in the sensing devices 300, 500, 700, and 800 of the four embodiments of the present invention is shown in FIG. Fig. 10B As shown, the voltage clamping circuit 920 includes a current source 922 , a transistor Mb, a transistor Mc and an operational amplifier 924 .

[0103] The current source 922 is connected between the supply voltage Vdd and the node k. The current source 922 can generate a bias current I BIAS3 The source of transistor Mb is connected to node h, the drain of transistor Mb is connected to node k, the gate of transistor Mb is connected to node k, and the voltage on node k is the clamping voltage V CLP. Therefore, transistor Mb is a diode-connected transistor. The drain of transistor Mc is connected to node h, the gate of transistor Mc is connected to the output terminal of operational amplifier 924, and the source of transistor Mc receives the ground voltage GND. Furthermore, the first input terminal (e.g., the inverting input terminal) of operational amplifier 924 receives a set voltage Vset, and the second input terminal (e.g., the non-inverting input terminal) of operational amplifier 924 is connected to node h. Therefore, when the voltage clamping circuit 920 operates normally, the voltage on node h will be equal to the set voltage Vset. The voltage on the gate of transistor Mb (i.e., node k) will be equal to the set voltage Vset plus the gate-source voltage V gsb That is, the clamping voltage V output by the voltage clamping circuit 920 is CLP Equal to the set voltage Vset plus the gate-source voltage V gsb , that is, V CLP =Vset+V gsb .

[0104] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

[0105] Explanation of symbols

[0106] 100, 200, 300, 500: Sensing device

[0107] 110, 210, 310, 912, 922: Current source

[0108] 120, 914, 924: Operational amplifier

[0109] 130, 230, 360, 760, 860: judgment circuit

[0110] 132, 134, 362, 762: NOT gate

[0111] 232: Comparator

[0112] 320, 330: Current mirror

[0113] 340: Voltage Control Circuit

[0114] 350: Current Sink

[0115] 510: Delay Circuit

[0116] 862, 864: NAND gate

[0117] 910, 920: Voltage clamping circuit

[0118] A brief explanation of the symbols used in the diagram

[0119] 300: Sensing device

[0120] 310: Current Source

[0121] 320, 330: Current mirror

[0122] 340: Voltage Control Circuit

[0123] 350: Current Sink

[0124] 360: Judgment circuit

[0125] 362: NOT Gate

Claims

1. A sensing device for a non-volatile memory, wherein the non-volatile memory comprises a storage unit, during a sensing cycle, the storage unit is coupled to a data line, and the sensing device comprises: a first current mirror, an input terminal of the first current mirror is connected to a first node to receive a reference current, an emitter terminal of the current mirror is connected to a second node, and the second node is connected to the data line; a first switch, a first terminal of the first switch being connected to the second node, a second terminal of the first switch being connected to a third node, and a control terminal of the first switch being used to receive an inverted reset pulse; a second switch, a first terminal of the second switch being connected to the second node, a second terminal of the second switch receiving a ground voltage, and a control terminal of the second switch being used to receive a reset pulse; a voltage control circuit, the voltage control circuit receiving a clamping voltage, and the voltage control circuit is connected to the third node, a fourth node and a determination node; a third switch, a first terminal of the third switch being connected to the fourth node, a second terminal of the third switch receiving the supply voltage, and a control terminal of the third switch being used to receive a control signal; a second current mirror, an input terminal of the second current mirror being connected to a fifth node to receive a first bias current, and an emitter terminal of the second current mirror being connected to the determination node; as well as A judgment circuit has an input terminal connected to the judgment node, and an output terminal of the judgment circuit is used to generate output data according to a judgment voltage on the judgment node.

2. The sensing device as claimed in claim 1, wherein the voltage control circuit comprises: a first voltage control component, a first terminal of the first voltage control component is connected to the fourth node, a second terminal of the first voltage control component is connected to the third node, and a control terminal of the first voltage control component is used to receive the clamping voltage; and a second voltage control component, a first terminal of the second voltage control component is connected to the determination node, a second terminal of the second voltage control component is connected to the third node, and a control terminal of the second voltage control component is used to receive the clamping voltage; A first threshold voltage of the first voltage control component is less than a second threshold voltage of the second voltage control component. 3 . The sensing device as claimed in claim 2 , wherein in a reset phase of the sensing cycle, the voltage of the second node is reset to the ground voltage, and the determination voltage of the determination node is the supply voltage. 4 . The sensing device as claimed in claim 3 , wherein in the reset phase of the sensing cycle, the first switch is in an open state, the second switch is in a closed state, and the third switch is in the closed state.

5. The sensing device as described in claim 3, wherein in the sensing cycle, in a voltage control phase after the reset phase, the first voltage control component in the voltage control circuit is turned on to charge the third node, so that the second voltage control component in the voltage control circuit is turned off and the judgment voltage of the judgment node is the supply voltage. 6 . The sensing device as claimed in claim 5 , wherein during the voltage control phase of the sensing cycle, the first switch is in a closed state, the second switch is in an open state, and the third switch is in the closed state. 7 . The sensing device as claimed in claim 5 , wherein in a sensing phase after the voltage control phase in the sensing cycle, the voltage on the second node varies according to a memory cell current of the memory cell.

8. The sensing device as described in claim 7, wherein in the sensing phase of the sensing cycle, when the storage cell current of the storage cell is less than the reference current, the second voltage control component in the voltage control circuit is turned on, the judgment voltage of the judgment node decreases, and the judgment circuit generates the output data of a first logic level to represent that the storage cell is in a closed state.

9. The sensing device as described in claim 7, wherein in the sensing phase of the sensing cycle, when the storage cell current of the storage cell is greater than the reference current, the second voltage control component in the voltage control circuit is turned off, the judgment voltage of the judgment node is the supply voltage, and the judgment circuit generates the output data of a second logic level to represent that the storage cell is in an open state. 10 . The sensing device as claimed in claim 7 , wherein in the sensing phase of the sensing cycle, the first switch is in a closed state, the second switch is in an open state, and the third switch is in the open state.

11. The sensing device as described in claim 2, wherein the first voltage control component includes a first transistor, the second voltage control component includes a second transistor, a drain of the first transistor is connected to the fourth node, a source of the first transistor is connected to the third node, a gate of the first transistor is used to receive the clamping voltage, a drain of the second transistor is connected to the determination node, a source of the second transistor is connected to the third node, a gate of the second transistor is used to receive the clamping voltage, a size of the first transistor is larger than a size of the second transistor, and the first threshold voltage of the first transistor is smaller than the second threshold voltage of the second transistor.

12. The sensing device as described in claim 2, wherein the first voltage control component includes J transistors, the second voltage control component includes K transistors, the drains of the J transistors are connected to the fourth node, the sources of the J transistors are connected to the third node, the gates of the J transistors are used to receive the clamping voltage, the drains of the K transistors are connected to the determination node, the sources of the K transistors are connected to the third node, the gates of the K transistors are used to receive the clamping voltage, all the J transistors are the same size as the K transistors, and J and K are positive integers.

13. The sensing device as claimed in claim 1, wherein the first current mirror comprises: a first transistor, a drain of the first transistor being connected to the first node, a gate of the first transistor being connected to the first node, and a source of the first transistor being used to receive the ground voltage; and A second transistor, a drain of the second transistor is connected to the second node, a gate of the second transistor is connected to the first node, and a source of the second transistor is used to receive the ground voltage.

14. The sensing device as claimed in claim 1, wherein the second current mirror comprises: a first transistor, a drain of the first transistor being connected to the determination node, a gate of the first transistor being connected to the fifth node, and a source of the first transistor being used for receiving the supply voltage; as well as A second transistor, a drain of the second transistor is connected to the fifth node, a gate of the second transistor is connected to the fifth node, and a source of the second transistor is used to receive the supply voltage.

15. The sensing device as claimed in claim 1, wherein the determination circuit comprises: A comparator, a first input terminal of the comparator is connected to the judgment node, a second input terminal of the comparator is used to receive a comparison voltage, an output terminal of the comparator generates the output data, the comparison voltage is greater than the ground voltage, and the comparison voltage is less than the supply voltage.

16. The sensing device as claimed in claim 1, wherein the determination circuit comprises: A NOT gate, an input end of the NOT gate is connected to the judgment node, and an output end of the NOT gate generates the output data.

17. The sensing device as claimed in claim 1, further comprising: a fourth switch, a first terminal of the fourth switch being connected to the second node, a second terminal of the fourth switch being connected to a sixth node, and a control terminal of the fourth switch being used to receive an inverted control signal; and A pull-down element is connected between the sixth node and a ground terminal, and according to the output data, the pull-down element is used for pulling the voltage of the second node to the ground voltage of the ground terminal.

18. The sensing device as claimed in claim 17, wherein the sensing device further comprises: a delay circuit, an input end of the delay circuit is used to receive the output data, and an output end of the delay circuit is used to generate a delay signal according to the output data, wherein the pull-down component is connected to the output end of the delay circuit to receive the delay signal, When the delay signal is activated, the voltage of the second node is pulled down to the ground voltage by the pull-down component.

19. The sensing device as claimed in claim 1, wherein the determination circuit is used to receive an enable signal and generate the output data and a notification signal according to the enable signal and the determination voltage of the determination node, and the sensing device further comprises: a fourth switch, a first terminal of the fourth switch being connected to the second node, a second terminal of the fourth switch being connected to a sixth node, and a control terminal of the fourth switch being used to receive an inverted control signal; and A pull-down element is connected between the sixth node and a ground terminal, and according to the notification signal, the pull-down element is used for pulling the voltage of the second node to the ground voltage of the ground terminal.

20. The sensing device as claimed in claim 19, wherein the sensing device further comprises: a delay circuit, an input end of the delay circuit is used to receive the notification signal, and an output end of the delay circuit is used to generate a delay signal according to the notification signal, wherein the pull-down component is connected to the output end of the delay circuit to receive the delay signal, When the delay signal is activated, the voltage of the second node is pulled down to the ground voltage by the pull-down component.

21. The sensing device as claimed in claim 19, wherein the determination circuit comprises: a first NAND gate, a first input terminal of the first NAND gate being connected to the determination node, a second input terminal of the first NAND gate being used to receive the enable signal, and an output terminal of the first NAND gate being used to generate the output data; and a second NAND gate, a first input terminal of the second NAND gate being connected to the determination node, a second input terminal of the second NAND gate being used to receive the enable signal, and an output terminal of the second NAND gate being used to generate the notification signal; A first transition voltage of the first NAND gate is greater than a second transition voltage of the second NAND gate.

22. The sensing device as claimed in claim 1, wherein the non-volatile memory further comprises a voltage clamping circuit, and the voltage clamping circuit comprises: A first current source is connected to a sixth node, wherein the first current source is used to generate a second bias current, and the voltage of the sixth node is the clamping voltage; a first transistor, a drain of the first transistor being connected to the sixth node, and a source of the first transistor being used for receiving the ground voltage; and An operational amplifier, a first input terminal of the operational amplifier is used to receive a set voltage, a second input terminal of the operational amplifier is connected to the sixth node, and an output terminal of the operational amplifier is connected to a gate of the first transistor.

23. The sensing device as claimed in claim 1, wherein the non-volatile memory further comprises a voltage clamping circuit, and the voltage clamping circuit comprises: A first current source is connected to a sixth node, wherein the first current source is used to generate a second bias current, and the voltage of the sixth node is the clamping voltage; a first transistor, a drain of the first transistor connected to the sixth node, a gate of the first transistor connected to the sixth node, and a source of the first transistor connected to a seventh node; a second transistor, a drain of the second transistor being connected to the seventh node, and a source of the second transistor being used for receiving the ground voltage; and An operational amplifier, a first input terminal of the operational amplifier is used to receive a set voltage, a second input terminal of the operational amplifier is connected to the seventh node, and an output terminal of the operational amplifier is connected to a gate of the second transistor.

24. A sensing device for a non-volatile memory, wherein the non-volatile memory comprises a storage unit, during a sensing cycle, the storage unit is coupled to a data line, and the sensing device comprises: A first current mirror is connected to a first node and a second node, and is used to control a first current from the second node according to a reference current flowing through the first node, wherein the second node is connected to a data line; A first switch is connected to the second node and a third node, and a control terminal of the first switch is used to receive an inverted reset pulse; A second switch is connected to the second node and a ground terminal, and a control terminal of the second switch is used to receive a reset pulse; A voltage control circuit is connected to the third node and a determination node, and is used to conduct a current from the determination node to the third node in a unidirectional manner according to a magnitude relationship between the reference current and a current of a storage unit on the data line in a sensing phase of the sensing cycle; A second current mirror is connected to the determination node and a fourth node, and is used to control a second current flowing to the determination node according to a first bias current flowing through the fourth node; as well as A judgment circuit is connected to the judgment node and is used for generating an output data according to a judgment voltage on the judgment node.

25. The sensing device of claim 24, wherein during the sensing phase of the sensing cycle, when the storage cell current on the data line is lower than the reference current, the voltage control circuit conducts the current unidirectionally from the determination node to the third node; and wherein during the sensing phase of the sensing cycle, when the storage cell current on the data line is greater than the reference current, the voltage control circuit electrically isolates the determination node from the third node.

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