Memory device and method of operating memory device

Abstract

The invention provides a memory device and a method of operating the memory device. The memory device includes: a memory cell array including a plurality of memory cells to store data; an error correction code (ECC) circuit; and an error check and scrubbing (ECS) circuit. The ECC circuit reads data from the memory cell array and corrects errors in the data. The ECS circuit performs a scrubbing operation on the memory cell array, transmits a signal of an error address detected based on the scrubbing operation to an external circuit, and stores the transmitted error address.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of operating a memory device. Background Art

[0002] Generally speaking, as a memory device, a dynamic random access memory (DRAM) has a volatile data characteristic, so that even in the case of a normal cell, the validity of data cannot be guaranteed after a certain period of time.

[0003] Additionally, as DRAM cells continue to become smaller, the probability that a single bit or more error occurs in a memory device and cannot be corrected by an error correction code (ECC) circuit or a physical error (eg, hard failure) occurs is increasing.

[0004] In the field of memory devices, there is a growing need for efficient management of error addresses in cases where error correction is not possible or in case of physical errors. Summary of the invention

[0005] For example, in some implementations, the present disclosure relates to a memory device that enables a memory controller to efficiently perform page management.

[0006] In some implementations, the present disclosure relates to a memory device that independently manages erroneous addresses to be excluded from an error check and scrub (ECS) mode.

[0007] In some implementations, the present disclosure relates to a memory device having improved efficiency of repair operations.

[0008] In some implementations, the present disclosure relates to a memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells configured to store data; an error correction code (ECC) circuit, the ECC circuit configured to read the data from the memory cell array and configured to correct errors in the data; and an error checking and scrubbing (ECS) circuit, the ECS circuit configured to perform a scrubbing operation on the memory cell array in an ECS mode, send a signal of an error address detected based on the scrubbing operation to an external circuit, and store the error address sent to the external circuit.

[0009] In some implementations, the present disclosure relates to a method for operating a memory device, the method comprising: generating an error row address table for the row addresses based on a first report command for the row addresses of a memory cell array; performing a scrubbing operation on a first row address among the row addresses in an ECS mode; comparing the first row address with the error row address table; and recording the first row address based on a result of comparing the first row address.

[0010] In some implementations, the present disclosure relates to a memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; an ECC circuit, the ECC circuit being configured to read data from the memory cell array and correct errors in the data; and an ECS circuit, the ECS circuit being configured to perform a scrubbing operation on the memory cell array in an ECS mode and to send a signal of an error address detected based on the scrubbing operation to an external circuit; and a row decoder, the row decoder comprising a repair unit, the repair unit being configured to perform a repair operation on the plurality of word lines based on the error address sent to the external circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating an example electronic system.

[0012] Figure 2 is a block diagram illustrating an example storage system.

[0013] Figure 3 is a block diagram illustrating a configuration of an example memory device.

[0014] Figure 4 is a diagram for describing an example ECC circuit.

[0015] Figure 5 is a diagram for describing a bank array of a memory cell array and an example ECC circuit.

[0016] Figure 6 is a block diagram illustrating an example ECS circuit.

[0017] Figure 7 Is used to describe Figure 6 Diagram of the ECS registers.

[0018] Figure 8 Is used to describe Figure 6 Figure 1. Error row address (ERA) register.

[0019] Fig. 9 is a flow chart for describing an example method of operating a storage system.

[0020] Fig.10 is a ladder diagram for describing an example method of operating a storage system.

[0021] Figures 11 to 13 is a diagram for describing an example method of operating a storage system.

[0022] Fig.14 is a ladder diagram for describing an example method of operating a storage system.

[0023] Figures 15 to 17 is a diagram for describing an example method of operating a storage system.

[0024] Fig.18 is a block diagram illustrating a configuration of an example memory device.

[0025] Fig.19 is a block diagram illustrating a computer device to which an example storage system is applied.

[0026] Fig. 20 is a diagram for describing a graphic card system to which an example storage system is applied.

[0027] Fig.21 is a diagram for describing a computing system to which an example storage system is applied. DETAILED DESCRIPTION

[0028] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, in which implementations of the present disclosure are shown. As will be appreciated by those skilled in the art, the described implementations may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0029] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals designate like elements.

[0030] For better understanding and ease of description, the size and thickness of each constituent element in the drawings are arbitrarily illustrated, and the following implementation is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions may be exaggerated for ease of description.

[0031] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0032] Figure 1 is a block diagram illustrating an example electronic system.

[0033] refer to Figure 1 , an electronic system (or electronic apparatus) 10 may include a host 15 and a memory system 20. The memory system 20 may include a memory controller 100 and a plurality of memory devices 200a to 200n.

[0034] The host 15 may use an interface protocol such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS) to communicate with the storage system 20. Additionally, the interface protocol between the host 15 and the storage system 20 is not limited to the above examples, and may be one of other interface protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced MiniDisk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0035] The memory controller 100 controls the overall operation of the memory system 20 and controls the overall data exchange between the host 15 and the plurality of memory devices 200a to 200n. For example, the memory controller 100 may control the plurality of memory devices 200a to 200n to write or read data at the request of the host 15.

[0036] The memory controller 100 also controls operations of the plurality of memory devices 200 a to 200 n by providing commands for controlling the plurality of memory devices 200 a to 200 n .

[0037] Depending on the implementation, the plurality of memory devices 200a to 200n may be a dynamic random access memory (DRAM) having dynamic memory cells. In some implementations, each of the plurality of memory devices 200a to 200n may be a memory device including a resistive memory cell, such as a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory (FRAM).

[0038] Figure 2 is a block diagram illustrating an example storage system. Figure 2 , a memory device 200a corresponding to the memory controller 100 will be described as an example.

[0039] refer to Figure 1 and Figure 2 , the memory system 20 may include a memory controller 100 and a memory device 200a. The memory controller 100 and the memory device 200a may be connected to each other through corresponding command pins 101 and 201, address pins 102 and 202, and data pins 103 and 203, respectively.

[0040] The command pins 101 and 201 may transmit a command CMD through a command transmission line TL1 , and the address pins 102 and 202 may transmit an address ADDR through an address transmission line TL2 .

[0041] The data pins 103 and 203 may exchange main data MD through the data transmission line TL3 in the normal mode. The data pin 203 of the memory device 200a may send an error information signal EIS to the data pin 103 of the memory controller 100 through the data transmission line TL3 in the ECS mode. Depending on the implementation, when the command CMD of the memory controller 100 corresponds to a report on an error row address, the memory device 200a may receive the error information signal EIS about the error row address through the data pins 103 and 203. The command for reporting may be, for example, a mode register read (MRR) command that reads mode information in a register, but is not limited thereto.

[0042] The memory controller 100 may include a mapping management device (MAP MGNT) 110. The mapping management device 110 may be implemented as a mapping table that manages a logical address and a corresponding physical address of the mapped memory device 200a. In particular, the mapping management device 110 may use the error information signal EIS received from the memory device 200a to offline page the corresponding error row address, or provide the memory device 200a with a command CMD for a repair operation such as PPR (Post Package Repair), soft PPR, hard PPR, etc. The command for the repair operation may be, for example, a mode register write (MRW) command that writes mode information to a register, but is not limited thereto.

[0043] The memory device 200a may include a memory cell array (MCA) 300 in which main data MD is stored, an error correction code (ECC) circuit 400, an error check and scrub (ECS) circuit 600a, and a control circuit 210a that controls the ECS circuit 600a.

[0044] When the command CMD provided from the memory controller 100 indicates the ECS mode, the ECS circuit 600a may perform ECC decoding on the data in the subpage at the address indicated by the address signal ADDR sequentially or by a predetermined scheduling method. The ECS circuit 600a may control the ECC circuit 400 to generate a flag signal according to the ECC decoding. The flag signal may include information on whether an error is detected and whether the error is corrected, but may vary depending on the implementation.

[0045] Depending on the implementation, the ECS circuit 600a may record the error information generated based on the flag signal and the candidate error row address of the error information. When the command CMD provided from the memory controller 100 is a report on the error row address, the memory device 200a may send the row address recorded in the ECS circuit 600a as the error row address to the memory controller 100.

[0046] Depending on the implementation, the row address sent to the memory controller 100 may be stored in the ECS circuit 600a as an error row address. The stored error row address may be compared before recording the row address. The memory device 200a may prevent the error row address sent by the comparison operation from being sent again to the memory controller 100 through the ECS circuit 600a. Through the operation of the above-mentioned ECS circuit 600a, the memory controller 100 may effectively perform page management.

[0047] Figure 3 is a block diagram illustrating a configuration of a memory device.

[0048] refer to Figure 2 and Figure 3 , the memory device 200a may include a control circuit 210a, an address register 220, a memory bank control logic 230, a refresh counter 297, a row address multiplexer (RA MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 299, an ECC circuit 400, and an ECS circuit 600a.

[0049] The memory cell array 300 may include first to fourth bank arrays 310 to 340. Each of the first to fourth bank arrays 310 to 340 may include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the bit lines BTL.

[0050] Each of the plurality of word lines WL may correspond to each of the plurality of rows of the plurality of memory cells MC disposed in each of the first to fourth memory arrays 310 to 340. Additionally, the first to fourth memory arrays 310 to 340 may include a plurality of pages corresponding to the plurality of rows. Figure 5 , depending on the implementation, a row 1 ROW among multiple rows may correspond to a page PAG among multiple pages.

[0051] The row decoder 260 may include first to fourth bank row decoders 260a to 260d respectively connected to the first to fourth bank arrays 310 to 340. The column decoder 270 may include first to fourth bank column decoders 270a to 270d respectively connected to the first to fourth bank arrays 310 to 340. The sense amplifier 285 may include first to fourth bank sense amplifiers 285a to 285d respectively connected to the first to fourth bank arrays 310 to 340.

[0052] The first to fourth bank arrays 310 to 340, the first to fourth bank sense amplifiers 285a to 285d, the first to fourth bank column decoders 270a to 270d, and the first to fourth bank row decoders 260a to 260d may configure the first to fourth banks, respectively.

[0053] Figure 3 An example of the memory device 200 a including four memory banks is shown, but the number of memory banks is not limited thereto, and the memory device 200 a may include any number of memory banks.

[0054] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250.

[0055] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, a bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 260a to the fourth bank row decoder 260d may be activated, and a bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 270a to the fourth bank column decoder 270d may be activated.

[0056] The refresh counter 297 may generate a refresh row address REF_ADDR for refreshing a plurality of memory cells MC corresponding to each row of the memory cell array 300 under the control of the control circuit 210 a .

[0057] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 297. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 260a to 260d, respectively.

[0058] Among the first to fourth bank row decoders 260a to 260d, the bank row decoder activated by the bank control logic 230 may decode the row address RA output from the row address multiplexer 240 and activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0059] Among the first to fourth bank column decoders 270 a to 270 d , the bank column decoder activated by the bank control logic 230 may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 290 .

[0060] The input / output gating circuit 290 may include input data masking logic, a read data latch for storing data output from the first memory array 310 to the fourth memory array 340 and a write driver for writing data to the first memory array 310 to the fourth memory array 340, and a circuit for gating input / output data.

[0061] Data to be read from one of the first to fourth memory bank arrays 310 to 340 may be read by a sense amplifier corresponding to the one memory bank array and stored in a read data latch. Main data MD to be written in one of the first to fourth memory bank arrays 310 to 340 may be provided from the memory controller 100 to the data input / output buffer 299. The main data MD provided to the data input / output buffer 299 is encoded into a code word CW in the ECC circuit 400 and provided to the input / output gating circuit 290. The code word CW may be written to the one memory bank array by a write driver.

[0062] The data input / output buffer 299 may provide the main data MD provided from the memory controller 100 to the ECC circuit 400 in a write operation, and may provide the main data MD provided from the ECC circuit 400 to the memory controller 100 in a read operation.

[0063] Depending on the implementation, when main data MD of a subpage (one unit) includes a correctable error, the control circuit 210a may correct the error and control the ECC circuit 400 to perform a scrubbing operation of rewriting the corrected data to the corresponding subpage.

[0064] Depending on the implementation, the control circuit 210 a provides the third control signal CTL3 to the ECS circuit 600 a , and when the third control signal CTL3 corresponds to the ECS mode, the ECS circuit 600 a may be activated and perform a scrubbing operation on the memory cell array 300 through the ECC circuit 400 .

[0065] During the scrubbing operation, the ECC circuit 400 may output a flag signal F1 including information on whether an error is detected and whether the error is corrected.

[0066] The control circuit 210a may generate error information EINF based on the flag signal F1 and provide the error information to the ECS circuit 600a for recording. Depending on the implementation, the error information EINF may include a row address corresponding to a page, a correctable error (CE) count value of the row address, and information about the presence or absence of an uncorrectable error (hereinafter referred to as UE) in the row address, etc.

[0067] Hereinafter, in the present disclosure, "CE count value" may mean the number of sub-pages including CE in a page corresponding to a verified row address. Therefore, when a scrubbing operation is performed on a page corresponding to a verified row address, the CE count value of the row address on which the scrubbing operation is performed may match the number of sub-pages in which errors have been corrected in the row address.

[0068] For a UE, for example, one subpage may include two or more multi-bit errors.

[0069] The control circuit 210a may control the operation of the memory device 200a. For example, the control circuit 210a may generate a control signal so that the memory device 200a performs a write operation or a read operation. The control circuit 210a may include a command decoder 211 for decoding a command CMD received from the memory controller 100 and a mode register 212 for setting an operation mode of the memory device 200a.

[0070] The control circuit 210a may further include a counter that performs a counting operation based on the flag signal F1 from the ECC circuit 400. For example, the counter may count the number of subpages whose errors in the page have been corrected by the flag signal F1 for the subpage. The counter may calculate the CE count value of the row address.

[0071] For example, the command decoder 211 may decode the write enable signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, the chip select signal / CS, etc. to generate a control signal corresponding to the command CMD. In particular, the control circuit 210a may decode the command CMD to generate a first control signal CTL1 for controlling the input / output gating circuit 290, a second control signal CTL2 for controlling the ECC circuit 400, and a third control signal CTL3 for controlling the ECS circuit 600a.

[0072] When the command CMD indicates the ECS mode, the control circuit 210a may generate first, second, and third control signals CTL1, CTL2, and CTL3 so that the above-described scrubbing operations of the input / output gating circuit 290 and the ECC circuit 400 and the recording operation of the ECS circuit 600a are performed.

[0073] The ECC circuit 400 may generate parity data based on the main data MD provided from the data input / output buffer 299 during a write operation, and provide a codeword CW including the main data MD and the parity data to the input / output gating circuit 290. The input / output gating circuit 290 may write the codeword CW to the memory bank array.

[0074] Additionally, the ECC circuit 400 may receive a code word CW read from a memory bank array from the input / output gating circuit 290 during a read operation. The ECC circuit 400 may perform decoding of parity data included in the read code word CW into main data MD. Through decoding, a single bit error included in the main data MD may be corrected or a multi-bit error may be detected.

[0075] The ECC circuit 400 may sequentially perform ECC decoding on sub-pages included in a page in the memory cell array 300 in the ECS mode. Depending on the implementation, a page in the memory cell array 300 may include a plurality of sub-pages, and the sub-pages may include main data MD and parity data corresponding thereto. After performing ECC decoding on the data of the sub-page, the ECC circuit 400 may provide a flag signal F1 to the control circuit 210a, the flag signal F1 including information on whether an error is detected and whether the error is corrected for the data of the sub-page.

[0076] The ECS circuit 600a may receive error information EINF from the control circuit 210a and perform a recording operation. The ECS circuit 600a may also record a candidate error row address based on the error information EINF generated by the above-mentioned scrubbing operation. The ECS circuit 600a may provide an error information signal EIS of an error row address to the memory controller 100 according to the third control signal CTL3. The ECS circuit 600a may store an error row address corresponding to the transmitted error information signal EIS. The ECS circuit 600a may perform a comparison between the stored error row address and the candidate error row address, and record the candidate error row address according to the result of the comparison.

[0077] By transmitting the error information signal EIS, storing the error row address, and performing comparison operations with the stored error row address in the above-mentioned ECS circuit 600a, the memory device 200a can independently manage the error address without intervention of the memory controller 100. Additionally, through the operations in the above-mentioned ECS circuit 600a, the memory controller 100 can effectively perform page management.

[0078] Figure 4 is a diagram used to describe the ECC circuit. Figure 5 A diagram for describing a bank array and an ECC circuit of a memory cell array.

[0079] refer to Figures 2 to 5 , the ECC circuit 400 may include an ECC encoding circuit 410 and an ECC decoding circuit 420. The ECC encoding circuit 410 may generate parity data PRT[0:7] for data WData[0:127] to be written to the normal cell array 310a in the first memory bank array 310 in response to the second control signal CTL2. The generated parity data PRT[0:7] may be stored in the ECC cell array 310b in the first memory bank array 310.

[0080] The normal cell array 310 a is a block that determines the storage capacity of the memory device 200 a , and the ECC cell array 310 b is used for ECC, data line repair, and block repair to repair a bad cell, which may also be referred to as an EDB block.

[0081] Reference together Figure 5 , depending on the implementation, one page PAG in the first memory array 310 may have 64 subpages SUBPAG. For example, one subpage SUBPAG may include 128 bits of data and 8 bits of parity data, and one subpage SUBPAG may have a data size of 136 bits. One page PAG may correspond to one row 1ROW of a plurality of memory cells MC in the first memory array 310 and to one word line among a plurality of word lines WL.

[0082] Depending on the implementation, the 128-bit data and 8-bit parity data of the subpage SUBPAG may be sequentially read and provided to the ECC circuit 400 .

[0083] Depending on the implementation, the ECC encoding circuit 410 may generate parity data PRT[0:7] for data WData[0:127] in memory cells MC including bad cells in response to the second control signal CTL2. Depending on the implementation, the ECC encoding circuit 410 may store a single parity code or a single error correction and double error detection (SEC-DED) code.

[0084] In response to the second control signal CTL2, the ECC decoding circuit 420 may correct error bit data using the data RData[0:127] read from the memory cells MC of the normal cell array 310a and the parity data PRT[0:7] read from the ECC cell array 310b to output error correction data Data[0:127].

[0085] Depending on the implementation, the ECC decoding circuit 420 may store a single parity code or a single error correction and double error detection (SEC-DED) code. For example, the ECC decoding circuit 420 may correct a single-bit error or detect a double-bit error for the read data RData[0:127] by decoding using the SEC-DED code to detect UE.

[0086] Although not shown, the ECC decoding circuit 420 can generate a syndrome including error position information and an error occurrence signal, etc. by operating based on the read data RData[0:127] and the parity data PRT[0:7]. The ECC decoding circuit 420 can output and provide a flag signal F1 to the control circuit 210a, the flag signal F1 including information on whether an error is detected and whether an error is corrected for the error correction data Data[0:127] output based on the generated syndrome, the error occurrence signal, etc.

[0087] Although not shown, depending on the implementation, the ECC decoding circuit 420 may directly provide the flag signal F1 to the ECS circuit 600 a , and the ECS circuit 600 a may perform a recording operation based on the provided flag signal F1 .

[0088] Figure 6 is a block diagram illustrating an ECS circuit. Figure 7 Is used to describe Figure 6 Diagram of the ECS registers. Figure 8 Is used to describe Figure 6 Diagram of the ERA register.

[0089] refer to Figure 3 and Figures 6 to 8 , the ECS circuit 600 a may include an ECS logic 610 , an ECS register 620 , and an ERA register 630 .

[0090] The ECS logic 610 is activated when the third control signal CTL3 corresponds to the ECS mode of the memory device 200 a , and may perform a scrubbing operation on the memory cell array 300 through the ECC circuit 400 .

[0091] When the third control signal CTL3 corresponds to a report command for an error row address, the ECS logic 610 may output the candidate error row address Pre_ERA recorded in the ECS register 620 as the error row address. The output error row address may be sent to the memory controller 200 as an error information signal EIS.

[0092] The ECS logic 610 may store the error row address ERA corresponding to the transmitted error information signal EIS in the error row address table ERA_TABL. Depending on the implementation, the error row address table ERA_TABL may include a plurality of error row addresses ERA.

[0093] The ECS logic 610 may compare the row address included in the received error information EINF with the error row address ERA stored in the error row address table ERA_TABL.

[0094] Depending on the implementation, if the stored error row address ERA is the same as the row address included in the received error information EINF, a record operation may not be performed based on the received error information EINF in the ECS register 620. Depending on the implementation, if the stored error row address ERA is different from the row address included in the received error information EINF, a record operation may be performed based on the received error information EINF in the ECS register 620. Depending on the implementation, the candidate error row address Pre_ERA recorded in the ECS register 620 may be different from the error row address ERA stored in the ERA register 630.

[0095] refer to Figure 8 As an example, if a row address included in the received error information EINF is identical to a plurality of error row addresses RAb, RAd, . . . , RAz stored in the error row address table ERA_TABL, the ECS logic 610 may not perform a logging operation based on the received error information EINF.

[0096] Through the comparison operation of the ECS logic 610, the memory device 200a can be operated without the memory controller 100 ( Figure 2 )’s intervention to manage the error row address independently.

[0097] The ECS logic 610 may record the candidate error row address Pre_ERA and error information about the candidate error row address Pre_ERA in the ECS register 620 based on the received error information EINF.

[0098] Reference now Figure 7 The ECS logic 610 may record the candidate error row address Pre_ERA, the CE count value CE_COUNT of the candidate error row address Pre_ERA, and the presence or absence of the UE of the candidate error row address Pre_ERA in the ECS register 620 .

[0099] Depending on the implementation, if the CE count value included in the error information EINF received in the ECS logic 610 is greater than the CE count value of the candidate error row address Pre_ERA stored in the ECS register 620, the ECS logic 610 may re-record the candidate error row address Pre_ERA in the ECS register 620 based on the received error information EINF.

[0100] Depending on the implementation, if the row address of the error information EINF received in the ECS logic 610 includes UE, the ECS logic 610 may re-record the candidate error row address Pre_ERA in the ECS register 620 based on the received error information EINF. For example, if the page of the row address of the received error information EINF includes a UE subpage having UE, the ECS logic 610 may perform a new recording operation on the ECS register 620.

[0101] The ECS register 620 can store the final candidate error row address Pre_ERA detected according to the scrubbing operation through the above-mentioned recording operation. Depending on the implementation, the ECS register 620 can record one candidate error row address Pre_ERA and the error information EINF of the one candidate error row address Pre_ERA. For example, according to the DDR5 specification, one error address is recorded for each memory chip. In addition, according to the HBM3 specification, one error address is recorded for each pseudo channel.

[0102] refer to Figure 7As an example, the ECS register 620 may record the y-th row address RAy (the CE count value of the y-th row address RAy is Cy) and information that does not include UE in the y-th row address RAy. For example, among the pages scrubbed after receiving the latest report command, the page corresponding to the y-th row address RAy may include the maximum number of sub-pages in which errors are corrected. That is, after receiving the latest report command, the CE count value may be the maximum at the y-th row address RAy.

[0103] The ERA register 630 may store an error row address table ERA_TABL. Depending on the implementation, the error row address table ERA_TABL may store up to a predetermined number of error row addresses.

[0104] refer to Figure 8 As an example, the error row address table ERA_TABL may include n tables and store up to n error row addresses, and Figure 8 The error row address table ERA_TABL in stores n-3 different error row addresses RAb, RAd, . . . , RAz, but is not limited to the above-mentioned number example.

[0105] Multiple error row addresses RAb, RAd, ..., RAz can be stored in the error row address table ERA_TABL by sending an error information signal EIS by the ECS logic 610, storing the error row address ERA, performing a comparison operation between the stored error row address ERA and the received error information EINF, and repeating the recording operation for the candidate error row address Pre_ERA.

[0106] In this figure, the ECS circuit 600a is shown as being configured as a separate dedicated circuit in the memory device 200a. However, depending on the implementation, the ECS circuit 600a may be a component in the control circuit 210a.

[0107] Fig. 9 is a flow chart for describing a method of operating a storage system. Fig.10 It is a ladder diagram used to describe the method of operating a storage system. Figures 11 to 13 is a diagram for describing a method of operating a storage system.

[0108] refer to Figure 3 , Figure 6 , Fig. 9 and Fig.10 , the memory device 200a generates an error row address table ERA_TABL based on the report command (S110).

[0109] The memory controller 100 may provide a report command requesting a report on an error row address to the memory device 200a (S111). The control circuit 210a of the memory device 200a may output a third control signal CTL3 to control the ECS circuit 600a in response to receiving the report command for the error row address from the memory controller 100.

[0110] In response to receiving the report command, the ECS circuit 600a of the memory device 200a may report the candidate error row address Pre_ERA recorded in the ECS register 620 as the error row address ERA to the memory controller 100 (S112). The report on the error row address ERA may be provided to the memory controller 100 in the form of an error information signal EIS.

[0111] The ECS circuit 600 a may store the error row address ERA corresponding to the error information signal EIS in the error row address table ERA_TABL ( S113 ).

[0112] The ECS circuit 600 a may remove the error row address ERA recorded in the ECS register 620 after the reporting and storage operations for the error row address ERA ( S114 ).

[0113] The memory controller 100 may provide a command for the ECS mode (ECS CMD) to the memory device 200a (S120). The ECS circuit 600a of the memory device 200a may be activated by the command for the ECS mode.

[0114] The ECS circuit 600a may perform a scrubbing operation on a page corresponding to a row address in the ECS mode (S130). The ECS circuit 600a may perform a scrubbing operation on a sub-page basis in a page through the ECC circuit 400.

[0115] The ECS logic 610 may compare the row address subjected to the scrubbing operation with the error row address ERA stored in the error row address table ERA_TABL (S140). The ECS logic 610 may receive the row address subjected to the scrubbing operation through the received error information EINF and compare the received row address subjected to the scrubbing operation with the error row address ERA.

[0116] The ECS circuit 600a may record the row address of the candidate error row address Pre_ERA in the ECS register 620 according to the result of the comparison in step S140 (S150). Depending on the implementation, the ECS circuit 600a may record the candidate error row address Pre_ERA in the ECS register 620 based on the CE count value of the row address and the result of the comparison in step S140 (S151).

[0117] Depending on the implementation, if the row address subject to scrubbing is different from the error row address ERA, the ECS circuit 600a may compare the CE count value of the candidate error row address Pre_ERA stored in the ECS register 620 with the CE count value of the row address subject to scrubbing received through the error information EINF.

[0118] If the scrubbed row address is different from the error row address ERA and the CE count value of the scrubbed row address received through the error information EINF is greater than the CE count value of the candidate error row address Pre_ERA, the ECS logic 610 may record the scrubbed row address in the ECS register 620 .

[0119] Depending on the implementation, if the row address is not recorded in the ECS register 620 , the ECS logic 610 may record the row address subject to the scrub operation in the ECS register 620 only by comparing it with the error row address ERA.

[0120] In addition, refer to Figure 8 , Fig.11 and Fig.12 For example, in the case where the x-th row address RAx is recorded in the ECS register 620 as the candidate error row address Pre_ERA, the ECS logic 610 may perform a scrubbing operation on the y-th row address RAy.

[0121] The ECS logic 610 may compare the y-th row address RAy with the error row address ERA of the error row address table ERA_TABL when performing a scrubbing operation on the y-th row address RAy. In addition, if the y-th row address RAy and the error row address ERA are different from each other, the ECS logic 610 may compare Cx, i.e., the CE count value of the x-th row address RAx recorded as the candidate error row address Pre_ERA, with Cy, i.e., the CE count value of the y-th row address RAy.

[0122] Among the multiple x_1th sub-pages SUBPAGx1 to x_Mth sub-pages SUBPAGxM included in the xth row address RAx, Cx sub-pages may include CE. Cx sub-pages may be error corrected during the scrubbing operation. Among the multiple y_1th sub-pages SUBPAGy1 to y_Mth sub-pages SUBPAGyM included in the yth row address RAy, Cy sub-pages may include CE. Cy sub-pages may be error corrected during the scrubbing operation. Depending on the implementation, Cy may be greater than Cx.

[0123] The ECS logic 610 may record, to the ECS register 620 , a y-th row address RAy corresponding to Cy greater than Cx and different from a plurality of error row addresses RAb, RAd, . . . , RAz stored in the error row address table ERA_TABL as a candidate error row address Pre_ERA.

[0124] The ECS logic 610 of the memory device 200a may check whether a report command for an error row address is received from the memory controller 100 (S160). Depending on the implementation, if the ECS logic 610 does not receive the third control signal CTL3 corresponding to the report command, the ECS logic 610 may operate by determining that the report command has not been received.

[0125] If the report command is not received, the ECS logic 610 may move to a row address subject to a next scrub operation (S170). The movement of the scrub operation to the target may be sequentially performed by row address or by a predetermined scheduling method.

[0126] Before receiving the next report command, the ECS logic 610 may repeatedly perform steps S130 to S170 .

[0127] The memory controller 100 may provide a report command requesting a report on an error row address to the memory device 200a (S161). The control circuit 210a of the memory device 200a may output a third control signal CTL3 to control the ECS circuit 600a in response to receiving the report command of the error row address of the memory controller 100.

[0128] In response to receiving the report command in step S161 , the ECS circuit 600 a of the memory device 200 a may report the candidate error row address Pre_ERA recorded in the ECS register 620 as the error row address ERA to the memory controller 100 ( S180 ).

[0129] refer to Figure 8 , Fig.11 and Fig.12 As an example, between step S120 and step S161 , the ECS circuit 600 a may perform sequential scrubbing operations for the x-th row address RAx to the y-th row address RAy.

[0130] If the CE count value of the yth row address RAy is the largest among the xth row addresses RAx to yth row addresses RAy subjected to the scrub operation, the yth row address RAy may be finally recorded in the ECS register 620 as a candidate error row address Pre_ERA.

[0131] The finally recorded y-th row address RAy may be provided to the memory controller 100 in the form of an error information signal EIS.

[0132] The ECS circuit 600 a may store the error row address ERA corresponding to the error information signal EIS in the error row address table ERA_TABL ( S190 ).

[0133] In addition, refer to Fig.13 , the ECS circuit 600a may add and store the yth row address RAy transmitted in the form of the error information signal EIS to the error row address table ERA_TABL. Thereafter, the ECS circuit 600a may remove the error row address ERA recorded in the ECS register 620 (S191). For example, the ECS circuit 600a may remove the recorded yth row address RAy from the ECS register 620.

[0134] By the method of operating the memory device 200a as described above, the memory device 200a can prevent error addresses from being redundantly transmitted to the memory controller 100. In addition, the memory device 200a can independently manage error row addresses without separate intervention of the memory controller 100.

[0135] Fig.14 It is a ladder diagram used to describe the method of operating a storage system. Figures 15 to 17 is a diagram for describing a method of operating a storage system.

[0136] Fig.14 is a ladder diagram for describing another method of operating the memory device 200a. For ease of description, the following description will focus on Fig.10 The description of the omitted steps can be replaced by the description of the method of operating the memory device 200a in FIG. Fig.10 Replace with the description of the corresponding step in .

[0137] refer to Fig. 9 and Fig.14 , the ECS circuit 600a may record the row address of the candidate error row address Pre_ERA in the ECS register 620 according to the result of the comparison in step S140 (S150). Depending on the implementation, the ECS circuit 600a may record the candidate error row address Pre_ERA in the ECS register 620 based on whether the row address includes UE together with the result of the comparison in step S140 (S152).

[0138] Depending on the implementation, if the row address subject to the scrub operation is different from the error row address ERA, the ECS circuit 600a may detect whether a page corresponding to the row address subject to the scrub operation has a subpage including the UE.

[0139] If the row address subject to the scrub operation is different from the error row address ERA and the UE is included in a page corresponding to the row address, the ECS logic 610 may preferentially record the row address subject to the scrub operation in the ECS register 620 .

[0140] Depending on the implementation, if the row address is not recorded in the ECS register 620 , the ECS logic 610 may record the row address subject to the scrub operation in the ECS register 620 only by comparing it with the error row address ERA.

[0141] In addition, refer to Figure 8 , Fig.15 and Fig.16 For example, in the case where the a-th row address RAa is recorded in the ECS register 620 as the candidate error row address Pre_ERA, the ECS logic 610 may perform a scrubbing operation on the z-th row address RAz.

[0142] The ECS logic 610 may compare the zth row address RAz with the error row address ERA of the error row address table ERA_TABL when performing a scrub operation on the zth row address RAz. Additionally, if the zth row address RAz and the error row address ERA are different from each other, the ECS logic 610 may check whether the zth row address RAz includes a UE.

[0143] Among the plurality of a_1th sub-pages SUBPAGA1 to a_Mth sub-pages SUBPAGAM included in the ath row address RAa, Ca sub-pages may include CE, and the xth row address RAx does not include UE. Ca sub-pages may be error corrected during the scrubbing operation. The z_3th sub-page SUBPAGz3 among the plurality of z_1th sub-pages SUBPAGz1 to z_Mth sub-pages SUBPAGzM included in the zth row address RAz may include UE detected by ECC decoding with the SEC-DED code.

[0144] However, the ECS logic 610 cannot record the zth row address RAz as the candidate error row address Pre_ERA in the ECS register 620 because the zth row address RAz matches a plurality of error row addresses RAb, RAd, . . . , RAz stored in the error row address table ERA_TABL.

[0145] In another implementation, if the zth row address RAz is different from a plurality of error row addresses stored in the error row address table ERA_TABL and the zth row address RAz includes UE, the zth row address RAz may be preferentially recorded in the ECS register 620 as a candidate error row address Pre_ERA.

[0146] In addition, refer to Fig.17 If the ath row address RAa is finally recorded in the ECS register 620, the ath row address RAa may be provided to the memory controller 100 in the form of the error information signal EIS. The ECS logic 610 may add and store the ath row address RAa sent in the form of the error information signal EIS to the error row address table ERA_TABL.

[0147] By the method of operating the memory device 200 a as described above, it is possible to prevent the same error row address from being repeatedly recorded in the ECS register 620 of the memory device 200 a .

[0148] Fig.18 is a block diagram illustrating a configuration of a memory device.

[0149] Fig.18 The memory device 200a' may correspond to Figure 3 In the following, for the convenience of description, the following description will focus on Figure 3 The description omitted in the configuration can be used to Figure 3 . The description of the storage device 200a in FIG.

[0150] refer to Fig.18 , the row decoder 260' may include a repair unit. Each of the first to fourth bank row decoders 260a' to 260d' may include a repair unit, and the first bank row decoder 260a' may include a first repair unit 261a.

[0151] The first repair unit 261 a may perform operations such as word line repair and block repair to repair defective cells in the first memory bank array 310 .

[0152] Depending on implementation, a fourth control signal CTL4 output from the control circuit 210 a and an error row address table ERA_TABL output from the ECS circuit 600 b may be provided.

[0153] When the fourth control signal CTL4 corresponds to a command CMD for a repair operation such as hard post package repair hPPR, the first repair unit 261a may perform a repair operation on a word line WL corresponding to an error row address stored in the error row address table ERA_TABL. Depending on the implementation, the word line on which the repair operation is performed may be replaced with a word line arranged in a redundant cell array.

[0154] Fig.18 The memory device 200a' can independently perform a repair operation without receiving a defective address from the outside, thereby improving the efficiency of the repair operation.

[0155] Fig.19 is a block diagram illustrating a computer device to which a storage system is applied. Fig.19 , the computer device 1000 includes a processor 1001, an input / output hub (IOH) 1002, an input / output controller hub (ICH) 1003, at least one memory module 1200a and a graphic card 1005.

[0156] Depending on the implementation, the computer device 1000 can be any computing system, such as a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, etc.

[0157] The processor 1001 may perform various computing functions such as specific calculations or tasks. For example, the processor 1001 may be a microprocessor or a central processing unit (CPU). Depending on the implementation, the processor 1001 may include one processor core (single core) or multiple processor cores (multi-core). For example, the processor 1001 may include multiple cores such as dual cores, quad cores, or hexa cores. Additionally, although Fig.19 The computer device 1000 including one processor 1001 is shown, but depending on the implementation, the computer device 1000 may include multiple processors. In addition, depending on the implementation, the processor 1001 may also include a cache memory located internally or externally.

[0158] The processor 1001 may include a memory controller 1100 that controls the operation of the memory module 1200a. The memory controller 1100 included in the processor 1001 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 1100 and the memory module 1200a may be implemented as a channel including a plurality of signal lines, or may be implemented as a plurality of channels. Additionally, one or more memory modules 1200a may be connected to each channel. Depending on the implementation, the memory controller 1100 may be located in the input / output hub 1002. The input / output hub 1002 including the memory controller 1100 may be referred to as a memory controller hub (MCH).

[0159] The memory module 1200a may include a memory device storing data provided from the memory controller 1100. Figures 1 to 18As described, each memory device may perform the above-mentioned ECS scrubbing operation, the transmission operation of the error information signal EIS, and the storage operation for the error row address corresponding to the error information signal EIS, thereby including a control circuit, an ECC circuit, and an ECS circuit.

[0160] Through the ECS scrubbing operation, the transmission operation of the error information signal EIS, and the storage operation for the error row address corresponding to the error information signal EIS, the memory module 1200a can prevent the error row address from being redundantly transmitted to the memory controller 1100. In addition, the memory device 1200a can independently manage the error row address without separate intervention of the memory controller 1100.

[0161] The input / output hub 1002 may manage data transmission between the processor 1001 and a device such as a graphics card 1005. The input / output hub 1002 may be connected to the processor 1001 through various interfaces. For example, the input / output hub 1002 and the processor 1001 may be connected via various standard interfaces such as a front side bus (FSB), a system bus, HyperTransport, a lightning data transfer (LDT), a quick path interconnect (QPI), a common system interface (CSI), etc.

[0162] although Fig.19 The computer device 1000 is shown to include one input / output hub 1002, but depending on the implementation, the computer device 1000 may include multiple input / output hubs.

[0163] The input / output hub 1002 may provide various interfaces with devices, such as an accelerated graphics port (AGP) interface, a peripheral component express interface (PCIe) interface, a communication stream architecture (CSA) interface, and the like.

[0164] The graphics card 1005 can be connected to the input / output hub 1002 via AGP or PCIe. The graphics card 1005 can control a display device for displaying an image. The graphics card 1005 may include an internal processor and an internal memory device for image data processing. Depending on the implementation, the input / output hub 1002 may include a graphics device located outside the input / output hub 1002 or inside the input / output hub 1002 instead of the graphics card 1005. The graphics device included in the input / output hub 1002 may be referred to as an integrated graphics card. Additionally, the input / output hub 1002 including a memory controller and a graphics device may be referred to as a graphics memory controller hub (GMCH).

[0165] The input / output controller hub 1003 can perform data buffering and interface arbitration so that various system interfaces work efficiently. The input / output controller hub 1003 can be connected to the input / output hub 1002 through an internal bus. For example, the input / output hub 1002 and the input / output controller hub 1003 can be connected through a direct media interface (DMI), a hub interface, an enterprise south bridge interface (ESI), PCIe, etc.

[0166] The input / output controller hub 1003 may provide various interfaces with peripheral devices. For example, the input / output controller hub 1003 may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input / output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.

[0167] Depending on the implementation, the processor 1001, the input / output hub 1002, and the input / output controller hub 1003 may be implemented as separate chipsets or integrated circuits, or two or more constituent elements among the processor 1001, the input / output hub 1002, or the input / output controller hub 1003 may be implemented as a single chipset.

[0168] Fig. 20 is a diagram for describing a graphics card system to which a storage system is applied. Fig. 20 In the graphics card system 2000, the GPU 2500 and the stacked DRAM 2300 may be connected to the package substrate 2100 through the build-up layer 2200. The DRAM 2300 may be connected to the HBM controller 2400 through TSV (via). The HBM controller 2400 may be connected to the GPU 2500 through the build-up layer 2200.

[0169] Each of the DRAM 2300 and the HBM controller 2400 may perform an ECS scrubbing operation, a transmission operation of an error information signal, and a storage operation for an error row address corresponding to the error information signal, such as Figures 1 to 18 Depending on the implementation, the HBM controller 2400 may include a control circuit, an ECC circuit, and an ECS circuit.

[0170] Through the ECS scrubbing operation, the transmission operation of the error information signal, and the storage operation for the error row address corresponding to the error information signal, the HBM controller 2400 can prevent the error row address of the DRAM 2300 from being redundantly transmitted to the GPU 2500. In addition, the HBM controller 2400 can independently manage the error row address of the DRAM 2300 without separate intervention of the GPU 2500.

[0171] Fig.21 is a diagram used to describe a computing system to which a storage system is applied. Fig.21 , the computing system 3000 may include a host processor 3100 and at least one memory package chip 3200 controlled by the host processor 3100. Depending on the implementation, the host processor 3100 and the memory package chip 3200 may send and receive data through a channel 3001.

[0172] The memory package chip 3200 may include a stacked memory chip and a controller chip. Fig.21 As shown, the memory package chip 3200 may include a plurality of DRAM memory chips formed on a DRAM controller chip. Figures 1 to 18 As described in the , between the memory chip and the controller chip of the memory package chip 3200, an ECS scrubbing operation, a transmission operation of an error information signal, and a storage operation for an error row address corresponding to the error information signal can be performed. The memory package chip 3200 can independently manage the error row address of the memory chip without separate intervention.

[0173] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of what can be claimed. Certain features described in the context of separate implementations in the present disclosure can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features can be described above as acting in certain combinations, one or more features from a combination can be removed from the combination in some cases, and the combination can be directed to a sub-combination or a variation of a sub-combination.

[0174] Although the implementations of the present disclosure have been described in detail, it should be understood that the present disclosure is not limited to the disclosed implementations, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells configured to store data; an error correction code circuit configured to read the data from the memory cell array and correct errors in the data; as well as An error check and scrub circuit is configured to perform a scrubbing operation on the memory cell array in an error check and scrub mode, send a signal of an error address detected based on the scrubbing operation to an external circuit, and store the error address sent to the external circuit.

2. The memory device according to claim 1, wherein: The error checking and scrubbing circuit comprises: a first register in which the first row address of the error address is recorded; and A second register in which the error address sent to the external circuit is stored.

3. The memory device according to claim 2, wherein: The error checking and scrubbing circuit is further configured to remove the first row address from the first register after the error address is sent to the external circuit.

4. The memory device according to claim 3, wherein: The error check and scrub circuit is further configured to record a second row address in the first register after the error address is sent to the external circuit.

5. The memory device according to claim 4, wherein: The second row address and the error address stored in the second register are different from each other.

6. The memory device according to claim 2, wherein: The first register is configured to store a first count value together with the first row address, the first count value being the number of subpages including correctable errors in the first row address.

7. The memory device according to claim 6, wherein: The error check and scrub circuit is configured to: perform a scrubbing operation on a second row address different from the first row address before sending the error address to the external circuit, The first count value is greater than a second count value, which is the number of subpages including correctable errors in the second row address.

8. The memory device according to claim 2, wherein: The first row address includes an uncorrectable error subpage having uncorrectable errors.

9. The memory device according to claim 8, wherein: The error correction code circuit is configured to detect the uncorrectable error sub-page by single error correction and double error detection codes.

10. The memory device according to claim 2, wherein: The error check and scrub circuit is configured to transmit the first row address recorded in the first register as the error address in response to a report command received from the external circuit.

11. The memory device according to claim 10, wherein: The report command is a mode register read command.

12. A method of operating a memory device, the method comprising: generating an error row address table for the row address based on a first report command for the row address of the memory cell array; performing a scrubbing operation on a first row address among the row addresses in an error checking and scrubbing mode; comparing the first row address with the error row address table; as well as The first row address is recorded according to a result of comparing the first row address.

13. The method for operating a memory device according to claim 12, wherein: Generating the error row address table includes: receiving the first report command; sending the candidate row address recorded in the first register to the memory controller in response to receiving the first report command; and The transmitted candidate row address is stored in the error row address table.

14. The method for operating a memory device according to claim 13, wherein: Generating the error row address table further includes: The row address is removed from the first register.

15. The method for operating a memory device according to claim 12, wherein: When the error address in the error row address table is different from the first row address, the first row address is recorded in the first register.

16. The method for operating a memory device according to claim 15, wherein: The first row of addresses includes a subpage having uncorrectable errors.

17. The method for operating a memory device according to claim 15, the method further comprising: performing a scrubbing operation on a second row address different from the first row address in the error checking and scrubbing mode; comparing the second row address with the error row address table; as well as If the second row address is different from the error address in the error row address table, and if the first count value is less than the second count value, the second row address is recorded to the first register, wherein the first count value is the number of subpages in the first row address that include correctable errors, and wherein the second count value is the number of subpages in the second row address that include correctable errors.

18. The method of operating a memory device according to claim 12, the method further comprising: receiving a second reporting command after the first reporting command; sending the recorded first row address to a memory controller in response to the second report command; as well as The transmitted first row address is stored in the error row address table.

19. A storage device, comprising: A memory cell array, the memory cell array comprising a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; an error correction code circuit configured to read data from the memory cell array and configured to correct errors in the data; as well as an error checking and scrubbing circuit configured to perform a scrubbing operation on the memory cell array in an error checking and scrubbing mode and to send a signal of an error address detected based on the scrubbing operation to an external circuit; as well as A row decoder includes a repair unit configured to perform a repair operation on the plurality of word lines based on the error address sent to the external circuit.

20. The memory device according to claim 19, wherein: The error checking and scrubbing circuit is further configured to store the error address sent to the external circuit.

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