Memory controller and 3D stacked memory

Abstract

The present invention provides a memory controller and a three-dimensional stacked memory, wherein a read cache area and a prefetch cache area are provided in the memory controller. Each time data is read, it is first determined whether the data to be read has been cached in advance in the prefetch cache area. If not, while reading the corresponding data in the hit layer of the multi-layer memory chip (i.e., the data stored in the hit storage unit), the corresponding data in at least one non-hit layer of the multi-layer memory chip is also read (i.e., prefetched), and error checking and correction are further performed on both the read and prefetched data. After the error checking and correction, the data in the hit layer is cached in the read cache area, the prefetched data is cached in the prefetch cache area, and the data cached in the read cache area is retrieved and returned to the main chip. This realizes the functions of prefetching data from the multi-layer memory chip, performing ECC error correction on the read and prefetched data first, and then caching them separately, thereby improving the reliability of stored data and system performance.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory controller and a three-dimensional stacked memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) has been widely used as main memory in various applications, covering high-performance computing, mobile applications and other fields due to its advantages such as high density, simple architecture, low latency and low power consumption.

[0003] Please refer to Figure 1 , a current DRAM has a memory controller 2 and stacked multi-layer memory chips (i.e. corresponding to Figure 1 The memory controller 2 is coupled to the main chip (logic die, also called "master die" or "compute die") 1, so that the main chip 1 can communicate with each layer of memory chips (i.e., DRAM chips) 30, 31, 32... directly through through-silicon vias (TSVs) or through a buffer chip (buffer die, also called "base die" or "interface die") and TSVs. This enables the main chip 1 to access each layer of memory chips (i.e., DRAM chips) 30, 31, 32... through an AXI interface, thereby expanding the memory capacity managed by the main chip 1. The memory controller 2 is set in the main chip 1 or in the buffer chip. Each layer of memory chip (i.e., DRAM chip) has multiple storage units (also called "DRAM units") of the same capacity. For the main chip 1, the multiple storage units in each layer of memory chip (i.e., DRAM chip) managed by the memory controller 2 are independent of each other.

[0004] To improve DRAM system stability, the ECC (Error Checking and Correcting) function (also known as "ECC error correction") is currently introduced to promptly detect and correct data storage errors within the DRAM, thereby extending the normal operation time of the DRAM system.

[0005] How to further improve the data reliability and system performance of DRAM is still one of the hot issues that technicians in this field need to solve. Summary of the Invention

[0006] An object of the present invention is to provide a memory controller and a three-dimensional stacked memory, which can improve the system performance of the memory.

[0007] To achieve the above objectives, the present invention provides a memory controller coupled between a main chip and a stack of multiple layers of memory chips, wherein each layer of the memory chips includes multiple storage units, wherein the memory controller has a data cache area, wherein the data cache area includes a read cache area and a prefetch cache area, and the memory controller is configured as follows:

[0008] Receive and analyze the corresponding read instruction, and determine whether the data read by the read instruction has been cached in the pre-fetch cache area in advance,

[0009] If not, perform the following steps:

[0010] Opening word lines of the memory chips of different layers that share the execution row address of the read instruction to read data of corresponding hit storage cells and non-hit storage cells in the multi-layer memory chips;

[0011] Perform error checking and correction on the read data;

[0012] caching the error-checked and corrected data corresponding to the hit storage unit into the read cache area, and caching the error-checked and corrected data corresponding to the non-hit storage unit into the prefetch cache area;

[0013] The data cached in the read cache area is retrieved and returned to the master chip.

[0014] Optionally, the memory controller is configured to: determine a hit layer in the multi-layer memory chip according to the chip select address of the read instruction, wherein the hit storage unit belongs to the hit layer, and the non-hit storage unit belongs to at least one non-hit layer other than the hit layer in the multi-layer memory chip; and / or

[0015] The memory controller is further configured to: if it is determined that the data read by the read instruction has been cached in the pre-fetch cache area in advance, fetch the data corresponding to the read instruction from the pre-fetch cache area and return it to the master chip.

[0016] Optionally, the memory controller further includes at least one IO interface, a control management module, and a plurality of storage control modules; the data cache is provided in the control management module and is correspondingly provided and coupled to the IO interface; each of the storage control modules is coupled to the control management module and the multi-layer memory chip; wherein:

[0017] The control management module is used to parse the read instruction to obtain the hit layer, the hit storage unit in the hit layer, and the execution row address of the hit storage unit, and determine whether the data read by the read instruction has been cached in advance in the prefetch cache area;

[0018] The storage control module is used to open the word lines sharing the execution row address in the memory chips of different layers including the hit layer, so as to read the data of the hit storage cells and the data of the non-hit storage cells, perform error checking and correction on the read data, and cache the error-checked and corrected data corresponding to the hit storage cells in the corresponding read cache area, and cache the error-checked and corrected data corresponding to the non-hit storage cells in the corresponding prefetch cache area;

[0019] The IO interface is used to receive the read instruction, and according to the judgment result of the control management module, fetch the data corresponding to the read instruction from the corresponding read buffer area or the pre-fetch buffer area, and return it to the main chip.

[0020] Optionally, the control management module further includes:

[0021] an address decoder, configured to parse the read instruction to obtain the hit layer of the read instruction, the hit storage unit in the hit layer, and the execution row address in the hit storage unit;

[0022] A discriminator is used to determine whether the data read by the read instruction has been cached in advance in the prefetch cache area according to the parsing result of the address decoder.

[0023] Optionally, the storage control module includes an error checking and correction control module, and the error checking and correction control module includes multiple error checking and correction control units. Each of the error checking and correction control units is arranged and coupled one-to-one with the memory chips of each layer managed by the storage control module. The error checking and correction control unit is used to perform error checking and correction on the data read from the memory chip to which it is coupled.

[0024] Optionally, the data read by the read instruction corresponds to data continuously stored in multiple hit storage units in the hit layer, and the multiple storage control modules that manage the multiple hit storage units synchronously cache data in the read cache area corresponding to the IO interface, so that the main chip obtains the data read by the read instruction.

[0025] Optionally, each of the storage control modules manages a plurality of the storage cells on a same through-silicon-via hybrid bonding path in the multi-layer memory chip, and each of the storage cells includes a plurality of word lines corresponding to a plurality of row addresses and a plurality of bit lines corresponding to a plurality of column addresses;

[0026] The control management module parses the read instruction to obtain the address of the storage control module hit by the read instruction, the layer address of the memory chip of the hit layer, and the execution row address and column address in the hit storage unit.

[0027] Optionally, the memory chip is a DRAM chip, and the IO interface is an AXI interface, a CHI interface, or an AHB interface.

[0028] Optionally, the storage control module or the memory controller is further configured to, when performing error checking and correction on the read data, write the corrected data back to the corresponding storage unit if a data error is found and the error is corrected.

[0029] Optionally, the operation of retrieving the data corresponding to the read instruction from the read cache or the prefetch cache and returning it to the master chip is defined as a first operation; the operation of writing the corrected data back to the corresponding storage unit is defined as a second operation.

[0030] The first operation and the second operation are performed in parallel, or the first operation and the second operation are performed in series, with the first operation being performed before the second operation.

[0031] Optionally, the memory controller is arranged in the buffer chip, and the main chip, the buffer chip and the multi-layer memory chip are stacked together; or, the memory controller is arranged in the main chip, and the main chip and the multi-layer memory chip are stacked together.

[0032] Based on the same inventive concept, the present invention further provides a three-dimensional stacked memory, which includes stacked multi-layer memory chips and the memory controller according to the present invention.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. A read cache and a prefetch cache are set in the memory controller. Each time data is read, it is first determined whether the data to be read has been cached in the prefetch cache in advance. If not, while reading the corresponding data in the hit layer of the multi-layer memory chip (i.e., the data stored in the hit storage unit), the corresponding data in at least one non-hit layer of the multi-layer memory chip is also read (i.e., prefetched). Error checking and correction (ECC) is further performed on both the read and prefetched data. After the error checking and correction, the data in the hit layer is cached in the read cache, and the prefetched data is cached in the prefetch cache. The data cached in the read cache is retrieved and returned to the main chip. This realizes the function of prefetching data from the multi-layer memory chip, performing ECC error correction on the read and prefetched data first, and then caching them separately, thereby improving the data reliability and system performance of the memory.

[0035] 2. Each time data is read, if it is determined that the data to be read has been cached in the pre-fetch cache area in advance, the data can be directly fetched from the pre-fetch cache area instead of from the stacked multi-layer memory chip, thereby saving the time of switching the word lines of the stacked multi-layer memory chip, improving the access speed of the stacked multi-layer memory chip, and further improving the bandwidth of the stacked multi-layer memory chip.

[0036] 3. If a data storage error is detected through the error checking and correction (ECC) function, the error is corrected and the corrected data is written back to the stacked multi-layer memory chip, thereby improving the reliability of the stored data without affecting the performance of the stacked multi-layer memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0038] Figure 1 This is a schematic diagram of a DRAM system architecture.

[0039] Figure 2 FIG. 4 is a schematic diagram of the system architecture of a three-dimensional stacked memory and a memory controller according to a specific embodiment of the present invention.

[0040] Figure 3 It is a schematic diagram of the packaging structure of a three-dimensional stacked memory according to a specific embodiment of the present invention.

[0041] Figure 4 It is a schematic structural diagram of a storage unit in a three-dimensional stacked memory according to a specific embodiment of the present invention.

[0042] Figure 5 FIG. 1 is a schematic diagram of the architecture of an error checking and correction (ECC) control module in a memory controller according to a specific embodiment of the present invention.

[0043] Figure 6 FIG. 4 is a schematic diagram of an exemplary system architecture of a three-dimensional stacked memory and a memory controller according to a specific embodiment of the present invention.

[0044] Figure 7 yes Figure 6 FIG. 4 is a schematic diagram of the architecture of an error checking and correction (ECC) control module in a memory controller. DETAILED DESCRIPTION

[0045] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Please refer to Figure 2 and Figure 3 An embodiment of the present invention provides a memory controller 2, which is coupled between a main chip 1 and a stacked j+1 layer memory chip (wherein, Figure 3 DRAM chips are used as an example in the figure, and other types of memory chips can also be used in other examples) between 30~3j. Each layer of memory chips in the memory chips 30~3j includes multiple storage units with the same capacity, such as Figure 2 As shown in U0~Uk in , where j≥1 and j is an integer.

[0047] The memory controller 2 can perform interface conversion between the main chip 1 and the memory chips 30-3j, converting read, write, and refresh instructions issued by the main chip 1 into signals recognizable by the stacked j+1 layer memory chips 30-3j. It also completes address decoding, data format conversion (such as data bit width), and operation instruction transmission between the main chip 1 and the stacked j+1 layer memory chips 30-3j, thereby achieving the necessary control of refresh operations, read and write operations, and other access to the stacked j+1 layer memory chips 30-3j (including control of address signals, data signals, and various instruction signals), allowing the main chip 1 to access (or "use" or "operate") the storage resources (i.e., the corresponding storage cells) on the stacked j+1 layer memory chips 30-3j according to user needs.

[0048] It should be understood that the present invention does not impose any specific limitation on the specific location of the memory controller 2 .

[0049] For example, the memory controller 2 is integrated with the stacked j+1 layer memory chips 30-3j and is independent of the main chip 1 to form a memory system chip that can be accessed by the main chip 1. For another example, please refer to Figure 3 The memory controller 2 can also be integrated into a buffer chip (also called a base die or interface die) 20. The buffer chip 20 is arranged between the main chip 1 and the stacked j+1 layer memory chips 30~3j. The main chip 1, the buffer chip 20 and the j+1 layer memory chips 30~3j are stacked together and stacked on the substrate 4 through silicon via (TSV) and hybrid bonding (HB) technology. At this time, the main chip 1 can communicate with each layer of memory chips 30~3j through the buffer chip 20 and the through silicon via (TSV) hybrid bonding path.

[0050] For another example, the memory controller 2 may also be integrated inside the main chip 1. In this case, the main chip 1 may directly communicate with each layer of memory chips 30 to 3j through a through silicon via (TSV) hybrid bonding path (or other non-vertical stacking methods).

[0051] Among them, the main chip 1 may include any type of processing device with computing processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processing device can be configured to execute instructions or software (including code, operating system or application, etc.) that can be executed by one or more computers, firmware or a combination thereof.

[0052] Each memory chip 30-3j may be a DRAM or any other suitable type of memory die structure. The DRAM may be any suitable type, such as synchronous DRAM (SDRAM) or wide I / O DRAM. The stacked multiple layers of memory chips 30-3j form a memory stack, which may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), or the like.

[0053] Please refer to Figure 4 Each memory unit in each memory chip 30-3j has a memory array with a corresponding capacity. This memory array comprises multiple cells, defined by the intersection of multiple word lines WL (each word line can be considered a row) and multiple bit lines BL (each bit line can be considered a column). Each cell represents a memory address. Each cell (corresponding to a "storage address" or "instruction execution address") is defined by a word line WL and a bit line BL. The word line WL is addressed by the row address (RA) in the memory address, and the bit line BL is addressed by the column address (CA). The memory controller 2 manages read operations and other accesses to the stacked multi-layer memory chips 30-3j, from the cell level (a cell address is a 1-bit memory address) down to the memory unit level. A memory unit can be a memory block, a sector, a page, or any other suitable management unit above the cell level, such as a stacked multi-layer memory chip 30-3j. A page contains multiple bytes (the address range of which can be determined by multiple word lines and bit lines), a sector contains multiple pages, and a memory block contains multiple sectors.

[0054] It is worth noting that, in the memory chips 30 - 3j, the corresponding word lines of the memory cells (units) coupled to the same TSV hybrid bonding path and located on different layers of the memory chips can share the same execution row address, such as Figure 2In the memory unit U0 in the even-numbered layer memory chip managed by IP0, when a read instruction hits the memory unit (unit) U0 in the memory chip 30 managed by IP0, and the execution row address of the read instruction is WL_800, the U0 in each even-numbered layer memory chip such as the memory chip 32 managed by IP0 all has a corresponding word line WL that shares the execution row address WL_800, that is, the U0 in each layer memory chip managed by IP0 has a word line WL that is hit by the execution row address WL_800.

[0055] In this embodiment, the memory controller 2 has a data cache area 21a, which includes a read cache area 210 and a pre-fetch cache area 211. The memory controller 2 is configured as follows:

[0056] Receive and parse the corresponding read instruction (read), and determine whether the data read by the read instruction has been cached in the corresponding pre-fetch buffer area 211 in advance,

[0057] If not, perform the following steps:

[0058] Opening the word lines WL in the memory chips 30-3j of different layers that share the execution row address of the read instruction, that is, opening the word line WL coupled to the hit memory cell in the hit layer of the read instruction, and simultaneously opening the word line WL coupled to the non-hit memory cell in the non-hit layer of the read instruction, wherein the word lines WL coupled to the non-hit memory cell and the hit memory cell share the execution row address of the read instruction;

[0059] After the word lines WL are turned on, data of the hit memory cell and data of the non-hit memory cell (which is coupled to the turned-on word line) are read;

[0060] Perform error checking and correction (ECC) on the read data;

[0061] Cache the error-checked and corrected data corresponding to the hit storage unit into the corresponding read cache area 210, and cache the error-checked and corrected data corresponding to the non-hit storage unit into the corresponding prefetch cache area 211;

[0062] The data cached in the read cache area 210 is retrieved and returned to the master chip 1 .

[0063] Optionally, the memory controller 2 determines a hit layer in the j+1 layer memory chip 30~3j based on the chip select address (CS, also called "chip select signal") parsed from the read instruction, and the hit storage unit belongs to the hit layer, and the non-hit storage unit belongs to other layers outside the hit layer in the memory chips 30~3j, that is, the non-hit storage unit and the hit storage unit are respectively located in memory chips of different layers in the memory chips 30~3j. When the length of data read by the read instruction exceeds the length of data stored in one storage unit, the hit storage unit can be a plurality of storage units continuously distributed in the same layer of memory chips (i.e., the hit layer), and the number of non-hit storage units whose data is read simultaneously (i.e., the data is pre-fetched) in each layer is the same as the number of hit storage units whose data is read in the hit layer. When parsing the read instruction, the memory controller 2 can parse out which storage control module IPs the read instruction specifically hits, which layer of memory chips managed by these hit storage control module IPs the read instruction specifically hits or chip selects (i.e., the hit layer), which storage unit or units in the hit layer the read instruction specifically hits (i.e., the hit storage unit, and this information can also be obtained from the information of which storage control module IPs are hit), and which row address (i.e., the execution row address, which is also the word line in the hit storage unit that the read instruction specifically hits) and which column addresses (i.e., which bit lines in the hit storage unit that the read instruction specifically hits) in the hit storage unit.

[0064] It should be understood that a storage unit has several word lines WL, for example, 16*1024 WLs, and the specific word line WL hit is obtained by the memory controller 2 decoding the address of the read instruction to be executed, that is, the execution row address of the read instruction decoded by the memory controller 2 (which is also the row address of the hit storage unit) is what (for example, WL_800), then the memory controller 2 will send the execution row address to the hit storage control module IP, and the word lines opened in the storage units managed by the hit storage control module IP are all addressed by the execution address, thereby reading the data of the hit storage unit in the hit layer of the read instruction, and also pre-fetching the data of the non-hit storage units whose word lines in these non-hit layers are opened by opening the chip select signal.

[0065] Optionally, if the memory controller 2 determines that the data read by the read instruction has been pre-cached in the pre-fetch buffer 211, the memory controller 2 retrieves the data corresponding to the read instruction from the pre-fetch buffer 211 and returns it to the master chip 1. In this case, the master chip 1 does not need to retrieve data from the stacked j+1 layer memory chips 30-3j, but instead directly retrieves data from the pre-fetch buffer 211. This saves the time of switching the word lines of the stacked j+1 layer memory chips 30-3j, improves the access speed of the stacked j+1 layer memory chips, and further improves the bandwidth of the stacked j+1 layer memory chips.

[0066] Optionally, the memory controller 2 is further configured to, when performing error checking and correction on the read data, if errors are found in the stored data and the errors are corrected, write the corrected data back to the corresponding storage unit.

[0067] The memory controller 2 has the following two operations when executing the read instruction: (1) a first operation: taking out the data corresponding to the read instruction from the read cache 210 or the pre-fetch cache 211 and returning it to the main chip 1; (2) the operation of writing the ECC-corrected data back to the corresponding storage unit is defined as a second operation; wherein, the first operation and the second operation can be performed in parallel, thereby not wasting additional time; or, the first operation and the second operation are performed in series, and the first operation is executed before the second operation, thereby adding a read-after-write time, but this time will not be very long and will not have a significant impact on system performance.

[0068] Please continue to refer to Figure 2 The memory controller 2 of this embodiment includes m+1 IO interfaces IO0~IOm, a control management module 21 and several storage control module IPs, where m is an integer and m≥0 (i.e., the memory controller 2 includes at least one IO interface). Preferably, m≥1. In this case, the m+1 IO interfaces are all parallel communication protocol interfaces that support multiple IOs.

[0069] The data cache 21a is provided in the control management module 21 and is arranged and coupled to each IO interface IO0-IOm in a one-to-one correspondence. This means that the number of data caches 21a in the control management module 21 is also m+1. Each data cache 21a is coupled to n+1 storage control modules IP0-IPn. Thus, each of the n+1 storage control modules IP0-IPn corresponds to one IO interface. This means that when the bit width of the data read from the hit layer by a storage control module IP0 is x, the bit width of the data returned by the IO interface to the main chip 1 is equal to (n+1)*x, where n is an integer and n≥1.

[0070] Please combine Figure 2 and Figure 5Each storage control module IP0-IPn is coupled to the control management module 21 and the p+1 layer of memory chips in the memory chips 30-3j, and is used to manage k+1 memory cells U0-Uk in each layer of memory chips to which it is coupled, where p, k, and j are all integers and k ≥ 1, p ≥ 1, and j ≥ 1. That is, each storage control module manages (p+1)*(k+1) memory cells. Specifically, in the p+1 layer of memory chips (e.g., memory chips in an even layer or an odd layer) managed by each storage control module IP0-IPn, each memory cell U0 is coupled to the same TSV hybrid bonding path, each memory cell U1 is coupled to the same TSV hybrid bonding path, and so on. Consequently, each memory cell Uk is coupled to the same TSV hybrid bonding path. Thus, the memory cells on the same TSV hybrid bonding path can share corresponding execution row addresses.

[0071] Each storage control module IP0~IPn is also used to open the word line WL of the execution row address of the shared read instruction in the memory chip of the p+1 layer to read the data of the hit storage unit in the hit layer of the read instruction, and simultaneously read (or "pre-fetch") the data of the non-hit storage unit corresponding to the execution row address of the read instruction in the non-hit layer of the p layer, and perform error checking and correction (ECC) on the read data, and cache the error-checked and corrected data corresponding to the hit storage unit in the corresponding read cache area 210, and cache the error-checked and corrected data corresponding to the non-hit storage unit in the corresponding pre-fetch cache area 211.

[0072] Alternatively, refer to Figure 2 and Figure 5Each storage control module IP includes an error checking and correction control module (i.e., ECC control module) 220. The error checking and correction control module 220 includes p+1 error checking and correction control units ECC_ctrl0 to ECC_ctrlp. Each error checking and correction control unit ECC_ctrl0 to ECC_ctrlp is configured and coupled to a p+1-layer memory chip managed by the storage control module IP. Each error checking and correction control unit ECC_ctrl0 to ECC_ctrlp is used to perform error checking and correction on data read from the memory chip to which it is coupled. For example, the storage control module IP0 manages the corresponding storage units in the even layers of the memory chips 30~3j, the error checking and correction control unit ECC_ctrl0 is coupled to the memory chip 30 (also referred to as the "first layer memory chip"), and is used to perform error checking and correction on the data read from the memory chip 30, the error checking and correction control unit ECC_ctrl1 is coupled to the memory chip 32 (also referred to as the "third layer memory chip"), and is used to perform error checking and correction on the data read from the memory chip 32, and so on. The error checking and correction control unit ECC_ctrlp is coupled to the memory chip 3(2*p) (also referred to as the "2p+1th layer memory chip"), and is used to perform error checking and correction on the data read from the memory chip, where when j is an even number, 2p=j, and when j is an odd number, 2p=j-1.

[0073] Further optionally, after each error checking and correction control unit ECC_ctrl0 to ECC_ctrlp detects a data error and performs error correction on the erroneous data, it writes the corrected data back to the corresponding storage unit.

[0074] The control management module 21 is used to parse the read instruction to obtain the hit layer of the read instruction (i.e., the memory chip that is hit or chip selected), the hit storage unit in the hit layer, and the execution row address of the hit storage unit, and determine whether the data read by the read instruction has been cached in advance in the corresponding pre-fetch cache area 211.

[0075] In one example, the control management module 21 includes, in addition to m+1 data caches 21a, an address decoder 213 and a discriminator 214. The address decoder 213 is used to parse a read instruction to obtain the address of the storage control module IP targeted by the read instruction (which may further include the number x of memory cells targeted), the layer address of the memory chip targeted (i.e., the targeted layer), and the row address (i.e., the execution row address of the targeted memory cell) and column address. The discriminator 214 is used to determine, based on the parsing result of the address decoder 213, whether the data read by the read instruction has been pre-cached in the corresponding prefetch cache 211. It is worth noting that, in some embodiments, the address decoding logic of the address decoder 213 of the present invention for the read / write instruction address can be designed so that the logical addresses corresponding to the same row addresses of adjacent storage layers are continuous, that is, the address decoder 213 can be designed to map the continuous logical addresses sent by the main chip 1 to the same WL of the adjacent layer (for example, after storing in WL_800 of the first-layer memory chip 30, it is then stored in WL_800 of the second-layer memory chip 31). In this way, the probability of the data pre-fetched and error-corrected from the non-hit layer (that is, the data in the pre-fetch cache area 211) of the present invention being hit by subsequent read instructions is increased.

[0076] Each IO interface IO0-IOm is used to communicate with the main chip 1 and the control and management module 21, implement interface conversion between the main chip 1 and the control and management module 21, receive instructions from the main chip 1 and data to be written to the memory chips 30-3j, and transmit the read data back to the main chip 1. IO interfaces IO0-IOm can be any suitable parallel communication protocol interface that supports multiple IOs, such as an AXI (Advanced eXtensible Interface) interface. The AXI interface is an on-chip bus interface designed for high-performance, high-bandwidth, and low-latency master-slave architectures. Its address, instruction, and data phases are separated, supporting unaligned data transmission. In burst transmissions, only the first address is required, with separate read and write data channels. It supports transmission access of a large number of outstanding pending instructions (e.g., the number of outstanding transactions such as read and write instructions) and out-of-order access, making timing closure easier and suitable for high-speed memory access. It is worth noting that although the AXI protocol is shown in the drawings of the specification, the present invention is not limited to this. The IO interfaces IO0~IOm can also adopt any other suitable high-bandwidth interface protocol, such as the AHB (Advanced High-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol.

[0077] In this embodiment, each IO interface IO0-IOm is configured to receive a read instruction from the master chip 1 and, based on the determination result of the control management module 21, retrieve the data corresponding to the read instruction from the coupled read buffer 210 or prefetch buffer 211 and return it to the master chip 1. For example, when the control management module 21 determines that the data to be read by the read instruction has been pre-cached in the corresponding prefetch buffer 211, the corresponding IO interface retrieves the corresponding data from the prefetch buffer 211 and transmits it to the master chip 1. When the control management module 21 determines that the data to be read by the read instruction has not been pre-cached in the corresponding prefetch buffer 211, the corresponding IO interface waits for the corresponding storage control module IP to read the data from the hit storage unit in the hit layer (i.e., the hit memory chip) of the read instruction, performs ECC error correction on the read data, and caches it in the corresponding read buffer 210. Then, the corresponding IO interface retrieves the corresponding data from the read buffer 210 and transmits it to the master chip 1.

[0078] Among them, when a read instruction needs to read data in multiple storage units of the same layer (i.e., the hit layer), that is, when the data read by a read instruction corresponds to data continuously stored in multiple hit storage units (hit unit) in the same layer (i.e., the hit layer), the multiple storage control modules IP that manage the multiple hit storage units (hit unit) synchronously cache the data in the read cache area 210 corresponding to the corresponding IO interface, so that the IO interface can retrieve the data read by the read instruction from the read cache area 210 at one time, so that the main chip 1 obtains the data read by the read instruction.

[0079] That is, the data bit width of each read instruction is equal to the bit width of the data returned by an IO interface to the master chip 1, and the data bit width of each IO interface is equal to the sum of the data bit widths cached by its corresponding n+1 storage control modules IP in the read cache 210 corresponding to the IO interface according to the read instruction. Specifically, when a storage control module IP manages p+1 layers of memory chips and k+1 memory cells U0-Uk in each layer of memory chips, when an IO interface receives a read instruction, the read cache 210 corresponding to the IO interface can cache the data of the (n+1)*(k+1) memory cells hit by the read instruction (i.e., the hit memory cells) (this data will undergo ECC error correction before being cached), and the prefetch cache 211 corresponding to the IO interface can cache the data of the (n+1)*(k+1)*p memory cells missed by the read instruction (i.e., the non-hit memory cells) (this data will also undergo ECC error correction before being cached). For example, when n+1=4, k+1=2, and p+1=4, when an IO interface receives a read instruction, the read cache 210 corresponding to the IO interface will cache 4*2=8 units of data hit by the read instruction (that is, the data that needs to be read by the read instruction is cached, and the cached data is read from one word line WL of each of the 8 units and has been ECC-corrected), and the prefetch cache 211 corresponding to the IO interface will cache 4*2*3=24 units of data that are not hit by the read instruction (that is, the data prefetched according to the read instruction is cached, and the cached data is read from one word line WL of each of the 24 units and has been ECC-corrected), and the data returned by the IO interface to the main chip 1 is the data of the 8 units cached in the read cache 210 (that is, the data read from the 8 hit storage units of the read instruction and has been ECC-corrected).

[0080] It should be understood that, in addition to the above-mentioned IO interface, control management module 21 and storage control module IP, the memory controller 2 of this embodiment may also have other control logic modules (not shown) to implement other functions. For example, the other control logic modules in the memory controller 2 may include any required circuits such as clock and frequency control circuits (such as phase-locked loops (PLLs)), circuits for managing power consumption and temperature, first-in-first-out queue registers (FIFOs), etc. These circuits are not the focus of the present invention and are therefore not described in detail here.

[0081] In addition, the division and internal composition of the various modules such as the IO interfaces IO0~IOm, the control management module 21, and the storage control module IP in the memory controller 2 of this embodiment are schematic, and are mainly a logical functional division. In actual implementation, other division methods may be used. The various functional modules in the embodiments of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into a physical module. The above-mentioned integrated modules can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., an SSD).

[0082] Based on the same invention concept, please refer to Figures 2 to 5 An embodiment of the present invention further provides a three-dimensional stacked memory, which includes stacked j+1 layers of memory chips 30-3j and the memory controller 2 as described in this embodiment.

[0083] In order to better understand the technical solutions of the memory controller 2 and the three-dimensional stacked memory of the present invention, a detailed description is given by taking j=7, p=3, m=3, k=2, n=4 and each layer of memory chips being DRAM as an example.

[0084] Please refer to Figure 6 and Figure 7The memory controller 2 of this example manages 8 layers of memory chips 30~37, and is internally provided with 4 parallel communication IO interfaces IO0~IO3, 4 data cache areas 21a and 16 storage control modules. Each data cache area 21a is coupled to the corresponding 4 storage control modules IP0~IP3. Each storage control module IP manages 4 layers of memory chips and manages two storage units U0 and U1 in each layer of memory chips. One read instruction can access 8 consecutively distributed storage units in the same layer of memory chips through one IO interface and the control management module 21 (that is, one read instruction will hit the data of 8 hit storage units in the same layer of memory chips, and the 8 storage units are managed by the corresponding 4 storage control modules IP0~IP3). Therefore, the ECC control module 220 inside each storage control module IP includes 4 error checking and correction control units ECC_ctrl0~ECC_ctrl3. Figure 6 Taking the storage control module IP0 of the first data cache area as an example, it manages memory chip 30, memory chip 32, memory chip 34, and memory chip 36, and the error checking and correction control unit ECC_ctrl0 is used to perform error checking and correction on the data read from memory chip 30, the error checking and correction control unit ECC_ctrl1 is used to perform error checking and correction on the data read from memory chip 32, the error checking and correction control unit ECC_ctrl2 is used to perform error checking and correction on the data read from memory chip 34, and the error checking and correction control unit ECC_ctrl3 is used to perform error checking and correction on the data read from memory chip 36.

[0085] In this example, the data that can be read by a read instruction is data continuously stored in one or more (for example, up to 8) storage cells of the same layer of memory chip, for example, the bit width of each storage cell is 256 bits.

[0086] From the perspective of the storage control module IP, a single storage control module IP manages four layers of memory chips (DRAM wafers and DRAM dies). A read instruction will only hit one layer of memory chips, hitting the corresponding word lines (WL) in two memory cells. The remaining three layers of memory chips are in a miss state. For example, if the execution row address of a read instruction is WL_800, the hit storage control module IP includes IP0. Memory chip 30 managed by IP0 is the hit layer for the read instruction and is responsible for fetching the data read by the read instruction. Memory chips 32, 34, and 36 managed by IP0 are the miss layers for the read instruction and are responsible for providing the corresponding prefetched data. Memory chips 30, 32, 34, and 36 managed by IP0 concurrently open the word lines (WL) corresponding to the execution address WL_800. Data from the two memory cells U0 and U1 in memory chip 30 corresponding to WL_800 and hit by the read instruction (i.e., the two hit memory cells managed by IP0, that is, the number x=2 memory cells managed by IP0 hit by the read instruction) is read, subjected to ECC error correction (i.e., error checking and correction by ECC_ctrl0 in IP0), and then cached in the corresponding read cache 210. Data from the six memory cells U0 and U1 corresponding to WL_800 in memory chips 32, 34, and 36 managed by IP0 is read (the column address range from which these six memory cells managed by IP0 are read is the same as the column address range from which the two hit memory cells U0 and U1 in memory chip 30 are read), subjected to ECC error correction by ECC_ctrl1 through ECC_ctrl3 in IP0, and then cached in the corresponding prefetch cache 211.

[0087] From the perspective of the control management module 21 (or memory controller 2), eight consecutive memory cells on the same memory chip layer may simultaneously open one word line WL to cooperate with data output. That is, the reading range of this read instruction can be up to eight memory cells on the same memory chip layer corresponding to the four storage control modules IP0-IP3 in a data cache area, and each memory cell only opens one word line WL to output data.

[0088] In this example, when a read instruction is received through IO interface IO0 and the 8-layer memory chip is read, the data of the hit layer is read and the data of the non-hit layer is pre-fetched. ECC error correction, caching, and error correction write-back are performed on both the read data and the pre-fetched data. The specific steps are as follows:

[0089] (1) Decode the read instruction to obtain the address of the hit memory control module IP (i.e., the address of IP0), the layer address of the memory chip (assuming it is memory chip 30), the hit memory unit (hit unit) and its execution line address WLcounter (also referred to as "WL number"; assuming WL number = WL_800). In a further embodiment, the decoding further obtains the number x of hit memory units (assuming Figure 6 Among the eight storage units of the same layer memory chip 30 corresponding to the first data cache area 21a, the number x of hit storage units can be at least 1 and at most 8).

[0090] (2) Determine whether the data to be read has been cached in advance Figure 6 If yes, then the data is taken from the pre-fetch buffer area 211 of the first data buffer area 21a and sent to the IO interface IO0, and then returned to the main chip 1, thereby improving the access speed; if no, execute the following step (3).

[0091] (3) One word line WL of each of the eight memory cells of memory chip 30, memory chip 32, memory chip 34, and memory chip 36 is opened. These opened word lines WL share the execution row address WL_800 (that is, they are all addressed by the execution row address WL_800). Therefore, from the perspective of IO interface IO0, 4*8=32 word lines WL are opened without wasting additional time.

[0092] (4) The 32 word lines WL that share the execution row address WL_800 output data simultaneously (i.e., 4*x storage cells output data simultaneously) without wasting any additional time.

[0093] (5) The data of the memory chip 30 is sent to Figure 6 The first data buffer 21a is coupled to the ECC_ctrl0 in the storage control module IP0~IP3 for error correction; the data of the memory chip 32 is sent to the corresponding Figure 6 The first data buffer 21a is coupled to the ECC_ctrl1 in the storage control module IP0~IP3 for error correction; the data of the memory chip 34 is sent to the corresponding Figure 6 The first data buffer 21a is coupled to the ECC_ctrl2 in the storage control module IP0~IP3 for error correction; the data of the memory chip 36 is sent to the corresponding Figure 6The ECC_ctrl3 in the storage control modules IP0-IP3 coupled to the first data buffer 21a performs error correction. The storage control modules IP0-IP3 simultaneously perform ECC error correction on the data read from the four-layer memory chips 30, 32, 34, and 36 without wasting extra time.

[0094] (6) The ECC-corrected data corresponding to the memory chip 30 is cached to the storage control module IP0~IP3. Figure 6 The data after ECC error correction corresponding to the memory chips 32, 34, and 36 are all cached to the storage control module IP0~IP3. Figure 6 The first data buffer 21a of the pre-fetch buffer 211 is stored in the memory control module. The four paths IP0 to IP3 send data to the memory control module at the same time. Figure 6 The first data buffer area 21a is read without wasting extra time.

[0095] (7) Figure 6 The data cached in the read cache area 210 of the first data cache area 21a is sent to the IO interface IO0, and then sent to the main chip 1 through the IO interface IO0.

[0096] (8) If data errors are found in the data corresponding to memory chips 32, 34, and 36 during ECC error correction, they are written back to the storage unit of the corresponding memory chip after ECC error correction. Steps (7) and (8) can be executed in parallel. If they are executed in parallel, no additional time is consumed. If steps (7) and (8) are executed serially, an additional read-after-write time is added, but this time is not very long and will not affect performance.

[0097] In summary, the memory controller and three-dimensional stacked memory of the present invention set a read cache area and a pre-fetch cache area in the memory controller. Each time data is read, it is first determined whether the data to be read has been cached in the pre-fetch cache area in advance. If not, while reading the corresponding data in the hit layer in the multi-layer memory chip (that is, the data stored in the hit storage unit), the corresponding data in at least one non-hit layer in the multi-layer memory chip is also read (that is, pre-fetched), and error checking and correction (ECC) is further performed on the read and pre-fetched data. After the error checking and correction, the data in the hit layer is cached in the read cache area, the pre-fetched data is cached in the pre-fetch cache area, and the data cached in the read cache area this time is taken out and returned to the main chip, thereby realizing the function of pre-fetching data of the multi-layer memory chip, performing ECC error correction on the read and pre-fetched data first, and then caching them separately, thereby improving the data reliability and system performance of the memory.

[0098] Optionally, each time data is read, if it is determined that the data to be read has been cached in advance in a pre-fetch cache area, the data may be directly fetched from the pre-fetch cache area instead of from the stacked multi-layer memory chip, thereby saving the time of switching the word lines of the stacked multi-layer memory chip, improving the access speed of the stacked multi-layer memory chip, and further improving the bandwidth of the stacked multi-layer memory chip.

[0099] Furthermore, if a data storage error is detected through the Error Checking and Correction (ECC) function, the error is corrected and the corrected data is written back to the stacked multi-layer memory chips. This improves the reliability of the stored data without affecting the performance of the stacked multi-layer memory chips.

[0100] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A memory controller coupled between a main chip and a stack of multiple layers of memory chips, each layer of the memory chips comprising a plurality of memory cells, characterized in that: The memory controller has a data cache area, the data cache area includes a read cache area and a prefetch cache area, and the memory controller is configured to: Receive and analyze the corresponding read instruction, and determine whether the data read by the read instruction has been cached in the pre-fetch cache area in advance, If not, perform the following steps: Determining a hit layer in the multi-layer memory chip according to the chip select address of the read instruction, opening word lines in the memory chips of different layers that share the execution row address of the read instruction, so as to read data of corresponding hit storage cells and non-hit storage cells in the multi-layer memory chip, wherein the hit storage cells belong to the hit layer, and the non-hit storage cells belong to at least one non-hit layer other than the hit layer in the multi-layer memory chip; Perform error checking and correction on the read data; caching the error-checked and corrected data corresponding to the hit storage unit into the read cache area, and caching the error-checked and corrected data corresponding to the non-hit storage unit into the prefetch cache area; The data cached in the read cache area is retrieved and returned to the master chip.

2. The memory controller according to claim 1, wherein The memory controller is configured to: if it is determined that the data read by the read instruction has been cached in the pre-fetch cache area in advance, fetch the data corresponding to the read instruction from the pre-fetch cache area and return it to the master chip.

3. The memory controller according to claim 2, wherein: The memory controller further includes at least one IO interface, a control management module, and a plurality of storage control modules. The data cache is provided in the control management module and is correspondingly provided and coupled to the IO interface. Each of the storage control modules is coupled to the control management module and the multi-layer memory chip. The control management module is used to parse the read instruction to obtain the hit layer, the hit storage unit in the hit layer, and the execution row address of the hit storage unit, and determine whether the data read by the read instruction has been cached in the prefetch cache area in advance; The storage control module is used to open the word lines sharing the execution row address in the memory chips of different layers including the hit layer, so as to read the data of the hit storage cells and the data of the non-hit storage cells, perform error checking and correction on the read data, and cache the error-checked and corrected data corresponding to the hit storage cells in the corresponding read cache area, and cache the error-checked and corrected data corresponding to the non-hit storage cells in the corresponding prefetch cache area; The IO interface is used to receive the read instruction, and according to the judgment result of the control management module, fetch the data corresponding to the read instruction from the corresponding read buffer area or the pre-fetch buffer area, and return it to the main chip.

4. The memory controller according to claim 3, wherein: The control management module also includes: an address decoder, configured to parse the read instruction to obtain the hit layer of the read instruction, the hit storage unit in the hit layer, and the execution row address in the hit storage unit; A discriminator is used to determine whether the data read by the read instruction has been cached in advance in the prefetch cache area according to the parsing result of the address decoder.

5. The memory controller according to claim 3, wherein: The storage control module includes an error checking and correction control module, and the error checking and correction control module includes multiple error checking and correction control units. Each of the error checking and correction control units is arranged and coupled one-to-one with the memory chips of each layer managed by the storage control module. The error checking and correction control unit is used to perform error checking and correction on the data read from the memory chip to which it is coupled.

6. The memory controller according to claim 3, wherein: The data read by the read instruction corresponds to the data continuously stored in the multiple hit storage units in the hit layer. The multiple storage control modules that manage the multiple hit storage units synchronously cache the data in the read cache area corresponding to the IO interface, so that the main chip obtains the data read by the read instruction.

7. The memory controller according to claim 3, wherein: Each of the storage control modules manages a plurality of the storage cells on the same through-silicon-via hybrid bonding path in the multi-layer memory chip, and each of the storage cells includes a plurality of word lines corresponding to a plurality of row addresses and a plurality of bit lines corresponding to a plurality of column addresses; The control management module parses the read instruction to obtain the address of the storage control module hit by the read instruction, the layer address of the memory chip of the hit layer, and the execution row address and column address in the hit storage unit.

8. The memory controller according to claim 3, wherein: The memory chip is a DRAM chip, and the IO interface is an AXI interface, a CHI interface, or an AHB interface.

9. The memory controller according to claim 3, wherein: The storage control module or the memory controller is further configured to perform error checking and correction on the read data, and if a data error is found and the error is corrected, write the corrected data back to the corresponding storage unit.

10. The memory controller according to claim 9, wherein: The operation of taking out the data corresponding to the read instruction from the read buffer or the prefetch buffer and returning it to the master chip is defined as the first operation; the operation of writing the corrected data back to the corresponding storage unit is defined as the second operation. The first operation and the second operation are performed in parallel, or the first operation and the second operation are performed in series, with the first operation being performed before the second operation.

11. The memory controller according to any one of claims 1 to 10, wherein: The memory controller is arranged in a buffer chip, and the buffer chip and the multi-layer memory chip are stacked together; or, the memory controller is arranged in the main chip, and the main chip and the multi-layer memory chip are stacked together.

12. A three-dimensional stacked memory, characterized in that: The invention comprises stacked multi-layer memory chips and the memory controller according to any one of claims 1 to 11.

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