Double-frequency direct-drive inductively coupled plasma source

Abstract

A direct drive system for providing RF power to a substrate processing system includes a direct drive housing including: a first direct drive circuit located in the direct drive housing and operating at a first frequency; and the first connector is connected with the first direct drive circuit. The junction box is disposed adjacent to the direct drive housing and includes: a first capacitive circuit connected to the first direct drive circuit; the second connector is positioned on one side of the junction box, is connected with one terminal of the first capacitive circuit and is matched with the first connector of the direct-drive shell; third and fourth connectors connected to the other terminal of the first capacitive circuit; and a coil housing disposed adjacent to the junction box, the coil housing including a first coil and a second coil; and a fifth connector and a sixth connector which are matched with the third connector and the fourth connector of the junction box.

Description

This application is a divisional application of the invention patent application with application number 202080048328.4, application date April 24, 2020, applicant is Rum Research Company, and the invention name is "Dual-frequency direct-drive inductively coupled plasma source". CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application No. 62 / 840,554, filed on April 30, 2019. The entire disclosure of the above-referenced application is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to substrate processing systems, and more particularly to a dual-frequency, direct-drive inductively coupled plasma (ICP) source for substrate processing systems. Background Art

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0004] Substrate processing systems are typically used to etch thin films on substrates, such as semiconductor wafers. Etching typically involves wet chemical etching or dry etching. Dry etching can be performed using plasma generated by inductively coupled plasma (ICP) or capacitively coupled plasma (CCP). ICP can be generated by an RF drive system and a coil arranged outside the processing chamber adjacent to a dielectric window. A process gas flowing within the processing chamber is ignited to generate plasma. Traditionally, the output impedance of the RF drive system should match the impedance of the coil and the processing chamber. When an impedance mismatch occurs, power is reflected, resulting in inefficiency and potentially causing other problems. Summary of the Invention

[0005] A method for providing RF power to a plasma processing system includes providing a junction box comprising: a first connector configured to connect to a first direct drive circuit; a plurality of second connectors configured to connect to a coil housing; and a first capacitive circuit connected between the first connector and the plurality of second connectors. The method also includes providing a coil housing comprising: a plurality of third connectors connected to the plurality of second connectors of the junction box; and a first coil and a second coil connected to the plurality of third connectors of the coil housing. The method includes positioning the junction box and the coil housing adjacent to a window of a processing chamber. The method also includes calibrating the capacitance of the first capacitive circuit.

[0006] In other features, the calibration is performed without energizing a plasma in the process chamber, the calibration is performed at atmospheric pressure, and the calibration is performed to provide series resonance of the first direct drive circuit at a first frequency.

[0007] In other features, the method further includes positioning a direct drive housing including the first direct drive circuit adjacent to the junction box after calibrating the capacitance value of the first capacitive circuit.

[0008] In other features, the junction box further includes: a fourth connector configured to connect to a second direct drive circuit; a plurality of fifth connectors configured to connect to the coil housing; and a second capacitive circuit connected between the fourth connector and the plurality of fifth connectors.

[0009] In other features, the coil housing includes: a plurality of sixth connectors connected to the plurality of fifth connectors of the junction box; and a third coil and a fourth coil connected to the plurality of sixth connectors of the coil housing.

[0010] In other features, the method includes calibrating a capacitance value of the second capacitive circuit.The third plurality of connectors of the coil housing are movable relative to the second plurality of connectors of the terminal block.

[0011] In other features, the first coil and the second coil are wound around each other in opposite directions; the third coil and the fourth coil are wound around each other in opposite directions; and the first coil and the second coil are arranged inside or outside the third coil and the fourth coil.

[0012] In other features, the first direct drive circuit includes: a clock generator that generates a clock signal at the first frequency; a gate driver that is connected to the output of the clock generator; a DC power supply; and a half-bridge that connects the gate driver and the DC power supply.

[0013] A direct drive system for providing RF power to a substrate processing system includes a direct drive housing, the direct drive housing including: a first direct drive circuit located in the direct drive housing and operating at a first frequency; and a first connector connected to the first direct drive circuit. A junction box is arranged adjacent to the direct drive housing and includes: a first capacitive circuit connected to the first direct drive circuit; a second connector located on a side of the junction box, connected to one terminal of the first capacitive circuit, and mated with the first connector of the direct drive housing; third and fourth connectors connected to the other terminal of the first capacitive circuit; and a coil housing arranged adjacent to the junction box, including a first coil and a second coil; and fifth and sixth connectors mated with the third and fourth connectors of the junction box.

[0014] In other features, the fifth and sixth connectors of the coil housing and the third and fourth connectors of the terminal box enable the first and second coils to be movable. The first direct drive circuit includes: a clock generator that generates a clock signal at the first frequency; a gate driver connected to an output of the clock generator; a DC power supply; and a half-bridge that connects the gate driver and the DC power supply.

[0015] In other features, the first and second coils are wound around each other in opposite directions.

[0016] In other features, the direct drive housing further includes: a second direct drive circuit located in the direct drive housing and operating at a second frequency; and a seventh connector connected to the second direct drive circuit.

[0017] In other features, the junction box also includes: a second capacitor circuit, which is connected to the second direct drive circuit; an eighth connector, which is located on one side of the junction box, connected to one terminal of the second capacitor circuit, and cooperates with the seventh connector of the direct drive housing; and ninth and tenth connectors, which are connected to the other terminal of the second capacitor circuit.

[0018] In other features, the coil housing further includes: third and fourth coils; and eleventh and twelfth connectors that mate with the ninth and tenth connectors of the junction box.

[0019] In other features, the first coil and the second coil are wound around each other in opposite directions. The third coil and the fourth coil are wound around each other in opposite directions. The first coil and the second coil are arranged inside or outside the third coil and the fourth coil.

[0020] In other features, first terminals of the first coil and the second coil are connected to the first capacitive circuit, first terminals of the third coil and the fourth coil are connected to the second capacitive circuit, and second terminals of the first, second, third, and fourth coils are connected to a reference potential.

[0021] In other features, the first terminals of the first, second, third, and fourth coils are connected to the fifth, sixth, eleventh, and twelfth connectors of the coil housing, respectively. The coil housing further includes thirteenth, fourteenth, fifteenth, and sixteenth connectors connected to the second terminals of the first, second, third, and fourth coils, respectively. The junction box further includes seventeenth, eighteenth, nineteenth, and twentieth connectors connected to a reference potential and mating with the thirteenth, fourteenth, fifteenth, and sixteenth connectors of the coil housing, respectively.

[0022] In other features, the junction box further includes a third capacitor circuit. The first terminals of the first coil and the second coil are connected to the first capacitor circuit. The first terminals of the third coil and the fourth coil are connected to the second capacitor circuit. The second terminals of the first coil and the second coil are connected to a reference potential. The second terminals of the third coil and the fourth coil are connected to the third capacitor circuit.

[0023] In other features, the junction box also includes a third capacitor circuit. The first terminals of the first, second, third, and fourth coils are connected to the fifth, sixth, eleventh, and twelfth connectors of the coil housing, respectively. The coil housing also includes thirteenth, fourteenth, fifteenth, and sixteenth connectors connected to the second terminals of the first, second, third, and fourth coils, respectively. The junction box also includes seventeenth and eighteenth connectors connected to a reference potential, and also includes nineteenth and twentieth connectors connected to the third capacitor circuit. The seventeenth, eighteenth, nineteenth, and twentieth connectors of the junction box mate with the thirteenth, fourteenth, fifteenth, and sixteenth connectors of the coil housing, respectively.

[0024] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings.The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0026] Figure 1 is a functional block diagram of an example of a substrate processing system of the present disclosure;

[0027] Figure 2 is a functional block diagram and electrical schematic diagram of an example of a direct drive system for generating ICP according to the present disclosure;

[0028] Figure 3 is a functional block diagram and electrical schematic diagram of an example of a direct drive circuit in a direct drive system according to the present disclosure;

[0029] Figure 4 is a functional block diagram of an example of a direct drive system during operation according to the present disclosure;

[0030] Figure 5 is a functional block diagram of an example of a direct drive system during calibration according to the present disclosure;

[0031] Figure 6 is a perspective view of an example of a coil assembly, a female connector, and a frame according to the present disclosure;

[0032] Figure 7is a perspective view of an example of a terminal block connecting a direct drive circuit to a coil assembly according to the present disclosure;

[0033] Figure 8 is a perspective view of an example of a female connector that enables relative movement between the male connector and the female connector according to the present disclosure; and

[0034] Figure 9 is a functional block diagram and electrical schematic of an example of a direct drive system for generating ICP according to the present disclosure.

[0035] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0036] Traditionally, the output impedance of an RF drive system should match the impedance of the coil and processing chamber. When an impedance mismatch occurs, power is reflected, resulting in inefficiencies and potentially other problems. Using Direct-Drive™ technology from Lam Research Corporation, there is no need to match the output impedance of the drive circuit to the coil / chamber impedance. Additional information related to direct-drive circuits can be found in commonly assigned U.S. patent application Ser. No. 16 / 007,481, entitled “DirectDrive RF Circuit for Substrate Processing Systems,” filed on June 13, 2018, which is incorporated herein by reference in its entirety.

[0037] Now refer to Figure 1 , shows an example of a substrate processing system 110 according to the present disclosure. The substrate processing system 110 includes a direct drive circuit 112, a resonant capacitor circuit 114, and a coil assembly 116, which includes an inner coil and an outer coil and an optional frame (such as Figure 4 and 6 In some examples, the direct drive circuit 112, the resonant capacitor circuit 114, and the coil assembly 116 are arranged in Figure 2 In some examples, the resonant capacitor circuit 114 includes one or more variable capacitors and does not include an inductor. In some examples, the RF power can be pulsed on and off and / or the amplitude or level of the RF power can be varied.

[0038] A window 124 made of a dielectric is arranged along one side of the process chamber 128. The process chamber 128 also includes a substrate support (or pedestal) 132. The substrate support 132 may include an electrostatic chuck (ESC), or a mechanical chuck or other type of chuck to support the substrate 134. A process gas is supplied to the process chamber 128 and a plasma 140 is generated inside the process chamber 128. The plasma 140 etches the exposed surface of the substrate 134. An RF bias circuit 152 may be used to provide an RF bias to the electrodes in the substrate support 132 during operation.

[0039] A gas delivery system 156 can be used to supply a process gas mixture to the process chamber 128. The gas delivery system 156 can include process and inert gas sources 157, a gas metering system 158 (e.g., valves and mass flow controllers), and a manifold 159. A heater / cooler 164 can be used to heat / cool the substrate support 132 to a predetermined temperature. An exhaust system 165 includes a valve 166 and a pump 167 to remove reactants from the process chamber 128 by purging or exhausting.

[0040] The controller 154 may be used to control the etching process. The controller 154 monitors system parameters and controls the delivery of the gas mixture, ignition, maintenance, and extinguishing of the plasma, removal of reactants, supply of cooling gases, and the like.

[0041] Now refer to Figure 2 , shows a direct drive system 200 . The direct drive circuit 112 may be disposed in a direct drive housing 210 . The capacitor circuit 114 may be disposed in a junction box 222 . The coil assembly 116 may be disposed in a coil housing 230 .

[0042] The direct drive housing 210 houses one or more direct drive circuits 112. For example, the direct drive housing 210 houses a first direct drive circuit 214-1 that operates at a first frequency and a second direct drive circuit 214-2 that operates at a second frequency (collectively referred to as direct drive circuits 214). In some examples, the first and second frequencies of the first and second direct drive circuits 214-1 and 214-2 are different frequencies. In some examples, the first frequency and the second frequency are in a range from 0.2 MHz to 20 MHz. In some examples, the first frequency is in a range from 1 MHz to 6 MHz and the second frequency is in a range from 7 MHz to 20 MHz. In some examples, the first frequency is in a range from 2 MHz to 4 MHz and the second frequency is in a range from 11 MHz-15 MHz. In some examples, the first frequency is 2 MHz and the second frequency is 13.56 MHz.

[0043] The first direct drive circuit 214-1 outputs a first RF signal to the first terminals of the first and second capacitors C1 and C2 of the capacitor circuit 114 located in the junction box 222 and connected in parallel. The second terminals of the first and second capacitors C1 and C2 are connected to the first terminals of the outer coils 234-A and 234-B (collectively referred to as the outer coil 234) of the coil assembly 116, respectively. The first and second capacitors C1 and C2 of the capacitor circuit 114 can be referred to as a first capacitance circuit. In some examples, the coil assembly 116 further includes a frame for supporting the coils 234 and 238 (see below). Figure 4 and 6 ). The second terminals of the outer coils 234-A and 234-B of the coil assembly 116 are grounded. In some examples, the first terminal is located at the radially inner end of the outer coil 234, the second terminal is located at the radially outer end of the outer coil 234, and the coils are wound around each other in opposite directions.

[0044] The second direct drive circuit 214-2 outputs a second RF signal to the first terminal of the third capacitor C3 of the capacitor circuit 114 in the junction box 222. The second terminal of the third capacitor C3 is connected to the first terminal of the inner coils 238-A and 238-B of the coil assembly 116. The second terminals of the inner coils 238-A and 238-B are grounded. The third capacitor C3 of the capacitor circuit 114 can be referred to as a second capacitor circuit. The outer coil 234 and the inner coil 238 can be arranged in the coil housing 230. In some examples, the first terminal is located at the radially inner end of the inner coil 238, the second terminal is located at the radially outer end of the inner coil 238, and the coils are wound around each other in opposite directions.

[0045] Now refer to Figure 3 , an example of a direct drive circuit 214 is shown. Although a specific example of a direct drive circuit is shown, other types of direct drive circuits can be used. The direct drive circuit 214 includes a clock generator 310 that outputs a clock signal at an RF frequency fRF (e.g., a first frequency or a second frequency). The output of the clock generator 310 is input to a gate driver 322. The output of the gate driver 332 is input to the switches of the half bridge 324. In some examples, the gate driver 322 includes an amplifier 344 and an inverting amplifier 346. The output of the gate driver 322 is input to the control terminal of the first switch 340 of the half bridge 324. The output of the inverting amplifier 346 is input to the control terminal of the second switch 342 of the half bridge 324.

[0046] A first terminal of first switch 340 is connected to DC power source 326. A second terminal of first switch 340 is connected to a first terminal of second switch 342. A second terminal of second switch 342 is grounded. In some examples, clock on / off circuit 364 provides an on / off signal to one input of multiplier 365. Another input of multiplier 365 receives the output of clock generator 310. Clock on / off circuit 364 and multiplier 365 can be used to enable or disable the output from clock generator 310.

[0047] In some examples, adjustment circuit 362 generates an on / off signal or a variable signal to one input of multiplier 363. Another input of multiplier 363 receives the output of DC power supply 326. Adjustment circuit 362 and multiplier 363 selectively change the amplitude of the output of DC power supply 326. In some examples, clock on / off circuit 364 and regulation circuit 362 can be used to pulse the plasma or change between different levels (level-to-level).

[0048] Now refer to Figure 4 The direct drive housing 210 is disposed adjacent to and in contact with the terminal box 222. The terminal box 222 is disposed adjacent to and in contact with the coil housing 230. The window 124 is disposed between the coil housing 230 and the process chamber 128.

[0049] The mating connector 418 is used to releasably connect the first and second direct drive circuits 214-1, 214-2 of the direct drive housing 210 to the capacitors C1 and C2 and C3 of the terminal block 222, respectively. In some examples, the mating connector 418 includes a female connector 420 and a male connector 422. In some examples, the male connector 422 includes a center conductor or shaft surrounded by an insulating base and extending from the insulating base. In some examples, the female connector 420 includes a central conductive cavity surrounded by an insulating base. In some examples, the male connector 422 can move vertically relative to the female connector 420 while maintaining an electrical connection therebetween.

[0050] Similarly, mating connector 428 is used to connect capacitors C1 and C2 to outer coil 234 and capacitor C3 to inner coil 238. In some examples, mating connector 428 includes a male connector 430 and a female connector 434. In some examples, male connector 430 includes a central conductor or shaft surrounded by an insulating outer portion and extending from the insulating outer portion. In some examples, female connector 434 includes a central conductive cavity surrounded by an insulating outer portion. In some examples, male connector 430 can move relative to female connector 434 while maintaining an electrical connection therebetween. Frame 436 can be used to support and maintain the relative position of outer coil 234 and inner coil 238. Frame 436 can include access holes through which female connector 434 connects to outer coil 234 and inner coil 238.

[0051] When the substrate processing chamber 128 is operated under vacuum, the window 124 bends inward. When the pressure in the processing chamber returns to atmospheric pressure, the window 124 returns to its nominal position. The mating connectors 418 and 428 compensate for the movement of the outer coil 234 and the inner coil 238 resting on the window 124 to maintain their position relative to the window 124, thereby reducing impedance changes.

[0052] Now refer to Figure 5 , shows a direct drive system during calibration. Calibration is performed before connecting the direct drive housing 210 (having the direct drive circuit 214) to the junction box 222. The junction box 222 is calibrated so that the outer coil 234 and the inner coil 238 are in series resonation with their respective capacitors located in the junction box 222. In some examples, calibration is performed for each input of the junction box 222 at a corresponding nominal center operating frequency (for example only, at 2 MHz or 13.56 MHz). In some examples, calibration is performed under no-load conditions (corresponding to a process chamber at atmospheric pressure with no plasma). Calibration eliminates variations caused by design tolerances, thereby presenting the same load to the dual frequency direct drive system from one process chamber to another.

[0053] In some examples, calibration circuit 520 is connected to one input of junction box 222 and network analyzer 530 is connected to the other input of junction box 222. Calibration circuit 520 generates a test signal and network analyzer 520 measures the response. If the capacitor's adjustment mechanism includes a motor, this process can be repeated using feedback from network analyzer 520. This process can be repeated for the other input of junction box 222 by switching the positions of calibration circuit 520 and network analyzer 520.

[0054] Now refer to Figure 6 , shows a coil assembly 600. Coil assembly 600 includes outer coil 234 and inner coil 238, frame 436, and female connector 434. In some examples, frame 436 has an "X" shape, with arms 610 arranged at 90° intervals and arcuate portions 620 extending circumferentially in both directions near the ends of arms 610. Fasteners 640, such as screws or rivets, can be used to directly connect frame 436 to outer coil 234 and inner coil 238. In some examples, frame 436 is made of an insulating material.

[0055] Now refer to Figure 7, the junction box 222 connects the direct drive circuit 214 in the direct drive housing 210 to the outer coil 234 and the inner coil 238. The junction box 222 includes side walls 710, 712, 716, and 718. Inner walls 722 and 724 are arranged between the side walls 710 and 716. Inner wall 726 is arranged between inner wall 724 and side wall 712. Capacitors C1 and C2 are arranged between side walls 710, 716, 718 and inner wall 720. Capacitor C3 is arranged between side walls 710, 712, 716 and inner walls 724 and 726.

[0056] A fan assembly 730 is positioned adjacent to side wall 712 to supply airflow into terminal box 222 through apertures 734 in side wall 712. A fan assembly 740 is also positioned adjacent to side wall 718 to supply airflow into terminal box 222 through apertures 744 in side wall 718. A first of male connectors 422-1 is connected to one plate of capacitor C3 via a strap 752. A second plate of capacitor C3 is connected to conductor 756 (surrounded by insulator 755) via a strap 754. Conductor 756 is connected to strap 757, which is connected to both male connectors 430. One or more apertures 780 may be provided to allow airflow through a bottom surface 782 of terminal box 222.

[0057] Strap 758 connects one of male connectors 430 to terminal block 222. Strap 764 connects to two of male connectors 430. Straps 770 and 772 connect two of male connectors 430 to terminal block 222. Strap 764 connects to strap 770 via conductor 766 (through insulator 768). Strap 770 connects to the first plates of capacitors C1 and C2. The second plates of capacitors C1 and C2 connect to the second of male connectors 422-2 via strap 772.

[0058] In some examples, capacitors C1, C2, and C3 are variable capacitors that include an adjustment mechanism that changes the relationship between the plates of capacitors C1, C2, and C3. In some examples, capacitors C1, C2, and C3 include first and second metal cylinders having different diameters and arranged concentrically. The capacitance of capacitors C1, C2, and C3 is defined by the amount of overlap between the first and second metal cylinders. In some examples, the adjustment mechanism 748 includes a threaded screw, a motor, or other mechanism that moves the first metal cylinder axially relative to the second metal cylinder (or vice versa) to change the overlap.

[0059] Fan assemblies 730 and 740 drive air flow into side compartments 790 and 792 of terminal box 222 and then into central compartment 794 of terminal box 222. The air is exhausted through apertures 780 in bottom surface 782 and / or through exhaust path 796.

[0060] Now refer to Figure 8, the female connector 434 allows relative movement between the male connector 430 and the female connector 434. In some examples, the female connector 434 includes a body 810. A shaft 814 extends from the body 810 and includes a threaded outer surface 818. The shaft of the male connector 430 is inserted into a cavity 820 defined by the body 810 of the female connector 434. The inner surface of the cavity 820 defines a spring-like surface 830 that engages the outer surface of the shaft of the male connector 430 while allowing movement between the male connector 430 and the female connector 434 and while maintaining an electrical connection therebetween.

[0061] Now refer to Figure 9 , shows a direct drive system 200-1 including a junction box 222-1. The junction box 222-1 of the direct drive system 200-1 is the same as that of the above reference Figure 2 The difference between the terminal block 222 of the direct drive system 200 shown and described is that the second terminals (labeled T3 and T4) of the inner coils 238-A and 238-B are not connected to ground, but are connected to a fourth capacitor C4 as shown. The fourth capacitor C4 can be referred to as a third capacitance circuit.

[0062] For example, the fourth capacitor C4 may be a fixed vacuum capacitor C4 (eg, 400 pF). Figure 2 Compared to the configuration shown without the fourth capacitor C4, for the same RF current in the inner coils 238-A and 238-B, the RF voltage at the first terminals (labeled as T1 and T2) of the inner coils 238-A and 238-B is reduced by about half. At the same time, the fourth capacitor C4 also increases the RF voltage at the terminals T3 and T4 to be approximately the same as the RF voltage at the terminals T1 and T2, but with opposite polarity. In contrast, in Figure 2 In the configuration shown, the RF voltage at terminals T3 and T4 is zero volts because terminals T3 and T4 are grounded. The fourth capacitor C4 reduces the maximum amplitude of the RF voltage across terminals T1, T2, T3, and T4 so that the terminals of the inner coil do not experience an RF voltage with an amplitude exceeding the threshold that causes sputtering on the ceramic window 124. This is advantageous because sputtering on the window 124 can generate metallic contaminants and particles on the substrate 134. The fourth capacitor C4 prevents sputtering on the window 124, and thus metallic contaminants and particles on the substrate 134.

[0063] The foregoing description is merely illustrative in nature and is in no way intended to limit the present disclosure, its application or use. The broad teachings of the present disclosure can be implemented in various forms. Therefore, although the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, because other modifications will become apparent when studying the drawings, description and appended claims. It should be understood that one or more steps in the method can be performed in a different order (or simultaneously) without changing the principles of the present disclosure. In addition, although each embodiment is described above as having certain features, any one or more of those features described with respect to any embodiment of the present disclosure can be implemented in the features of any other embodiment and / or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the embodiments described are not mutually exclusive, and the replacement of one or more embodiments with each other remains within the scope of the present disclosure.

[0064] Various terms are used to describe the spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless the relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the above disclosure, the relationship can be a direct relationship, in which there are no other intervening elements between the first and second elements, but can also be an indirect relationship, in which there are one or more intervening elements (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be construed to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be construed to mean "at least one of A, at least one of B, and at least one of C."

[0065] In some implementations, the controller is part of a system that can be part of the examples above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or system type, the controller can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out tools and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0066] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various separate settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more process steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or the die of the wafer.

[0067] In some implementations, the controller can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller can be in the "cloud" or all or part of a wafer fab host system that can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance metrics for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network (which can include a local network or the Internet). The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0068] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0069] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport of wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

Claims

1. A system for providing a radio frequency signal to a plasma processing system, comprising: a junction box configured to be placed adjacent to a direct-drive RF signal generating system, the junction box comprising a junction box input connector located on a first side of the junction box, the junction box input connector configured to be electrically connected to an RF signal output of the direct-drive RF signal generating system, the junction box comprising a variable capacitor having an input end electrically connected to the junction box input connector, the variable capacitor having an output end electrically connected to a junction box output connector located on a second side of the junction box; as well as A coil housing is disposed beside the junction box, the coil housing including a coil having a coil input connector, the coil input connector and the junction box output connector being configured to be electrically connected to each other, the coil input connector and the junction box output connector being configured to move relative to each other while remaining electrically connected to each other, so that the coil can move relative to the junction box while maintaining electrical connection between the junction box output connector and the coil input connector.

2. The system of claim 1 , wherein the terminal block output connector includes a center conductor surrounded by a first insulating exterior and extending from the first insulating exterior, and wherein the coil input connector includes a center conductive cavity surrounded by a second insulating exterior.

3. The system of claim 2, wherein the center conductor of the terminal block output connector is inserted into the center conductive cavity of the coil input connector for electrically connecting the output terminal of the variable capacitor in the terminal block to the coil.

4. The system of claim 1, wherein the coil housing is disposed between the terminal block and a window of a substrate processing chamber, and wherein the coil is disposed on the window of the substrate processing chamber.

5. The system of claim 4, wherein a window of the substrate processing chamber is configured to flex and cause corresponding movement of the coil relative to the terminal block.

6. The system of claim 1 , wherein the variable capacitor is a first variable capacitor within the junction box, wherein the junction box includes a second variable capacitor having an input end electrically connected to the junction box input connector and an output end electrically connected to the junction box output connector, such that the first variable capacitor and the second variable capacitor are electrically connected in parallel to each other.

7. The system of claim 6, wherein the junction box input connector is a first junction box input connector, wherein the junction box output connector is a first junction box output connector, wherein the direct-drive RF signal generating system is a first direct-drive RF signal generating system, wherein the junction box is configured to be placed next to a second direct-drive RF signal generating system, wherein the junction box includes a second junction box input connector located on a first side of the junction box, the second junction box input connector configured to electrically connect to an RF signal output of the second direct-drive RF signal generating system, wherein the junction box includes a third variable capacitor, the third variable capacitor having an input terminal electrically connected to the second junction box input connector, and the third variable capacitor having an output terminal electrically connected to the second junction box output connector located on a second side of the junction box.

8. The system of claim 7, wherein the coil is a first coil, wherein the coil input connector is a first coil input connector, wherein the coil housing includes a second coil having a second coil input connector, the second coil input connector and a second terminal box output connector being configured to be electrically connected to each other, the second coil input connector and the second terminal box output connector being configured to move relative to each other while remaining electrically connected to each other, thereby enabling the second coil to move relative to the terminal box while maintaining electrical connection between the second terminal box output connector and the second coil input connector.

9. The system of claim 8, wherein the first coil is configured and positioned to constrain the second coil.

10. The system of claim 8, wherein the first coil is a first outer coil, wherein the second coil is a first inner coil, wherein the terminal block includes a third terminal block output connector electrically connected to output terminals of the first variable capacitor and the second variable capacitor, wherein the terminal block includes a fourth terminal block output connector electrically connected to output terminals of the third variable capacitor, wherein the first coil is a first outer coil, wherein the second coil is a first inner coil, wherein the coil housing includes a third coil input connector electrically connected to the third terminal block output connector, wherein the coil housing includes a second outer coil electrically connected to the third coil input connector, wherein the coil housing includes a fourth coil input connector electrically connected to the fourth terminal block output connector, wherein the coil housing includes a second inner coil electrically connected to the fourth coil input connector.

11. The system of claim 10, wherein the third coil input connector and the third terminal box output connector are configured to move relative to each other while remaining electrically connected to each other so as to enable the second external coil to move relative to the terminal box while maintaining an electrical connection between the third terminal box output connector and the third coil input connector, and wherein the fourth coil input connector and the fourth terminal box output connector are configured to move relative to each other while remaining electrically connected to each other so as to enable the fourth external coil to move relative to the terminal box while maintaining an electrical connection between the fourth terminal box output connector and the fourth coil input connector.

12. The system of claim 11, wherein the first coil input connector is connected to a first end of the first outer coil, wherein the third coil input connector is connected to a first end of the second outer coil, wherein a second end of the first outer coil is electrically connected to a reference ground potential, wherein a second end of the second outer coil is electrically connected to the reference ground potential, wherein the second coil input connector is connected to a first end of the first inner coil, wherein the fourth coil input connector is connected to a first end of the second inner coil, wherein a second end of the first inner coil is electrically connected to the reference ground potential, wherein a second end of the second inner coil is electrically connected to the reference ground potential.

13. The system of claim 12, wherein the second outer coil is interleaved with the first outer coil, and wherein the second inner coil is interleaved with the first inner coil.

14. The system of claim 13, wherein each of the first, second, third, and fourth terminal block output connectors includes a respective center conductor surrounded by a respective insulating exterior and extending therefrom, and wherein each of the first, second, third, and fourth coil input connectors includes a respective center conductive cavity surrounded by a respective insulating exterior.

15. The system of claim 14, wherein the center conductors of the first, second, third and fourth terminal block output connectors are inserted into the center conductive cavities of the first, second, third and fourth coil input connectors, respectively.

16. The system of claim 15, wherein each of the central conductive cavities of the first, second, third, and fourth coil input connectors has a spring surface that engages a corresponding one of the center conductors of the first, second, third, and fourth terminal block output connectors.

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