Chip packaging structure, preparation method thereof and electronic device

Abstract

The application discloses a chip packaging structure and a preparation method thereof and electronic equipment, and is suitable for the technical field of semiconductors. The preparation method comprises the following steps: forming a first re-wiring layer on a first wafer to obtain a first stacking structure; forming a second re-wiring layer and a third re-wiring layer on opposite side surfaces of at least one second wafer to obtain at least one second stacking structure; and bonding the at least one second stacking structure and the first stacking structure, and the second re-wiring layer is electrically connected with the first re-wiring layer. The technical scheme of the application reduces the difficulty of the preparation process of the chip packaging structure and improves the packaging precision of the chip packaging structure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a chip packaging structure, a preparation method thereof, and an electronic device. BACKGROUND

[0002] With the pursuit of the integration of chips in the semiconductor industry and the exploration of three-dimensional (3D) packaging technology, chip-wafer hybrid bonding technology (Hybrid Bonding) has emerged. How to reduce the process difficulty of the preparation process of the chip packaging structure and improve the packaging precision of the chip packaging structure has become a problem to be solved. SUMMARY

[0003] The present application provides a chip packaging structure, a preparation method thereof, and an electronic device, which aims to reduce the process difficulty of the preparation process of the chip packaging structure and improve the packaging precision of the chip packaging structure.

[0004] To achieve the above-mentioned purpose, embodiments of the present application provide the following technical solutions:

[0005] In one aspect, a preparation method of a chip packaging structure is provided, which includes: forming a first re-distribution layer on a first wafer to obtain a first stacked structure; forming a second re-distribution layer and a third re-distribution layer on opposite side surfaces of at least one second wafer to obtain at least one second stacked structure; and bonding the at least one second stacked structure with the first stacked structure, and the second re-distribution layer is electrically connected with the first re-distribution layer.

[0006] In some embodiments, the opposite side surfaces of the second wafer are a first surface and a second surface respectively, and the second wafer includes a device layer extending from the first surface into the second wafer. Forming the second re-distribution layer and the third re-distribution layer on the opposite side surfaces of the at least one second wafer includes: forming the second re-distribution layer on the first surface of the second wafer, and the second re-distribution layer is electrically connected with the device layer; bonding the second wafer and the second re-distribution layer with a first carrier, and a surface of the second re-distribution layer away from the second wafer is connected with the first carrier; removing part of the second surface of the second wafer to expose the device layer; and forming the third re-distribution layer on the second surface, and the third re-distribution layer is electrically connected with the device layer to obtain the second stacked structure.

[0007] In some embodiments, removing part of the second surface of the second wafer includes grinding and etching the second surface to expose the device layer.

[0008] In some embodiments, after the third re-wiring layer is formed, the method further comprises: connecting the second stack structure with a second carrier, the surface of the third re-wiring layer away from the second wafer is connected with the second carrier; removing the first carrier to expose the surface of the second re-wiring layer away from the second wafer; forming a gap in the second stack structure, the gap penetrates through the second re-wiring layer, the second wafer and the third re-wiring layer, and the gap separates the second stack structure into a plurality of chips.

[0009] In some embodiments, the forming the gap in the second stack structure comprises: forming a mask layer on the side of the second stack structure away from the second carrier, the mask layer has an opening; etching the second stack structure through the opening of the mask layer to form the gap.

[0010] The method for preparing the chip packaging structure provided by the embodiments of the present application first forms a first re-wiring layer on a first wafer to obtain a first stack structure. Then, a second re-wiring layer and a third re-wiring layer are respectively formed on the opposite surfaces of at least one second wafer to form at least one second stack structure. Finally, the at least one second stack structure is bonded with the first stack structure to obtain a bonded chip packaging structure (bonding structure).

[0011] Compared with forming a silicon oxide film layer for planarization on the bonding structure, and then thinning the silicon oxide film layer to facilitate the formation of a re-wiring layer on the bonding structure, in the above embodiments of the present application, the re-wiring layers are first formed on the opposite sides of the second stack structure, and the opposite sides of the second stack structure can be directly bonded with the first stack structure, without the need to deposit a relatively thick silicon oxide film layer on the bonding structure, thereby avoiding warpage of the bonding structure due to the relatively large stress and avoiding the problem that the subsequently formed film layer is prone to falling off. Moreover, the silicon oxide film layer does not need to be thinned, which improves the wafer processing quantity per hour (Wafer Per Hour, WPH) and the efficiency of chip packaging, and improves the production efficiency.

[0012] Moreover, the present application does not need to form a re-wiring layer on the bonding structure, thereby avoiding the photolithography process, etching process, film layer deposition process and the like on the bonding structure, thus reducing the process difficulty of tape-out and improving the process feasibility. In the case where the number of layers of the bonding structure is large, since the process flow is optimized, the subsequent process of the multi-layer bonding structure at this time is only the bonding process (including activation before bonding and cleaning process), which greatly reduces the requirement for modification of subsequent equipment, also reduces the difficulty of tape-out, and improves the process feasibility.

[0013] In another aspect, the present application also provides a chip packaging structure, which comprises a first stack structure and at least one second stack structure. The first stack structure comprises a first wafer and a first re-distribution layer which are arranged in a stack manner, and the at least one second stack structure is bonded with the first stack structure. The second stack structure comprises a second re-distribution layer, a second wafer and a third re-distribution layer which are arranged in a stack manner in sequence, and a surface of the second re-distribution layer away from the second wafer is bonded with a surface of the first re-distribution layer away from the first wafer. The second stack structure further comprises a gap which penetrates through the second re-distribution layer, the second wafer and the third re-distribution layer, and the gap is used to separate the second stack structure into a plurality of chips.

[0014] In some embodiments, the chip packaging structure comprises a plurality of second stack structures which are arranged in a stack manner on the first stack structure.

[0015] Compared with the chip packaging structure formed by forming a silicon oxide film layer for planarization on the bonding structure, then thinning the silicon oxide film layer, and then forming a re-distribution layer on the bonding structure, in the chip packaging structure of the present application, the second stack structure comprises a gap which penetrates through the second re-distribution layer, the second wafer and the third re-distribution layer, and the gap separates the second stack structure into a plurality of chips, so that a relatively thick silicon oxide film layer does not need to be deposited on the bonding structure, the bonding structure is prevented from being warped due to bearing a relatively large stress, and the problem that the subsequently formed film layer is prone to falling off is also avoided, thereby improving the packaging precision of the chip packaging structure.

[0016] In another aspect, the present application also provides an electronic device, which comprises the above-mentioned chip packaging structure and a circuit board, and the chip packaging structure is electrically connected with the circuit board. The chip packaging structure in the electronic device improves the packaging precision, improves the reliability of the chip packaging structure, and thus improves the reliability of the electronic device.

[0017] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0019] Figures 1-5 A partial preparation process diagram of a chip packaging structure in the related art is provided;

[0020] Figure 6 A preparation method flowchart of a chip packaging structure according to an embodiment of the present application is provided;

[0021] Figures 7-24A step diagram of a preparation method provided by an embodiment of the present application is shown in the following.

[0022] Figure 25 A structural diagram of an electronic device provided by an embodiment of the present application is shown in the following. DETAILED DESCRIPTION

[0023] Embodiments of the present application are described in detail below with reference to the accompanying drawings. Examples of the embodiments are shown in the drawings, in which the same or similar components are denoted by the same or similar reference numerals throughout. The embodiments described below by reference to the drawings are exemplary and are for the purpose of explanation only and are not to be understood as limiting the present application.

[0024] The terms "first", "second", and the like in the description and claims of the present application are used for distinguishing between similar objects and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that the use of the terms so construed can interchange depending on the context in which it is used, and that the embodiments of the present application are well suited to perform different orders of operations than those described herein without departing from the essence of the embodiments of the present application. The aforementioned terms do not connote an obligatory sequence or order unless explicitly stated that a particular sequence or order is required.

[0025] In the description of the present application, the meaning of "a plurality of" is two or more.

[0026] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "certain embodiments", "example", "specific example", or "some examples" means that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the present application. The appearances of the aforementioned terms in the description of the present application do not necessarily refer to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0027] In describing some embodiments, the term "connected" and variations thereof can be used. The term "connected" is used broadly and can encompass both direct and indirect connections, fixed and removable connections, and the like. The term "electrically connected" means that two or more components have direct physical or electrical contact with each other, or can mean that two or more components have no direct contact with each other but are still in cooperation or interaction with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0028] With the development of integrated circuits, the feature size of transistors arranged on a chip is continuously scaled down, but when approaching the physical limit, quantum tunneling effect and short channel effect limit the further scaling down of the transistor. The traditional method of improving performance by scaling down the feature size of the transistor becomes more and more difficult, and 3D packaging technology emerges as the times require, and the chip-wafer hybrid bonding process has gradually become a very promising 3D packaging technology due to its various performance advantages.

[0029] High-Bandwidth Memory (HBM) is a typical application of chip-wafer 3D advanced packaging. After stacking multiple Double Data Rate SDRAM (DDR) chips together, it is packaged with a Graphic Processing Unit (GPU) to realize a large-capacity, high-bit-width DDR combined array. This multi-chip stacking technology uses chip-wafer hybrid bonding to integrate more functional chips.

[0030] In the above process of preparing a chip packaging structure by the chip-wafer hybrid bonding process, there are problems of great process difficulty and difficult operation, Figures 1-5 For example, the problems of the chip-wafer hybrid bonding process are described with reference to the partial preparation process steps of the chip packaging structure in the related art. Figures 1-5

[0031] As shown in Figure 1 , the second stacked structure B' is bonded to the side of the first stacked structure A' provided with the first re-distribution layer 11', and then annealing treatment is performed. The second stacked structure B' includes multiple chips 5', and there is a gap 24' between the multiple chips 5'. Next, as shown in Figure 2 , a Chemical Vapor Deposition (CVD) process is used to deposit a dielectric material 6 into the gap 24' between the multiple chips 5' of the second stacked structure B' to fill the gap 24'. Then, as shown in Figure 3 , the dielectric material 6 beyond the second surface 202' of the second stacked structure B' is mechanically ground to planarize the surface of the second stacked structure B' and expose the device layer 21' in the second stacked structure B'.

[0032] On the one hand, as shown in Figure 2 ​As shown, in the process of depositing the dielectric material 6 such as silicon oxide into the gap 24', since the depth of the gap 24' along the direction Z is much greater than its width along the direction X, in order to fill the gap 24' with the dielectric material 6 and form a flat surface for subsequent processes, a super-thick dielectric material film layer (≥40 microns) needs to be deposited. The thickness of the second stack structure B' is usually about tens of microns, and the thickness of the dielectric material 6 is at least tens of microns. The thicker the film layer of the dielectric material 6, the greater the stress it generates, and the more significant the warping and peeling defects of the surface of the second stack structure B' caused. The deposition rate of chemical vapor deposition is relatively slow, and the deposition of a film layer of tens of microns thick takes a long time, which seriously reduces the number of wafers processed per hour, thereby affecting the production efficiency of the chip packaging structure.

[0033] On the other hand, as shown, Figure 3 In the process of grinding the dielectric material 6, since the dielectric material 6 is usually silicon oxide, the hardness of silicon oxide is greater than that of the material silicon of the wafer, making it very difficult to cut the film layer with a grinding wheel for thinning, and the grinding wheel itself is consumed greatly.

[0034] After the bonding of the second stack structure B' and the first stack structure A' is completed, as shown, Figure 4 A redistribution layer (RDL) needs to be made on the second surface 202' of the second stack structure B' to form a third redistribution layer 23', and then as shown, Figure 5 The second stack structure B' with excellent performance is selected to continue bonding with the second stack structure B', and the above operations are repeated to realize the multi-layer stacking of the chip 5'.

[0035] After bonding, the first stack structure A' is subjected to the stress of multiple chips 5' in the second stack structure B', which causes the warping degree of the first stack structure A' to become large, and further causes the surface of the second stack structure B' to warp. Since excessive warping can seriously affect the alignment accuracy of the photolithography process, causing the deformation of the photolithography pattern, the photolithography accuracy of the second stack structure B' and other wafers arranged on the second stack structure B' will be affected, and the process of making the third redistribution layer 23' as shown will also be affected. Figure 4

[0036] As shown, Figure 5 When multiple layers (≥3 layers) of wafers are bonded, the total thickness of the wafers becomes significantly thick. The excessively thick wafers can cause problems in the subsequent process-related equipment for wafer grabbing, adsorption, transfer, etc. Not only does this require higher requirements for the subsequent process-related equipment, but it can also cause the equipment to alarm, thereby affecting the wafer preparation process.​

[0037] To solve the above problems, the application provides a chip packaging structure preparation method, Figure 6 The chip packaging structure preparation method provided by the embodiment of the application is shown in a flowchart, Figures 7-24 To Figure 6 The preparation method is shown in a step-by-step diagram, Figure 6 The preparation method includes the following steps S1-S3:

[0038] Step S1: as shown in the figure, Figure 7 The first wafer 1 is provided, and then as shown in the figure, Figure 8 A first redistribution layer 11 is formed on the first wafer 1 to obtain a first stacked structure A.

[0039] Step S2: as shown in the figure, Figure 9 At least one second wafer 2 is provided, and as shown in the figure, Figures 10-16 A second redistribution layer 22 and a third redistribution layer 23 are formed on the opposite two side surfaces of the second wafer 2. It can be understood that the number of second wafers 2 is at least one, and the opposite two side surfaces of the second wafer 2 are a first surface 201 and a second surface 202. The second redistribution layer 22 and the third redistribution layer 23 are formed on the first surface 201 and the second surface 202 respectively to obtain at least one second stacked structure B.

[0040] In some embodiments, as shown in the figure, Figure 10 The second wafer 2 further includes a device layer 21, which extends from the first surface 201 to the inside of the second wafer 2. The second redistribution layer 22 and the third redistribution layer 23 are formed on the opposite two side surfaces of the at least one second wafer 2, and the specific formation includes the following steps S201-S204:

[0041] Step S210: as shown in the figure, Figure 10 A device is made on the first surface 201 of the second wafer 2 to form a device layer 21, and a through hole 20 is made inside the second wafer 2 by a through silicon via (TSV) technology and filled with conductive material in the through hole 20 to realize vertical connection between chips. Then, as shown in the figure, Figure 11 A second redistribution layer 22 is made on the first surface 201, which is electrically connected with the device layer 21. The second redistribution layer 22 includes a third surface 220 away from the second wafer 2, which can be used as a bonding interface for subsequent bonding.

[0042] Step S220: as shown in the figure, Figure 12 The second wafer 2 and the second redistribution layer 22 are subjected to trimming processing, and then as shown in the figure, Figure 13As shown, the second wafer 2 and the second redistribution layer 22 are inverted and temporarily bonded to the first carrier 31. The third surface 220 of the second redistribution layer 22 is connected to the first carrier 31, and the first carrier 31 is used to protect the third surface 220 of the second redistribution layer 22 from wear during subsequent processing.

[0043] Step S230: As Figures 14-15 As shown, a portion of the second surface 202 of the second wafer 2 is removed, that is, the second surface 202 of the second wafer 2 is thinned to expose the device layer 21.

[0044] In some embodiments, removing a portion of the second surface 202 of the second wafer 2 includes grinding and etching the second surface 202 to expose the device layer 21. For example, Figure 14 As shown, the second surface 202 is first mechanically ground, resulting in a relatively rough surface. Then, chemical mechanical polishing (CMP) is used to polish the second surface 202, reducing the thickness of the second wafer 2 and preparing it for subsequent etching steps. Next, as... Figure 15 As shown, a backside via reveal (BVR) process is performed on the second surface 202 to expose the device layer 21 and the via 20. The BVR process can be either dry etching or wet etching.

[0045] Step S240: As Figure 16 As shown, a third redistribution layer 23 is formed on the second surface 202. The third redistribution layer 23 is electrically connected to the device layer 21. Since the second surface 202 is planarized in step S230, the formation accuracy of the third redistribution layer 23 is improved. The third redistribution layer 23 includes a fourth surface 230 away from the second wafer 2. The fourth surface 230 can serve as the bonding interface for subsequent bonding processes. After completing the above steps, the second stacked structure B can be obtained.

[0046] In some embodiments, after forming the third redistribution layer 23, the above-described fabrication method further includes the following steps S241 to S245:

[0047] Step S241: As Figure 17 As shown, the second stacked structure B is inverted with the first carrier 31, and then the second stacked structure B is connected with the second carrier 32. The fourth surface 230 of the third redistribution layer 23 is connected with the second carrier 32. The second carrier 32 can be an ultraviolet-cured (UV) film. The second carrier 32 can protect the second surface 202 of the second wafer 2 from wear during subsequent processing.

[0048] Step S242: As shown in Figure 18 , the first carrier 31 is removed, exposing the third surface 220 of the second rewire layer 22.

[0049] Step S243: As shown in Figures 19-21 , a gap 24 is formed in the second stacked structure B, the gap 24 penetrates the second rewire layer 22, the second wafer 2 and the third rewire layer 23, and the gap 24 separates the second stacked structure B into a plurality of chips 5. The second rewire layer 22 and the third rewire layer 23 are formed on opposite sides of the second wafer 2, and the gap 24 divides the second wafer 2 into a plurality of chips 5, which do not need to be re-wired and filled and polished with dielectric material after subsequent bonding with the first stacked structure A, reducing the overall process difficulty.

[0050] In some embodiments, the specific steps of forming the gap 24 in the second stacked structure B in step S243 include:

[0051] As shown in Figure 19 , the mask layer 4 is formed on the second stacked structure B away from the second carrier 32, and the mask layer 4 has an opening 41. Then as shown in Figure 20 , the second stacked structure B is etched through the opening 41 of the mask layer 4 by dry etching to form the gap 24.

[0052] For example, after the gap 24 is formed, as shown in Figure 20 , the mask layer 4 is removed to obtain a plurality of chips 5. The above steps S2 are repeated in the same way to obtain a plurality of second stacked structures B containing a plurality of chips 5.

[0053] The second stacked structure B has been separated into a plurality of chips 5 before being bonded with the first stacked structure A, and the process steps after bonding have been optimized, reducing the process steps such as Figures 2-4 described in the related art, such as the manufacture of the rewire layer and the filling and polishing of the dielectric material 6, thereby avoiding the problems of warping and film separation of the chip 5 surface caused by the over-thickness of the dielectric material 6 film layer, and avoiding the problem of low film layer precision caused by the manufacture of the rewire layer after bonding, so that the preparation precision of the chip 5 is significantly improved.

[0054] Step S3: As shown in Figures 22-23 , at least one second stacked structure B is bonded with the first stacked structure A, and the second rewire layer 22 is electrically connected with the first rewire layer 11. Wherein, before the at least one second stacked structure B is bonded with the first stacked structure A, as shown in Figure 22As shown, multiple chips 5 need to be plasma activated and cleaned to remove dirt and particles from the surface of multiple chips 5, so as to ensure the cleanliness of the surface of multiple chips 5 and avoid affecting the subsequent bonding process.

[0055] Then as Figure 23 As shown, after removing the second substrate 32, the third surface 220 of the second stacked structure B is bonded to the surface 110 of the first stacked structure A. The bonding process adopts hybrid bonding to achieve a higher interconnect density between the second stacked structure B and the first stacked structure A.

[0056] Since bonding processes can be directly performed on both opposite sides of the second stacked structure B, compared to Figures 1-5 The second stacked structure B' shown in this embodiment of the application eliminates the need for deposition of dielectric material 6, polishing of dielectric material 6, and other process steps. This avoids problems such as excessive stress on the wafer due to excessively thick dielectric material 6, excessively long process time due to excessive deposition of dielectric material 6, and wear on the polishing wheel due to polishing dielectric material 6. It shortens the process time, increases the number of wafers processed per hour and the efficiency of chip packaging, and also reduces the process difficulty and the requirements for related equipment.

[0057] Then as Figure 24 As shown, another second stacked structure B that has passed the electrical test is selected and bonded to the fourth surface 230 of the second stacked structure B. The above operation is repeated to achieve multi-layer stacking of chip 5, finally forming chip package structure 7. Selecting the second stacked structure B that has passed the electrical test and using only the qualified second stacked structure B for bonding can minimize chip waste, maximize the product yield of the final packaged chip package structure 7, and maximize the product yield to reduce manufacturing costs. During the multi-layer stacking of chip 5, due to the optimization of the above process, the impact of the increased warpage of the first stacked structure A on the photolithography accuracy of chip 5 is reduced, the packaging accuracy of chip package structure 7 is improved, and the process difficulty of multi-layer stacking is greatly reduced, and the requirements for subsequent equipment are also greatly reduced, which improves the feasibility of the chip package structure fabrication method provided in this application.

[0058] On the other hand, this application also provides a chip packaging structure, the schematic diagram of which is shown below. Figure 24As shown, the chip packaging structure 7 includes a first stacked structure A and two second stacked structures B, the first stacked structure A includes the first wafer 1 and the first re-wiring layer 11 which are arranged in a stack, and the two second stacked structures B are bonded with the first stacked structure A in sequence. The second stacked structure B includes the second re-wiring layer 22, the second wafer 2 and the third re-wiring layer 23 which are arranged in a stack in sequence, and the surface of the second re-wiring layer 22 away from the second wafer 2 is bonded with the surface of the first re-wiring layer A away from the first wafer 1. Wherein, the second stacked structure B further includes a gap 24, the gap 24 penetrates through the second re-wiring layer 22, the second wafer 2 and the third re-wiring layer 23, and the gap 24 is used to separate the second stacked structure B into a plurality of chips 5.

[0059] The chip packaging structure 7 provided by the embodiment of the present application, the gap 24 on the second stacked structure B separates the second stacked structure B into a plurality of chips 5, and the second re-wiring layer 22 and the third re-wiring layer 23 are arranged on the opposite sides of the second stacked structure B, after the second stacked structure B is bonded with the first stacked structure A, the second stacked structure B does not need to be provided with the re-wiring layer again, and the gap 24 does not need to be filled with the medium material and polished, which avoids the problems of warping of the surface of the chip 5 and separation of the film layer caused by the over-thickness of the medium material film layer, and avoids the problem of low precision of the film layer caused by the re-wiring layer manufacturing after bonding, so that the precision of the chip 5 is improved. Further, due to the improvement of the precision of the chip 5, the packaging precision of the chip packaging structure 7 is also improved.

[0060] In some embodiments, as Figure 24 As shown, the chip packaging structure 7 includes a plurality of second stacked structures B, the plurality of second stacked structures B are arranged in a stack on the first stacked structure A, and the number of the second stacked structures B is at least one, and the embodiment of the present application takes two second stacked structures B as an example for description. Since the re-wiring layers on the opposite sides of the second stacked structure B have been manufactured before the second stacked structure B is bonded with the first stacked structure A, the re-wiring layer manufacturing, the medium material filling and the polishing process are not needed after the two are bonded, which avoids the problem of over-stress of the wafer caused by the over-thickness of the medium material, and avoids the problem of low precision of the chip 5 caused by the re-wiring layer manufacturing after bonding, so that the packaging precision of the whole chip packaging structure 7 is improved.

[0061] In a third aspect, Figure 25 The electronic device provided by the embodiment of the present application, as Figure 25As shown, the application also provides an electronic device 8, which comprises the chip packaging structure 7 mentioned above, and a circuit board 81, and the chip packaging structure 7 is electrically connected with the circuit board 81 through solder balls 82. The chip packaging structure 7 in the electronic device 8 realizes the improvement of packaging precision, thereby improving the reliability of the chip packaging structure 7, and further improving the reliability of the electronic device 8.

[0062] Although the embodiments of the application have been shown and described, it should be understood by those ordinary skilled in the art that various changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the application, and the scope of the application is defined by the claims and their equivalents.

Claims

1. A method for fabricating a chip packaging structure, characterized in that, include: A first redistribution layer is formed on a first wafer to obtain a first stacked structure; A second redistribution layer and a third redistribution layer are formed on opposite sides of at least one second wafer to obtain at least one second stacked structure; The at least one second stacked structure is bonded to the first stacked structure, and the second redistribution layer is electrically connected to the first redistribution layer; The second wafer has a first surface and a second surface on opposite sides, and the second wafer includes a device layer that extends from the first surface into the second wafer. A second redistribution layer and a third redistribution layer are formed on opposite two surfaces of at least one second wafer, including: A second redistribution layer is formed on a first surface of the second wafer, and the second redistribution layer is electrically connected to the device layer. The second wafer and the second redistribution layer are bonded to the first substrate, and the surface of the second redistribution layer on the side away from the second wafer is connected to the first substrate. Remove a portion of the second surface of the second wafer to expose the device layer on the second surface; The third redistribution layer is formed on the second surface, and the third redistribution layer is electrically connected to the device layer to obtain the second stacked structure; After forming the third redistribution layer, the fabrication method further includes: The second stacked structure is connected to the second wafer, and the surface of the third redistribution layer on the side away from the second wafer is connected to the second wafer; Remove the first substrate to expose the surface of the second redistribution layer on the side away from the second wafer; A gap is formed in the second stacked structure, the gap extending through the second redistribution layer, the second wafer, and the third redistribution layer, to divide the second stacked structure into multiple chips.

2. The preparation method according to claim 1, characterized in that, Removing a portion of the second surface of the second wafer includes: The second surface is ground and etched to expose the device layer.

3. The preparation method according to claim 1, characterized in that, Forming gaps in the second stacked structure includes: A mask layer is formed on the side of the second stacked structure away from the second substrate, the mask layer having an opening; The second stacked structure is etched through the opening in the mask layer to form the gap.

4. A chip packaging structure, characterized in that, include: The first stacked structure includes a first wafer and a first redistribution layer stacked together. At least one second stacked structure is bonded to the first stacked structure; The second stacked structure includes a second redistribution layer, a second wafer, and a third redistribution layer stacked sequentially, wherein the surface of the second redistribution layer away from the second wafer is bonded to the surface of the first redistribution layer away from the first wafer; The second stacked structure further includes a gap that extends through the second redistribution layer, the second wafer, and the third redistribution layer, for dividing the second stacked structure into multiple chips.

5. The chip packaging structure according to claim 4, characterized in that, The chip packaging structure includes a plurality of second stacked structures, which are stacked on the first stacked structure.

6. An electronic device, characterized in that, include: The chip packaging structure as described in claim 4 or 5; The circuit board, wherein the chip package structure is electrically connected to the circuit board.

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