Low-inductance silicon carbide power module and commutation loop structure

Abstract

The invention discloses a low-inductance silicon carbide power module and commutation loop structure, which comprises a large-area current planning interconnection structure and an ultra-short-path terminal direct connection capacitor structure, parasitic inductance in the silicon carbide power module is greatly reduced through mutual inductance between a large-area current planning interconnection structure and a conductive circuit of the ceramic substrate, and meanwhile, the length of a path from a terminal leading-out position in the power module to an external capacitor is shortened by utilizing a terminal direct connection capacitor structure; and the parasitic inductance of an external connection circuit of the silicon carbide power module is reduced, so that the parasitic inductance of the whole commutation loop is reduced, the switching voltage overshoot and oscillation are inhibited, and the working loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a low-inductance silicon carbide power module and a commutation circuit structure. Background Art

[0002] A power module is a module formed by packaging and integrating a series of power semiconductor chips according to a certain topology to achieve a certain function. Compared with the topology composed of discrete power chips, the power module is highly integrated and has great advantages in electrical performance, thermal performance, safety, chip life, cost, etc.

[0003] With the continuous development of semiconductor power chips, the application environment requirements of important fields such as new energy grid connection, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, pulse power, military and civilian applications are constantly increasing, as well as the influence of energy saving and the "double carbon" slogan. Power modules are constantly developing in the direction of miniaturization, low loss, high power density, high reliability and high integration. In particular, the emergence of a new generation of wide bandgap semiconductor chips represented by silicon carbide and gallium nitride materials has gradually replaced silicon-based chips in various industrial fields, accelerating the development of power modules, making power modules using wide bandgap power semiconductor chips have a smaller volume at the same voltage and current level, can work at higher temperatures, and work at higher switching frequencies, thereby further reducing the volume of passive chips and improving the efficiency of converters. Among them, power chips represented by silicon carbide MOSFET are expected to replace traditional silicon IGBTs in medium and high power conditions.

[0004] However, the traditional power module interconnection structure, namely the aluminum bonding wire, cannot fully utilize the performance advantages of silicon carbide. This is because the traditional power module interconnection structure has large parasitic parameters, which can easily cause oscillation during the high-speed switching process of the silicon carbide chip, exacerbating the loss of the silicon carbide chip. At the same time, the traditional power module is connected to the external circuit by bolting the lead-out terminal, which makes the path from the terminal to the external capacitor too long and introduces more line parasitic inductance, which makes it difficult to reduce the parasitic inductance of the overall commutation circuit even if the internal power module is optimized.

[0005] In summary, the excellent characteristics of silicon carbide chips are limited by the packaging method, especially the parasitic inductance caused by the upper surface interconnection and lead-out terminals of the silicon carbide chip. Therefore, a new packaging structure is needed to overcome the shortcomings of the traditional power module packaging method, and to reduce the parasitic inductance of the overall commutation circuit by controlling the parasitic inductance of the internal and external circuits of the power module. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a low-inductance silicon carbide power module and commutation circuit structure in response to the above-mentioned deficiencies in the prior art. The parasitic inductance inside the silicon carbide power module is greatly reduced by the mutual inductance between the large-area current planning interconnection structure and the conductive circuit of the ceramic substrate. At the same time, the terminal direct-connected capacitor structure is utilized to shorten the path length from the terminal lead-out position inside the power module to the external capacitor, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, thereby reducing the parasitic inductance of the entire commutation circuit, and is used to solve the technical problem of large overall parasitic inductance of the commutation circuit of the existing silicon carbide power module.

[0007] The present invention adopts the following technical solutions: A low-inductance silicon carbide power module and commutation loop structure, comprising a power substrate, a silicon carbide power semiconductor chip is mounted on the upper surface of the power substrate, a current planning interconnection structure having a current direction opposite to that of the power substrate is arranged above the silicon carbide power semiconductor chip, and the current planning interconnection structure is connected to a conductive layer of the power substrate through the silicon carbide power semiconductor chip; The current planning interconnection structure comprises a lower bridge arm current planning interconnection structure and an upper bridge arm current planning interconnection structure arranged oppositely, and the upper surfaces of the lower bridge arm current planning interconnection structure and the upper bridge arm current planning interconnection structure arranged oppositely are both provided with a chip connector and a substrate connector connected to the chip connector; The upper bridge arm current planning interconnection structure is connected to an AC lead-out power terminal, and the lower bridge arm current planning interconnection structure is connected to a DC lead-out power terminal, and a terminal direct-connected capacitor structure is provided on the DC lead-out power terminal.

[0008] Furthermore, the terminal directly connected capacitor structure includes a DC circuit board electrically connected to the DC lead-out power terminal, and a plurality of capacitors are arranged on the DC circuit board.

[0009] Furthermore, the capacitor with a higher capacitance among the plurality of capacitors is arranged outside the DC lead-out power terminal.

[0010] Furthermore, an AC lead-out terminal connector is provided on the outer side of the upper bridge arm current planning interconnection structure, and the AC lead-out power terminal is connected to the AC lead-out terminal connector.

[0011] Furthermore, the plane where the current planning interconnection structure is located is parallel to the upper surface of the power substrate.

[0012] Furthermore, the current planning interconnect structure is provided with a through hole having the same shape as that of the silicon carbide power semiconductor chip.

[0013] Furthermore, the upper surface of the power substrate is grooved.

[0014] Furthermore, the silicon carbide power semiconductor chip includes an upper bridge arm chip and a lower bridge arm chip, the upper bridge arm current planning interconnection structure is arranged above the upper bridge arm chip, and the lower bridge arm current planning interconnection structure is arranged above the lower bridge arm chip; The upper bridge arm chip is electrically connected to the upper bridge arm drain on the power substrate, and the lower bridge arm chip is electrically connected to the lower bridge arm drain on the power substrate.

[0015] Furthermore, the power substrate and the current planning interconnection structure are externally wrapped with a bottom shell and a top shell.

[0016] Furthermore, a metal base plate is connected to the bottom of the power substrate.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: The present invention provides a low-inductance silicon carbide power module and a commutation loop structure, comprising a current planning interconnection structure arranged above a silicon carbide power semiconductor chip and a power substrate for mounting the silicon carbide power semiconductor chip, the current planning interconnection structure being connected to a conductive layer of the power substrate, the current planning interconnection structure being connected to the silicon carbide power semiconductor chip through chip connectors on a lower bridge arm current planning interconnection structure and an upper bridge arm current planning interconnection structure respectively, and being electrically connected to the power substrate through a substrate connector electrically connected to the chip connector, the current direction of the conductive layer on the power substrate being opposite to the current direction on the current planning interconnection structure, a large-area current planning interconnection structure being used to complete the electrical connection of the upper surface of the power semiconductor chip inside the power module, and the parasitic inductance inside the power module being greatly reduced; a terminal direct-connected capacitor structure being used on the side close to the power terminal leading out of the power module, and the parasitic inductance of the commutation loop being further reduced by reducing the distance from the terminal to the capacitor, thereby reducing the voltage overshoot and oscillation of the power module during the switching process, accelerating the switching speed, reducing the switching loss, and improving the working efficiency of the power converter upper bridge arm current planning interconnection structure.

[0018] The current planning interconnection structure is set according to the current flow direction, so that the current flow direction of the upper conductive layer of the power substrate is opposite to the current flow direction on the current planning interconnection structure, thereby utilizing mutual inductance to weaken the self-inductance value of the internal circuit of the power module and reduce the internal parasitic inductance of the power module.

[0019] Furthermore, the plane where the current planning interconnection structure is located is parallel to the upper surface of the power substrate. The current planning interconnection structure ensures that the distance to the upper conductive layer of the power substrate is as close as possible while ensuring the necessary insulation gap, thereby maximizing the mutual inductance between the lines and making the mutual inductance value between the lines close to the self-inductance value, thereby greatly reducing the parasitic inductance inside the power module.

[0020] Furthermore, the terminal direct-connected capacitor structure places the capacitor of the commutation loop at one end of the power module lead-out power terminal close to the power module, which reduces the parasitic inductance of almost the entire lead-out terminal length compared to the traditional bolt-connected lead-out terminal.

[0021] Furthermore, the terminal direct-connect capacitor structure allows low-inductance capacitors to be placed near the lead-out power terminals, further reducing parasitic inductance outside the power module.

[0022] Furthermore, the power substrate, the silicon carbide power semiconductor chip mounted on the power substrate, and the current planning interconnection structure are arranged together in the bottom shell and the top shell to protect the power module therein.

[0023] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings to be used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is an exploded schematic diagram of the low inductance silicon carbide power module and commutation circuit structure of the present invention; Figure 2 It is a schematic diagram of the upper surface circuit diagram of the power substrate of the silicon carbide power module of the present invention and the location of the silicon carbide power semiconductor chip; Figure 3 A schematic diagram of the current planning interconnection structure of the present invention; Figure 4 A schematic diagram of the internal current flow of the silicon carbide power module of the present invention; Figure 5 It is a top view schematic diagram of a terminal direct-connected capacitor structure of the present invention; Figure 6 It is a schematic side view of the terminal direct-connected capacitor structure of the present invention.

[0026] Wherein: 100. power substrate; 111. first drain region of upper bridge arm of upper conductive layer of power substrate; 112. second drain region of upper bridge arm of upper conductive layer of power substrate; 113. source region of lower bridge arm of upper conductive layer of power substrate; 114. source region of upper bridge arm of upper conductive layer of power substrate; 115. first drain region of lower bridge arm of upper conductive layer of power substrate; 116. second drain region of lower bridge arm of upper conductive layer of power substrate; 200. current planning interconnection structure; 201. current planning interconnection structure of lower bridge arm; 202. current planning interconnection structure of upper bridge arm; 211. first chip connector of lower bridge arm; 212. second chip connector of lower bridge arm; 213. The third chip connector of the lower bridge arm; 214. The fourth chip connector of the lower bridge arm; 215. The fifth chip connector of the lower bridge arm; 216. The sixth chip connector of the lower bridge arm; 217. The seventh chip connector of the lower bridge arm; 218. The eighth chip connector of the lower bridge arm; 221. The first chip connector of the upper bridge arm; 222. The second chip connector of the upper bridge arm; 223. The third chip connector of the upper bridge arm; 224. The fourth chip connector of the upper bridge arm; 225. The fifth chip connector of the upper bridge arm; 226. The sixth chip connector of the upper bridge arm; 227. The seventh chip connector of the upper bridge arm; 228. The eighth chip connector of the upper bridge arm; 231. The first substrate connector of the lower bridge arm; 232 . The second substrate connector of the lower bridge arm; 233. The third substrate connector of the lower bridge arm; 241. The first substrate connector of the upper bridge arm; 242. The second substrate connector of the upper bridge arm; 251. The first connector of the AC lead-out terminal; 252. The second connector of the AC lead-out terminal; 300. Silicon carbide power semiconductor chip; 311. The first chip of the lower bridge arm; 312. The second chip of the lower bridge arm; 313. The third chip of the lower bridge arm; 314. The fourth chip of the lower bridge arm; 315. The fifth chip of the lower bridge arm; 316. The sixth chip of the lower bridge arm; 317. The seventh chip of the lower bridge arm; 318. The eighth chip of the lower bridge arm; 321. The first chip of the upper bridge arm; 322. The second chip of the upper bridge arm Chip; 323. The third chip of the upper bridge arm; 324. The fourth chip of the upper bridge arm; 325. The fifth chip of the upper bridge arm; 326. The sixth chip of the upper bridge arm; 327. The seventh chip of the upper bridge arm; 328. The eighth chip of the upper bridge arm; 400. The AC lead-out power terminal; 410. The DC lead-out power terminal; 411. The first positive terminal of the DC bus; 412. The second positive terminal of the DC bus; 413. The negative terminal of the DC bus; 501. The metal base plate; 511. The bottom shell; 512. The top shell; 600. The terminal is directly connected to the capacitor structure; 610. The circuit board is directly connected; 620. The low-inductance capacitor; 630. The high-capacitance capacitor. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "one side", "one end", "one side" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0032] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0034] The present invention provides a low-inductance silicon carbide power module and commutation loop structure, comprising a power substrate 100 and a current planning interconnection structure 200 connected to a conductive layer on the upper surface of the power substrate 100, a silicon carbide power semiconductor chip 300 is arranged between the power substrate 100 and the current planning interconnection structure 200, and the silicon carbide power semiconductor chip 300 is mounted on the upper surface of the power substrate 100; The direction of the current on the power substrate 100 is opposite to the direction of the current on the current planning interconnect structure 200; The current planning interconnect structure 200 includes a lower bridge arm current planning interconnect structure 201 and an upper bridge arm current planning interconnect structure 202 which is arranged oppositely, and both the lower bridge arm current planning interconnect structure 201 and the upper bridge arm current planning interconnect structure 202 which are arranged oppositely include a chip connector and a substrate connector, wherein the chip connector and the substrate connector are electrically connected, the chip connector is used to connect to the silicon carbide power semiconductor chip 300, and the substrate connector is used to connect to the power substrate 100, and the current planning interconnect structure 200 realizes electrical connection with the conductive layer of the power substrate 100 through the silicon carbide power semiconductor chip 300; An AC lead-out power terminal 400 is connected to the outer side of the upper bridge arm current planning interconnection structure 202, and correspondingly, a DC lead-out power terminal 410 is provided on the outer side of the lower bridge arm current planning interconnection structure 201, and a terminal direct-connected capacitor structure 600 is arranged on the upper surface of the DC lead-out power terminal 410, and one end of the lead-out power terminal 410 is arranged on the power substrate 100. In this embodiment, the terminal direct-connected capacitor structure 600 is connected to the lead-out power terminal 410 by directly connecting the bottom of the circuit board 610. Specifically, the terminal direct-connected capacitor structure 600 includes a DC circuit board 610, a low-inductance capacitor 620 and a high-capacitance capacitor 620. The direct-connected circuit board 610 is made of a printed circuit board or a laminated busbar according to its required working current. The DC lead-out power terminal 410 is provided with a DC bus positive first terminal 411, a DC bus positive second terminal 412 and a DC bus positive terminal 413. The DC bus negative terminal 413, the DC circuit board 610 is connected to the DC bus positive first terminal 411, the DC bus positive second terminal 412 and the DC bus negative terminal 413, and the connection method includes solder welding, micro-nano metal particle sintering or laser welding, and a low-inductance capacitor 620, such as a ceramic capacitor and a silicon chip capacitor, is arranged on the side close to the DC lead-out power terminal 410, and a high-capacitance capacitor 630, such as a film capacitor and an electrolytic capacitor, is arranged on the side away from the DC lead-out power terminal 410.

[0035] In one feasible implementation, a groove is formed in the center of the upper surface of the power substrate 100 for mounting the silicon carbide power semiconductor chip 300; The upper surface conductive layer of the power substrate 100 mainly includes an upper bridge arm drain first region 111, an upper bridge arm drain second region 112, a lower bridge arm source region 113, and an upper bridge arm source region 114. In addition, it also includes a lower bridge arm drain first region 115 and a lower bridge arm drain second region 116. The lower bridge arm drain first region 115, the lower bridge arm drain second region 116, and the lower bridge arm source region 113 are arranged between the upper bridge arm drain first region 111 and the upper bridge arm drain second region 112. The lower bridge arm source region 113 and the upper bridge arm source region 114 are arranged at both ends of the power substrate 100.

[0036] In another embodiment, the lower surface of the silicon carbide power semiconductor chip 300 is arranged on the upper conductive layer of the power substrate 100 to complete the electrical connection and transfer heat, and the upper surface of the silicon carbide power semiconductor chip 300 is provided with a current planning interconnect structure 200 to complete the electrical connection of the upper surface; The silicon carbide power semiconductor chip 300 includes a first chip 311 of a lower bridge arm, a second chip 312 of a lower bridge arm, a third chip 313 of a lower bridge arm, a fourth chip 314 of a lower bridge arm, a fifth chip 315 of a lower bridge arm, a sixth chip 316 of a lower bridge arm, a seventh chip 317 of a lower bridge arm and an eighth chip 318 of a lower bridge arm, and a first chip 321 of an upper bridge arm, a second chip 322 of an upper bridge arm, a third chip 323 of an upper bridge arm, a fourth chip 324 of an upper bridge arm, a fifth chip 325 of an upper bridge arm, a sixth chip 326 of an upper bridge arm, a seventh chip 327 of an upper bridge arm and an eighth chip 328 of an upper bridge arm arranged corresponding to the lower bridge arm; The current planning interconnect structure 200 is an integrally formed high-conductivity metal structure that simultaneously connects one side or all the upper surfaces of parallel chips with the same potential. The overall structure includes three height layers: a substrate layer, a chip layer, and a routing layer. The substrate layer is connected to the power substrate 100, the chip layer is connected to the silicon carbide power semiconductor chip 300, and the routing layer completes the electrical routing and provides a transition connection joint to the substrate layer and the chip layer.

[0037] The wiring layer layout of the current planning interconnection structure 200 is arranged according to the current flow direction during the internal commutation process of the power module, so that the current direction of the wiring layer of the current planning interconnection structure 200 is opposite to the current direction of the conductive layer on the power substrate 100 facing it; Correspondingly, a chip connector connected to the lower bridge arm chip is provided on the lower bridge arm current planning interconnect structure 201 of the current planning interconnect structure 200, including a lower bridge arm first chip connector 211, a lower bridge arm second chip connector 212, a lower bridge arm third chip connector 213, a lower bridge arm fourth chip connector 214, a lower bridge arm fifth chip connector 215, a lower bridge arm sixth chip connector 216, a lower bridge arm seventh chip connector 217 and a lower bridge arm eighth chip connector 218; in the upper bridge arm current planning interconnect structure 200, The planning interconnect structure 202 is provided with chip connectors connected to the upper bridge arm chips, including the upper bridge arm first chip connector 221, the upper bridge arm second chip connector 222, the upper bridge arm third chip connector 223, the upper bridge arm fourth chip connector 224, the upper bridge arm fifth chip connector 225, the upper bridge arm sixth chip connector 226, the upper bridge arm seventh chip connector 227 and the upper bridge arm eighth chip connector 228, and the chips on the silicon carbide power semiconductor chip 300 correspond one to one to the chip connectors on the current planning interconnect structure 200; The height of the wiring layer of the current planning interconnect structure 200 is as small as possible from the upper conductive layer of the power substrate 100 while ensuring the necessary insulation gap; In addition, a substrate connector electrically connected to the lower bridge arm chip connector is provided on the lower bridge arm current planning interconnection structure 201, including a lower bridge arm first substrate connector 231, a lower bridge arm second substrate connector 232 and a lower bridge arm third substrate connector 233; a substrate connector electrically connected to the upper bridge arm chip connector is provided on the upper bridge arm current planning interconnection structure 202, including an upper bridge arm first substrate connector 241 and an upper bridge arm second substrate connector 242; The outer side of the upper bridge arm current planning interconnection structure 202 is connected to the first lead-out power terminal 400 through the first AC lead-out terminal connector 251 and the second AC lead-out terminal connector 352 .

[0038] In another embodiment of the present invention, the power substrate 100, the silicon carbide power semiconductor chip 300 mounted on the power substrate 100, and the current planning interconnection structure 200 are arranged together in the bottom shell 511 and the top shell 512, and the bottom of the power substrate 100 is also connected to a metal base plate.

[0039] In another embodiment of the present invention, a low-inductance silicon carbide power module and commutation circuit structure is provided, including a large-area current planning interconnection structure 200 and an extremely short path terminal direct-connected capacitor structure 600. The mutual inductance between the large-area current planning interconnection structure 200 and the conductive line of the ceramic substrate greatly reduces the parasitic inductance inside the silicon carbide power module. At the same time, the terminal direct-connected capacitor structure 600 is used to shorten the path length from the terminal lead-out position inside the power module to the external capacitor, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, thereby reducing the parasitic inductance of the entire commutation circuit, suppressing the overshoot and oscillation of the switching voltage, and reducing the working loss.

[0040] See also Figure 1 The present invention discloses a low inductance silicon carbide power module and a commutation circuit structure. The silicon carbide power module is a single-sided heat dissipation structure, including a power substrate 100, a current planning interconnection structure 200, a silicon carbide power semiconductor chip 300, an AC lead-out power terminal 400, a DC lead-out power terminal 410, a metal base plate 501, a bottom shell 511, a top shell 512 and a terminal direct-connected capacitor structure 600.

[0041] See also Figure 2 The upper surface conductive area of ​​the power substrate 100 mainly includes the upper bridge arm drain first area 111, the upper bridge arm drain second area 112, the lower bridge arm source area 113, and the upper bridge arm source area 114. The silicon carbide power semiconductor core 300 is divided into two groups. The upper bridge arm chip is installed in the upper bridge arm drain first area 111 and the upper bridge arm drain second area 112, and the lower bridge arm chip is installed in the lower bridge arm drain first area 115 and the lower bridge arm drain second area 116.

[0042] See also Figure 3 The current planning interconnection structure 200 includes a lower bridge arm current planning interconnection structure 201 and an upper bridge arm current planning interconnection structure 202. The lower bridge arm current planning interconnection structure 201 includes a chip connector and a substrate connector, and the upper bridge arm current planning interconnection structure 202 includes a chip connector, a substrate connector and an AC lead-out terminal connector.

[0043] See also Figure 4During the commutation process of the silicon carbide power module, the current flows from the upper bridge arm drain region, passes through the upper bridge arm chip, flows into the upper bridge arm current planning interconnection structure 202, then flows into the lower bridge arm drain region, passes through the lower bridge arm chip, flows into the lower bridge arm current planning interconnection structure 201, and finally reaches the lower bridge arm source region 113.

[0044] See also Figure 5 The terminal direct-connected capacitor structure 600 is connected to the DC bus positive terminals 411 , 412 and the DC bus negative terminal 413 , and includes a direct-connected circuit board 610 , a low-inductance capacitor 620 and a high-capacitance capacitor 630 .

[0045] See also Figure 6 The terminal direct-connected capacitor structure 600 is connected to the DC lead-out power terminal 410 by directly connecting the bottom of the circuit board 610, and a low-inductance capacitor 620 is arranged on the side close to the terminal, and a high-capacitance capacitor 630 is arranged on the side far from the terminal.

[0046] In an optional implementation, this embodiment includes 1 silicon carbide power module, which includes 16 silicon carbide power semiconductor chips, forming a half-bridge structure. In actual work, other topologies can be formed as needed. The number of parallel chips can be increased or decreased to change the current capacity or the number of series chips can be increased or decreased to change the voltage resistance. Anti-parallel diode chips can also be added as needed.

[0047] 1. Use current planning interconnect structure 200 to control parasitic inductance inside the power module: See also Figure 2 , Figure 3 A current planning interconnection structure 200 is arranged on the upper surface conductive layer corresponding to the power substrate 100 to complete the upper surface interconnection, the upper bridge arm chip of the silicon carbide power semiconductor chip 300 corresponds to the upper bridge arm current planning interconnection structure 202, and the lower bridge arm chip of the silicon carbide power semiconductor chip 300 corresponds to the lower bridge arm current planning interconnection structure 201.

[0048] The arrangement principle of the current planning interconnect structure 200 is to first make the current direction of the conductive layer on the power substrate 100 opposite to the current direction on the current planning interconnect structure 200 during commutation, and then make the distance between the conductive path of the current planning interconnect structure 200 and the conductive layer on the power substrate 100 as small as possible.

[0049] See also Figure 4The commutation loop current starts from the upper bridge arm drain region, flows through the upper bridge arm chip and then flows into the upper bridge arm current planning interconnection structure 202, and flows through the area on the upper bridge arm current planning interconnection structure 202 opposite to the upper bridge arm drain region, and the current direction is opposite to that of the upper bridge arm drain region; then flows into the lower bridge arm drain region, and after an extremely short current path, it converges into the lower bridge arm chip, and then flows upward into the lower bridge arm current planning interconnection structure 201. The current direction on the lower bridge arm current planning interconnection structure 201 is still opposite to that of the upper bridge arm drain region, and finally flows into the lower bridge arm source region 113 and flows out of the power module.

[0050] In the entire conductive path, the upper bridge arm drain region with the longest path on the power substrate 100 is weakened in parasitic inductance by the mutual inductance of currents in opposite directions by the lower bridge arm current planning interconnection structure 201 and the upper bridge arm current planning interconnection structure 202, and the inductance of the current planning interconnection structure 200 is reduced at the same time, thereby reducing the parasitic inductance inside the power module.

[0051] 2. Use terminal direct connection capacitor structure 600 to control external parasitic inductance of power module See also Figure 5 , Figure 6 In the half-bridge structure, capacitors need to be installed between the DC bus positive first terminal 411, the DC bus positive second terminal 412 and the DC bus negative terminal 413 to achieve voltage stabilization and filtering. A terminal direct-connected capacitor structure 600 is used above the DC lead-out power terminal 410 to directly connect the direct-connected circuit board 610 to the DC bus positive first terminal 411, the DC bus positive second terminal 412 and the DC bus negative terminal 413, and a low-inductance capacitor 620 is placed near the DC lead-out power terminal 410 to limit the area of ​​the commutation loop outside the power module to a very small range, shorten the loop path and thus reduce the area of ​​the external loop of the power module, and place a high-capacitance capacitor 630 far away from the DC lead-out power terminal 410 to meet the requirements of reliable voltage stabilization.

[0052] 3. Effect evaluation Control of the internal inductance of the power module: After adopting the method of the present invention, the internal parasitic inductance of the power module can be controlled from >8nH to <4nH, and the internal parasitic inductance of the power module can be reduced by more than 50%; Power module external inductance control: After adopting the method of the present invention, the parasitic inductance of the external loop of the power module is controlled from >12nH to <2nH, and the external parasitic inductance of the power module is reduced by more than 80%; Control of overall parasitic inductance of the commutation loop: After adopting the method of the present invention, the overall parasitic inductance of the commutation loop is controlled from >20nH to <5nH, and the overall parasitic inductance of the commutation loop is reduced by more than 75%.

[0053] In summary, the present invention provides a low inductance silicon carbide power module and commutation circuit structure, which greatly reduces the parasitic inductance inside the silicon carbide power module through the mutual inductance between the large-area current planning interconnect structure 200 and the conductive circuit of the ceramic substrate. At the same time, the terminal direct-connected capacitor structure 600 is utilized to shorten the path length from the terminal lead-out position inside the power module to the external capacitor, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, thereby reducing the parasitic inductance of the entire commutation circuit.

[0054] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A low inductance silicon carbide power module and commutation circuit structure, characterized in that: Comprising a power substrate (100), a silicon carbide power semiconductor chip (300) being mounted on the upper surface of the power substrate (100), a current planning interconnection structure (200) having a current direction opposite to that of the power substrate (100) being arranged above the silicon carbide power semiconductor chip (300), and the current planning interconnection structure (200) being connected to the conductive layer of the power substrate (100) via the silicon carbide power semiconductor chip (300); The current planning interconnection structure (200) comprises a lower bridge arm current planning interconnection structure (201) and an upper bridge arm current planning interconnection structure (202) arranged opposite to each other, wherein both the lower bridge arm current planning interconnection structure (201) and the upper bridge arm current planning interconnection structure (202) arranged opposite to each other are provided with a chip connector and a substrate connector electrically connected to the chip connector; The upper bridge arm current planning interconnection structure (202) is connected to an AC lead-out power terminal (400), a DC lead-out power terminal (410) is provided outside the lower bridge arm current planning interconnection structure (201), and a terminal direct-connected capacitor structure (600) is provided on the DC lead-out power terminal (410).

2. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: The terminal directly connected capacitor structure (600) comprises a DC circuit board (610) electrically connected to a DC lead-out power terminal (410), and a plurality of capacitors are arranged on the DC circuit board (610).

3. The low inductance silicon carbide power module and commutation circuit structure according to claim 2, characterized in that: A capacitor with a high capacitance value among the plurality of capacitors is arranged outside the DC lead-out power terminal (410).

4. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: An AC lead-out terminal connector is provided on the outer side of the upper bridge arm current planning interconnection structure (202), and an AC lead-out power terminal (400) is connected to the AC lead-out terminal connector.

5. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: The plane where the current planning interconnection structure (200) is located is parallel to the upper surface of the power substrate.

6. The low inductance silicon carbide power module and commutation circuit structure according to claim 1 or 5, characterized in that: The current planning interconnection structure (200) is provided with a through hole having the same shape as the silicon carbide power semiconductor chip (300).

7. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: The upper surface of the power substrate (100) is grooved.

8. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: The silicon carbide power semiconductor chip (300) comprises an upper bridge arm chip and a lower bridge arm chip, the upper bridge arm current planning interconnection structure (202) is arranged above the upper bridge arm chip, and the lower bridge arm current planning interconnection structure (201) is arranged above the lower bridge arm chip; The upper bridge arm chip is electrically connected to the upper bridge arm drain on the power substrate (100), and the lower bridge arm chip is electrically connected to the lower bridge arm drain on the power substrate (100).

9. The low inductance silicon carbide power module and commutation circuit structure according to claim 1, characterized in that: The power substrate (100) and the current planning interconnection structure (200) are externally wrapped with a bottom shell (511) and a top shell (512).

10. The low inductance silicon carbide power module and commutation circuit structure according to claim 9, characterized in that: The bottom of the power substrate (100) is connected to a metal base plate (501).

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