Semiconductor device and manufacturing method thereof, and semiconductor device offset amount determination method

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a semiconductor device offset determination method. The semiconductor device comprises a first semiconductor structure, wherein a first alignment mark is arranged in the first semiconductor structure; the second semiconductor structure and the first semiconductor structure are stacked in the first direction; a second alignment mark is arranged in the second semiconductor structure; the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; each of the first alignment mark and the second alignment mark comprises a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; therefore, the alignment efficiency and the alignment precision of the first semiconductor structure and the second semiconductor structure can be improved, and the reliability and the yield of the semiconductor device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a method for determining an offset of a semiconductor device. Background Art

[0002] With the increasing demand for efficiency and miniaturization of big data analysis in the fields of Internet of Things (IoT), artificial intelligence (AI), three-dimensional imaging (3D), etc., the bonding method of chips plays a vital role in semiconductor manufacturing. Hybrid bonding has higher interconnection density and interconnection accuracy than flip chip bonding and wire bonding, and is widely used in the semiconductor field. Hybrid bonding can achieve an interconnection pitch of less than 10 microns (um), and can reduce parasitic capacitance and resistance after directly interconnecting the metal and metal between chips; at the same time, direct bonding allows better heat dissipation, can eliminate solder bumps, and reduce thermal stress of interconnected metals.

[0003] However, under the requirements of high-density and high-precision technology, how to determine the alignment between chips has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, in order to solve one or more of the existing technical problems, an embodiment of the present disclosure proposes a semiconductor device, comprising: a first semiconductor structure; a first alignment mark is arranged in the first semiconductor structure; a second semiconductor structure is stacked and arranged with the first semiconductor structure in a first direction; a second alignment mark is arranged in the second semiconductor structure; the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; wherein the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0005] In some embodiments, the outer boundary size of the first image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the first alignment mark in the third direction; the outer boundary size of the first image in the first alignment mark in the second direction is the same as the outer boundary size of the third image in the first alignment mark in the second direction.

[0006] In some embodiments, the outer boundary size of the second image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the second alignment mark in the third direction; the outer boundary size of the third image in the first alignment mark in the second direction is the same as the outer boundary size of the third image in the second alignment mark in the second direction.

[0007] In some embodiments, the first image includes a circle, an annular ring, a square, a matrix or a cross-shaped pattern; the second image includes a plurality of long strip patterns evenly arranged along the third direction; the third image includes a plurality of long strip patterns evenly arranged along the second direction; the fourth image includes a long strip pattern extending along the fourth direction, and / or a plurality of circular patterns evenly arranged in a straight line or arc in a direction perpendicular to the fourth direction.

[0008] In some embodiments, the number of long strip graphics in the second image of the first alignment mark is the same as the number of long strip graphics in the second image of the second alignment mark; and / or the number of long strip graphics in the third image of the first alignment mark is the same as the number of long strip graphics in the third image of the second alignment mark.

[0009] In some embodiments, the sizes of the plurality of long strip-shaped graphics in the second image and / or the third image are different in their extending direction.

[0010] In some embodiments, among the multiple long strip graphics of the second image or the third image, the size of a portion of the long strip graphics in the extension direction is a first size, and the size of another portion of the long strip graphics in the extension direction is a second size; wherein the long strip graphics with the first size and the long strip graphics with the second size are arranged alternately.

[0011] In some embodiments, the first image in the first alignment mark at least partially overlaps the first image in the second alignment mark in the first direction.

[0012] In some embodiments, when the first alignment mark and the second alignment mark completely overlap in the first direction, multiple long strip graphics in the second image of the first alignment mark are aligned one by one with multiple long strip graphics in the second image of the second alignment mark in the second direction; and multiple long strip graphics in the third image of the first alignment mark are aligned one by one with multiple long strip graphics in the third image of the second alignment mark in the third direction.

[0013] The embodiment of the present disclosure also provides a method for determining the offset of a semiconductor device, wherein the semiconductor device is the semiconductor device described in the above embodiment of the present disclosure, and the determination method comprises: obtaining a layer image of the semiconductor device on a first plane; the layer image comprises a first alignment mark and a second alignment mark; the semiconductor device comprises a first semiconductor structure and a second semiconductor structure stacked and arranged in a first direction, the first semiconductor structure is provided with the first alignment mark, and the second semiconductor structure is provided with the second alignment mark; the first plane is perpendicular to the first direction; the offset between the first semiconductor structure and the second semiconductor structure is determined by the relative position of the first alignment mark and the second alignment mark; wherein the first alignment mark and the second alignment mark both comprise a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0014] In some embodiments, determining the offset between the first semiconductor structure and the second semiconductor structure by the relative position of the first alignment mark and the second alignment mark includes: determining the offset between the first semiconductor structure and the second semiconductor structure in the third direction by the relative position between the second image of the first alignment mark and the second image of the second alignment mark; determining the offset between the first semiconductor structure and the second semiconductor structure in the second direction by the relative position between the third image of the first alignment mark and the third image of the second alignment mark; determining the rotational offset between the first semiconductor structure and the second semiconductor structure along the clockwise / counterclockwise direction on the first plane by the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark.

[0015] The disclosed embodiment also proposes a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure; providing a first alignment mark in the first semiconductor structure; forming a second semiconductor structure; providing a second alignment mark in the second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure in a first direction; wherein the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0016] In the disclosed embodiment, a first alignment mark is set in the first semiconductor structure, a second alignment mark is set in the second semiconductor structure, and both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; after the first semiconductor structure and the second semiconductor structure are stacked and bonded, the offsets of the first semiconductor structure and the second semiconductor structure in multiple directions are determined by the alignment of the first image, the second image, the third image, and the fourth image in the first alignment mark with the first image, the second image, the third image, and the fourth image in the second alignment mark. In this way, on the one hand, the offsets of the first semiconductor structure and the second semiconductor structure can be directly determined by manual visual inspection without the need for additional equipment, thereby improving the alignment efficiency; on the other hand, the alignment results of multiple groups of images can more accurately reflect the specific position of the misalignment, and the alignment accuracy can be improved by comparing the alignment results of multiple groups, thereby improving the reliability and yield of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the alignment of four groups of alignment marks in the related art provided by the present disclosure; Figure 2 A schematic diagram of a first semiconductor structure and a second semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a first alignment mark provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a first alignment mark provided in another embodiment of the present disclosure; Figure 5 A schematic diagram of a second alignment mark provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of a second alignment mark provided in another embodiment of the present disclosure; Figure 7 Schematic diagrams of specific shapes of three first alignment marks provided in one embodiment of the present disclosure; Figure 8 Schematic diagrams of specific shapes of three second alignment marks provided in one embodiment of the present disclosure; Fig. 9 A schematic diagram showing that three groups of first alignment marks and second alignment marks are fully aligned according to an embodiment of the present disclosure; Fig.10 A schematic diagram showing that three groups of first alignment marks and second alignment marks are offset from each other in one embodiment of the present disclosure; Fig.11 A schematic flow chart of a method for determining an offset of a semiconductor device provided by an embodiment of the present disclosure; Fig.12 A schematic flow chart of a method for manufacturing a semiconductor device provided in one embodiment of the present disclosure.

[0018] In the above drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0019] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0021] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0023] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0026] There are two main hybrid bonding process methods: wafer-to-wafer hybrid bonding and chip-to-wafer hybrid bonding. Under the requirements of high-density and high-precision technology, whether the position between wafers (die) and wafers after bonding is accurate can be determined by the alignment of the alignment marks between the wafers (die) and the wafers, or it can be determined by electrical measurements.

[0027] On the one hand, reference Figure 1 , Figure 1 The figure shows the alignment of four groups of alignment marks; wherein the first mark 101 is located in the first wafer, and the second mark 102 is located in the second wafer; Figure 1 It can be seen that the offset between the first wafer and the second wafer in the X-axis direction and / or the Y-axis direction can be roughly determined by the alignment of the first mark 101 and the second mark 102, but it cannot be determined whether the first wafer and the second wafer are rotated.

[0028] On the other hand, when using electrical test results to judge alignment, if no electrical information is detected during the electrical test (or inline test), there will be a deviation between the electrical test data and the predicted offset value, which cannot effectively reflect the alignment. In addition, the alignment reflected by the electrical test results is relatively rough and not accurate enough, resulting in signal delays in some semiconductor devices that have passed the electrical test due to inaccurate alignment.

[0029] Based on one or more of the above problems, an embodiment of the present disclosure proposes a semiconductor device. The semiconductor device includes a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure; a second semiconductor structure is stacked and arranged with the first semiconductor structure in a first direction; a second alignment mark is provided in the second semiconductor structure; the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; wherein the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0030] In this way, a first alignment mark can be set in the first semiconductor structure, a second alignment mark can be set in the second semiconductor structure, and both the first alignment mark and the second alignment mark include a first image, a second image, a third image, and a fourth image; after the first semiconductor structure and the second semiconductor structure are stacked and bonded, the offsets of the first semiconductor structure and the second semiconductor structure in multiple directions can be determined by aligning the first image, the second image, the third image, and the fourth image in the first alignment mark with the first image, the second image, the third image, and the fourth image in the second alignment mark. In this way, on the one hand, the offsets of the first semiconductor structure and the second semiconductor structure can be directly determined by manual visual inspection without the need for additional equipment, thereby improving the alignment efficiency; on the other hand, the alignment results of multiple groups of images can more accurately reflect the specific position of the misalignment, and the alignment accuracy can be improved by comparing the alignment results of multiple groups, thereby improving the reliability and yield of semiconductor devices.

[0031] Before introducing the semiconductor device proposed in the present disclosure in detail, various directions that may be used in the following description are defined first. In the present disclosure, the stacking direction of the first semiconductor structure and the second semiconductor structure is defined as a first direction (such as the Z-axis direction). In a plane perpendicular to the Z-axis direction, an intersecting second direction (such as the X-axis direction), a third direction (such as the Y-axis direction) and a fourth direction (such as the P direction) are defined. Here, the first direction, the second direction and the third direction are perpendicular to each other, that is, the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other. The fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction, that is, the P direction is perpendicular to the Z-axis direction, and the P direction intersects with both the X-axis direction and the Y-axis direction. It should be noted that based on the different extension directions of the X-axis and the Y-axis, the P direction can include two directions.

[0032] refer to Figure 2 The first semiconductor structure 201 and the second semiconductor structure 202 are stacked and arranged in the Z-axis direction. The first semiconductor structure 201 may be provided with a storage unit (not shown in the figure) and a first alignment mark 203, and the second semiconductor structure 202 may be provided with a logic circuit (not shown in the figure) and a second alignment mark 204. From the material level, the first semiconductor structure 201 and the second semiconductor structure 202 both include a silicon substrate and a metal layer, and the silicon substrate may include a silicon dioxide layer and a silicon dielectric layer.

[0033] Here, the first semiconductor structure 201 and the second semiconductor structure 202 may be bonded face to face by hybrid bonding, and the alignment of the first semiconductor structure 201 and the second semiconductor structure 202 may be determined by the overlap of the first alignment mark 203 and the second alignment mark 204 in the Z-axis direction. Figure 2When the first alignment mark 203 and the second alignment mark 204 completely overlap in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are completely aligned. When the first alignment mark 203 and the second alignment mark 204 partially overlap in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are partially aligned, that is, there is an offset between the two. When the first alignment mark 203 and the second alignment mark 204 do not overlap at all in the Z-axis direction, it indicates that the first semiconductor structure 201 and the second semiconductor structure 202 are completely misaligned.

[0034] The first alignment mark and the second alignment mark are described in detail below with reference to the accompanying drawings.

[0035] The graphics of the first alignment mark and the graphics of the second alignment mark may be the same or different. In the embodiment of the present disclosure, the first alignment mark and the second alignment mark both include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in the X-axis direction; the third image is located on at least one side of the first image in the Y-axis direction; and the fourth image is located on at least one side of the first image in the P direction. In other words, the second image, the third image, and the fourth image surround the first image.

[0036] refer to Figure 3 and Figure 4 The first alignment mark 203 includes a first image 301, a second image 302, a third image 303 and a fourth image 304, wherein: Figure 3 In the illustrated first alignment mark 203 , the second image 302 , the third image 303 , and the fourth image 304 are respectively located only on one side of the first image 301 ; Figure 4 In the first alignment mark 203 shown, the second image 302 is located on two opposite sides of the first image 301 in the X-axis direction; the third image 303 is located on two opposite sides of the first image 301 in the Y-axis direction; the fourth image 304 is located on two opposite sides of the first image 301 in the P direction (it should be understood that the P direction includes two directions, and here, the fourth image 304 is located on four sides of the first image 301).

[0037] In some embodiments, reference Figure 3 , the outer boundary size L1 of the first image 301 in the first alignment mark 203 in the Y-axis direction is the same as the outer boundary size L2 of the second image 302 in the first alignment mark in the Y-axis direction, that is, L1=L2; the outer boundary size L3 of the first image 301 in the first alignment mark in the X-axis direction is the same as the outer boundary size L4 of the third image 303 in the first alignment mark in the X-axis direction, that is, L3=L4. It should be understood that the outer boundary size is the size of the outermost edge of the image.

[0038] refer to Figure 5 and Figure 6 The second alignment mark 204 includes a first image 501, a second image 502, a third image 503 and a fourth image 504, wherein: Figure 5 In the second alignment mark 204 shown, the second image 502 , the third image 503 , and the fourth image 504 are respectively located only on one side of the first image 501 ; Figure 6 In the second alignment mark 204 shown, the second image 502 is located on the opposite sides of the first image 501 in the X-axis direction; the third image 503 is located on the opposite sides of the first image 501 in the Y-axis direction; the fourth image 504 is located on the opposite sides of the first image 501 in the P direction (it should be understood that the P direction includes two directions, here, the fourth image 504 is located on the four sides of the first image 501).

[0039] In some embodiments, in conjunction with reference Figure 3 and Figure 5 , the outer boundary size L2 of the second image 302 in the first alignment mark 203 in the Y-axis direction is the same as the outer boundary size R2 of the second image 502 in the second alignment mark 204 in the Y-axis direction; that is, L2=R2. The outer boundary size L4 of the third image 303 in the first alignment mark 203 in the X-axis direction is the same as the outer boundary size R4 of the third image 503 in the second alignment mark 204 in the X-axis direction, that is, L4=R4.

[0040] In this way, during the process of aligning the first alignment mark 203 and the second alignment mark 204, the offset between the first semiconductor structure and the second semiconductor structure in the Y-axis direction can be more intuitively determined by comparing the two second images with the same outer boundary size; and the offset between the first semiconductor structure and the second semiconductor structure in the X-axis direction can be more intuitively determined by comparing the two third images with the same outer boundary size.

[0041] In some embodiments, in conjunction with reference Figure 4 and Figure 6, the distance L5 between the second image 302 in the first alignment mark 203 and the third image 303 in the first alignment mark 203 in the X-axis direction is less than the distance R5 between the second image 502 in the second alignment mark 204 and the third image 503 in the second alignment mark 204 in the X-axis direction, that is, L5<R5. And the distance L6 between the second image 302 in the first alignment mark 203 and the third image 303 in the first alignment mark 203 in the Y-axis direction is less than the distance R6 between the second image 502 in the second alignment mark 204 and the third image 503 in the second alignment mark 204 in the Y-axis direction, that is, L6<R6. In this way, during the alignment process, the second image 302 in the first alignment mark 203 and the second image 502 in the second alignment mark 204 can be misaligned and compared, and the third image 303 in the first alignment mark 203 and the third image 503 in the second alignment mark 204 can be misaligned and compared. In this way, the offset between the first alignment mark and the second alignment mark can be determined more intuitively.

[0042] In some embodiments, the outer boundary size of the first image in the second alignment mark in the Y-axis direction may be the same as or different from the outer boundary size of the second image in the second alignment mark in the Y-axis direction. The outer boundary size of the first image in the second alignment mark in the X-axis direction may be the same as or different from the outer boundary size of the third image in the second alignment mark in the X-axis direction. When the sizes of the two are different, it indicates that the sizes of the first image in the first alignment mark and the first image in the second alignment mark are different, which is conducive to comparing the first image in the first alignment mark with the first image in the second alignment mark.

[0043] Exemplary, reference Figure 5, the outer boundary dimension R1 of the first image 501 in the second alignment mark in the Y-axis direction is smaller than the outer boundary dimension R2 of the second image 502 in the second alignment mark in the Y-axis direction, that is, R1<R2; the outer boundary dimension R3 of the first image 501 in the second alignment mark in the X-axis direction is smaller than the outer boundary dimension R4 of the third image 503 in the second alignment mark in the X-axis direction, that is, R3<R4. In other words, in this embodiment, the outer boundary dimension R1 of the first image 501 in the second alignment mark 204 in the Y-axis direction is smaller than the outer boundary dimension L1 of the first image 301 in the first alignment mark in the Y-axis direction, that is, R1<L1. The outer boundary dimension R3 of the first image 501 in the second alignment mark in the X-axis direction is smaller than the outer boundary dimension L3 of the first image 301 in the first alignment mark in the X-axis direction, that is, R3<L3. In this way, during the alignment process of the first alignment mark 203 and the second alignment mark 204, the first image 301 in the first alignment mark and the first image 501 in the second alignment mark can be made not to completely overlap (i.e., there is a misalignment), so that the offset position of the two can be determined more intuitively and the difficulty of identification can be reduced.

[0044] It should be noted that the fourth image in the first alignment mark and the fourth image in the second alignment mark can be used to determine the offset of the first semiconductor structure and the second semiconductor structure in the clockwise / counterclockwise direction on the XY plane, that is, the rotation offset of the first semiconductor structure and the second semiconductor structure on the XY plane. The following is a detailed description in conjunction with the specific graphics of the image.

[0045] In some embodiments, the first image includes a circle, annular ring, square, matrix or cross-shaped pattern; the second image includes a plurality of long strip patterns evenly arranged along the Y-axis direction; the third image includes a plurality of long strip patterns evenly arranged along the X-axis direction; the fourth image includes a long strip pattern extending along the P direction, and / or a plurality of circular patterns evenly arranged in straight lines or arcs in a direction perpendicular to the P direction.

[0046] Here, the multiple long strips in the second image and the third image are evenly arranged, indicating that the multiple long strips divide the size of the second image and the third image equally, and each of the multiple long strips occupies the same size. Figure 3 and Figure 5 When the second image 302 in the first alignment mark 203 and the second image 502 in the second alignment mark 204 have the same shape, the offset between the two on the Y axis can be quickly determined by the number of long strips of graphics that are offset between the two. Similarly, when the third image 303 in the first alignment mark 203 and the third image 503 in the second alignment mark 204 have the same shape, the offset between the two on the X axis can be quickly determined by the number of long strips of graphics that are offset between the two.

[0047] It should be understood that the shapes of the first image in the first alignment mark and the first image in the second alignment mark may be the same or different; the shapes of the fourth image in the first alignment mark and the fourth image in the second alignment mark may be the same or different.

[0048] Exemplary, reference Figure 7 , Figure 7 Schematic diagrams of specific shapes of three first alignment marks 203 are shown; among them, Figure 7 In (1), the first image 301 is a ring shape, the second image 302 is a plurality of long strips evenly arranged along the Y axis, the third image 303 is a plurality of long strips evenly arranged along the X axis, and the fourth image 304 is a long strip extending along the P direction. Figure 7 In (2), the first image 301 is in the shape of a ring, the second image 302 is a plurality of long strips evenly arranged along the Y-axis direction, the third image 303 is a plurality of long strips evenly arranged along the X-axis direction, and the fourth image 304 is a plurality of circular shapes evenly arranged in an arc in a direction perpendicular to the P direction. Figure 7 In (3), the first image 301 is in the shape of a ring, the second image 302 is a plurality of long strips evenly arranged along the Y-axis direction, the third image 303 is a plurality of long strips evenly arranged along the X-axis direction, and the fourth image 304 is a combination of a long strip extending along the P direction and a plurality of circular shapes evenly arranged in an arc in a direction perpendicular to the P direction.

[0049] It should be noted that when the fourth image is a combination of a long strip and multiple circular graphics, the circle may not be set at the position where the long strip overlaps with the circular graphics in the extension direction. In this way, image overlap can be avoided, the difficulty of resolution can be reduced, and the alignment efficiency can be improved.

[0050] Exemplary, reference Figure 8 , Figure 8 Schematic diagrams of specific shapes of three types of second alignment marks 204 are shown; among them, Figure 8 In (1), the first image 501 is a ring shape, the second image 502 is a plurality of long strips evenly arranged along the Y axis, the third image 503 is a plurality of long strips evenly arranged along the X axis, and the fourth image 504 is a long strip extending along the P direction. Figure 8 In (2), the first image 501 is in the shape of a ring, the second image 502 is a plurality of long strips evenly arranged along the Y-axis direction, the third image 503 is a plurality of long strips evenly arranged along the X-axis direction, and the fourth image 504 is a plurality of circular shapes evenly arranged in an arc in a direction perpendicular to the P direction. Figure 8In (3), the first image 501 is in the shape of a ring, the second image 502 is a plurality of long strips evenly arranged along the Y-axis direction, the third image 503 is a plurality of long strips evenly arranged along the X-axis direction, and the fourth image 504 is a combination of a long strip extending along the P direction and a plurality of circular shapes evenly arranged in an arc in a direction perpendicular to the P direction.

[0051] In other embodiments, the shapes of the first image, the second image, the third image and the fourth image in the first alignment mark and the shapes of the first image, the second image, the third image and the fourth image in the second alignment mark may also be any other suitable shapes, which is not limited in the present disclosure.

[0052] refer to Figure 7 and Figure 8 , the number of long strip graphics in the second image 302 of the first alignment mark 203 is the same as the number of long strip graphics in the second image 502 of the second alignment mark 204; and / or, the number of long strip graphics in the third image 303 of the first alignment mark 203 is the same as the number of long strip graphics in the third image 503 of the second alignment mark 204. In this way, the size occupied by each long strip shape in the multiple long strip graphics in the second image 302 of the first alignment mark 203 can be the same as the size occupied by each long strip shape in the multiple long strip graphics in the second image 502 of the second alignment mark 204. When the two are compared for alignment, the offset of the two in the Y-axis direction can be determined by the number of long strip graphics that differ between the two. Similarly, the size of each of the multiple long strips of the third image 303 in the first alignment mark 203 can be made the same as the size of each of the multiple long strips of the third image 503 in the second alignment mark 204. When the two are compared for alignment, the offset of the two in the X-axis direction can be determined by the number of different long strips between the two.

[0053] On this basis, the offset between the first semiconductor structure and the second semiconductor structure in the X-axis and Y-axis directions can be quickly determined by manually visually inspecting the difference in the number of long strip patterns in the second image or the third image in the first alignment mark and the second alignment mark, thereby improving the alignment efficiency and alignment accuracy.

[0054] In some embodiments, the multiple long strip-shaped graphics in the second image and / or the third image have different sizes in their extending directions.

[0055] In some embodiments, among the multiple long strip graphics of the second image or the third image, the size of a portion of the long strip graphics in the extension direction is a first size, and the size of another portion of the long strip graphics in the extension direction is a second size; wherein the long strip graphics with the first size and the long strip graphics with the second size are arranged alternately.

[0056] Exemplary, reference Figure 7 , the multiple long strip graphics in the third image 303 in the first alignment mark 203 have different sizes in the Y-axis direction, wherein the size of a part of the long strip graphics (such as 701) in the Y-axis direction is the first size, and the size of another part of the long strip graphics (such as 702) in the Y-axis direction is the second size, where the first size is larger than the second size, and the long strip graphics with the first size and the long strip graphics with the second size are arranged alternately. In this way, the size between each two adjacent long strip graphics of the specific first size (or second size) is a fixed value, and when performing alignment comparison, the recognition of the long strip graphics can be improved, the specific difference between the two images can be determined more quickly, and the alignment efficiency is improved. In some other embodiments, the first size may also be smaller than the second size. In addition, the ratio of the number of alternating intervals between the long strip graphics of the first size and the long strip graphics of the second size can be selected and set according to actual needs, and the present disclosure does not limit this.

[0057] It should be noted that the second image in the first alignment mark, the second image in the second alignment mark and the third image in the second alignment mark can all adopt the above-mentioned long strip patterns of different sizes to be arranged alternately and at intervals to further improve the alignment efficiency.

[0058] In some specific embodiments, reference Figure 7 and Figure 8 , the width of a long strip of graphics in the second image is S1, and the width of a long strip of graphics in the third image is S2, where S1 can be equal to S2. Exemplarily, S1=S2=1um. In some specific embodiments, the spacing width between each two adjacent long strip of graphics in the second image is S3, and the spacing width between each two adjacent long strip of graphics in the third image is S4, where S3 can be equal to S4. Exemplarily, S3=S4=1um. In this way, the specific offset between the two second images or between the two third images can be determined by the number of long strip graphics and the number of spacings.

[0059] It should be noted that, in order to more intuitively obtain the offset between the first alignment mark and the second alignment mark, in actual applications, the first image in the first alignment mark needs to at least partially overlap with the first image 501 in the second alignment mark 204 in the Z-axis direction. In other words, if the first semiconductor structure and the second semiconductor structure are bonded face to face, the position of the first alignment mark in the first semiconductor structure, the position of the second alignment mark in the second semiconductor structure, and the relative position of the first alignment mark and the second alignment mark after the two are bonded should be considered.

[0060] In some embodiments, when the first alignment mark and the second alignment mark completely overlap in the Z-axis direction, multiple long strip graphics in the second image of the first alignment mark are aligned one by one with multiple long strip graphics in the second image of the second alignment mark in the X-axis direction; and multiple long strip graphics in the third image of the first alignment mark are aligned one by one with multiple long strip graphics in the third image of the second alignment mark in the Y-axis direction.

[0061] Exemplary, reference Fig. 9 , Fig. 9 3 shows schematic diagrams of three groups of first alignment marks 203 and second alignment marks 204 being fully aligned (fully overlapped). In the three groups of schematic diagrams, the fourth image 304 in the first alignment mark 203 is different from the fourth image 504 in the second alignment mark 204. Among them, the multiple long strip graphics in the second image 302 in the first alignment mark 203 and the multiple long strip graphics in the second image 502 in the second alignment mark 204 are aligned one by one in the X-axis direction. The multiple long strip graphics in the third image 303 in the first alignment mark 203 and the multiple long strip graphics in the third image 503 in the second alignment mark 204 are aligned one by one in the X-axis direction.

[0062] refer to Fig. 9 , the first image 301 in the first alignment mark 203 and the first image 501 in the second alignment mark 204 are both circular; and the first image 301 in the first alignment mark 203 and the first image 501 in the second alignment mark 204 are concentric circles. The diameter of the first image 301 in the first alignment mark 203 is M1, and M1=80um is exemplary, and the diameter of the first image 501 in the second alignment mark 204 is M2, and M2=40um is exemplary.

[0063] like Fig. 9As shown, the width of the first alignment mark 203 in the X-axis direction (or Y-axis direction) is smaller than the width of the second alignment mark 204 in the X-axis direction (or Y-axis direction); in some specific embodiments, the width of the second alignment mark 204 in the X-axis direction (or Y-axis direction) is M3, and for example, M3=120um or 200um. The width of the first alignment mark 203 in the X-axis direction (or Y-axis direction) can be set according to actual needs, and the present disclosure does not limit this.

[0064] It should be understood that Fig. 9 The three groups of fourth image graphics are only exemplarily shown. In other embodiments, the fourth image 304 in the first alignment mark 203 and the fourth image 504 in the second alignment mark 204 may also be other graphics, which is not limited in the present disclosure.

[0065] It should be noted that when the angles between the P direction and the X-axis direction and the Y-axis direction are all 45°, only one long strip-shaped pattern extending along the P direction may be provided in the fourth image. At this time, the angle between the long strip-shaped pattern and the second image is 45°, and the angle between the long strip-shaped pattern and the third image is also 45°. The rotation offset between the first semiconductor structure and the second semiconductor structure is determined by judging the long strip-shaped pattern of the fourth image 304 in the first alignment mark 203 and the long strip-shaped pattern of the fourth image 504 in the second alignment mark 204.

[0066] When multiple circular graphics are set in the fourth image, the multiple circular graphics and the second image and the third image form a right-angle sector, and the multiple circular graphics divide the right angle equally; in some embodiments, 319, 318, 200, 100, 35, 19, etc. circular graphics can be set in the fourth image. At this time, the 319, 318, 200, 100, 36, 20 circular graphics divide the right angle (90°) into 320, 319, 201, 101, 36, 20 equal parts. Exemplarily, when the right angle (90°) is divided into 320 equal parts, the angle of each equal part is 0.28125°. On this basis, by comparing the two corresponding fourth images in the first alignment mark and the second alignment mark, the rotation angle of the two alignment marks on the XY plane, that is, the rotation offset, can be determined.

[0067] When the fourth image 304 in the first alignment mark 203 includes 318 circular graphics (i.e., 90° is divided into 319 equal parts), and the fourth image 504 in the second alignment mark 204 includes 319 circular graphics (i.e., 90° is divided into 320 equal parts), by comparing the fourth image 304 in the first alignment mark 203 with the fourth image 504 in the second alignment mark 204, the accuracy can reach about 0.00088° (90° / 319 / 320≈0.00088°). In this way, the measurement accuracy can be improved, and the accuracy of alignment measurement can be improved.

[0068] It should be understood that the more circular graphics there are in the fourth image, the higher the precision and accuracy of the determined rotation offset. In some specific embodiments, the diameter of the circular graphics may be 1 um.

[0069] In some embodiments, when the first alignment mark and the second alignment mark do not completely overlap (ie, there is an offset between the two), graphics in at least one group of images of the first alignment mark and the second alignment mark are not aligned.

[0070] Exemplary, reference Fig.10 , Fig.10 (1) shows a schematic diagram of the offset between the second image 1001 of the first alignment mark and the second image 1002 of the second alignment mark. Exemplarily, the second image 1001 of the first alignment mark is offset by a width distance S1 of a long strip pattern, such as 1 um, on the X-axis compared to the second image 1002 of the second alignment mark. Fig.10 (2) shows a schematic diagram showing that there is an offset between the third image 1003 of the first alignment mark and the third image 1004 of the second alignment mark. Exemplarily, the third image 1003 of the first alignment mark is offset on the Y axis by a width distance S2 of a long strip and a spacing S4, such as 2 um, compared to the third image 1004 of the second alignment mark. Fig.10 (3) shows a schematic diagram showing that there is an offset between the fourth image of the two groups of first alignment marks and the fourth image of the second alignment marks.

[0071] Fig.10 In the set of illustrations in (3), the fourth image of the first alignment mark includes a long strip shape 1005 and a plurality of circular shapes 1006 evenly arranged in arcs, and the fourth image of the second alignment mark includes a long strip shape 1007, wherein the long strip shape 1005 of the first alignment mark is rotated by an angle α compared with the long strip shape 1007 of the second alignment mark, that is, the rotation offset is an angle α. Fig.10In another group of illustrations in (3), the fourth image of the first alignment mark includes a plurality of circular graphics 1008 evenly arranged in an arc, and the fourth image of the second alignment mark includes a plurality of circular graphics 1009 evenly arranged in an arc, wherein the plurality of circular graphics 1008 of the first alignment mark are rotated by an angle corresponding to a circular graphic compared to the plurality of circular graphics 1009 of the second alignment mark. In this way, the rotation offset of the two adjacent circular graphics can be determined based on the angles corresponding to the two adjacent circular graphics.

[0072] Based on this, in the embodiment of the present disclosure, the offset amount of the first semiconductor structure and the second semiconductor structure in the Y-axis direction can be determined by the relative position between the second image in the first alignment mark and the second image in the second alignment mark; the offset amount of the first semiconductor structure and the second semiconductor structure in the X-direction can be determined by the relative position between the third image of the first alignment mark and the third image of the second alignment mark; the rotation offset amount of the first semiconductor structure and the second semiconductor structure in the clockwise / counterclockwise direction on the XY plane can be determined by the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark; thereby improving the alignment accuracy of the first semiconductor structure and the second semiconductor structure and improving the reliability of the semiconductor device.

[0073] Furthermore, by graphically setting the first alignment mark and the second alignment mark, the offset between the first semiconductor structure and the second semiconductor structure can be determined directly by manual visual inspection without the need for additional equipment, thereby improving the alignment efficiency; on the other hand, through the alignment results of multiple sets of images, the specific position of the misalignment can be more accurately reflected, and the alignment accuracy can be improved by comparing multiple sets of alignment results, thereby further improving the reliability and yield of semiconductor devices.

[0074] Based on the above semiconductor device, the embodiment of the present disclosure further provides a method for determining an offset of a semiconductor device. The semiconductor device is the semiconductor device described in the above embodiment of the present disclosure. Fig.11 , Fig.11 A schematic flow chart of a method for determining an offset of a semiconductor device is shown in FIG. 1 , wherein the method comprises: Step S1101, obtaining a layer image of a semiconductor device on a first plane; the layer image includes a first alignment mark and a second alignment mark; the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked and arranged in a first direction, the first semiconductor structure is provided with a first alignment mark, and the second semiconductor structure is provided with a second alignment mark; the first plane is perpendicular to the first direction.

[0075] Step S1102: Determine the offset between the first semiconductor structure and the second semiconductor structure by the relative position of the first alignment mark and the second alignment mark. The first alignment mark and the second alignment mark each include a first image, a second image, a third image, and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction, and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0076] In some embodiments, the offset between the first semiconductor structure and the second semiconductor structure is determined by the relative position of the first alignment mark and the second alignment mark, including: determining the offset between the first semiconductor structure and the second semiconductor structure in a third direction by the relative position between the second image of the first alignment mark and the second image of the second alignment mark.

[0077] The offset between the first semiconductor structure and the second semiconductor structure in the second direction is determined according to the relative position between the third image of the first alignment mark and the third image of the second alignment mark.

[0078] The rotation offset of the first semiconductor structure and the second semiconductor structure along the clockwise / counterclockwise direction on the first plane is determined according to the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark.

[0079] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device, wherein, referring to Fig.12 , Fig.12 , a schematic flow chart of a method for manufacturing a semiconductor device is shown, the method comprising: step S1201: forming a first semiconductor structure; a first alignment mark is provided in the first semiconductor structure.

[0080] Step S1202: forming a second semiconductor structure; and disposing a second alignment mark in the second semiconductor structure.

[0081] Step S1203: Bonding the first semiconductor structure to the second semiconductor structure in the first direction; wherein the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction and intersects with both the second direction and the third direction.

[0082] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0083] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor structure; A first alignment mark is disposed in the first semiconductor structure; A second semiconductor structure, stacked and arranged with the first semiconductor structure in a first direction; A second alignment mark is disposed in the second semiconductor structure; The relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; Among them, the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

2. The semiconductor device according to claim 1, wherein: The outer boundary size of the first image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the first alignment mark in the third direction; An outer boundary size of the first image in the first alignment mark in the second direction is the same as an outer boundary size of the third image in the first alignment mark in the second direction.

3. The semiconductor device according to claim 2, characterized in that The outer boundary size of the second image in the first alignment mark in the third direction is the same as the outer boundary size of the second image in the second alignment mark in the third direction; An outer boundary size of the third image in the first alignment mark in the second direction is the same as an outer boundary size of the third image in the second alignment mark in the second direction.

4. The semiconductor device according to claim 3, characterized in that The first image includes a circle, a ring, a square, a matrix or a cross; The second image includes a plurality of long strip-shaped graphics evenly arranged along the third direction; The third image includes a plurality of long strip-shaped graphics evenly arranged along the second direction; The fourth image includes a long strip-shaped figure extending along the fourth direction, and / or a plurality of circular figures evenly arranged in a straight line or an arc in a direction perpendicular to the fourth direction.

5. The semiconductor device according to claim 4, characterized in that The number of long strip graphics in the second image of the first alignment mark is the same as the number of long strip graphics in the second image of the second alignment mark; and / or the number of long strip graphics in the third image of the first alignment mark is the same as the number of long strip graphics in the third image of the second alignment mark.

6. The semiconductor device according to claim 5, characterized in that The multiple long strip-shaped graphics in the second image and / or the third image have different sizes in their extending directions.

7. The semiconductor device according to claim 6, characterized in that Among the multiple long strip graphics of the second image or the third image, the size of some of the long strip graphics in their extension direction is a first size, and the size of other parts of the long strip graphics in their extension direction is a second size; wherein the long strip graphics with the first size and the long strip graphics with the second size are arranged alternately.

8. The semiconductor device according to claim 7, characterized in that The first image in the first alignment mark at least partially overlaps the first image in the second alignment mark in the first direction.

9. The semiconductor device according to claim 8, characterized in that When the first alignment mark and the second alignment mark completely overlap in the first direction, a plurality of long strip patterns in the second image of the first alignment mark are aligned one by one with a plurality of long strip patterns in the second image of the second alignment mark in the second direction; Furthermore, the plurality of long strip-shaped patterns in the third image of the first alignment mark and the plurality of long strip-shaped patterns in the third image of the second alignment mark are aligned one by one in the third direction.

10. A method for determining an offset of a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 9, characterized in that: The determination method comprises: Acquire a layer image of the semiconductor device on a first plane; the layer image includes a first alignment mark and a second alignment mark; the semiconductor device includes a first semiconductor structure and a second semiconductor structure stacked and arranged in a first direction, the first semiconductor structure is provided with the first alignment mark, and the second semiconductor structure is provided with the second alignment mark; the first plane is perpendicular to the first direction; Determining an offset between the first semiconductor structure and the second semiconductor structure according to a relative position of the first alignment mark and the second alignment mark; Among them, the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

11. The determination method according to claim 10, characterized in that: The step of determining the offset between the first semiconductor structure and the second semiconductor structure by the relative position of the first alignment mark and the second alignment mark comprises: determining an offset between the first semiconductor structure and the second semiconductor structure in the third direction according to a relative position between the second image of the first alignment mark and the second image of the second alignment mark; determining an offset between the first semiconductor structure and the second semiconductor structure in the second direction according to a relative position between the third image of the first alignment mark and the third image of the second alignment mark; The rotation offset of the first semiconductor structure and the second semiconductor structure along the clockwise / counterclockwise direction on the first plane is determined according to the relative position between the fourth image of the first alignment mark and the fourth image of the second alignment mark.

12. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a first semiconductor structure; a first alignment mark is disposed in the first semiconductor structure; forming a second semiconductor structure; a second alignment mark is disposed in the second semiconductor structure; bonding the first semiconductor structure and the second semiconductor structure in a first direction; Among them, the relative position of the first alignment mark and the second alignment mark can determine the offset between the first semiconductor structure and the second semiconductor structure; the first alignment mark and the second alignment mark both include a first image, a second image, a third image and a fourth image; the second image is located on at least one side of the first image in the second direction; the third image is located on at least one side of the first image in the third direction; the fourth image is located on at least one side of the first image in the fourth direction; the first direction, the second direction and the third direction are perpendicular to each other; the fourth direction is perpendicular to the first direction, and intersects with both the second direction and the third direction.

Images