Power-off self-locking circuit of data link dual-power supply system

Abstract

The invention discloses a power-off self-locking circuit of a data link dual-power supply system, which comprises an external system, the external system is connected with an external power supply through an ideal diode I to construct a first circuit, and the external system is connected with a battery through an ideal diode II to construct a second circuit, the power-off self-locking circuit further comprises a power-off self-locking module arranged on the second circuit, the power-off self-locking module comprises a voltage stabilizing diode, the output end of the voltage stabilizing diode is connected with the power input end of a reset chip and the power input end of a J-K negative edge trigger type trigger, and an output signal of the reset chip is connected with the power input end of the J-K negative edge trigger type trigger. And the J-K negative edge trigger type trigger is connected with the ideal diode II. According to the invention, redundant backup of dual power supplies is realized by an ideal diode, power supply state self-locking is realized by a J-K trigger, power supply of a state self-locking circuit is realized by a voltage-regulator tube, control of a self-locking state is expanded by an external interface circuit, and charging of a battery by an external power supply is realized by a load switch.

Description

Technical Field

[0001] The present invention relates to the field of power supply, and more specifically to a power-off self-locking circuit of a data link dual-power supply system. Background Art

[0002] In the power supply system of the data link, in order to ensure the continuity and reliability of the external system, the equipment can use a DC dual power supply. The DC dual power supply can realize the backup or redundancy of the input power supply, ensure the reliability of the input power supply of the external system, and when one power supply fails or disconnects, the other power supply can automatically take over to ensure the continuity of the power supply. Usually, one power supply uses a DC power supply device or an AC adapter; the other power supply uses a battery.

[0003] If both power supplies are external and both are in working order, the power supply for the external system can be flexibly selected. For the design of external system and battery integration, it is necessary to consider the self-locking of the dual power supply working state, and the self-locking of the battery power-off state is particularly important. The self-locking of the battery power-off state does not refer to the battery's undervoltage protection or over-discharge current protection. It means that when the battery can work normally, the output state of the battery power supply channel is locked and controlled through the external interface to prevent the battery from supplying power when the external system is not working, thereby reducing battery power loss.

[0004] The invention patent with patent application number 202311833594.X discloses a dual power adaptive switching control circuit with a self-locking function. This patent is a voltage monitoring of dual power supplies. After one power supply is powered off, the comparison circuit controls the optocoupler circuit to realize voltage detection (POWER detection circuit), and then uses the OR gate circuit to control the enable of the driver with three-state output control, so that the driver with three-state output control has no output, and then uses the pull-down resistor to realize the closure and lock of the switch. It mainly realizes adaptive switching when one power supply is powered off. The control is more complicated and involves more devices. It can only adapt to the control of switching to another power supply when one power supply is powered off; if both power supplies are powered off, switches S1 and S2 will be closed, and the power supply channels of the two power supplies will be turned on; it cannot be used in a dual power supply system containing batteries, which will cause excessive discharge of the battery and cause battery damage.

[0005] There is also a utility model patent with patent application number 202223410442.2 that discloses a self-locking power supply circuit for BMS. The key switch 10 is an external power supply contact switch. When it is short pressed, it can be turned on, and when it is long pressed, it can be turned off. The specific working principle is as follows. During normal operation, the key switch 10 is short pressed, and the key switch 10 outputs a short-time high-level wake-up signal, and transmits the high-level wake-up signal to the power supply chip 20. The power supply chip 20 starts working upon receiving the high-level wake-up signal, and outputs a low-voltage power supply to the control chip 30. The control chip 30 also detects the effective time of the high-level wake-up signal at the same time. When it meets the time for short-pressing to start, it can be considered that the system needs to be turned on, so that the control chip 30 will enter the working state; the control chip 30 that is cut into the working state, the control chip 30 outputs a short-time high-level signal to the trigger 40, and the trigger 40 outputs a high-level signal and maintains it to the power supply chip 20. After the key cancels the key operation, that is, the high-level wake-up signal disappears, and the system can self-maintain power supply. In this way, the startup operation of the entire system is completed. When it is necessary to shut down the system, that is, long press the button switch 10, the button switch 10 outputs a long high-level wake-up signal, and the control chip 30 detects whether the effective time of the high-level wake-up signal matches the long-press shutdown time. When it matches, it is considered that the system needs to be shut down, and the control chip 30 outputs a high-level signal to the trigger 40 again. The trigger 40 outputs a signal to the power supply chip 20, the power supply chip 20 stops supplying power, the control chip 30 stops working, and the system is powered off and shut down.

[0006] This patent requires human intervention to power on through an external key switch. After power on, the control chip determines the key pressing time, and then controls the trigger to turn on and off the power supply chip. It mainly controls the power supply through the control chip to detect the key pressing time, and both the on and off control are high-level signals, which may cause the risk of false operation.

[0007] Or a dual power automatic control and detection circuit disclosed in the utility model patent with patent application number 201620887101.X, which can only effectively shut down the battery power supply channel. The RS trigger implemented with discrete transistors is just a simple combinational logic circuit, and the output of the trigger is only determined by the current input. There is no edge trigger signal like a clock. When there is power input at the DC power input port, the DCDC cannot be shut down through the RS trigger circuit. Even if it is shut down through the MCU, it will restart through the DCDC after the MCU is powered off. The DCDC shutdown can only be realized when there is no external power input. Summary of the invention

[0008] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0009] In order to achieve these purposes and other advantages of the present invention, a power-off self-locking circuit of a data link dual-power supply system is provided, comprising: an external system, wherein the external system is connected to an external power supply through an ideal diode I to construct a first circuit, and the external system is connected to a battery through an ideal diode II to construct a second circuit, characterized in that it also includes: a power-off self-locking module arranged on the second circuit, which locks the state of the ideal diode II when the external power supply is normally supplied, and the power-off self-locking module comprises: a voltage-stabilizing diode connected to the output end of the battery, the output end of the voltage-stabilizing diode is electrically connected to the input end of a reset chip and a JK negative edge triggered trigger respectively, the output signal of the reset chip is connected to the SD interface of the JK negative edge triggered trigger, the Q port of the JK negative edge triggered trigger is connected to the EN interface of the ideal diode II, and the control signal of the external system is connected to the Q interface of the JK negative edge triggered trigger.

[0010] Preferably, both J and K input terminals of the JK negative-edge triggered flip-flop are connected to a high level.

[0011] Preferably, the self-locking process of the power-off self-locking module is as follows:

[0012] When the external system receives the signal of battery power failure, the CP_CTRL signal output by the external system changes from high level to low level, and the output end of the JK negative edge triggered trigger outputs a low level signal to the enable EN of the ideal diode II in the battery path, and the ideal diode II is cut off, so that the power supply channel from the battery to the external system is disconnected, and the battery power failure state is locked. After the power supply channel from the battery to the external system is disconnected, the CP_CTRL signal will be pulled up to a high level again by the power failure self-locking module.

[0013] Preferably, the unlocking process of the power-off self-locking module is as follows:

[0014] When the external power supply supplies power to the external system again, after the external system receives the signal of battery status unlocking, the external system outputs a low-level CP_CTRL signal to the CP interface of the JK negative-edge triggered trigger, and the output terminal Q of the JK negative-edge triggered trigger will output a high-level signal to the enable EN of the ideal diode II in the battery path, and the ideal diode II is turned on, realizing the opening of the power supply channel from the battery to the external system.

[0015] Preferably, the initial process of the battery power-on operation of the power-off self-locking module is:

[0016] After the battery is connected to the circuit, the reset chip and the JK negative edge triggered trigger are powered through the voltage regulator diode. After the reset time is reached, the reset chip completes the initial setting of the JK negative edge triggered trigger through the SD pin of the JK negative edge triggered trigger, and the JK negative edge triggered trigger outputs a high level to the ideal diode II, and the ideal diode II is turned on.

[0017] Preferably, when the external power supply and the battery are powered on at the same time, when the power-off self-locking module is in the unlocking working state, the external power supply of the first circuit with a higher input voltage or the battery of the second circuit is used as the output.

[0018] Preferably, it further comprises: a charging circuit for connecting the battery and the external power source, the charging circuit comprising: a load switch provided on the circuit connecting the battery and the external power source;

[0019] Wherein, the load switch and the battery are respectively connected to the external system for communication.

[0020] Preferably, the working process of the load switch is:

[0021] The external system controls the enablement of the load switch through the GPIO interface to realize the on and off of the load switch. When the load switch is turned on, the external power supply charges the battery; when the load switch is turned off, the charging is terminated, and the positive and negative poles of the battery are connected to the ADC acquisition circuit of the external system. The external system collects the battery voltage through the ADC circuit and determines the on and off of the charging circuit based on the collected battery voltage.

[0022] The present invention includes at least the following beneficial effects: the present invention realizes redundant backup of dual power supplies through ideal diodes, realizes power supply state self-locking through JK triggers, realizes power supply of state self-locking circuits through voltage regulators, and expands control of self-locking states through external interface circuits. The present invention can be extended to systems for multi-power supply DC power supply control, has a wide range of applications, and has low cost.

[0023] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a connection block diagram of the power-off self-locking circuit of the data link dual power supply system of the present invention;

[0025] Figure 2 This is the circuit diagram of the power-off self-locking module;

[0026] Figure 3 The circuit diagram for dual power switching;

[0027] Figure 4A connection block diagram of a charging circuit of a dual power supply system of the present invention;

[0028] Figure 5 is a circuit diagram of a charging circuit;

[0029] Figure 6 A control circuit diagram of the first circuit and the second circuit being self-locking when powered off;

[0030] Figure 7 This is a dual power supply switching control circuit diagram.

[0031] Markings in the figure: 1. External system, 2. Ideal diode I, 3. External power supply, 4. Ideal diode II, 5. Battery, 6. Zener diode, 7. Reset chip, 8. JK negative-edge triggered trigger, 9. Load switch. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0033] It should be understood that the terms such as “having”, “including” and “comprising” used herein do not exclude the existence or addition of one or more other elements or combinations thereof.

[0034] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the term is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0035] In the description of the present invention, unless otherwise clearly stipulated and limited, the terms "installed", "provided with", "mounted / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be a direct connection or an indirect connection through an intermediate medium. It can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In addition, in the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0037] Figure 1-Figure 3 A power-off self-locking circuit of a data link dual-power supply system of the present invention is shown, comprising: an external system 1, wherein the external system 1 is connected to an external power supply 3 through an ideal diode I2 to construct a first circuit, and the external system 1 is connected to a battery 5 through an ideal diode II4 to construct a second circuit, and further comprising: a power-off self-locking module arranged on the second circuit, which locks the state of the ideal diode II4 when the external power supply 3 is normally powered, and the power-off self-locking module comprises: a voltage-stabilizing diode connected to the output end of the battery 5, the output end of the voltage-stabilizing diode 6 is electrically connected to the input end of a reset chip 7 and a JK negative edge triggered trigger 8 respectively, the output signal of the reset chip 7 is connected to the SD interface of the JK negative edge triggered trigger 8, the 1Q port of the JK negative edge triggered trigger 8 is connected to the EN interface of the ideal diode II4, and the control signal of the external system 1 is connected to the 1Q interface of the JK negative edge triggered trigger 8.

[0038] Working principle:

[0039] In the data link power supply system, the ideal diode I2 and the external power supply 3 are used as the first output circuit, the ideal diode II4 and the battery 5 are used as the second output circuit, and the circuit with a higher voltage is used as the input of the external system 1. The ideal diode I2 and the ideal diode II4 can block the reverse current from the output to the input with the help of the integrated back-to-back FET. The operation can be turned on and off by enabling the ideal diode II4. When the battery 5 is connected to the device, the battery 5 supplies power to the reset chip 7MAX811 and the JK negative edge triggered trigger 8 (74HC112PW) through the voltage regulator diode 6BZT52C7V5. MAX811 and 74HC112PW start working according to the initial hardware configuration. After power-on initialization, the output end of the 74HC112PW outputs a high-level signal to the ideal diode II4, the ideal diode II4 is turned on, and the power supply channel from the battery 5 to the external system 1 is opened. The system can work normally after being powered, and the clock output to 74HC112PW will be set to high level. If the system receives the instruction to shut down battery 5, the clock output to 74HC112PW will be set to low level, and the output end of 74HC112PW will output a low level signal to enable the ideal diode II4, so as to disconnect the power supply channel from battery 5 to the system, and the low level signal at the output end of 74HC112PW will be locked, completing the self-locking of the power-off state of battery 5.

[0040] In the above scheme, the J and K inputs of the JK negative edge triggered flip-flop 8 are both connected to a high level. Using this technical method, the 74HC112PW device is a JK negative edge triggered flip-flop 8. The low level of the preset (SD) or clear (RD) input will set or reset the output level, and will not be affected by the levels of other inputs. When SD and RD are in an inactive state (high level), the data of the J and K inputs that meet the setup time requirements will be transmitted to the output at the negative edge of the clock (CLK) pulse; if the clock signal remains at a high level, the output level remains unchanged. After the hold time interval, the data of the J and K inputs can be changed without affecting the level of the output. This device operates the flip-flop as a switching flip-flop by connecting J and K to a high level. The switching flip-flop flips the output state at the negative edge of each clock.

[0041] In the above scheme, the self-locking process of the power-off self-locking module is as follows:

[0042] When the external system 1 receives the signal that the battery 5 is powered off, the external system 1 outputs a low-level signal to the 1Q interface of the JK negative edge triggered trigger 8. The output end of the JK negative edge triggered trigger 8 will output a low-level signal to the ideal diode II4 on the battery 5 path. The ideal diode II4 is cut off, and the power supply channel from the battery 5 to the external system 1 is disconnected, and the battery 5 is self-locked in the power-off state. Using this technical method, the MAX811 has a microprocessor reset chip 7 with a voltage detection function, which can provide a reset signal when powered on. Because the initial power-on state of the JK trigger is unstable, it is necessary to input a low level at the trigger preset (SD) end to ensure that the trigger stably outputs a high level. MAX811 meets this requirement. Even if the reset time is reached, MAX811 outputs a high level to the trigger preset (SD) end, and the trigger output can maintain a high level. This device uses the generated reset signal as the input of the preset end of the switching trigger to control the initial power-on state of the switching trigger. It is ensured that the battery 5 can meet the output through the ideal diode II4 when it is powered on for the first time. The nominal voltage regulation value of the voltage stabilizing diode 6 (BZT52C7V5) is 7.5V. Under normal working conditions, the diode can maintain a stable voltage drop of 7.5V. This device connects the voltage stabilizing diode between the battery 5 and the MAX811 and 74HC112PW to reduce the voltage of the battery 5 to 3.3V to 5.1V, which meets the use conditions of the MAX811 and 74HC112PW. At the same time, the ideal diode I2 and the ideal diode II4 are controlled by the power-off self-locking module to turn on and off the ideal diode II4, and the high level is configured to turn on and the low level is turned off. When the external power supply is connected to the external system 1, the external power supply can be directly connected to the ideal diode I2, and the ideal diode I2 is turned on when powered on. After the external power supply 3 is powered on, the system can be powered on. The external power supply stops supplying power, and the battery 5 supplies power. When the system receives the instruction to power off the battery 5, the clock output by the system to the 74HC112PW is set to a low level, and the output end of the 74HC112PW will output a low-level signal to enable the ideal diode LM73100, so that the power supply channel from the battery 5 to the system is disconnected, and the power-off state of the battery 5 is self-locked. The low-level signal at the output end of the 74HC112PW will be locked. The power-off state of the battery 5 is self-locked.

[0043] In the above scheme, the unlocking process of the power-off self-locking module is as follows:

[0044] When the external circuit supplies power to the external system 1 again, after the external system 1 receives the signal of battery 5 status unlocking, the external system 1 outputs a low-level signal to the CP interface of the JK negative edge triggered trigger 8, and the output end of the JK negative edge triggered trigger 8 will output a high-level signal to enable the ideal diode on the battery 5 path, and the ideal diode will be turned on, so that the power supply channel from the battery 5 to the external system 1 is opened. With this technical method, when the external power supply is connected again and the system is restarted, the control level of the 74HC112PW clock (CP) must be set to a high level first. After receiving the battery 5 status unlocking instruction, the system sets the clock output to the 74HC112PW to a low level. Because the 74HC112PW is triggered by the falling edge of the clock, it will output a high-level signal to the LM73100 at the output end, so that the power supply channel from the battery 5 to the system is turned on again, and the battery 5 power-off state is unlocked.

[0045] In the above scheme, when the external power supply 3 and the battery 5 are powered on at the same time, when the power-off self-locking module is in the unlocked working state, the external power supply 3 of the first circuit with a higher input voltage or the battery 5 of the second circuit will be used as the output. With this technical scheme, 1. When the two power supplies are powered on at the same time, only the power-off self-locking module is in the unlocked working state, and the output of the 1st circuit with a higher input voltage determines whether the first circuit or the second circuit supplies power to the system. 2. If the battery 5 channel is in the power-off self-locking state, if the two power supplies are powered on at the same time, only the external power supply 3 can output power through the ideal diode. 3. In a further case, if both circuits have self-locking circuits and are in the power-off self-locking state, neither power supply will output power. At this time, the only way is to unplug the battery 5 and then reconnect the battery 5, which is equivalent to resetting the self-locking circuit.

[0046] In the above scheme, if Figure 4 , Figure 5 As shown, the battery 5 charging process is as follows:

[0047] The external power source 3 and the battery 5 are connected via a load switch 9 (TPS1HC100). By configuring the enable terminal, the external power source 3 can charge the battery 5 autonomously, or the external system 1 can collect the voltage of the battery 5 and control the load switch 9 to charge according to demand. TPS1HC100 is a high-side power switch that can detect current and programmably limit output current to prevent excessive current from damaging the battery 5.

[0048] The above circuit can also be further Figure 6 , Figure 7The configuration is changed to a dual-channel self-locking control circuit. The enable of each ideal diode in the dual-channel power switching control circuit is controlled. The external system 1 provides VBAT_CTRL and VOUT_CTRL, which can flexibly select the power supply channel to achieve the shutdown and conduction control of any power supply channel; or both power supplies can be shut down to achieve self-locking of the power-off state of the power supply channel.

[0049] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A power-off self-locking circuit for a data link dual power supply system, comprising: An external system, wherein the external system is connected to an external power supply through an ideal diode I to construct a first circuit, and the external system is connected to a battery through an ideal diode II to construct a second circuit, and is characterized in that it also includes: a power-off self-locking module arranged on the second circuit, which locks the state of the ideal diode II when the external power supply is normally powered, and the power-off self-locking module includes: a voltage-stabilizing diode connected to the output end of the battery, the output end of the voltage-stabilizing diode is electrically connected to the input end of the reset chip and the JK negative edge triggered trigger respectively, the output signal of the reset chip is connected to the SD interface of the JK negative edge triggered trigger, the Q port of the JK negative edge triggered trigger is connected to the EN interface of the ideal diode II, and the control signal of the external system is connected to the Q interface of the JK negative edge triggered trigger.

2. The power-off self-locking circuit of the data link dual power supply system according to claim 1, characterized in that: The J and K input terminals of the JK negative edge triggered flip-flop are both connected to a high level.

3. The power-off self-locking circuit of the data link dual power supply system according to claim 1, characterized in that: The self-locking process of the power-off self-locking module is as follows: When the external system receives the battery power-off signal, the CP_CTRL signal output by the external system changes from a high level to a low level, and the output end of the JK negative edge triggered trigger outputs a low level signal to the enable EN of the ideal diode II in the battery path, and the ideal diode II is cut off, so that the power supply channel from the battery to the external system is disconnected, and the battery power-off state is locked. After the power supply channel from the battery to the external system is disconnected, the CP_CTRL signal will be pulled up to a high level again by the power-off self-locking module.

4. The power-off self-locking circuit of the data link dual power supply system according to claim 1, characterized in that: The unlocking process of the power-off self-locking module is as follows: When the external power supply supplies power to the external system again, after the external system receives the signal of battery status unlocking, the external system outputs a low-level CP_CTRL signal to the CP interface of the JK negative-edge triggered trigger, and the output terminal Q of the JK negative-edge triggered trigger will output a high-level signal to the enable EN of the ideal diode II in the battery path, and the ideal diode II is turned on, realizing the opening of the power supply channel from the battery to the external system.

5. The power-off self-locking circuit of the data link dual power supply system according to claim 1, characterized in that: The initial process of the battery power-on operation of the power-off self-locking module is as follows: After the battery is connected to the circuit, the reset chip and the JK negative-edge-triggered trigger are powered by the voltage-stabilizing diode. After the reset time is reached, the reset chip completes the initial setting of the JK negative-edge-triggered trigger through the SD pin of the JK negative-edge-triggered trigger. The JK negative-edge-triggered trigger outputs a high level to the ideal diode II, and the ideal diode II is turned on.

6. The power-off self-locking circuit of the data link dual power supply system according to claim 4, characterized in that: When the external power supply and the battery are powered on at the same time, when the power-off self-locking module is in the unlocking working state, the external power supply of the first circuit with a higher input voltage or the battery of the second circuit is used as the output.

7. The power-off self-locking circuit of the data link dual power supply system according to claim 1, characterized in that: Also includes: A charging circuit for connecting the battery to an external power source, the charging circuit comprising: a load switch provided on the circuit connecting the battery to the external power source; Wherein, the load switch and the battery are respectively connected to the external system for communication.

8. The power-off self-locking circuit of the data link dual power supply system according to claim 7, characterized in that: The working process of the load switch is: The external system controls the enablement of the load switch through the GPIO interface to realize the on and off of the load switch. When the load switch is turned on, the external power supply charges the battery; when the load switch is turned off, the charging is terminated, and the positive and negative poles of the battery are connected to the ADC acquisition circuit of the external system. The external system collects the battery voltage through the ADC circuit and determines the on and off of the charging circuit based on the collected battery voltage.

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