A method and system for suppressing sudden leakage current during grid connection

Abstract

The present application discloses a method and system for suppressing sudden leakage current during grid connection, which are applied to Heric and H4 inverter topologies. The suppression method includes the following steps: collecting the ground voltage, bus voltage, and grid voltage of the inverter system; constructing a safe voltage threshold range based on the collected ground voltage and bus voltage; and closing the grid connection relay when the grid voltage falls within the safe time zone corresponding to the safe voltage threshold range. The suppression system is used to implement the above suppression method. The beneficial effects of the present application are as follows: The present application does not need to change the hardware structure of the system circuit. Only by utilizing the characteristics of the circuit itself and controlling the closing timing of the grid connection relay, sudden leakage current can be completely eliminated, the working stability of the inverter system is enhanced, and the damage to other components of the system caused by the large voltage of the Y capacitor generated together with the sudden current is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of new energy power generation, and particularly relates to a method for suppressing sudden leakage current during the grid connection stage. Background Art

[0002] An inverter system generally includes a power generation unit, a DC / DC unit, a DC / AC unit, etc. The inverter system can be connected to the grid through the AC side of the DC / AC unit. And in order to realize the grid connection and disconnection control of the inverter system, a relay is often connected between the DC / AC unit and the grid to realize the grid connection and disconnection control of the inverter system.

[0003] When the inverter system is operating in grid connection, in order to ensure the safe operation of the inverter system, it is often necessary to first perform self-check on the relay, and only after ensuring that all relays can work normally can the grid connection of the inverter system be carried out. However, during the self-check process of the relay, the leakage current of the inverter system may suddenly increase, which may trigger the tripping of the leakage current protector, easily leading to the phenomenon of grid connection failure and disconnection of the inverter system. Summary of the Invention

[0004] One of the purposes of the present application is to provide a method for suppressing sudden leakage current during the grid connection stage that can solve at least one defect in the above background art.

[0005] To achieve at least one of the above purposes, the technical solution adopted by the present application is: A method for suppressing sudden leakage current during the grid connection stage, which is applied to Heric and H4 inverter topologies, includes the following steps: collecting the ground voltage, bus voltage, and grid voltage of the inverter system; constructing a safe voltage threshold range according to the collected ground voltage and bus voltage; and closing the grid connection relay within the safe time zone corresponding to the grid voltage falling within the safe voltage threshold range.

[0006] Preferably, the lower limit of the safe voltage threshold range is the ground voltage, and the upper limit of the safe voltage threshold range is the sum of the ground voltage and the bus voltage.

[0007] Preferably, the closing delay time of the grid connection relay is ΔT; the safe time zone is obtained by advancing the safe time period corresponding to the positions where the grid voltage intersects the upper and lower limits of the safe voltage threshold range by ΔT time.

[0008] Preferably, there are a plurality of consecutive safe time zones corresponding to the grid voltage falling within the safe voltage threshold range; the grid connection relay is adapted to close within the nearest safe time zone that meets the closing time requirement from the current moment.

[0009] Preferably, if the current time is within the nearest safe time period, the determination of the nearest safe time zone that meets the closing time requirement includes the following process: Calculate the time interval between the current time and the end of the nearest safe time period; if the calculated time interval is greater than ΔT, the safe time zone corresponding to the nearest safe time period meets the closing time requirement; if the calculated time interval is less than or equal to ΔT, continue to calculate the time interval between the current time and the end of the nearest safe time period; if the calculated time interval is greater than ΔT, the safe time zone corresponding to the nearest safe time period meets the closing time requirement; otherwise, the safe time zone corresponding to the nearest safe time period does not meet the closing time requirement, and at this time, the next safe time zone is used as the nearest safe time zone that meets the closing time requirement.

[0010] Preferably, if the current time is outside the nearest safe time period, the determination of the nearest safe time zone that meets the closing time requirement includes the following process: Calculate the first time interval between the current time and the start of the nearest safe time period; if the calculated first time interval is greater than ΔT, the safe time zone corresponding to the nearest safe time period meets the closing time requirement; if the calculated first time interval is less than or equal to ΔT, continue to calculate the second time interval between the current time and the end of the nearest safe time period; if the calculated second time interval is greater than ΔT, the safe time zone corresponding to the nearest safe time period meets the closing time requirement; otherwise, the safe time zone corresponding to the nearest safe time period does not meet the closing time requirement, and at this time, the next safe time zone is used as the nearest safe time zone that meets the closing time requirement.

[0011] Preferably, when the duration of the safe time zone does not meet the closing time requirement of the grid connection relay, the bus voltage is boosted to increase the upper limit of the safe voltage threshold range, thereby increasing the duration of the safe time zone to meet the closing time requirement; after the grid connection relay is closed, the grid voltage is stepped down and reset.

[0012] Preferably, the bus voltage is boosted to be greater than the peak value of the grid voltage.

[0013] Preferably, the bus voltage is boosted by a BOOST boost circuit.

[0014] A system for suppressing the sudden leakage current during the grid connection stage, which is used to implement the method for suppressing the sudden leakage current during the grid connection stage, includes a collection unit, a calculation unit, and a control unit; the collection unit is used to collect the ground voltage, bus voltage, and grid voltage of the inverter system; the calculation unit calculates the safe voltage threshold range according to the voltage data obtained by the collection unit, and constructs a safe time zone in which the grid voltage falls within the safe voltage threshold range; the control unit is adapted to send a closing control signal to the grid connection relay so that the grid connection relay completes the closing within the safe time zone.

[0015] Compared with the prior art, the beneficial effects of the present application are as follows:

[0016] The present application does not need to change the hardware structure of the system circuit. By utilizing the characteristics of the circuit itself and controlling the closing time of the grid-connected relay, the sudden leakage current can be completely eliminated, the working stability of the inverter system is enhanced, and the damage to other components of the system caused by the large voltage of the Y capacitor generated together with the sudden current is reduced. Brief Description of the Drawings

[0017] Figure 1 It is a schematic structural diagram of an existing Heric-type inverter topology system.

[0018] Figure 2 It is a schematic structural diagram of an existing H4-type inverter topology system.

[0019] Figure 3 It is a schematic diagram of the leakage current equivalent circuit of the Heric-type inverter topology system and the H4-type inverter topology system.

[0020] Figure 4 It is a schematic waveform diagram of the grid voltage.

[0021] Figure 5 It is a schematic diagram of the leakage current loop formed by the equivalent circuit of the grid voltage at 0 - T / 4.

[0022] Figure 6 It is a schematic diagram of the leakage current loop formed by the equivalent circuit of the grid voltage at T / 2 - 3T / 4.

[0023] Figure 7 For Figure 1 and Figure 2 It is a schematic waveform diagram obtained by simulating the inverter system shown.

[0024] Figure 8 It is a partially enlarged schematic diagram of the oscillating current waveform of the Y capacitor.

[0025] Figure 9 It is a schematic diagram of the sudden leakage current waveform of the inverter system.

[0026] Figure 10 It is a schematic diagram of the time-domain response waveform of the leakage current when the positive and negative poles of the diode in the inverter system are short-circuited.

[0027] Figure 11 It is a partially enlarged schematic diagram of the time-domain response waveform of the leakage current when the positive and negative poles of the diode in the inverter system are short-circuited.

[0028] Figure 12 It is a schematic diagram of the working process of the suppression method in the present application.

[0029] Figure 13Schematic diagram for dividing the safe time zone of the grid-connected relay in this application.

[0030] Figure 14 Schematic diagram of the control logic for the grid-connected relay to close in this application.

[0031] Figure 15 Schematic diagram for dividing the safe time zone after the bus voltage is lifted in this application.

[0032] Figure 16 Schematic diagram of the working process of the suppression system in this application.

[0033] In the figure: acquisition unit 100, calculation unit 200, control unit 300. Detailed implementation manners

[0034] Next, in combination with the detailed implementation manners, the present application will be further described. It should be noted that in the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0035] In the description of the present application, it should be noted that for the orientation terms, such as the terms "center", "horizontal", "vertical", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., the indicated orientation and position relationships are based on the orientation or position relationships shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as limiting the specific protection scope of the present application.

[0036] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence.

[0037] In this application, unless otherwise clearly specified or limited, the terms "installed", "connected", "connected to", "fixed", etc. shall be understood in a broad sense. For example, it can be a connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] In this application, unless otherwise clearly specified or limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the first feature being "above", "over" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "under" and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0039] The terms "comprising" and "having" in the description and claims of this application, as well as any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] It should be known that sudden changes in leakage current are likely to occur during the grid connection process of Heric-type and H4-type inverter topology systems. For the convenience of understanding the technical solutions of this application, the specific reasons for the sudden changes in leakage current generated during the grid connection process of Heric-type and H4-type inverter topology systems can be analyzed first below.

[0041] As Figure 1 and Figure 2 shown, they are respectively schematic diagrams of the typical architectures of the existing Heric-type inverter topology system and H4-type inverter topology system. The specific structures and working principles of the architectures are well-known to those skilled in the art, so they will not be elaborated in detail here.

[0042] By Figure 1 and Figure 2It can be known that before the inverter system starts the inversion work, the only difference between the Heric inverter topology system and the H4 inverter topology system lies in two IGBT switches, S5 and S6. Taking photovoltaic power generation as an example, if the voltage output by the solar cell PV is lower than the grid-connected voltage, the BOOST boost circuit needs to first increase the bus voltage to a certain value, and then the BOOST boost circuit stops working. However, regardless of whether the BOOST circuit is working or not, in the leakage current analysis loop, assuming that the output voltage of the PV cell is constant or changes very little, the Y capacitor C on the PV cell side PV+ and the Y capacitor C on the bus side DC+ can be equivalent to a capacitor C on the bus side after they are connected in parallel. That is, C POS can be set as C POS = C PV+ + C DC+ . The specific proof process is well-known to those skilled in the art, so it will not be elaborated in detail here.

[0043] In addition, during the relay self-checking stage and the grid-connected stage, the Heric inverter topology does not work, and the switches S1~S6 do not act. The two freewheeling IGBT switches, S5 and S6, are connected in series at the reverse ends. Due to the existence of the anti-parallel diodes, no current is allowed to pass through them. That is, in the leakage current loop analysis, the leakage current loops of the Heric inverter topology and the H4 inverter topology are the same.

[0044] In a general power system, the grid N line is connected to the ground, that is, the voltage between the N line and the ground is V N = 0V and the voltage change rate is 0. Since the bus voltage v bus is greater than the peak value v gmax of the grid voltage, then in the case of no huge leakage current passing through the Y capacitor to the ground, the voltage v NEG of the Y capacitor C neg < 0V, v neg ≤ V N (i.e., 0V) ≤ v dc+ ; where v dc+ represents the positive bus voltage to the ground, which causes the anti-parallel diodes of the switches S1~S4 to be reverse-biased. When the grid-connected relays T3 and T4 are both attracted and conducted, the N line cannot form a leakage current loop with the DC side. Therefore, the Heric and H4 inverter topology systems can construct the same leakage current equivalent loop, and the specific loop structure is as shown in Figure 3 . Based on the leakage current equivalent loop shown in Figure 3 , the specific generation process of the leakage current will be described in detail below.

[0045] As shown in Figure 4 , it is a schematic diagram of the waveform structure of the grid voltage v g ; fromFigure 4 It can be known that the waveform of the grid voltage v g is sinusoidally periodic. When the bus voltage v bus is greater than the peak value v gmax of the grid voltage, the inverter system will be connected to the grid. At this time, the grid-connected relays T1 and T2 will always be in the closed state. Then, the specific analysis of the leakage current generation process can be carried out according to the waveform change of the grid voltage. The waveform change process of the grid voltage can be divided into four processes, which will be specifically described below.

[0046] Process 1: As Figure 4 shown, within the 0 - T / 4 period of the grid voltage, 0 < v g < v gmax , and the change amount dv g / dt ≥ 0 of the grid voltage. When the grid voltage rises to v g >v pos , the diode D1 conducts, and the conduction state of the leakage current equivalent circuit is as Figure 5 shown. Among them, v pos represents the voltage of the equivalent capacitor C POS , and v pos = v bus + v neg .

[0047] After the diode D1 conducts, the equivalent capacitor C POS is charged and its voltage v pos increases with the increase of the grid voltage until v pos = v gmax . Then, the current i POS flowing through the equivalent capacitor C p = C POS × dv pos / dt. The bus voltage v bus is approximately constant. Then, according to the KVL equation, it can be known that the capacitor C NEG is charged and its voltage v neg increases. And because the bus voltage stabilizing capacitor C BUS (generally hundreds to thousands of microfarads, related to the inverter power) is much larger than the capacitor C POS and the capacitor C NEG , so according to the capacitor series formula, the series equivalent capacitor of C BUS and C NEG can be approximated as C NEG . Then, the current i NEG of the capacitor C n = C NEG × dv pos / dt; furthermore, i p / i n = C POS / CNEG In Figure 5 the leakage current equivalent circuit shown, the loop current i L According to the KCL equation, we can get:

[0048] i L = i p +i n =( C POS + C NEG )×dv pos / dt.

[0049] Since the damping resistance in the current loop is very small, almost only the parasitic resistance of the inductor copper wire and the PCB copper pour, about several hundred milliohms, and the ratio of the inductance value of inductor L1 to the total capacitance value of the Y capacitor is large, series oscillation is likely to occur. At the same time, during this period, the grid voltage is continuously rising, so the voltage waveforms of capacitor C BUS and capacitor C POS are rising curves with slight oscillations. Since the capacitor current is proportional to the derivative of the capacitor voltage (leading the voltage), the capacitor voltage oscillation will also cause the currents i p and i n to oscillate violently.

[0050] Process two: As shown in Figure 4 , after process one is completed, there is v pos =v gmax , v neg =v pos -v bus = v gmax -v bus <0. Then, within the T / 4~T / 2 period of the grid voltage, there is 0<v g <v gmax , and the rate of change of the grid voltage dv g / dt ≤ 0. After the grid voltage exceeds the peak time point (t>T / 4), the grid voltage starts to decrease. At this time, v g >0, v pos =v gmax , v neg <0. Since v pos >v g and v neg <v g , the diodes D1 and D3 are turned off. At this time, the leakage current loop cannot be formed, so the loop current i L =0, and the voltages of capacitor C POS and capacitor C NEG will remain unchanged.

[0051] Process three: As shown in Figure 4 , within the T / 2~3T / 4 period of the grid voltage, there is 0<vg <v gmax , and the rate of change of the grid voltage dv g / dt ≤ 0; the grid voltage v g is less than 0 and keeps decreasing. In the initial short period of time, because v pos = v gmax > 0 > v g > v neg , so the diodes D1 and D3 still remain cut-off, that is, no leakage current loop is generated. At this time, the capacitors C POS and the capacitor C NEG still maintain a constant voltage. However, when the grid voltage drops to v g < v neg , the diode D3 conducts, and the corresponding leakage current loop formed is as shown in Figure 6 .

[0052] As can be seen from Figure 6 , when the diode D3 conducts, the capacitor C NEG discharges, causing its voltage v neg to decrease with the grid voltage until v neg = -v gmax , then i n = C NEG × dv neg / dt. The bus voltage v bus is approximately constant. Then, according to the KVL equation, the capacitor C POS discharges, causing its voltage v pos to decrease. And because the bus voltage stabilizing capacitor C BUS (generally hundreds to thousands of microfarads, related to the inverter power) is much larger than the capacitors C POS and the capacitor C NEG , so according to the capacitor series formula, the series equivalent capacitance of C BUS and C POS can be approximated as C POS , then i p = C POS × dv neg / dt; furthermore, there is i p / i n = C POS / C NEG . According to the KCL equation, it can be known that:

[0053] i L = -(i p + i n ) = -(C POS + C NEG ) × dv neg / dt.

[0054] Similar to Process 1, in Process 3, since the damping resistance in the current loop is very small and the grid voltage is continuously decreasing during this period, capacitor C BUS and C POS have a voltage waveform that is a decreasing curve with slight oscillations. Since the capacitor current is proportional to the derivative of the capacitor voltage, the capacitor voltage oscillations will also cause current i p and i n to oscillate violently.

[0055] Process 4: As Figure 4 shown, within the period of 3T / 4 to T of the grid voltage, -v gmax < v g < 0, and the rate of change of the grid voltage dv g / dt ≥ 0. After the time point when the grid voltage exceeds the negative peak (t > 3T / 4), the grid voltage starts to increase. At this time, v g <0, v neg = -v gmax , v pos >0. Since v pos > v g and v neg < v g , diodes D1 and D3 are turned off. At this time, the leakage current loop cannot be formed, so the loop current i L = 0, and capacitors C POS and capacitor C NEG will maintain a constant voltage.

[0056] From the analysis of the above four processes, it can be seen that when the grid-connected relays T1 and T2 are always closed, the magnitude of the leakage current is proportional to the sum of all Y capacitors on the DC side. To more clearly understand the formation of the leakage current, the waveform structure of the leakage current can also be obtained through software simulation.

[0057] For example, a simulation model can be built in MATLAB / SIMULINK software. Determine the parameters of each component in the simulation software: C POS = C NEG = 20 nF (total capacitance value is 40 nF), inductance L1 is 450 μH, bus voltage is 400 V, and the initial voltage v POS of Y capacitor C pos = 150 V. Through software simulation, the simulation waveforms of Process 1 to Process 4 can be obtained. Specifically, as Figure 7 shown, the peak value of the leakage current is about 7 mA. By locally magnifying the waveform of the loop current, a schematic diagram of the locally magnified waveform as Figure 8 shown can be obtained. From Figure 8 it can be seen that the waveform of the Y capacitor current in the loop is in a continuous oscillation state.

[0058] However, in the actual working process, the grid-connected relays T1 and T2 are not always in the closed state. Instead, they have multiple processes of closing and opening. If the moment when both grid-connected relays T1 and T2 are closed is not selected correctly, it will lead to a huge leakage current, causing the leakage protector to misreport and trip the grid. For example, Figure 9 As shown, when the grid-connected relays T1 and T2 are closed at t = T + T / 4, at this time, due to the grid voltage v g being greater than v pos , the diode D1 conducts, and the Y-capacitor is charged, resulting in a leakage current spike. When performing simulations with the same component parameters, if the closing moment of the grid-connected relay is not selected appropriately, the peak value of the leakage current can reach more than 1.5 A. Compared with the peak leakage current of 7 mA generated when the grid-connected relay is always closed, an inappropriate closing moment of the grid-connected relay is more likely to cause the leakage protector to misreport and trip the grid, which has a huge impact on the grid connection stage. At the same time, due to the half-period LC oscillation of the Y-capacitor and the inductor L1, the value of the voltage v pos is much greater than the grid voltage, and the peak value can reach 500 V. Such a large voltage will seriously threaten the safe operating performance of the Y-capacitor.

[0059] For the convenience of understanding, the generation process of the mutant current will be described below through specific parameters. The LCR series circuit composed of the Y-capacitor, the inductor L1, and the parasitic resistor R para , the parasitic resistor R para is basically only a few hundred milliohms. The closing of the grid-connected relays T1 and T2 is equivalent to inputting a step voltage signal to the LCR series circuit. According to the calculation of the critical damping formula of the LCR oscillation, the minimum resistance R CRI that can prevent the voltage oscillation of the Y-capacitor is:

[0060] .

[0061] Since the resistance R para is much smaller than R CRI , the voltage of the Y-capacitor will oscillate, making the voltage across the Y-capacitor much greater than the input step voltage (i.e., v g ). If the positive and negative poles of the diode are short-circuited, the leakage current passing through the Y-capacitor and the inductor L1 will continue to oscillate. In the mathematical tool Mathcad, the time-domain function expression of the leakage current can be relatively simply solved through the relevant knowledge of Laplace. The time-domain waveform of the leakage current is as Figure 10 shown. It can be seen that when the positive and negative poles of the diode are short-circuited, the value of the leakage current will oscillate back and forth in the positive and negative regions.

[0062] However, due to the presence of diodes D1 and D3, the leakage current can only flow unidirectionally, and its value can only be limited to above 0 A or below 0 A, resulting in the inability to release the current after the Y-capacitor voltage oscillates for half a cycle (similar to quickly transitioning from process one to process two or from process three to process four). That is, as Figure 11 shown, the circuit only oscillates for half a cycle, causing a very large leakage current spike to appear at the moment of closing. The leakage current spike may cause the leakage protector to trip or the inverter to fail to connect to the grid.

[0063] Based on the above analysis process, one aspect of the present application provides a method for suppressing the sudden change of leakage current during the grid connection stage, which is applied to Heric-type and H4-type inverter topology systems. As Figure 1 shown, one preferred embodiment includes the following steps: collecting the ground voltage, bus voltage, and grid voltage of the inverter system; constructing a safe voltage threshold range based on the collected ground voltage and bus voltage; and closing the grid connection relay within the safe time zone corresponding to the grid voltage falling within the safe voltage threshold range.

[0064] It can be understood that the prerequisite for the sudden change of leakage current is that the leakage current loop can be formed; from the above analysis process, it can be seen that when the grid voltage rises to v g > v pos , diode D1 conducts to form a leakage current loop, or when the grid voltage drops to v g < v neg , diode D3 conducts to form a leakage current loop as well. Then those skilled in the art should know that if the leakage current loop cannot be formed, the sudden change of leakage current will not occur either. Therefore, the idea of the technical solution of the present application to suppress the sudden change of leakage current is to truncate the formation of the leakage current loop; that is, the closing timing of grid connection relays T1 and T2 is selected in the time period when both diodes D1 and D3 are reverse-biased, so as to ensure that the leakage current loop cannot be formed and the corresponding sudden change of leakage current will not occur.

[0065] Compared with the traditional method of suppressing the sudden change of leakage current, the present application does not need to change the hardware structure of the system circuit. It only utilizes the characteristics of the circuit itself and can completely eliminate the sudden change of leakage current by controlling the closing timing of the grid connection relay, enhancing the working stability of the inverter system and reducing the damage to other components of the system caused by the large voltage of the Y-capacitor generated along with the sudden change current.

[0066] It should be known that there are various ways to define the range of the safe time zone for the simultaneous closing of the grid connection relay. However, from the above analysis process, it can be seen that the voltage range corresponding to the safe time zone needs to be between the voltages v neg and v pos ; that is, as Figure 13 shown, the lower limit of the safe voltage threshold range is the ground voltage vneg The upper limit of the safe voltage threshold range is the sum of the ground voltage and the bus voltage, v pos .

[0067] In this embodiment, during the actual closing process of the grid-connected relay, there is a time delay ΔT between the issuance of the grid-connected relay closing signal and the successful full closing of the grid-connected relay. This is related to the type of the grid-connected relay, the supply voltage, etc., but the closing delay of each model can basically be measured actually. Therefore, when setting the safe time zone, the closing delay time ΔT of the grid-connected relay needs to be considered; that is, the actual required safe time zone can be obtained by advancing the safe time period corresponding to the intersection positions of the grid voltage with the upper and lower limits of the safe voltage threshold range by ΔT time. That is, the duration of the safe time period and the safe time is equal, but the safe time zone is advanced by ΔT time relative to the safe time period. The grid-connected relay only needs to close within the safe time zone to ensure that the moment of full closing is within the safe time period.

[0068] For the convenience of understanding, specific examples will be described in detail below. As Figure 13 shown, the time nodes corresponding to the intersection points of the grid voltage and the voltages v neg and v pos are t 01 , t 02 , t 03 and t 04 . Among them, a safe time period can be formed between t 01 and t 02 , and a safe time period can also be formed between t 03 and t 04 . When the grid-connected inverter system is connected to the grid, it only needs to include that the time point of the full closing of the grid-connected relay is between t 01 and t 02 or between t 03 and t 04 . Then, for the closing timing of the grid-connected relay, only the time nodes t 01 , t 02 , t 03 and t 04 are all advanced by a ΔT time, and then the time nodes t1, t2, t3, and t4 can be obtained; among them, a safe time zone can be formed between t1 and t2, and a safe time zone can be formed between t3 and t4; then the grid-connected relay starts to close between t1 and t2 or between t3 and t4, and then the time node when the grid-connected relay terminates to achieve full closing must be between t 01 and t 02 or between t 03 and t 04 .

[0069] In this embodiment, as Figure 13 shown, there are multiple consecutive safety time zones corresponding to the grid voltage falling within the range of the safety voltage threshold. The grid-connected relay can be closed in any safety time zone to completely suppress the sudden change of the leakage current. However, in order to improve the self-checking efficiency of the grid-connected relay, the grid-connected relay preferably closes in the nearest safety time zone that meets the closing time requirement from the current moment.

[0070] In this embodiment, the judgment of the nearest safety time zone that meets the closing time requirement for the grid-connected relay from the current moment is related to the position of the current moment. Based on different positions of the current moment, the judgment process for the nearest safety time zone that meets the closing time requirement is different. For the convenience of understanding, the following will be described in detail.

[0071] Position 1: If the current moment is outside the nearest safety time period, the judgment of the nearest safety time zone that meets the closing time requirement includes the following process: Calculate the first time interval between the current moment t p and the start point t s of the nearest safety time period. If the calculated first time interval is greater than ΔT, the safety time zone corresponding to this nearest safety time period meets the closing time requirement. If the calculated first time interval is less than or equal to ΔT, continue to calculate the second time interval between the current moment and the end point t k of the nearest safety time period; if the calculated second time interval is greater than ΔT, the safety time zone corresponding to this nearest safety time period meets the closing time requirement; otherwise, the safety time zone corresponding to this nearest safety time period does not meet the closing time requirement. At this time, the next safety time zone is used as the nearest safety time zone that meets the closing time requirement.

[0072] Position 2: If the current moment is within the nearest safety time period, the judgment of the nearest safety time zone that meets the closing time requirement includes the following process: Calculate the time interval between the current moment t p and the end point t k of the nearest safety time period; if the calculated time interval is greater than ΔT, the safety time zone corresponding to this nearest safety time period meets the closing time requirement; if the calculated time interval is less than or equal to ΔT, the safety time zone corresponding to this nearest safety time period does not meet the closing time requirement. At this time, the next safety time zone is used as the nearest safety time zone that meets the closing time requirement.

[0073] For the convenience of understanding, the following will describe the specific closing process of the grid-connected relay in detail. As Figure 14 shown, first collect the ground voltage v neg , the bus voltage v bus , and the grid voltage v g . According to the collected voltage parameters, the range of the safety voltage threshold [vneg , v neg +v bus , and then, according to the intersection of the grid voltage v g and the safety voltage threshold range, all safety time periods are divided.

[0074] Then, it is judged whether the closing of the grid-connected relays T1 and T2 needs to be carried out simultaneously. If the grid-connected relays T1 and T2 are closed successively, a grid-connected relay closing signal is directly sent to the grid-connected relays T1 and T2; if the grid-connected relays T1 and T2 need to be closed simultaneously, the current time t p to the starting point t s of the nearest safety time period and the end point t k are calculated.

[0075] If the current time t p and the starting point t s of the safety time period have an interval greater than the closing delay time ΔT of the grid-connected relay, that is, t s - t p > ΔT, it means that the current time t p is outside the nearest safety time period. Then, a grid-connected relay closing signal can be sent to the grid-connected relays T1 and T2 after delaying at least t s - t p - ΔT time.

[0076] If the current time t p and the starting point t s of the safety time period have an interval less than or equal to the closing delay time ΔT of the grid-connected relay, that is, t s - t p ≤ ΔT; there are two cases at this time, which are described in detail below.

[0077] The first case: t s - t p ≥ 0, it means that the current time t p is still outside the nearest safety time period. At this time, it is necessary to judge whether the duration of the safety time period can meet the requirement of the closing delay time of the grid-connected relay. Then, the interval between the current time t p and the end point t k of the safety time period is calculated and judged whether it is greater than the closing delay time ΔT of the grid-connected relay. If t k - t p > ΔT, a grid-connected relay closing signal is sent to the grid-connected relays T1 and T2 immediately or at most after delaying t k - t p - ΔT time. If t k - t p > ΔT is not satisfied, the starting point t of the next safety time period is searched.s And calculate again whether the interval time between this starting point and the current moment meets the requirement of the closing delay time ΔT of the grid-connected relay. Generally speaking, the interval of the next safe time period can meet the requirement of the closing delay time ΔT of the grid-connected relay. Then, it is only necessary to delay at least for t s -t p -ΔT time and then send the grid-connected relay closing signal to the grid-connected relays T1 and T2

[0078] The second case: t s -t p <0, which means that the current moment t p is within the nearest safe time period. At this time, it is necessary to judge whether the remaining duration of the safe time period can meet the requirement of the closing delay time of the grid-connected relay. Then, calculate the interval between the current moment t p and the end point t k of the safe time period and judge whether it is greater than the closing delay time ΔT of the grid-connected relay. If t k -t p >ΔT, immediately or at most delay for t k -t p -ΔT time and send the grid-connected relay closing signal to the grid-connected relays T1 and T2. If t k -t p >ΔT is not satisfied, then find the starting point t s of the next safe time period and calculate whether the interval time between this starting point and the current moment meets the requirement of the closing delay time ΔT of the grid-connected relay. Generally speaking, the interval of the next safe time period can meet the requirement of the closing delay time ΔT of the grid-connected relay. Then, it is only necessary to delay at least for t s -t p -ΔT time and then send the grid-connected relay closing signal to the grid-connected relays T1 and T2

[0079] In this embodiment, if the frequency of the grid voltage is too high, it may cause the duration of the safe time zone to be shortened to not meet the requirement of the closing time of the grid-connected relay, that is, the duration from when the grid-connected relay receives the closing signal to being fully closed may need to span multiple safe time zones; since the selection of the closing timing of the grid-connected relay needs to calculate the time interval of each safe time zone it spans, this will increase the overall calculation amount of the inverter system, thereby reducing the response speed and affecting the closing accuracy of the grid-connected relay. Therefore, when the duration of the safe time zone does not meet the requirement of the closing time of the grid-connected relay, the bus voltage can be boosted to increase the upper limit of the safe voltage threshold range, thereby increasing the duration of the safe time zone to meet the requirement of the closing time; after the grid-connected relay is closed, the grid voltage is stepped down and reset

[0080] It can be understood that, from the foregoing, the upper limit of the safe voltage threshold range is the sum of the ground voltage and the bus voltage. Then, by boosting the bus voltage, the upper limit of the safe voltage threshold range can be increased, thereby shifting the intersection position of the grid voltage and the upper limit of the safe voltage range upward, and the duration of the corresponding safe time zone will gradually increase. The degree of increase in the duration of the safe time zone can be selected according to actual needs; for the convenience of further simultaneous energization of the grid-connected relays T1 and T2, as Figure 15 shown, in this embodiment, it is preferably to boost the bus voltage to be greater than the peak value of the grid voltage.

[0081] It should be known that there are various ways to boost the bus voltage. Considering that the converter of the inverter system often uses a BOOST boost circuit, the bus voltage can be boosted through the BOOST boost circuit.

[0082] Another aspect of the present application provides a system for suppressing the sudden leakage current during the grid connection stage, which is used to implement the method for suppressing the sudden leakage current during the grid connection stage, as Figure 16 shown. One preferred embodiment includes an acquisition unit 100, a calculation unit 200, and a control unit 300; the acquisition unit 100 is used to acquire the ground voltage, bus voltage, and grid voltage of the inverter system; the calculation unit 200 calculates the safe voltage threshold range according to the voltage data obtained by the acquisition unit 100, and constructs a safe time zone in which the grid voltage falls within the safe voltage threshold range; the control unit 300 can send an energization control signal to the grid-connected relay so that the grid-connected relay completes energization within the safe time zone.

[0083] It should be known that the specific structures and working principles of the acquisition unit 100, the calculation unit 200, and the control unit 300 are all well-known technologies to those skilled in the art, so they will not be elaborated in detail here. The common acquisition unit 100 can use a voltage sensor, and the ground voltage, bus voltage, and grid voltage can be acquired through the corresponding voltage sensors respectively. The calculation unit 200 and the control unit 300 can be set independently or integrated, such as MCU chips and DSP chips.

[0084] The above describes the basic principle, main features, and advantages of the present application. Those skilled in the art of this industry should understand that the present application is not limited by the above embodiments. What is described in the above embodiments and the specification is only the principle of the present application. Without departing from the spirit and scope of the present application, the present application will have various changes and improvements, and these changes and improvements all fall within the scope of the present application claimed. The scope of protection required by the present application is defined by the appended claims and their equivalents.

Claims

1. A method for suppressing sudden leakage current during the grid-connected phase, applied to Heric and H4 inverter topology systems, characterized in that: The steps include: Collect the ground voltage, bus voltage and grid voltage of the inverter system; construct a safe voltage threshold range based on the collected ground voltage and bus voltage; and close the grid-connected relay in the safe time zone corresponding to the safe voltage threshold range when the grid voltage falls into the safe time zone; The lower limit of the safety voltage threshold range is the ground voltage, and the upper limit of the safety voltage threshold range is the sum of the ground voltage and the bus voltage; The pick-up delay time of the grid-connected relay is ; Prefix the safety time period corresponding to the upper and lower limits of the safety voltage threshold range where the grid voltage intersects Time gets safe time zone; If the duration of the safety time zone does not meet the closing time requirement of the grid-connected relay, the bus voltage is raised to increase the upper limit of the safety voltage threshold range, thereby increasing the duration of the safety time zone to meet the closing time requirement; after the grid-connected relay is closed, the grid voltage is reduced and reset.

2. The method for suppressing sudden leakage current during the grid connection phase according to claim 1, characterized in that: There are multiple continuous safety time zones corresponding to the grid voltage falling into the safety voltage threshold range; the grid-connected relay is suitable for being attracted in the nearest safety time zone that meets the attraction time requirement at the current moment.

3. The method for suppressing sudden leakage current during the grid connection phase according to claim 2, characterized in that: If the current time is within the nearest safe time period, the determination of the nearest safe time zone that meets the pull-in time requirements includes the following process: Calculate the time interval between the current time and the end point of the nearest safe time period; If the calculated time interval is greater than , the safety time zone corresponding to the most recent safety time period meets the pull-in time requirements; If the calculated time interval is less than or equal to , the safety time zone corresponding to the most recent safety time period does not meet the pull-in time requirement, and the next safety time zone is used as the most recent safety time zone that meets the pull-in time requirement.

4. The method for suppressing sudden leakage current during the grid connection phase according to claim 2, characterized in that: If the current time is outside the nearest safe time period, the determination of the nearest safe time zone that meets the pull-in time requirements includes the following process: Calculate the first time interval between the current time and the starting point of the nearest safe time period; If the first time interval calculated is greater than , the safety time zone corresponding to the most recent safety time period meets the pull-in time requirements; If the calculated first time interval is less than or equal to , continue to calculate the second time interval between the current moment and the end point of the nearest safe time period; If the calculated second time interval is greater than , the safety time zone corresponding to the most recent safety time period meets the pull-in time requirements; Otherwise, the safety time zone corresponding to the nearest safety time period does not meet the pull-in time requirement, and the next safety time zone is used as the nearest safety time zone that meets the pull-in time requirement.

5. The method for suppressing sudden leakage current during the grid connection phase according to claim 1, characterized in that: The bus voltage rises to a peak value greater than the grid voltage.

6. The method for suppressing sudden leakage current during the grid connection phase according to claim 1, characterized in that: The bus voltage is boosted by the BOOST circuit.

7. A system for suppressing sudden leakage current during the grid-connection phase, used for implementing the method for suppressing sudden leakage current during the grid-connection phase according to any one of claims 1 to 6, characterized in that: include: Acquisition unit; The acquisition unit is used to collect the ground voltage, bus voltage and grid voltage of the inverter system; Computational unit; The calculation unit calculates the safe voltage threshold range according to the voltage data acquired by the acquisition unit, and constructs a safe time zone in which the grid voltage falls within the safe voltage threshold range; as well as Control unit; the control unit is suitable for sending a pull-in control signal to the grid-connected relay so that the grid-connected relay completes the pull-in within the safe time zone.

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