Standby power supply automatic switching circuit, MCU chip and device

Abstract

The invention discloses a standby power supply automatic switching circuit, an MCU chip and a device, and the circuit comprises a PMOS turn-off voltage selection module, a level shift module, a PMOS switch gating module and an LDO module, the circuit is automatically switched to a standby battery for power supply when an external power supply is powered down, and the circuit is switched back to the external power supply for power supply when the external power supply is recovered. Therefore, the dynamic switching of the standby battery and the external power supply is realized. Besides, on the basis of flexibly switching the power supply mode, the voltage drop characteristic of the input voltage is optimized through a PMOS switch gating module, so that the circuit can still work normally within the wide voltage range of 1.8-3.6 V. Based on a PMOS turn-off voltage selection module, a voltage capable of turning off a PMOS (switch) is selected from an external power supply voltage and a standby battery voltage as a grid voltage, so that an electric leakage phenomenon when the PMOS is turned off is avoided, and the circuit stability is ensured. And extra quiescent current generated when the battery is not gated is avoided, the total current consumption of the battery at normal temperature is ensured to be lower than 5 microamperes, and the power consumption is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a backup power supply automatic switching circuit, an MCU chip and a device. Background Art

[0002] In the design of microcontroller unit (MCU) chips, the development and optimization of power management modules are widely involved. In some MCU and related chip products, a dual power design scheme of external power supply and backup battery power supply is often adopted. This design is mainly used to automatically switch to the backup battery power supply when the external power supply is cut off to ensure the preservation of the core static random access memory (SRAM) data and the normal operation of the real-time clock (RTC) function. When the external power is restored, the system will automatically switch back to the external power supply.

[0003] Most power management structures that automatically switch between external power and backup batteries usually use two diodes to pre-select the maximum external voltage as the operating voltage of modules such as the bandgap reference circuit, hysteresis comparator, and level shift circuit to achieve power switching. However, this structure has many shortcomings in practical applications, especially in application scenarios that meet the requirements of wide voltage range (1.8V~3.6V) and low power consumption (battery power consumption is less than 5μA at room temperature). The normal operation of the system is limited and cannot adapt to the requirements of the wide voltage range. At the same time, when the system selects an external power supply as the power source, if the backup battery voltage is greater than the external power supply voltage, the path that should be turned off is prone to leakage problems, affecting the stability of the circuit. In addition, when the backup battery power supply is selected, there is a non-negligible static current consumption in the level shift circuit. For products with strict restrictions on current consumption (μA level), this problem becomes a major obstacle to achieving low-power design.

[0004] In summary, the power management structure in the related art has technical problems such as being unable to meet the usage scenarios of a wide voltage range, high power consumption, and insufficient circuit stability. Summary of the invention

[0005] The main purpose of the present invention is to propose a backup power automatic switching circuit, MCU chip and device, aiming to at least solve the technical problems existing in the power management structure in the related technology, such as the inability to meet the usage scenarios of a wide voltage range, high power consumption, and insufficient circuit stability.

[0006] In a first aspect of the present invention, a backup power automatic switching circuit is provided, which is applied to an MCU chip, and the backup power automatic switching circuit includes a PMOS shutdown voltage selection module, a level shift module, a PMOS switch gating module and an LDO module;

[0007] The output end of the PMOS shutdown voltage selection module is electrically connected to the input end of the level shift module, the output end of the level shift module is electrically connected to the control signal input end of the PMOS switch gating module, the output end of the PMOS switch gating module is electrically connected to the input end of the LDO module, the voltage input end of the PMOS switch gating module is used to receive an external power supply voltage or a backup battery voltage, and the input end of the PMOS shutdown voltage selection module is used to receive the external power supply voltage and the backup battery voltage;

[0008] Among them, the PMOS shutdown voltage selection module is used to select one from the external power supply voltage and the backup battery voltage as a first target voltage to output to the level shift module, the level shift module is used to output a switch state control signal to the control signal input end of the PMOS switch gating module according to the first target voltage, and the PMOS switch gating module is used to select one from the external power supply voltage and the backup battery voltage as the current power supply voltage according to the switch state control signal, and output the current power supply voltage to the LDO module to control the LDO module to output a second target voltage to the MCU chip.

[0009] A second aspect of the present invention provides an MCU chip, comprising a chip body and a backup power automatic switching circuit as in the first aspect integrated in the chip body.

[0010] A third aspect of the present invention provides an automatic backup power supply switching device, wherein the automatic backup power supply switching device is equipped with the automatic backup power supply switching circuit of the first aspect.

[0011] The automatic switching circuit, MCU chip and device of the backup power supply of the present invention, by including a PMOS shutdown voltage selection module, a level shift module, a PMOS switch gating module and an LDO module, automatically switches to the backup battery power supply when the external power supply is powered off, and switches back to the external power supply when the external power supply is restored, that is, the dynamic switching of the backup battery and the external power supply is realized. In addition, on the basis of the above-mentioned flexible switching power supply mode, the voltage drop characteristics of the input voltage are optimized through the PMOS switch gating module to ensure that the circuit can still work normally in a wide voltage range of 1.8V to 3.6V. And based on the PMOS shutdown voltage selection module, a voltage that can turn off the PMOS (switch) is selected from the external power supply voltage and the backup battery voltage as its gate voltage to avoid leakage when the PMOS is turned off to ensure circuit stability. And avoid the additional static current generated when the battery is not gated, ensure that the total current consumption of the battery is less than 5μA at room temperature, and greatly reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 It is a structural block diagram of an external power supply and a battery switch provided in the related art;

[0014] Figure 2 A circuit connection diagram of a level shift circuit provided in the related art;

[0015] Figure 3 A schematic diagram of module connections in the automatic backup power switching circuit provided in an embodiment of the present application;

[0016] Figure 4 This is a circuit connection diagram of a PMOS turn-off voltage selection module in an embodiment of the present application;

[0017] Figure 5 This is a DC scan simulation waveform diagram of the evaluation of the PMOS turn-off voltage selection module in the embodiment of the present application;

[0018] Figure 6 This is a transient simulation waveform diagram of the first target voltage VMAX output by the PMOS turn-off voltage selection module when VBAT is powered on first in the embodiment of the present application;

[0019] Figure 7 This is a transient simulation waveform diagram of the first target voltage VMAX output by the PMOS turn-off voltage selection module when VDD is powered on first in the embodiment of the present application;

[0020] Figure 8 Schematic diagram of circuit connection of the level shift module in the embodiment of the present application;

[0021] Fig. 9 This is a circuit connection diagram of a PMOS switch gating module in an embodiment of the present application;

[0022] Fig.10 Schematic diagram of circuit connection of the second bandgap reference module in the embodiment of the present application;

[0023] Fig.11 A waveform diagram of a second reference voltage VREF2 output by a second bandgap reference module in accordance with an embodiment of the present application with respect to a VCC DC scan simulation;

[0024] Fig.12This is a waveform diagram of a temperature scan simulation of a second reference voltage VREF2 output by a second bandgap reference module in an embodiment of the present application.

[0025] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0027] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and the second component can also be referred to as a first component similarly. The term "and / or" refers to any one or more combinations of related items and description items.

[0028] See also Figure 1 and Figure 2 The power management structure of the related technology has four shortcomings: 1. The operating voltage of the bandgap reference circuit and the hysteresis comparator is V H , compared to the input voltage V DD or V BAK The voltage is about 0.6V lower. In the case of low input voltage (such as 1.8V), this structure has limitations. 2. The application conditions of the level shift circuit are limited. When V DD As power supply (at this time, V S =V DD ), if V BAK -V DD >|V TH |, then connect to V BAK and V S The PMOS switch will be turned on (it should be turned off); 3. When VDD is selected for power supply, if V BAK >V DD , due to V H The selected BAK , so the bandgap reference circuit and hysteresis comparator are still powered by the battery, resulting in a shortened battery life; 4. When V BAK When power is supplied, there is a current V in the level shift circuit. BAK / R2. In products that require low battery power consumption (μA level), the current on this level shift circuit R2 cannot be ignored. That is, the power management structure in the related art has technical problems such as being unable to meet the use scenarios of a wide voltage range, high power consumption, and insufficient circuit stability.

[0029] To solve the above technical problems, please refer to Figure 3 An embodiment of the present application provides a backup power automatic switching circuit, which is applied to an MCU chip. The backup power automatic switching circuit includes a PMOS shutdown voltage selection module 10, a level shift module 20, a PMOS switch selection module 30 and an LDO module 40.

[0030] Specifically, the output end of the PMOS shutdown voltage selection module 10 is electrically connected to the input end of the level shift module 20, the output end of the level shift module 20 is electrically connected to the control signal input end of the PMOS switch gating module 30, the output end of the PMOS switch gating module 30 is electrically connected to the input end of the LDO module 40, the voltage input end of the PMOS switch gating module 30 is used to receive the external power supply voltage VDD or the backup battery voltage VBAT, and the input end of the PMOS shutdown voltage selection module 10 is used to receive the external power supply voltage VDD and the backup battery voltage VBAT.

[0031] In the backup power automatic switching circuit, the PMOS shutdown voltage selection module 10 is used to select between the external power supply voltage VDD and the backup battery voltage VBAT, and select one of the above two voltages as the first target voltage VMAX to output to the level shift module 20, the level shift module 20 is used to output the switch state control signal SW to the control signal input end of the PMOS switch gating module 30 according to the first target voltage VMAX, the PMOS switch gating module 30 is used to select one from the external power supply voltage VDD and the backup battery voltage VBAT as the current power supply voltage VCC according to the switch state control signal SW, and output the current power supply voltage VCC to the LDO module 40 to control the LDO module 40 to output the second target voltage VDD12 to the MCU chip.

[0032] The automatic switching circuit, MCU chip and device of the backup power supply of the present invention automatically switch to the backup battery power supply when the external power supply is powered off, and switch back to the external power supply power supply when the external power supply is restored, that is, the dynamic switching of the backup battery and the external power supply is realized to ensure the stable power supply of the MCU system. In addition, on the basis of the above-mentioned flexible switching power supply mode, the voltage drop characteristics of the input voltage are optimized through the PMOS switch gating module to ensure that the circuit can still work normally in the wide voltage range of 1.8V to 3.6V. And based on the PMOS shutdown voltage selection module, a voltage that can turn off the PMOS (switch) is selected from the external power supply voltage and the backup battery voltage as its gate voltage to avoid leakage when the PMOS is turned off to ensure circuit stability. And avoid the additional static current generated when the battery is not gated, ensure that the total current consumption of the battery is less than 5μA at room temperature, and greatly reduce power consumption.

[0033] In an optional implementation of this embodiment, the backup power automatic switching circuit also includes a VDD power-on reset module 50, the input end of the VDD power-on reset module 50 is used to receive the external power supply voltage VDD, and the output end of the VDD power-on reset module 50 is electrically connected to the input end of the level shift module 20.

[0034] Specifically, the VDD power-on reset module 50 is used to output a power-on reset signal to the level shift module 20 according to the first reference voltage VREF1. The power-on reset signal POR is used to initialize the working state of the level shift module 20, ensuring that the level shift module 20 enters a stable working state when the system is powered on, thereby providing a correct switch state control signal SW for the PMOS switch gating module 30. By introducing the VDD power-on reset module 50, when the system is powered on or the external power supply voltage VDD is restored, the level shift module 20 can be quickly reset based on the power-on reset signal POR, avoiding erroneous operation or power supply switching delay caused by abnormal initialization of the level shift module.

[0035] In an optional implementation of this embodiment, the automatic backup power switching circuit further includes a first bandgap reference module 60, the input end of the first bandgap reference module 60 is used to receive the external power supply voltage VDD, and the output end of the first bandgap reference module 60 is electrically connected to the input end of the VDD power-on reset module 50. The first bandgap reference module 60 is used to transmit the generated first reference voltage VREF1, the first bias current Ibp1 and the external power supply state signal BG_OK to the VDD power-on reset module 50. The external power supply state signal indicates the current working state of the external power supply,

[0036] Specifically, by introducing the first bandgap reference module 60, based on the first reference voltage VREF1, the first bias current Ibp1 and the power state signal BG_OK provided by it, the working state of the level shift module 20 is effectively initialized in cooperation with the VDD power-on reset module 50, the working stability of the automatic switching circuit of the backup power supply and the reliability of the power supply switching are further improved, and the application requirements of the MCU chip in a wide voltage domain (1.8V~3.6V) and low power consumption conditions are met. The specific principle is as follows: the first reference voltage and the first bias current generated by the first bandgap reference module 60 ensure that the VDD power-on reset module 50 can work stably under different power supply voltage conditions, thereby improving the working reliability and adaptability of the entire circuit. The first bandgap reference module 60 generates an external power state signal BG_OK, which indicates the current working state of the external power supply VDD in real time, provides accurate power state information for the VDD power-on reset module 50, and avoids initialization failures caused by incorrect power state judgment. Based on the reference voltage and status signal provided by the first bandgap reference module 60, the VDD power-on reset module 50 can quickly output a reset signal when the system is powered on, initialize the working state of the level shift module 20, and ensure the rapid response and stable execution of the power supply switching process. The first bandgap reference module 60 can provide a stable output within a wide voltage range (1.8V to 3.6V), which solves the problem of unstable operation of traditional bandgap reference circuits under low voltage conditions, and ensures that the system can still operate normally under low input voltage conditions. Through the coordinated work of the first bandgap reference module 60 and the VDD power-on reset module 50, the entire backup power automatic switching circuit shows higher stability and accuracy during power-on initialization and power switching, avoiding initialization abnormalities or power supply switching delays.

[0037] It should be noted that the first bandgap reference module is powered by an external power supply voltage VDD, has a slightly loose power consumption index, can be implemented using a conventional operational amplifier structure, and belongs to the category of ordinary circuits. The specific internal circuit connection relationship is not described in detail here.

[0038] In an optional implementation of the present embodiment, the automatic switching circuit of the backup power supply also includes a second bandgap reference module 70, the input end of the second bandgap reference module 70 is electrically connected to the output end of the PMOS switch selection module 30, and the output end of the second bandgap reference module 70 is electrically connected to the PMOS turn-off voltage selection module 10 and the LDO module 40 respectively.

[0039] Specifically, the second bandgap reference module 70 is used to transmit the generated working current Ibn to the PMOS shutdown voltage selection module 10, and transmit the generated second reference voltage VREF2 and the second bias current Ibp2 to the LDO module, and the working current is used to control the PMOS shutdown voltage selection module 10 to compare the backup battery voltage VBAT and the external power supply voltage VDD to select the first target voltage VMAX. That is, in this embodiment, through the introduction of the second bandgap reference module 70, the system can efficiently switch the power supply between the external power supply and the backup battery, ensuring the stability and low power consumption characteristics of the power supply process. The corresponding working principle is as follows: the second bandgap reference module 70 provides a stable working current Ibn to the PMOS shutdown voltage selection module 10, effectively controlling its comparison process of the external power supply voltage VDD and the backup battery voltage VBAK, ensuring the accurate selection of the first target voltage VMAX under different power supply states, and avoiding power switching errors. The second reference voltage VREF2 and the second bias current Ibp2 generated by the second bandgap reference module 70 can effectively guarantee the stable operation of the LDO module 40 in a wide voltage range (1.8V~3.6V), ensure that the output second target voltage is highly accurate and stable, and meet the power supply requirements of the MCU chip. By reasonably designing the second bandgap reference module 70, the operating current, reference voltage and bias current provided are optimized to ensure that the system operates at low power consumption at the μA level, meet the strict requirements for power consumption when powered by a backup battery, and extend the battery life. The coordinated work of the second bandgap reference module, the PMOS shutdown voltage selection module and the LDO module can maintain the continuity and stability of the system power supply when the external power supply is powered off, restored and in a low voltage state, avoiding problems such as power jitter or switching delay. The second bandgap reference module supports wide voltage input (1.8V~3.6V), can generate stable operating current and bias voltage under low voltage conditions, and solves the limitation that the traditional bandgap reference circuit cannot work stably under low voltage.

[0040] The following will describe the device connection relationship in the specific internal circuit of the PMOS off voltage selection module, the level shift module, the PMOS switch gating module, and the second bandgap reference module 70 in turn through different implementation methods:

[0041] See also Figure 4 In the PMOS turn-off voltage selection module, a first PMOS tube P1, a second PMOS tube P2, a first inverter INV1, a second inverter INV2, a Schmidt inverter INV_SCHMT, a first current mirror, a second current mirror and a current switch device are included.

[0042] The source of the first PMOS tube is used to receive the external power supply voltage VDD, the drain of the first PMOS tube is electrically connected to the VMAX port, the gate of the first PMOS tube is electrically connected to the output end of the first inverter, the source of the second PMOS tube is used to receive the backup battery voltage VBAT, the drain of the second PMOS tube is electrically connected to the VMAX port, the gate of the second PMOS tube is electrically connected to the output end of the second inverter, the first input end of the first inverter is used to receive the backup battery voltage VBAT, the first input end of the second inverter is used to receive the external power supply voltage VDD, the input end of the Schmitt inverter is electrically connected to the voltage comparison node Vx, the output end of the Schmitt inverter is electrically connected to the second input end of the first inverter, the output end of the first current mirror I1 is used to mirror generate a third reference current I3 to be electrically connected to the voltage comparison node Vx, the source end of the current switch device P5 is used to receive the backup battery voltage VBAT, the gate end indirectly receives the external power supply voltage VDD, and the output end of the current switch device is used to output the second reference current I2 to the voltage comparison node Vx.

[0043] When the external power supply voltage VDD received by the voltage comparison node Vx is greater than the backup battery voltage VBAT, the Schmitt inverter outputs a high level signal to the first inverter, controls the first PMOS tube to be turned on, and outputs the external power supply voltage VDD as the first target voltage to the VMAX port;

[0044] When the external power supply voltage VDD received by the voltage comparison node is less than the backup battery voltage VBAT, the Schmitt inverter outputs a low-level signal, which outputs a high-level signal to the second input terminal of the second inverter after passing through the first inverter, controls the second PMOS tube to be turned on, and outputs the backup battery voltage VBAT as the first target voltage to the VMAX port.

[0045] The detailed working principle of the PMOS turn-off voltage selection module is described below:

[0046] Specifically, the inverter INV1 power supply is VBAT, and its output is used to control the first PMOS tube P1 that acts as a selection switch of VDD; the inverter INV2 power supply is VDD, and its output is used to control the second PMOS tube P2 that acts as a selection switch of VBAT; I3 is mirrored on I1, and the mirror current multiple is X3.

[0047] In the PMOS turn-off voltage selection module, the Vx voltage received by the voltage comparison node determines the flip of the Schmitt inverter INV_SCHMT, that is, determines whether the first target voltage VMAX is selected as VDD or VBAT, and V X The value depends on the comparison between the second reference current I2 and the third reference current I3.

[0048] When I2 > I3, the voltage of Vx rises, causing the output V of the Schmitt inverter INV_SCHMT to be X - = 0;

[0049] When I2 < I3, the voltage of Vx drops, causing the output V of the Schmitt inverter INV_SCHMT to be X - = 1;

[0050] In this way, when the fifth PMOS transistor P5 is in the linear region and the third NMOS transistor N3 is in the saturation region or cut-off region, V X is pulled high, and the output V of the Schmitt inverter INV_SCHMT is X - = 0, and the circuit selects the backup battery voltage VBAT to output to the VMAX port; when the fifth PMOS transistor P5 is in the cut-off region and N3 is in the saturation region, V X is pulled low, and the output V of the Schmitt inverter INV_SCHMT is X - = 1, and the circuit selects the external power supply voltage VDD to output to the VMAX port.

[0051] What needs to be discussed in detail is the comparison of I2 and I3 when both devices P5 and N3 are in the saturation region. At this time, there are the following relational expressions:

[0052]

[0053] In the formula, After the MCU chip is manufactured, |V TH | is no longer variable and can be regarded as a fixed value. In the circuit, the third reference current I3 is a current source.

[0054] It can be seen from the corresponding formulas (1-1) and (1-2) that when the backup battery voltage VBAT rises or the external power supply voltage VDD drops, the second reference current I2 rises, Vx has an upward trend, its output Vx- tends to change towards 0, then Y0 tends to 1, and Y1 tends to 0. Therefore, it tends to select VBAT, which is consistent with the actual phenomenon; conversely, Vx has a downward trend, and the circuit tends to select VDD.

[0055] In practice, VDD and VBAT can be roughly divided into four states, as shown in Table 1 below.

[0056] Table 1

[0057] state VDD VBAT 1 0 There is voltage 2 There is voltage 0 3 There is voltage There is voltage 4 0 0

[0058] In Table 1, "0" -- represents no voltage or there is voltage but it fails to reach the voltage value required for the normal operation of the device; "has voltage" -- indicates that the voltage value meets the voltage required for all devices in the circuit to operate normally. In addition, the following three states will be discussed separately.

[0059] The first state is: VDD = 0, VBAT has voltage. At this time, the inverter INV2 outputs Y1 = 0V due to the power supply VDD, the P7 tube is turned on, VMAX = VBAT; since VDD = 0V, POR = 0V, so the PMOS switch selects to output VCC = VBAT, Ibn has been generated, and since I3 = 0, V A =0, P5 is turned on, V X =VBAT, INV1 outputs Y0 =VBAT, and the first PMOS tube P1 is turned off.

[0060] The second state is: VBAT = 0, VDD has voltage. At this time, the first inverter INV1 outputs Y0 = 0V because the power supply is VBAT, the first PMOS tube P1 is turned on, VMAX = VDD; because Y0 = 0V, the second inverter INV2 outputs Y1 = VDD, and the second PMOS tube P2 is turned off.

[0061] The third state is when both VDD and VBAT have voltage. At this time, the selection of VMAX is determined by the comparison between I2 and I3.

[0062] The flip condition of the Schmitt inverter INV_SCHMT set in the circuit is: when VDD-VBAT>100mv, the output V X -=1, then VMAX=VDD; at the same time, Schmitt INV_SCHMT input voltage V X The hysteresis voltage value is set to 40mV through N4, that is, when VDD-VBAT<60mv, the output V X -=0, then VMAX=VBAT. It is worth mentioning that the design needs to have a certain hysteresis voltage to avoid the gate circuit switching back and forth due to power supply fluctuations when VDD-VBAT is near the flip threshold. Therefore, there is always a voltage that is slightly smaller and is still selected. However, it is necessary to ensure that when the difference between the two is greater than about 100mV, the largest one is always selected for output. When VBAT is slightly less than VDD, this circuit will output VBAT to VMAX as the turn-off voltage of the PMOS switch. Since |VBAT-VDD|=100mV<|V TH |(~700mV), and |VBAT-VDD| is higher than |V TH |Small enough to ensure that the switching device does not enter subthreshold conduction, so even if VBAT is slightly small, the PMOS switch can be turned off well.

[0063] See also Figure 5 The simulation results shown are used to verify the leakage evaluation of the backup battery voltage VBAT as the turn-off voltage (first target voltage) of the PMOS switch.

[0064] The simulation conditions are: VDD-VBAT=200mV, VDD: DC scan of 0.4V to 3.6V (PMOS switch W=20μm, L=0.4μm, m=25). It can be seen that the leakage current is 3.76nA, which is almost negligible.

[0065] It should also be noted that the second inverter INV2 in the circuit is a conversion of different voltage domains, from VBAT to VDD output. According to conventional requirements, a level shift circuit is used, but it is not necessary here. Because the output Y0 of the inverter INV1 has only two states, Y0 = 0V or Y0 = VBAT, and from the above discussion, when Y0 = VBAT, VBAT ≥ VDD-60mV must be satisfied. At this time, INV2 will output a certain state 1 and safely shut down the PMOS in the inverter without leakage.

[0066] Please refer to Figure 6 and Figure 7 , which are the VMAX output waveforms of different power-on sequences of VDD and VBAT. The input voltages VABT and VDD in the waveforms are put together for easy viewing. The black solid line is VDD and the blue dotted line is VBAT.

[0067] From the simulation, we can see that the PMOS shutdown voltage selection module is not affected by the power-on sequence of VDD or VBAT, and will not cause leakage. The first target voltage VMAX can always be output normally. (When the voltage difference between the two is greater than 100mV, the maximum voltage is always selected for output).

[0068] See also Figure 8 The level shift module includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a sixth NMOS tube N6, a seventh NMOS tube N7, a third inverter INV3 and a fourth inverter INV4.

[0069] The circuit connection relationship in the level shift module is as follows: the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube PMOS are all used to receive the first target voltage VMAX, the gate of the sixth PMOS tube P6 is electrically connected to the source of the seventh NMOS tube N7, the preset voltage switching node VA, the drain of the seventh PMOS tube P7, the drain of the ninth PMOS tube P9, and the input end of the fourth inverter INV4, the drain of the sixth PMOS tube P6 is electrically connected to the source of the sixth NMOS tube N6 and the gate of the seventh PMOS tube P7, and the sixth NMOS The gate of the transistor N6 is electrically connected to the output end of the third inverter INV3, the input end of the third inverter INV3 is electrically connected to the output end of the VDD power-on reset module and the gate of the seventh NMOS transistor N7 at the same time, the drain of the sixth NMOS tube N6 and the drain of the seventh NMOS tube N7 are both grounded, the gate of the eighth PMOS tube P8 and the gate of the ninth PMOS tube P9 are both used to receive the power-on reset signal POR, the drain of the eighth PMOS tube P8 is electrically connected to the source of the ninth PMOS tube P9, and the power supply end of the third inverter INV3 is used to receive the second target voltage VDD12 output by the LDO module.

[0070] The basic circuit principle of the level shift module is:

[0071] When the power-on reset signal is at a low level, the eighth PMOS tube and the ninth PMOS tube are in the on state and the seventh NMOS tube is in the off state, and the fourth inverter outputs a low-level switch state control signal; when the power-on reset signal is at a high level, the eighth PMOS tube and the ninth PMOS tube are in the off state, and the power-on reset signal is transmitted to the seventh NMOS tube to be turned on, so that the fourth inverter outputs a high-level switch state control signal SW.

[0072] It should be noted that the low voltage domain of the level shift circuit is VDD12, and the high voltage domain is VMAX; VDD12 comes from the output of LDO, and VMAX comes from the PMOS shutdown voltage selection module. The level shift circuit is one of the innovations of the present invention. The input signal of the level shift circuit is POR, which has two states, namely POR = 0V or POR = VDD. The circuit structure can ensure that the output meets the requirements when POR = 0V and VDD12 = 0V, and realize the conversion of the POR signal from the voltage domain VDD to VMAX. The output signal is SW, which is used to control the gate of the power switching switch PMOS.

[0073] It should be noted that this circuit uses VDD12, which comes from the LDO output, and the power supply of LDO comes from the switch selection circuit, and the control signal of the switch selection circuit comes from this module circuit. Therefore, it is necessary to carefully consider the state of this module before VDD12 is formed, which cannot affect the generation of LDO working voltage. The following is a detailed analysis based on its input signal POR=0V or POR=VDD.

[0074] In the first case: when VDD≤2.4V, output POR=0V; if LDO outputs VDD12=1.2V, VA=VMAX, SW=0V, the switch selects VBAT to VCC; if LDO outputs VDD12=0V, because POR=0V, N2 tube in the circuit is turned off, P8 and P9 tubes are turned on, VA=VMAX, SW=0V, and the switch still selects VBAT to VCC.

[0075] This is consistent with the design requirement: the circuit always switches VBAT to VCC when VDD≤2.4V.

[0076] Let's continue to discuss the VBAT situation: If VBAT has voltage and meets the minimum voltage in the indicator, the bandgap reference 2 and LDO can rely on the battery VBAT to start and work normally before VDD rises to 2.4V; if VBAT=0V, the second bandgap reference module and LDO module will not start at this time, and it is necessary to wait until VDD>2.4V, POR=VDD, the switch automatically selects VDD to VCC, and the second bandgap reference module and LDO module also output normally.

[0077] From this, we can see that as long as VDD>2.4V or VBAT meets the minimum operating voltage, bandgap reference 2 and LDO can always enter normal working state, of course, the premise is that VMAX needs to output normally. And from the previous PMOS shutdown voltage selection circuit, we know that VMAX can always output normally under any power-on sequence of VDD and VBAT.

[0078] In the second case: VDD>2.4V, output POR=VDD; at this time, no matter LDO outputs VDD12=0V or VDD12=1.2V, N6 tube is always turned off, N7 tube is turned on, VA=0V, SW=VMAX, so VDD is selected as the working voltage, and the second bandgap reference 2 and LDO work normally.

[0079] Also note that when VMAX=VBAT, and VBAT-VDD>VTH(~700mV), there will be a certain leakage in P8 and P9 in the figure. In the design, the L value of P8 and P9 can be appropriately increased to control the leakage current. Assume that the voltage range of VDD and VBAT of the product is defined as: 2.5V≤VDD≤3.6V, 1.8V≤VDD≤3.6V, and the simulation selects VBAT=3.6V, VDD=2.5V (at this time |VBAT-VDD|=1.1V>|V TH |) Evaluation simulation shows that the leakage current of the level shift module is only 60nA.

[0080] Through the above analysis, the level shift module can realize voltage domain conversion: the level shift circuit successfully converts the signal from the low voltage domain (VDD12) to the high voltage domain (VMAX), ensuring that the control signal SW can accurately drive the gate of the power switch PMOS. Ensure the normal startup of the circuit: before VDD12 is formed, the circuit design ensures that the power switch module defaults to the backup battery voltage VBAT, ensuring that the bandgap reference 2 and LDO can start and work normally. Adapt to different power supply conditions: when VBAT meets the minimum operating voltage, the bandgap reference 2 and LDO can start and work through VBAT. When VBAT = 0V and VDD reaches 2.4V, the circuit automatically switches to VDD power supply to ensure that the system enters normal working state. Low leakage current design: by reasonably designing the parameters of PMOS tubes (such as P8, P9), the leakage current of the level shift circuit under special conditions is controlled at 60nA, meeting the low power consumption requirements and extending the service life of the backup battery. Power supply stability and reliability: Regardless of the power-on sequence of VDD and VBAT, the level shift module cooperates with the PMOS shutdown voltage selection module to ensure that the output of the first target voltage VMAX is always normal, ensuring continuous power supply and stable operation of the system. Low power consumption and high efficiency: The circuit operates stably under low voltage and wide voltage domain conditions, and has extremely low quiescent current, meeting the low power design requirements.

[0081] See also Fig. 9 The PMOS switch gating module includes a fifth inverter INV5, a sixth inverter INV6, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12 and a thirteenth PMOS tube P13.

[0082] The circuit connection relationship of the PMOS switch gating module is as follows: the input end of the fifth inverter INV5 is used to receive the switch state control signal, the output end of the fifth inverter INV5 is electrically connected to the input end of the sixth inverter INV6, the gate of the twelfth PMOS tube P12, and the gate of the thirteenth PMOS tube P13 at the same time, the output end of the sixth inverter INV6 is electrically connected to the gate of the tenth PMOS tube P10 and the gate of the eleventh PMOS tube P11 at the same time, the source of the tenth PMOS tube P10 is used to receive the backup battery voltage VBAT, the source of the twelfth PMOS tube P12 is used to receive the external power supply voltage VDD, the substrate of the tenth PMOS tube P10 is electrically connected to the substrate of the eleventh PMOS tube P11, the drain of the tenth PMOS tube P10, and the source of the eleventh PMOS tube P11 at the same time, and the substrate of the twelfth PMOS tube P12 is electrically connected to the substrate of the thirteenth PMOS tube P13, the drain of the twelfth PMOS tube P12, and the source of the thirteenth PMOS tube P13 at the same time.

[0083] The basic circuit principle of the PMOS switch gating module is as follows: when the switch state control signal SW is at a high level, the fifth inverter INV5 outputs a low-level reverse control signal, the twelfth PMOS tube P12 and the thirteenth PMOS tube P13 are in a conducting state, the tenth PMOS tube P10 and the eleventh PMOS tube P11 are in a disconnected state, and the drain of the thirteenth PMOS tube P13 outputs the external power supply voltage VDD as the current power supply voltage VCC; when the switch state control signal is at a low level, the fifth inverter INV5 outputs a high-level reverse control signal, the twelfth PMOS tube P12 and the thirteenth PMOS tube P13 are in a disconnected state, the tenth PMOS tube P10 and the eleventh PMOS tube P11 are in a conducting state, and the drain of the eleventh PMOS tube P11 outputs the backup battery voltage VBAT as the current power supply voltage VCC.

[0084] In the PMOS switch gating module, in order to minimize the voltage loss on the switch, PMOS tubes (P10, P11, P12 and P13) are used as power gating switches. When one power supply is turned on, the other power supply must be turned off. In fact, the switch gating circuit also takes hot plugging into account to prevent overshoot of the LDO module output. In addition, since the PMOS substrate NWELL must be connected to the highest potential of the S or D terminal, otherwise when the S or D terminal potential is greater than the diode conduction voltage, a forward diode from S or D to the substrate NWELL is formed, which will seriously damage the device. P10 and P11 are connected in series, and the substrate SB1 of the two is connected to the S / D connection of P10 and P11; P12 and P13 are connected in series, and the substrate SB2 of the two is connected to the S / D connection of P12 and P13. That is, this design significantly reduces the switching voltage loss by using series PMOS tubes and reasonably accessing the substrate NWELL potential, preventing parasitic diode misconduction and device damage, while taking into account the reliability of hot plug protection and power switching, meeting the requirements of efficient, low loss and stable power management.

[0085] See also Fig.10 The second bandgap reference module includes a PMOS component, an NMOS component, a resistor component, a transistor component and a filter capacitor C1. The PMOS component and the NMOS component are electrically connected to form a current mirror structure to transmit a constant current to the transistor component. The resistor component is electrically connected between the emitter of the transistor component and the NMOS source or the PMOS drain, and the filter capacitor is connected between the relevant resistor component and the ground.

[0086] Specifically, the PMOS component includes a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16 and a seventeenth PMOS tube P17, the NMOS component includes a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12 and a thirteenth NMOS tube N13, the resistor component includes a first resistor R1, a second resistor R2 and a third resistor R3, and the triode component includes a first triode Q1, a second triode Q2 and a third triode Q3. Among them, the NMOS component is used to transmit the generated working current to the PMOS shutdown voltage selection module, and the filter capacitor and the resistor component are used to transmit the second reference voltage and the second bias current to the LDO module.

[0087] In the second bandgap reference module, the operating voltage is VCC, which is obtained by switching on VDD or VBAT. A low-voltage, low-power circuit structure (the circuit operating current is only about 0.7μA, and the minimum operating voltage is 1.6V lower) is adopted to meet the battery's wide voltage range (1.8V to 3.6V). Within the input voltage range of 1.8V to 3.6V, the output VREF2 changes only 14mV with VBAT, which serves as the reference voltage of the backup LDO, meeting the normal operation of the SRAM backup and RTC functions.

[0088] The detailed working principle of the second bandgap reference module is described below:

[0089] In the second bandgap reference module, P14 and P15 have the same size, N10 and N11 have the same size, and N8 and N9 have the same size. The second reference voltage VREF2 of bandgap reference 2 is derived as follows. From the circuit, it can be seen that I4=I5, and the current flowing through Q1 and Q2 is equal, so:

[0090] V q2 -V q1 =V T ln(n)

[0091] In the formula, n = m1 / m2. Since the current flowing through N10 and N11 is also equal, their source terminal voltages are equal, that is,

[0092] V q2 =V q3

[0093] thus,

[0094] V q3 -V q1 =V T ln(n)

[0095] From the circuit, we get:

[0096]

[0097] Therefore,

[0098]

[0099] Then from the circuit, we get:

[0100] VREF2=I6R2+V be3 =kI4R2+V be3

[0101] In the formula,

[0102] therefore,

[0103]

[0104] The above formula is the expression of the second reference voltage.

[0105] Where V T Expressed as a positive temperature coefficient, V be3 It represents the BE junction voltage of the third transistor Q3, and its value is a negative temperature coefficient. By selecting appropriate n, k, and R2 / R1, a VREF2 that basically does not change with temperature can be obtained.

[0106] Please refer to 11. When the input voltage VBAT changes between 1.8V and 3.6V, the output reference voltage VREF2 changes very little, only about 14mV. This result shows that the second bandgap reference module can provide a highly stable output reference voltage in a wide input voltage range (especially in the low voltage domain), meeting the requirements of low voltage domain applications. This feature enables it to be used as a high-precision reference voltage for LDO modules and other low-power circuits.

[0107] See also Fig.12 , the simulation waveforms with temperature changes (-55℃~125℃) under different process angles (SS process, TT process, FF process). The results show that the second bandgap reference module has good temperature stability, the amplitude of the output voltage change with temperature is very small (the typical temperature drift of the reference voltage is 2mV, and the fluctuation is very small), and it shows consistency and reliability under different process angles. The low temperature drift characteristic makes it suitable for environments with large temperature changes and meets the needs of high-precision applications.

[0108] An embodiment of the present application also provides an MCU chip, including a chip body and an automatic backup power switching circuit integrated in the chip body.

[0109] The embodiment of the present application also provides a backup power supply automatic switching device, which has a built-in backup power supply automatic switching circuit.

[0110] The beneficial effects of the present invention include the following:

[0111] 1) The present invention proposes a circuit architecture different from the prior art, which adopts a dual bandgap reference circuit structure to provide reference voltage and bias current to the VDD power-on reset circuit and the PMOS shutdown voltage selection circuit respectively; the working voltage of the bandgap reference 1 is VDD, and the working voltage of the bandgap reference 2 is VCC (which is an uninterrupted voltage), so that the power supply voltage can be selected without the voltage drop problem caused by passing through a diode.

[0112] 2) The PMOS turn-off voltage selection circuit of the present invention uses a simple circuit structure with very low current to select a suitable PMOS turn-off voltage from VDD and VBAT.

[0113] 3) The level shift module of the present invention can ensure that the output signal is certain before VDD12 reaches a normal value and meets the circuit logic requirements.

[0114] 4) The present invention makes the operating voltage of the bandgap reference circuit close to the input voltage, which can reduce the input voltage by about 0.6V compared with the prior art and still work normally;

[0115] 5) When VDD is selected as the power supply, when VNAT>VDD, the battery power consumption of the present invention is only about 50nA (because the PMOS shutdown voltage selection module requires a current of about 50nA, and this current is provided by VBAT to compare the size of VBAT and VDD in real time), while the currently disclosed related technologies require a battery as the working voltage of the bandgap reference circuit and the comparator circuit, and the battery power consumption is generally above μA level;

[0116] 6) When VBAT is selected as the power supply, under the same structure and conditions, the battery consumption current of the technology of the present invention is less than that of the prior art.

[0117] 7) The present invention supports the normal shutdown of the PMOS switch when there is a large voltage difference between the external battery VBAT and the power supply VDD;

[0118] 8) The circuit architecture of the present invention is universal, and only the design of each module needs to be adjusted for different processes, and the circuit structure does not need to be changed;

[0119] 9) The present invention is scalable and can be flexibly modified and expanded according to different design requirements. When the core requires a larger operating current, the aspect ratio of the PMOS switch can be appropriately increased to solve the problem.

[0120] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0121] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A backup power automatic switching circuit, characterized in that: Applied to MCU chip, the backup power automatic switching circuit includes a PMOS shutdown voltage selection module, a level shift module, a PMOS switch gating module and an LDO module; The output end of the PMOS shutdown voltage selection module is electrically connected to the input end of the level shift module, the output end of the level shift module is electrically connected to the control signal input end of the PMOS switch gating module, the output end of the PMOS switch gating module is electrically connected to the input end of the LDO module, the voltage input end of the PMOS switch gating module is used to receive an external power supply voltage and a backup battery voltage, and the input end of the PMOS shutdown voltage selection module is used to receive the external power supply voltage and the backup battery voltage; Among them, the PMOS shutdown voltage selection module is used to select one from the external power supply voltage and the backup battery voltage as a first target voltage to output to the level shift module, the level shift module is used to output a switch state control signal to the control signal input end of the PMOS switch gating module according to the first target voltage, and the PMOS switch gating module is used to select one from the external power supply voltage and the backup battery voltage as the current power supply voltage according to the switch state control signal, and output the current power supply voltage to the LDO module to control the LDO module to output a second target voltage to the MCU chip.

2. The automatic backup power switching circuit according to claim 1, characterized in that: The automatic backup power supply switching circuit further comprises a VDD power-on reset module, the input end of the VDD power-on reset module is used to receive an external power supply voltage, and the output end of the VDD power-on reset module is electrically connected to the input end of the level shift module; The VDD power-on reset module is used to output a power-on reset signal to the level shift module according to a first reference voltage, wherein the power-on reset signal is used to initialize the working state of the level shift module.

3. The automatic backup power switching circuit according to claim 2, characterized in that: The automatic backup power switching circuit further comprises a first bandgap reference module, the input end of the first bandgap reference module is used to receive an external power supply voltage, and the output end of the first bandgap reference module is electrically connected to the input end of the VDD power-on reset module; The first bandgap reference module is used to transmit the generated first reference voltage, first bias current and external power supply status signal to the VDD power-on reset module; wherein the external power supply status signal is used to indicate the current working state of the external power supply.

4. The automatic backup power switching circuit according to claim 3, characterized in that: The automatic backup power supply switching circuit further includes a second bandgap reference module, the input end of the second bandgap reference module is electrically connected to the output end of the PMOS switch gating module, and the output end of the second bandgap reference module is electrically connected to the PMOS turn-off voltage selection module and the LDO module respectively; The second bandgap reference module is used to transmit the generated operating current to the PMOS shutdown voltage selection module, and transmit the generated second reference voltage and second bias current to the LDO module; wherein the operating current is used to control the PMOS shutdown voltage selection module to compare the backup battery voltage and the external power supply voltage to select a first target voltage.

5. The automatic backup power switching circuit according to claim 4, characterized in that: The PMOS turn-off voltage selection module includes a first PMOS tube, a second PMOS tube, a first inverter, a second inverter, a Schmidt inverter, a first current mirror, a second current mirror and a current switch device; The source of the first PMOS tube is used to receive an external power supply voltage, the drain of the first PMOS tube is electrically connected to the VMAX port, the gate of the first PMOS tube is electrically connected to the output end of the first inverter, the source of the second PMOS tube is used to receive a backup battery voltage, the drain of the second PMOS tube is electrically connected to the VMAX port, the gate of the second PMOS tube is electrically connected to the output end of the second inverter, the first input end of the first inverter is used to receive the backup battery voltage, the first input end of the second inverter is used to receive the external power supply voltage, the input end of the Schmitt inverter is electrically connected to the voltage comparison node, the output end of the Schmitt inverter is electrically connected to the second input end of the first inverter, the output end of the first current mirror is used to mirror generate a third reference current to be electrically connected to the voltage comparison node, the source end of the current switch device is used to receive the backup battery voltage, the gate end indirectly receives the external power supply voltage, and the output end of the current switch device is used to output a second reference current to the voltage comparison node; When the external power supply voltage received by the voltage comparison node is greater than the backup battery voltage, the Schmitt inverter outputs a high level signal to the first inverter, controls the first PMOS tube to be turned on, and outputs the external power supply voltage as the first target voltage to the VMAX port; When the external power supply voltage received by the voltage comparison node is less than the backup battery voltage, the Schmitt inverter outputs a low level signal, and outputs a high level signal to the second input terminal of the second inverter after passing through the first inverter, controls the second PMOS tube to be turned on, and outputs the backup battery voltage as the first target voltage to the VMAX port.

6. The automatic backup power switching circuit according to claim 4, characterized in that: The level shift module includes a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third inverter and a fourth inverter; The source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are all used to receive the first target voltage, the gate of the sixth PMOS tube is electrically connected to the source of the seventh NMOS tube, the preset voltage switching node, the drain of the seventh PMOS tube, the drain of the ninth PMOS tube and the input end of the fourth inverter at the same time, the drain of the sixth PMOS tube is electrically connected to the source of the sixth NMOS tube and the gate of the seventh PMOS tube at the same time, the gate of the sixth NMOS tube is electrically connected to the output end of the third inverter, the input end of the third inverter is electrically connected to the output end of the VDD power-on reset module and the gate of the seventh NMOS tube at the same time, the drain of the sixth NMOS tube and the drain of the seventh NMOS tube are both grounded, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube are both used to receive the power-on reset signal POR, the drain of the eighth PMOS tube is electrically connected to the source of the ninth PMOS tube, and the power supply end of the third inverter is used to receive the second target voltage output by the LDO module; Among them, when the power-on reset signal is at a low level, the eighth PMOS tube and the ninth PMOS tube are in a conducting state and the seventh NMOS tube is in a shut-off state, and the fourth inverter outputs a low-level switch state control signal; when the power-on reset signal is at a high level, the eighth PMOS tube and the ninth PMOS tube are in a shut-off state, and the power-on reset signal is transmitted to the seventh NMOS tube to be turned on, so that the fourth inverter outputs a high-level switch state control signal.

7. The automatic backup power switching circuit according to claim 4, characterized in that: The PMOS switch gating module includes a fifth inverter, a sixth inverter, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube; The input end of the fifth inverter is used to receive a switch state control signal, the output end of the fifth inverter is electrically connected to the input end of the sixth inverter, the gate of the twelfth PMOS tube, and the gate of the thirteenth PMOS tube at the same time, the output end of the sixth inverter is electrically connected to the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube at the same time, the source of the tenth PMOS tube is used to receive a backup battery voltage, the source of the twelfth PMOS tube is used to receive an external power supply voltage, the substrate of the tenth PMOS tube is electrically connected to the substrate of the eleventh PMOS tube, the drain of the tenth PMOS tube P10, and the source of the eleventh PMOS tube P11 at the same time, and the substrate of the twelfth PMOS tube is electrically connected to the substrate of the thirteenth PMOS tube, the drain of the twelfth PMOS tube P12, and the source of the thirteenth PMOS tube P13 at the same time; When the switch state control signal is at a high level, the fifth inverter INV5 outputs a low-level reverse control signal, the twelfth PMOS tube and the thirteenth PMOS tube are in a conducting state, the tenth PMOS tube and the eleventh PMOS tube are in a disconnected state, and the drain of the thirteenth PMOS tube outputs the external power supply voltage as the current power supply voltage; When the switch state control signal is at a low level, the fifth inverter INV5 outputs a high level reverse control signal, the twelfth PMOS tube and the thirteenth PMOS tube are in a disconnected state, the tenth PMOS tube and the eleventh PMOS tube are in a turned-on state, and the drain of the eleventh PMOS tube outputs the backup battery voltage as the current power supply voltage.

8. The automatic backup power switching circuit according to claim 4, characterized in that: The second bandgap reference module includes a PMOS component, an NMOS component, a resistor component, a triode component and a filter capacitor; The PMOS component is electrically connected to the NMOS component to form a current mirror structure, transmitting a constant current to the triode component, the resistor component is electrically connected between the emitter of the triode component and the NMOS source or the PMOS drain, and the filter capacitor is connected between the resistor component and the ground; The NMOS component is used to transmit the generated operating current to the PMOS shutdown voltage selection module, and the filter capacitor and the resistor component are used to transmit the second reference voltage and the second bias current to the LDO module.

9. An MCU chip, characterized in that: It comprises a chip body and the automatic backup power switching circuit as claimed in any one of claims 1 to 8, wherein the automatic backup power switching circuit is integrated in the chip body.

10. A backup power supply automatic switching device, characterized in that: The automatic backup power switching device has a built-in automatic backup power switching circuit as described in any one of claims 1 to 8.

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