An automatic backup power switching circuit, MCU chip and device

Abstract

The application discloses a kind of standby power automatic switching circuit, MCU chip and device, by including PMOS off voltage selection module, level displacement module, PMOS switch gating module and LDO module, when external power supply power failure, it is automatically switched to standby battery power supply, and when external power supply recovers, it is switched back to external power supply power supply, i.e. realize the dynamic switching of standby battery, external power supply.In addition, on the basis of the above flexible switching power supply mode, by PMOS switch gating module, the voltage drop characteristics of input voltage are optimized, to ensure that the circuit can still work normally in the wide voltage range of 1.8V-3.6V.And based on PMOS off voltage selection module, select one voltage from external power supply voltage and standby battery voltage, which can turn off PMOS (switch) as its gate voltage, to avoid the leakage phenomenon when PMOS is turned off, to ensure circuit stability.And avoid the extra static current generated when the battery is not gated, to ensure that the total current consumption of battery at room temperature is less than 5 μA, greatly reduce power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a backup power automatic switching circuit, MCU chip and device. BACKGROUND

[0002] In the design of microcontroller unit (MCU) chips, the development and optimization of power management modules are widely involved. In some MCU and related chip products, a dual power supply design scheme of external power supply and backup battery is often adopted. This design is mainly used to automatically switch to backup battery power supply in the case of external power supply failure, so as to protect the saving of static random access memory (SRAM) data and the normal operation of real-time clock (RTC) function. When the external power supply is restored, the system will automatically switch back to external power supply.

[0003] Most of the power management structures of external power supply and backup battery automatic switching usually use two diodes to pre-select the maximum external voltage as the working voltage of modules such as bandgap reference circuit, hysteresis comparator and level shift circuit to realize power switching. However, this structure has many deficiencies in actual application, especially in the application scenarios of wide voltage domain (1.8V-3.6V) and low power consumption (battery power consumption less than 5μA at room temperature), the normal operation of the system is limited and cannot meet the requirements of wide voltage domain. At the same time, when the system selects external power supply as the power source, if the backup battery voltage is greater than the external power supply voltage, the path that should be turned off is easy to have a leakage problem, which affects the stability of the circuit. And when the backup battery power supply is selected, there is a non-negligible static current consumption in the level shift circuit. For products with strict current consumption limit (μA level), this problem becomes the main obstacle to realize low power consumption design.

[0004] In summary, the power management structure in the related art has the technical problems of being unable to meet the use scenarios of wide voltage domain, high power consumption, and insufficient circuit stability. SUMMARY

[0005] The main purpose of the present application is to provide a backup power automatic switching circuit, MCU chip and device, which aims to at least solve the technical problems of the power management structure in the related art, such as being unable to meet the use scenarios of wide voltage domain, high power consumption, and insufficient circuit stability.

[0006] In a first aspect, the present application provides a backup power automatic switching circuit applied to an MCU chip, which comprises a PMOS turn-off voltage selection module, a level shift module, a PMOS switch gating module and an LDO module.

[0007] The output end of the PMOS off voltage selection module is electrically connected with the input end of the level shift module, the output end of the level shift module is electrically connected with the control signal input end of the PMOS switch gating module, the output end of the PMOS switch gating module is electrically connected with the input end of the LDO module, the voltage input end of the PMOS switch gating module is used for receiving an external power supply voltage or a backup battery voltage, and the input end of the PMOS off voltage selection module is used for receiving the external power supply voltage and the backup battery voltage.

[0008] The PMOS off voltage selection module is used for selecting one of the external power supply voltage and the backup battery voltage as a first target voltage and outputting the first target voltage to the level shift module, the level shift module is used for outputting a switch state control signal to the control signal input end of the PMOS switch gating module according to the first target voltage, the PMOS switch gating module is used for selecting one of the external power supply voltage and the backup battery voltage as a current power supply voltage according to the switch state control signal, and outputting the current power supply voltage to the LDO module, so as to control the LDO module to output a second target voltage to the MCU chip.

[0009] In a second aspect of the present application, an MCU chip is provided, which comprises a chip body and a backup power supply automatic switching circuit as in the first aspect integrated in the chip body.

[0010] In a third aspect of the present application, a backup power supply automatic switching device is provided, which is internally provided with a backup power supply automatic switching circuit as in the first aspect.

[0011] The backup power supply automatic switching circuit, the MCU chip and the device of the present application can automatically switch to backup battery power supply when the external power supply is powered off, and switch back to external power supply when the external power supply is restored, that is, realize dynamic switching of the backup battery and the external power supply. In addition, on the basis of the flexible switching power supply mode, the PMOS switch gating module is used to optimize the voltage drop characteristics of the input voltage, so as to ensure that the circuit can still work normally in a wide voltage range of 1.8V-3.6V. Based on the PMOS off voltage selection module, one of the external power supply voltage and the backup battery voltage is selected as the gate voltage of the PMOS (switch) to avoid the leakage phenomenon when the PMOS is off, so as to ensure the stability of the circuit. In addition, the extra static current generated when the battery is not gated is avoided, so as to ensure that the total current consumption of the battery at room temperature is less than 5μA, and the power consumption is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0013] Figure 1 A structure block diagram of an external power supply and a battery switching provided in the related art;

[0014] Figure 2 A circuit connection schematic diagram of a level shift circuit provided in the related art;

[0015] Figure 3 A module connection schematic diagram of an automatic switching circuit of a backup power supply provided in the embodiments of the present application;

[0016] Figure 4 A circuit connection schematic diagram of a PMOS off voltage selection module in the embodiments of the present application;

[0017] Figure 5 An evaluation DC scan simulation waveform diagram of the PMOS off voltage selection module in the embodiments of the present application;

[0018] Figure 6 A first target voltage VMAX output transient simulation waveform diagram output by the PMOS off voltage selection module in the embodiments of the present application when VBAT is powered first;

[0019] Figure 7 A first target voltage VMAX output transient simulation waveform diagram output by the PMOS off voltage selection module in the embodiments of the present application when VDD is powered first;

[0020] Figure 8 A circuit connection schematic diagram of a level shift module in the embodiments of the present application;

[0021] Figure 9 A circuit connection schematic diagram of a PMOS switch gating module in the embodiments of the present application;

[0022] Figure 10 A circuit connection schematic diagram of a second bandgap reference module in the embodiments of the present application;

[0023] Figure 11 A second reference voltage VREF2 output by the second bandgap reference module in the embodiments of the present application about a VCC direct current scan simulation waveform diagram;

[0024] Figure 12The second reference voltage VREF2 output by the second bandgap reference module in the embodiment of the present application is scanned with respect to temperature.

[0025] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0026] It should be understood that the specific embodiments described herein merely exemplify the present application and do not limit the present application.

[0027] It should be noted that related terms such as "first", "second" and the like can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present application, the first component can be referred to as the second component, and the second component can also be referred to as the first component. The term "and / or" means the combination of any one or more of the related terms and the described terms.

[0028] Please refer to Figure 1 and Figure 2 , the power management structure of the related art has four shortcomings: 1. The operating voltage of the bandgap reference circuit and the hysteresis comparator is V H , which is about 0.6V lower than the input voltage V DD or V BAK . In the case of low input voltage (such as 1.8V), this structure has limitations; 2. The application condition of the level shift circuit has limitations. When V DD is selected as the power supply (at this time, V S = V DD ), if V BAK -V DD >|V TH |, the PMOS switch connected to V BAK and V S will be turned on (which should be turned off); 3. When the gating VDD is powered, if V BAK >V DD , since V H is selected as V BAK , the bandgap reference circuit and the hysteresis comparator are still powered by the battery, which shortens the battery life; 4. When the gating V BAK is powered, there is a current V BAK / R2 in the level shift circuit. In products that require low battery consumption (μA level) in the index, the current on the level shift circuit R2 cannot be ignored. That is, the power management structure in the related art has technical problems such as inability to meet the use scenarios of wide voltage domain, high power consumption, and insufficient circuit stability.

[0029] In order to solve the above technical problems, please refer toFigure 3 The embodiment of the application provides a backup power automatic switching circuit, which is applied to an MCU chip, and the backup power automatic switching circuit comprises a PMOS off voltage selection module 10, a level shift module 20, a PMOS switch gating module 30 and an LDO module 40.

[0030] Specifically, the output end of the PMOS off voltage selection module 10 is electrically connected with the input end of the level shift module 20, the output end of the level shift module 20 is electrically connected with the control signal input end of the PMOS switch gating module 30, the output end of the PMOS switch gating module 30 is electrically connected with the input end of the LDO module 40, the voltage input end of the PMOS switch gating module 30 is used for receiving an external power supply voltage VDD or a backup battery voltage VBAT, and the input end of the PMOS off voltage selection module 10 is used for receiving the external power supply voltage VDD and the backup battery voltage VBAT.

[0031] In the backup power automatic switching circuit, the PMOS off voltage selection module 10 is used for selecting one of the external power supply voltage VDD and the backup battery voltage VBAT and outputting the selected one as a first target voltage VMAX to the level shift module 20, the level shift module 20 is used for outputting a switch state control signal SW to the control signal input end of the PMOS switch gating module 30 according to the first target voltage VMAX, and the PMOS switch gating module 30 is used for selecting one of the external power supply voltage VDD and the backup battery voltage VBAT as a current power supply voltage VCC according to the switch state control signal SW and outputting the current power supply voltage VCC to the LDO module 40 to control the LDO module 40 to output a second target voltage VDD12 to the MCU chip.

[0032] The backup power automatic switching circuit, the MCU chip and the device provided by the application can automatically switch to backup battery power supply when the external power supply is powered off, and can switch back to the external power supply when the external power supply is restored, that is, the dynamic switching of the backup battery and the external power supply is realized, and the stable power supply of the MCU system is ensured. In addition, on the basis of the flexible switching power supply mode, the PMOS switch gating module is used to optimize the voltage drop characteristics of the input voltage, so that the circuit can still work normally in a wide voltage range of 1.8V-3.6V. The PMOS off voltage selection module is used to select a voltage that can turn off the PMOS (switch) as the gate voltage of the PMOS, so as to avoid the leakage phenomenon of the PMOS when the PMOS is turned off, to ensure the stability of the circuit, and to avoid the extra static current generated when the battery is not gated, to ensure that the total battery current consumption is less than 5uA at room temperature, and to greatly reduce the power consumption.

[0033] In an optional implementation of the embodiment, the automatic backup power switching circuit further comprises a VDD power-on reset module 50, an input terminal of the VDD power-on reset module 50 being configured to receive the external power supply voltage VDD, and an output terminal of the VDD power-on reset module 50 being electrically connected to an input terminal of the level shift module 20.

[0034] Specifically, the VDD power-on reset module 50 is configured to output a power-on reset signal POR to the level shift module 20 according to the first reference voltage VREF1, the power-on reset signal POR being configured to initialize the working state of the level shift module 20, and to ensure that the level shift module 20 enters a stable working state when the system is powered on, thereby providing a correct switch state control signal SW for the PMOS switch gating module 30. By introducing the VDD power-on reset module 50, the level shift module 20 can be quickly reset based on the power-on reset signal POR when the system is powered on or the external power supply voltage VDD is restored, thereby avoiding misoperation or power supply switching delay caused by abnormal initialization of the level shift module.

[0035] In an optional implementation of the embodiment, the automatic backup power switching circuit further comprises a first bandgap reference module 60, an input terminal of the first bandgap reference module 60 being configured to receive the external power supply voltage VDD, and an output terminal of the first bandgap reference module 60 being electrically connected to an input terminal of the VDD power-on reset module 50. The first bandgap reference module 60 is configured to transmit the generated first reference voltage VREF1, a first bias current Ibp1, and an external power supply state signal BG_OK to the VDD power-on reset module 50. The external power supply state signal indicates the current working state of the external power supply,

[0036] Specifically, by introducing the first bandgap reference module 60, based on the first reference voltage VREF1, the first bias current Ibp1 and the power state signal BG_OK provided by it, cooperating with the VDD power-on reset module 50, the working state of the level shift module 20 is effectively initialized, which further improves the working stability of the backup power automatic switching circuit and the reliability of power supply switching, and meets the application requirements of MCU chip under the conditions of wide voltage domain (1.8V-3.6V) and low power consumption. The specific principle is as follows: the first reference voltage and the first bias current generated by the first bandgap reference module 60 ensure that the VDD power-on reset module 50 can work stably under different power supply voltage conditions, and improve the working reliability and adaptability of the entire circuit. The first bandgap reference module 60 generates an external power state signal BG_OK, which indicates the current working state of the external power VDD in real time, and provides accurate power state information for the VDD power-on reset module 50, avoiding initialization failure caused by power state judgment error. The VDD power-on reset module 50 can quickly output a reset signal based on the reference voltage and state signal provided by the first bandgap reference module 60 when the system is powered on, initialize the working state of the level shift module 20, and ensure the fast response and stable execution of the power supply switching process. The first bandgap reference module 60 can provide stable output within a wide voltage domain (1.8V-3.6V), solving the problem of unstable operation of traditional bandgap reference circuits under low voltage conditions, and ensuring that the system can still operate normally under low input voltage conditions. Through the cooperative work of the first bandgap reference module 60 and the VDD power-on reset module 50, the entire backup power automatic switching circuit shows higher stability and accuracy during power-on initialization and power supply switching, avoiding initialization abnormalities or power supply switching delays.

[0037] It should be noted that the first bandgap reference module is powered by the external power supply voltage VDD, and the power consumption index is slightly loose, which can be realized by adopting a conventional operational amplifier structure, and belongs to the category of ordinary circuits. The internal specific circuit connection relationship is not described in detail here.

[0038] In an optional embodiment of the present embodiment, the backup power automatic switching circuit further comprises a second bandgap reference module 70, the input end of the second bandgap reference module 70 is electrically connected with the output end of the PMOS switch gating module 30, and the output end of the second bandgap reference module 70 is electrically connected with the PMOS off voltage selection module 10 and the LDO module 40 respectively.

[0039] Specifically, the second bandgap reference module 70 is configured to transmit the generated operating current Ibn to the PMOS turn-off voltage selection module 10, and transmit the generated second reference voltage VREF2 and the second bias current Ibp2 to the LDO module, where the operating current is used to control the PMOS turn-off voltage selection module 10 to compare the backup battery voltage VBAT and the external power supply voltage VDD to select the first target voltage VMAX. That is, in the present embodiment, by introducing the second bandgap reference module 70, the system can efficiently switch the power supply between the external power supply and the backup battery, ensuring the stability and low power consumption characteristics of the power supply process. The corresponding working principle is as follows: the second bandgap reference module 70 provides a stable operating current Ibn to the PMOS turn-off voltage selection module 10, effectively controls the comparison process of the external power supply voltage VDD and the backup battery voltage VBAK, ensures the accurate selection of the first target voltage VMAX under different power supply states, and avoids power supply switching errors. The second reference voltage VREF2 and the second bias current Ibp2 generated by the second bandgap reference module 70 can effectively ensure the stable operation of the LDO module 40 in a wide voltage domain (1.8V-3.6V), ensure the high accuracy and stability of the output second target voltage, and meet the power supply requirements of the MCU chip. By reasonably designing the second bandgap reference module 70, the operating current, reference voltage and bias current provided are all optimized to ensure that the system operates at a low power consumption of μA level, meets the strict requirements for power consumption when the backup battery is powered, and prolongs the service life of the battery. The cooperative work of the second bandgap reference module, the PMOS turn-off voltage selection module and the LDO module can maintain the continuity and stability of the system power supply under the conditions of external power supply power failure, recovery and low voltage state, and avoid problems such as power supply jitter or switching delay. The second bandgap reference module supports wide voltage input (1.8V-3.6V), can generate stable operating current and bias voltage under low voltage conditions, and solves the limitation that the traditional bandgap reference circuit cannot work stably under low voltage.

[0040] The device connection relationship in the specific internal circuit of the PMOS turn-off voltage selection module, the level shift module, the PMOS switch gating module and the second bandgap reference module 70 will be described in detail in different embodiments as follows:

[0041] Please refer to Figure 4 In the PMOS turn-off voltage selection module, the first PMOS tube P1, the second PMOS tube P2, the first inverter INV1, the second inverter INV2, the Schmidt inverter INV_SCHMT, the first current mirror, the second current mirror and the current switching device are included.

[0042] The source of the first PMOS transistor is used to receive the external power supply voltage VDD, the drain of the first PMOS transistor is electrically connected to the VMAX port, and the gate of the first PMOS transistor is electrically connected to the output of the first inverter. The source of the second PMOS transistor is used to receive the backup battery voltage VBAT, the drain of the second PMOS transistor is electrically connected to the VMAX port, and the gate of the second PMOS transistor is electrically connected to the output of the second inverter. The first input of the first inverter is used to receive the backup battery voltage VBAT, the first input of the second inverter is used to receive the external power supply voltage VDD, the input of the Schmitt trigger is electrically connected to the voltage comparator node Vx, the output of the Schmitt trigger is electrically connected to the second input of the first inverter, the output of the first current mirror I1 is used to mirror and generate a third reference current I3 to the voltage comparator node Vx, and the source of the current switching device P5 is used to receive the backup battery voltage VBAT, the gate of which indirectly receives the external power supply voltage VDD, and the output of the current switching device is used to output a second reference current I2 to the voltage comparator node Vx.

[0043] When the external power supply voltage VDD received by the voltage comparison node Vx is greater than the backup battery voltage VBAT, the Schmitt inverter outputs a high-level signal to the first inverter, controls the first PMOS transistor to turn on, and outputs the external power supply voltage VDD as the first target voltage to the VMAX port.

[0044] When the external power supply voltage VDD received by the voltage comparator node is less than the backup battery voltage VBAT, the Schmitt inverter outputs a low-level signal, which is then output as a high-level signal after passing through the first inverter to the second input terminal of the second inverter, controlling the second PMOS transistor to turn on and output the backup battery voltage VBAT as the first target voltage to the VMAX port.

[0045] The working principle of the PMOS turn-off voltage selection module is explained in detail below:

[0046] Specifically, inverter INV1 is powered by VBAT, and its output is used to control the first PMOS transistor P1, which acts as a selection switch for VDD; inverter INV2 is powered by VDD, and its output is used to control the second PMOS transistor P2, which acts as a selection switch for VBAT; I3 is mirrored by I1, and the mirror current multiple is X3.

[0047] In the PMOS turn-off voltage selection module, the Vx voltage received by the voltage comparator node determines the toggling of the Schmitt inverter INV_SCHMT, which in turn determines whether the first target voltage VMAX is VDD or VBAT. X The value depends on the comparison between the second reference current I2 and the third reference current I3.

[0048] When I2>I3, Vx voltage rises, so that the output V X - = 0;

[0049] When I2<I3, Vx voltage drops, so that the output V X - = 1;

[0050] So, when the fifth PMOS tube P5 is in the linear region, the third NMOS tube N3 is in the saturation region or the cutoff region, V X is pulled high, the Schmitt inverter INV_SCHMT outputs V X - = 0, the circuit selects the backup battery voltage VBAT output to the VMAX port; when the fifth PMOS tube P5 is in the cutoff region, N3 is in the saturation region, V X is pulled low, the Schmitt inverter INV_SCHMT outputs V X - = 1, the circuit selects the external power supply voltage VDD output to the VMAX port.

[0051] Need to be discussed is the comparison of I2, I3 when the device P5, N3 are in the saturation region, at this time there are the following relationships:

[0052]

[0053] In the formula, After the MCU chip is manufactured, |V TH |All have become invariable and can be regarded as constant values. In the circuit, the third reference current I3 is a current source.

[0054] From the corresponding formula (1-1) (1-2), it can be seen that when the backup battery voltage VBAT rises or the external power supply voltage VDD drops, the second reference current I2 rises, Vx has a rising trend, its output Vx- tends to change to 0, Y0 tends to 1, Y1 tends to 0, so it tends to select VBAT, which is consistent with the actual phenomenon; on the contrary, Vx has a downward trend, and the circuit tends to select VDD.

[0055] In practice, VDD, VBAT can be roughly divided into four states, as shown in the following table 1.

[0056] Table 1

[0057] State VDD VBAT 1 0 Voltage present 2 Voltage present 0 3 Voltage present Voltage present 4 0 0

[0058] In table 1, "0" represents no voltage or voltage that fails to reach the voltage value required for normal operation of the device; "voltage" means that the voltage value meets the voltage required for normal operation of all devices in the circuit. In addition, the following three states are discussed respectively.

[0059] The first state is: VDD=0, VBAT has voltage. At this time, the inverter INV2 has VDD as power supply, Y1=0V, P7 is on, VMAX=VBAT; since VDD=0V, POR=0V, thus PMOS switch selects output VCC=VBAT, Ib has been generated, and since I3=0, V A =0, P5 is on, V X =VBAT, INV1 outputs Y0=VBAT, the first PMOS P1 is off.

[0060] The second state is: VBAT=0, VDD has voltage. At this time, the first inverter INV1 has VBAT as power supply, Y0=0V, the first PMOS P1 is on, VMAX=VDD; since Y0=0V, the second inverter INV2 outputs Y1=VDD, the second PMOS P2 is off.

[0061] The third state is: when VDD or VBAT has voltage. At this time, the selection of VMAX is determined by the comparison of I2 and I3.

[0062] Among them, the Schmitt inverter INV_SCHMT set in the circuit flips the condition: when VDD-VBAT>100mv, output V X -=-1, then VMAX=VDD; at the same time, the hysteresis voltage value of the input voltage V X of the Schmitt INV_SCHMT is set to 40mV by N4, that is, when VDD-VBAT<60mv, output V X -=-0, then VMAX=VBAT. It is worth mentioning that the design needs to have a certain hysteresis voltage to avoid the selection circuit from switching back and forth due to power fluctuations when VDD-VBAT is near the flip threshold. Therefore, there is always a voltage that is slightly smaller and is still selected. However, it needs to be ensured that when the difference between the two is greater than 100mV or so, the maximum is always selected as the output. In the case of VBAT slightly smaller than VDD, the circuit will output VBAT to VMAX as the off voltage of the PMOS switch. Since |VBAT-VDD|=100mV<|V TH |(~700mV), and |VBAT-VDD| is much smaller than |V TH |, it can be ensured that the switch device does not enter sub-threshold conduction, so even if VBAT is slightly smaller, it can still turn off the PMOS switch well.

[0063] Please refer to Figure 5 , which shows the simulation results to verify the leakage evaluation of the standby battery voltage VBAT as the off voltage of the PMOS switch (the first target voltage).

[0064] Where the simulation conditions are: VDD-VBAT=200mV, DC scan of VDD: 0.4V-3.6V (PMOS switch W=20μm, L=0.4μm, m=25). The drain current is 3.76nA, which can be ignored.

[0065] It should also be noted that the second inverter INV2 in the circuit is a conversion of different voltage domains, converted from VBAT to VDD output, which conventionally requires a level shift circuit, but here it can not be needed. Because the output Y0 of the inverter INV1 only has two states, Y0=0V or Y0=VBAT, and as discussed above, when Y0=VBAT, it must satisfy VBAT≥VDD-60mV, at this time INV2 will output a certain state 1, and safely turn off the PMOS in the inverter, without leakage.

[0066] Please refer to Figure 6 and Figure 7 , which are VMAX output waveforms of different power-on sequences of VDD and VBAT, respectively. The input voltages VABT and VDD in the waveforms are put together for easy viewing. The black solid line is VDD, and the blue dashed line is VBAT.

[0067] As seen from the simulation, the PMOS turn-off voltage selection module is not affected by the power-on sequence of VDD or VBAT, and no leakage occurs. The first target voltage VMAX is always normally outputted. (When the voltage difference between the two is greater than 100mV, the maximum one is always selected to be outputted).

[0068] Please refer to Figure 8 , the level shift module includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a sixth NMOS tube N6, a seventh NMOS tube N7, a third inverter INV3 and a fourth inverter INV4.

[0069] The circuit connection relationship in the level shift module is that the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube PMOS are all used for receiving a first target voltage VMAX, the gate of the sixth PMOS tube P6 is electrically connected with the source of the seventh NMOS tube N7, a preset voltage switching node VA, the drain of the seventh PMOS tube P7, the drain of the ninth PMOS tube P9 and the input end of the fourth inverter INV4, the drain of the sixth PMOS tube P6 is electrically connected with the source of the sixth NMOS tube N6 and the gate of the seventh PMOS tube P7, the gate of the sixth NMOS tube N6 is electrically connected with the output end of the third inverter INV3, the input end of the third inverter INV3 is electrically connected with the output end of the power-on reset module of VDD and the gate of the seventh NMOS tube N7, the drain of the sixth NMOS tube N6 and the drain of the seventh NMOS tube N7 are all grounded, the gate of the eighth PMOS tube P8 and the gate of the ninth PMOS tube P9 are all used for receiving a power-on reset signal POR, the drain of the eighth PMOS tube P8 is electrically connected with the source of the ninth PMOS tube P9, and the power supply end of the third inverter INV3 is used for receiving a second target voltage VDD12 output by the LDO module.

[0070] The basic circuit principle of the level shift module is that:

[0071] When the power-on reset signal is at a low level, the eighth PMOS tube, the ninth PMOS tube and the seventh NMOS tube are in a conductive state and a turn-off state, and the fourth inverter outputs a low-level switching state control signal; when the power-on reset signal is at a high level, the eighth PMOS tube and the ninth PMOS tube are in a turn-off state, and the power-on reset signal is transmitted to be opened by the seventh NMOS tube, so that the fourth inverter outputs a high-level switching state control signal SW.

[0072] It should be noted that the low-voltage domain of the level shift circuit is VDD12, and the high-voltage domain is VMAX; VDD12 comes from the output of the LDO, and VMAX comes from the PMOS turn-off voltage selection module, and the level shift circuit is one of the innovations of the present application. The input signal of the level shift circuit is POR, which has two states, i.e. POR=0V or POR=VDD, and the circuit structure can ensure that the output meets the demand of the determined state value under the condition of POR=0V and VDD12=0V, and realizes the conversion of the POR signal from the voltage domain VDD to VMAX, and the output signal is SW, which is used to control the gate of the power switching switch PMOS.

[0073] It should be noted that this circuit uses VDD12 from the LDO output, and the power supply of the LDO comes from the switch selection circuit, and the control signal of the switch selection circuit comes from the module circuit, so it needs to be carefully considered that the state of the module before VDD12 is formed cannot affect the generation of the LDO operating voltage. The following is a detailed analysis according to its input signal POR=0V or POR=VDD.

[0074] In the first case: when VDD≤2.4V, the output POR=0V; if the LDO output VDD12=1.2V, VA=VMAX, SW=0V, the switch selects VBAT to VCC; if the LDO output VDD12=0V, because POR=0V, N2 tube in the circuit is off, P8, P9 tube is on, VA=VMAX, SW=0V, the switch still selects VBAT to VCC.

[0075] This is consistent with the design requirements: when VDD≤2.4V, the circuit always selects VBAT to VCC.

[0076] The following continues to discuss the case of VBAT: if VBAT has voltage and meets the minimum voltage on the index, before VDD rises to 2.4V, both the bandgap reference 2 and the LDO can rely on the battery VBAT to start and work normally; if VBAT=0V, at this time the second bandgap reference module and the LDO module will not start, and need to wait until VDD>2.4V, POR=VDD, the switch automatically selects VDD to VCC, and the second bandgap reference module and the LDO module also normally output.

[0077] From this, it can be seen that as long as VDD>2.4V or VBAT meets the minimum working voltage, the bandgap reference 2 and the LDO can always enter the normal working state, of course, the prerequisite is that VMAX needs to be normally output. From the previous PMOS off voltage selection circuit, it is known that VMAX can always be normally output under any power-on sequence of VDD, VBAT.

[0078] The second case: VDD>2.4V, the output POR=VDD; at this time, no matter the LDO output VDD12=0V or VDD12=1.2V, N6 tube is always off, N7 tube is on, VA=0V, SW=VMAX, so VDD is selected as the working voltage, and the second bandgap reference 2 and the LDO work normally.

[0079] It is also noted that when VMAX=VBAT and VBAT-VDD>VTH(~700mV), there will be some leakage current in P8 and P9. In the design, the L value of P8 and P9 can be appropriately increased to control the leakage current. Assuming that the voltage range of VDD and VBAT is defined as: 2.5V≤VDD≤3.6V, 1.8V≤VDD≤3.6V, the simulation selects VBAT=3.6V and VDD=2.5V (at this time |VBAT-VDD|=1.1V>|V TH

[0080] Through the above analysis, the level shift module can realize voltage domain conversion: the level shift circuit successfully converts the signal from the low voltage domain (VDD12) to the high voltage domain (VMAX), ensuring that the control signal SW can accurately drive the gate of the power switching switch PMOS. Ensure normal start of the circuit: before VDD12 is formed, the circuit design ensures that the power switching module selects the standby battery voltage VBAT by default, ensuring that the bandgap reference 2 and the LDO can start and work normally. Adapt to different power supply situations: when VBAT meets the minimum working voltage, the bandgap reference 2 and the LDO can start and work through VBAT. When VBAT=0V and VDD reaches 2.4V, the circuit automatically switches to VDD power supply, ensuring that the system enters a normal working state. Low leakage current design: by reasonably designing the parameters of the PMOS tube (such as P8, P9), the leakage current of the level shift circuit under special conditions is controlled at 60nA, meeting the low power consumption requirement and prolonging the service life of the standby battery. Power supply stability and reliability: no matter the power-up sequence of VDD and VBAT, the level shift module cooperates with the PMOS off voltage selection module to ensure that the output first target voltage VMAX is always normal, ensuring the continuous power supply and stable operation of the system. Low power consumption, high efficiency: the circuit runs stably under low voltage and wide voltage domain conditions, and has extremely low static current, meeting the low power consumption design requirement.

[0081] Please refer to Figure 9 , the PMOS switch selection module includes a fifth inverter INV5, a sixth inverter INV6, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, and a thirteenth PMOS tube P13.

[0082] ​The circuit connection relationship of the PMOS switch gating module is that: the input end of the fifth inverter INV5 is used for receiving a switch state control signal, the output end of the fifth inverter INV5 is electrically connected with the input end of the sixth inverter INV6, the gate of the twelfth PMOS P12 and the gate of the thirteenth PMOS P13, the output end of the sixth inverter INV6 is electrically connected with the gate of the tenth PMOS P10 and the gate of the eleventh PMOS P11, the source of the tenth PMOS P10 is used for receiving a backup battery voltage VBAT, the source of the twelfth PMOS P12 is used for receiving an external power supply voltage VDD, the substrate of the tenth PMOS P10 is electrically connected with the substrate of the eleventh PMOS P11, the drain of the tenth PMOS P10 and the source of the eleventh PMOS P11, and the substrate of the twelfth PMOS P12 is electrically connected with the substrate of the thirteenth PMOS P13, the drain of the twelfth PMOS P12 and the source of the thirteenth PMOS P13.

[0083] The basic principle of the circuit of the PMOS switch gating module is that: when the switch state control signal SW is high, the fifth inverter INV5 outputs a low-level reverse control signal, the twelfth PMOS P12 and the thirteenth PMOS P13 are in a conductive state, the tenth PMOS P10 and the eleventh PMOS P11 are in a disconnected state, and the drain of the thirteenth PMOS P13 outputs the external power supply voltage VDD as the current supply voltage VCC; when the switch state control signal is low, the fifth inverter INV5 outputs a high-level reverse control signal, the twelfth PMOS P12 and the thirteenth PMOS P13 are in a disconnected state, the tenth PMOS P10 and the eleventh PMOS P11 are in a conductive state, and the drain of the eleventh PMOS P11 outputs the backup battery voltage VBAT as the current supply voltage VCC.

[0084] In the PMOS switch gating module, in order to reduce the voltage loss on the switch as much as possible, PMOS tubes (P10, P11, P12 and P13) are used as power gating switches. When one power supply is selected, the other power supply must be turned off. In fact, the switch gating circuit also considers the hot plug situation to prevent overshoot of the LDO module output. In addition, since the PMOS substrate NWELL must be connected to the highest potential of the S or D terminal, otherwise when the S or D terminal potential is greater than the diode conduction voltage, a forward diode conduction from S or D to the substrate NWELL is formed, which can seriously damage the device. P10 and P11 are connected in series, and the substrate SB1 of the two is connected to the S / D connection of P10 and P11; P12 and P13 are connected in series, and the substrate SB2 of the two is connected to the S / D connection of P12 and P13. That is, by using series PMOS tubes and reasonably connecting the substrate NWELL potential, the switch voltage loss is significantly reduced, the parasitic diode mis-conduction and device damage are prevented, and the reliability of hot plug protection and power switching is considered, meeting the requirements of efficient, low-loss and stable power management.

[0085] Please refer to Figure 10 The second bandgap reference module includes PMOS components, NMOS components, resistance components, transistor components, and a filter capacitor C1. The PMOS components and the NMOS components are electrically connected to form a current mirror structure, transmit a constant current to the transistor components, the resistance components are respectively electrically connected between the emitter of the transistor components and the source of the NMOS or the drain of the PMOS, and the filter capacitor is connected between the related resistance components and the ground.

[0086] Specifically, the PMOS components include a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, and a seventeenth PMOS tube P17. The NMOS components include a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, and a thirteenth NMOS tube N13. The resistance components include a first resistance R1, a second resistance R2, and a third resistance R3. The transistor components include a first transistor Q1, a second transistor Q2, and a third transistor Q3. The NMOS components are used to transmit the generated working current to the PMOS off-voltage selection module. The filter capacitor and the resistance components are used to transmit the second reference voltage and the second bias current to the LDO module.

[0087] In the second bandgap reference module, the working voltage is VCC, which is obtained by switching VDD or VBAT, and the circuit structure is low voltage and low power (the circuit working current is only about 0.7 μA, and the minimum working voltage is 1.6 V) to meet the requirements of the wide voltage domain (1.8 V-3.6 V) of the battery. Within the input voltage range of 1.8 V-3.6 V, the output VREF2 changes only by 14 mV with VBAT, which serves as the reference voltage of the backup LDO, and meets the normal operation of the backup and RTC functions of the SRAM.

[0088] The detailed working principle of the second bandgap reference module is described below:

[0089] In the second bandgap reference module, P14 and P15 have the same size, N10 and N11 have the same size, and N8 and N9 have the same size. The second reference voltage VREF2 of the bandgap reference 2 is derived as follows. According to the circuit, I4=I5, the currents flowing through Q1 and Q2 are equal, so there is:

[0090] V q2 -V q1 =V T ln(n)

[0091] In the formula, n=m1 / m2. Since the currents flowing through N10 and N11 are also equal, their source voltages are equal, that is,

[0092] V q2 =V q3

[0093] Therefore,

[0094] V q3 -V q1 =V T ln(n)

[0095] From the circuit, we get:

[0096]

[0097] Therefore,

[0098]

[0099] From the circuit, we get:

[0100] VREF2=I6R2+V be3 =kI4R2+V be3

[0101] In the formula,

[0102] Therefore,

[0103]

[0104] The above formula is an expression of the second reference voltage.

[0105] In the formula, V T is a positive temperature coefficient, V be3 represents the BE junction voltage of the third diode Q3, which is a negative temperature coefficient, and by selecting appropriate n, k, R2 / R1, a VREF2 which is substantially not subject to temperature change can be obtained.

[0106] Referring to FIG. 11, when the input voltage VBAT changes in the range of 1.8V-3.6V, the output reference voltage VREF2 changes very little, only about 14mV. The result shows that the second bandgap reference module can provide a highly stable output reference voltage in a wide input voltage range (especially in the low voltage domain), meeting the requirements of low voltage domain applications. This feature enables it to be used as a high-precision reference voltage for LDO modules and other low-power circuits.

[0107] Referring to FIG. 11, when the input voltage VBAT changes in the range of 1.8V-3.6V, the output reference voltage VREF2 changes very little, only about 14mV. The result shows that the second bandgap reference module can provide a highly stable output reference voltage in a wide input voltage range (especially in the low voltage domain), meeting the requirements of low voltage domain applications. This feature enables it to be used as a high-precision reference voltage for LDO modules and other low-power circuits. Figure 12 , the simulation waveform changes with temperature (-55℃-125℃) under different process angles (SS process, TT process, FF process). The result shows that the second bandgap reference module has good temperature stability, and the output voltage changes very little with temperature (the typical temperature drift of the reference voltage is 2mV, with very small fluctuations), and is consistent and reliable under different process angles. The low temperature drift makes it suitable for environments with large temperature changes, meeting the needs of high-precision applications.

[0108] The embodiment of the present application also provides an MCU chip, which comprises a chip body and an automatic switching circuit of a backup power supply integrated in the chip body.

[0109] The embodiment of the present application also provides an automatic switching device of a backup power supply, which is internally provided with an automatic switching circuit of a backup power supply.

[0110] The beneficial effects of the present application include the following:

[0111] 1) The present application proposes a circuit architecture different from the prior art, which adopts a double bandgap reference circuit structure to provide reference voltages and bias currents for a VDD power-on reset circuit and a PMOS off voltage selection circuit, respectively; the working voltage of the bandgap reference 1 is VDD, and the working voltage of the bandgap reference 2 is VCC (an uninterrupted voltage), so that the gating of the power supply voltage does not need to pass through the voltage drop caused by a diode.

[0112] 2) The PMOS off voltage selection circuit of the present application uses a simple and small-current circuit structure to select a suitable PMOS off voltage from VDD and VBAT.

[0113] 3) The level shift module of the present application can ensure that the output signal is determined before VDD12 reaches the normal value, and meets the circuit logic requirements.

[0114] 4) The present application makes the bandgap reference circuit operating voltage close to the input voltage, which can reduce the input voltage by about 0.6V to work normally, compared with the prior art;

[0115] 5) When the VDD is selected as the power supply, when VNAT>VDD, the battery power consumption of the present application is only about 50nA (because the PMOS off voltage selection module needs a current of about 50nA, which is provided by VBAT to compare the size of VBAT and VDD in real time), while the currently disclosed related technology needs a battery as the operating voltage of the bandgap reference circuit and the comparator circuit, and the battery power consumption is generally above the μA level;

[0116] 6) When the VBAT is selected as the power supply, under the same structure and conditions, the battery consumption current of the present application is reduced compared with the original technology.

[0117] 7) The present application supports that the external battery VBAT and the power supply VDD have a large pressure difference to normally turn off the PMOS switch;

[0118] 8) The circuit architecture of the present application has universality, and only needs to adjust the design of each module for different processes, and the circuit structure does not need to be changed;

[0119] 9) The present application has scalability, and can be flexibly modified and expanded according to different design requirements. When the core needs a larger working current, the width-length ratio of the PMOS switch can be appropriately increased to solve the problem.

[0120] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0121] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. An automatic transfer switch for an emergency power supply, characterized by comprising: The application is applied to an MCU chip, and the automatic backup power supply switching circuit comprises a PMOS off voltage selection module, a level shift module, a PMOS switch gating module and an LDO module. The output end of the PMOS off voltage selection module is electrically connected with the input end of the level shift module, the output end of the level shift module is electrically connected with the control signal input end of the PMOS switch gating module, the output end of the PMOS switch gating module is electrically connected with the input end of the LDO module, the voltage input end of the PMOS switch gating module is used for receiving an external power supply voltage and a backup battery voltage, and the input end of the PMOS off voltage selection module is used for receiving the external power supply voltage and the backup battery voltage. The PMOS off voltage selection module is used for selecting one of the external power supply voltage and the backup battery voltage as a first target voltage and outputting the first target voltage to the level shift module, the level shift module is used for outputting a switch state control signal to the control signal input end of the PMOS switch gating module according to the first target voltage, the PMOS switch gating module is used for selecting one of the external power supply voltage and the backup battery voltage as a current power supply voltage according to the switch state control signal and outputting the current power supply voltage to the LDO module, and the LDO module is used for outputting a second target voltage to the MCU chip. The automatic backup power supply switching circuit further comprises a VDD power-on reset module, the input end of the VDD power-on reset module is used for receiving an external power supply voltage, and the output end of the VDD power-on reset module is electrically connected with the input end of the level shift module. The VDD power-on reset module is used for outputting a power-on reset signal to the level shift module according to a first reference voltage, and the power-on reset signal is used for initializing the working state of the level shift module. The automatic backup power supply switching circuit further comprises a first bandgap reference module, the input end of the first bandgap reference module is used for receiving an external power supply voltage, and the output end of the first bandgap reference module is electrically connected with the input end of the VDD power-on reset module. The first bandgap reference module is used for transmitting the generated first reference voltage, first bias current and external power supply state signal to the VDD power-on reset module, and the external power supply state signal is used for indicating the current working state of the external power supply. The automatic backup power supply switching circuit further comprises a second bandgap reference module, the input end of the second bandgap reference module is electrically connected with the output end of the PMOS switch gating module, and the output end of the second bandgap reference module is electrically connected with the PMOS off voltage selection module and the LDO module respectively. The second bandgap reference module is configured to transmit the generated working current to the PMOS turn-off voltage selection module, and transmit the generated second reference voltage and second bias current to the LDO module; wherein the working current is configured to control the PMOS turn-off voltage selection module to compare the backup battery voltage and the external power supply voltage to select a first target voltage.

2. The automatic transfer switch of claim 1, wherein, The PMOS turn-off voltage selection module comprises a first PMOS tube, a second PMOS tube, a first inverter, a second inverter, a Schmitt inverter, a first current mirror and a current switching device. The source of the first PMOS tube is configured to receive an external power supply voltage, the drain of the first PMOS tube is electrically connected to a VMAX port, the gate of the first PMOS tube is electrically connected to the output of the first inverter, the source of the second PMOS tube is configured to receive a backup battery voltage, the drain of the second PMOS tube is electrically connected to the VMAX port, the gate of the second PMOS tube is electrically connected to the output of the second inverter, the first input of the first inverter is configured to receive the backup battery voltage, the first input of the second inverter is configured to receive the external power supply voltage, the input of the Schmitt inverter is electrically connected to a voltage comparison node, the output of the Schmitt inverter is electrically connected to the second input of the first inverter, the output of the first current mirror is configured to mirror a third reference current to the voltage comparison node, the source of the current switching device is configured to receive the backup battery voltage, the gate of the current switching device is configured to receive the external power supply voltage, and the output of the current switching device is configured to output a second reference current to the voltage comparison node. When the external power supply voltage received by the voltage comparison node is greater than the backup battery voltage, the Schmitt inverter outputs a high-level signal to the first inverter, controls the first PMOS tube to be turned on, and outputs the external power supply voltage as a first target voltage to the VMAX port. When the external power supply voltage received by the voltage comparison node is less than the backup battery voltage, the Schmitt inverter outputs a low-level signal, and after the first inverter, outputs a high-level signal to the second input of the second inverter, controls the second PMOS tube to be turned on, and outputs the backup battery voltage as a first target voltage to the VMAX port.

3. The automatic transfer switch of claim 1, wherein: The level shift module comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third inverter and a fourth inverter. The source of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are used for receiving a first target voltage, the gate of the sixth PMOS tube is electrically connected with the source of the seventh NMOS tube, a preset voltage switching node, the drain of the seventh PMOS tube, the drain of the ninth PMOS tube and the input end of the fourth inverter, the drain of the sixth PMOS tube is electrically connected with the source of the sixth NMOS tube and the gate of the seventh PMOS tube, the gate of the sixth NMOS tube is electrically connected with the output end of the third inverter, the input end of the third inverter is electrically connected with the output end of the VDD power-on reset module and the gate of the seventh NMOS tube, the drain of the sixth NMOS tube and the drain of the seventh NMOS tube are grounded, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube are used for receiving a power-on reset signal, the drain of the eighth PMOS tube is electrically connected with the source of the ninth PMOS tube, and the power supply end of the third inverter is used for receiving the second target voltage output by the LDO module; When the power-on reset signal is at a low level, the eighth PMOS tube and the ninth PMOS tube are in a conducting state and the seventh NMOS tube is in an off state, and the fourth inverter outputs a low-level switch state control signal; when the power-on reset signal is at a high level, the eighth PMOS tube and the ninth PMOS tube are in an off state, the power-on reset signal is transmitted by the seventh NMOS tube to be opened, so that the fourth inverter outputs a high-level switch state control signal.

4. The automatic transfer switch of claim 1, wherein, The PMOS switch gating module comprises a fifth inverter, a sixth inverter, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube. The input end of the fifth inverter is used for receiving a switch state control signal, the output end of the fifth inverter is electrically connected with the input end of the sixth inverter, the gate of the twelfth PMOS tube and the gate of the thirteenth PMOS tube, the output end of the sixth inverter is electrically connected with the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube, the source of the tenth PMOS tube is used for receiving a backup battery voltage, the source of the twelfth PMOS tube is used for receiving an external power supply voltage, the substrate of the tenth PMOS tube is electrically connected with the substrate of the eleventh PMOS tube, the drain of the tenth PMOS tube and the source of the eleventh PMOS tube, and the substrate of the twelfth PMOS tube is electrically connected with the substrate of the thirteenth PMOS tube, the drain of the twelfth PMOS tube and the source of the thirteenth PMOS tube; When the switch state control signal is at a high level, the fifth inverter outputs a low-level reverse control signal, the twelfth PMOS tube and the thirteenth PMOS tube are in a conducting state, the tenth PMOS tube and the eleventh PMOS tube are in an off state, and the drain of the thirteenth PMOS tube outputs the external power supply voltage as the current power supply voltage. When the switch state control signal is low, the fifth inverter outputs a high level reverse control signal, the twelfth and thirteenth PMOS tubes are in an off state, the tenth and eleventh PMOS tubes are in a conductive state, and the drain of the eleventh PMOS tube outputs the backup battery voltage as the current power supply voltage.

5. The automatic transfer switch of claim 1, wherein, The second band gap reference module comprises a PMOS component, an NMOS component, a resistance component, a transistor component and a filter capacitor. The PMOS component and the NMOS component are electrically connected to form a current mirror structure, and constant current is transmitted to the transistor component; the resistance component is respectively electrically connected between the emitter of the transistor component and the source of the NMOS component or the drain of the PMOS component; and the filter capacitor is connected between the resistance component and the ground. The NMOS component is used to transmit the generated working current to the PMOS off voltage selection module; and the filter capacitor and the resistance component are used to transmit the second reference voltage and the second bias current to the LDO module.

6. An MCU chip, characterized by The chip body comprises a chip body and an automatic backup power switching circuit as claimed in any one of claims 1 to 5, and the automatic backup power switching circuit is integrated in the chip body.

7. An automatic transfer switch for backup power supplies, characterized by The automatic backup power switching device is internally provided with an automatic backup power switching circuit as claimed in any one of claims 1 to 5.

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