A SiC MOSFET driving method and system for quantitative suppression of voltage overshoot spikes

Abstract

The application provides a SiC MOSFET driving method and system for quantitative suppression of voltage overshoot spikes, and the method steps are as follows: reducing the drain-source voltage of the SiC MOSFET to a voltage range that can be detected by a subsequent circuit; detecting the output of the reduced drain-source voltage, maintaining the overshoot peak value of the drain-source voltage and outputting; sampling the output overshoot peak value of the drain-source voltage; outputting a pulse signal according to the current drop stage of the device shutdown identified by the drain-source voltage; obtaining a voltage-controlled reference voltage at the input end of a voltage-controlled current source by running a PI control module; and taking the voltage-controlled reference voltage in step S5 as the input of the voltage-controlled current source, and triggering the voltage-controlled current source to output by the pulse signal, so as to inject an additional driving current into the gate of the SiC MOSFET and control the voltage overshoot spikes. The application realizes closed-loop control of the voltage overshoot peak value, quantitatively suppresses the voltage overshoot peak value, and improves the reliability and efficiency.

Description

Technical Field

[0001] This invention relates to the field of power electronics and electric drives, and in particular to a SiCMOSFET driving method and system for quantitative suppression of voltage overshoot spikes. Background Technology

[0002] Wide-bandgap power semiconductor devices, represented by silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), possess superior performance. Compared to traditional silicon-based devices, they offer faster switching speeds, lower on-resistance, and higher operating temperatures, leading to their widespread application in electric vehicles, new energy power generation, and aerospace. Their high switching speed effectively reduces switching losses, but it also introduces some negative impacts. Due to the unavoidable introduction of parasitic inductance in the power circuit by device packaging and printed circuit board (PCB) layout, severe voltage overshoot occurs when the SiC MOSFET is turned off. The peak voltage overshoot is directly proportional to the load current, becoming extremely severe under high load current conditions, potentially causing overvoltage damage to the device. This significantly reduces the operational reliability of the SiC MOSFET.

[0003] To suppress turn-off voltage overshoot spikes in SiC MOSFETs, there are currently two main categories of methods. One category involves passive suppression methods such as adding snubber or damping circuits. These methods have relatively simple circuit structures, but require different snubber circuit parameters for different operating conditions (e.g., input voltage, load current level, circuit parasitic parameters), resulting in limited suppression effectiveness under varying load current conditions. Furthermore, passive devices are often directly connected to the device drain and source or bridge arm, facing frequent high-voltage surges, making high-reliability design a challenge. The second category uses active gate drive circuits. These methods can dynamically adjust device drive parameters to flexibly control dv / dt, di / dt, current overshoot, and voltage overshoot during device switching, which is an effective way to improve SiC MOSFET performance. However, in terms of SiC MOSFET turn-off voltage overshoot suppression, existing active gate drive circuits often only provide a fixed voltage overshoot suppression effect and cannot achieve quantitative suppression of voltage overshoot spikes. In addition, most existing active gate drive circuits can only operate under specific input and output conditions, and are still insufficient under variable load conditions, causing additional switching losses under low load current.

[0004] Currently, SiC MOSFET design and manufacturing technologies are developing rapidly, creating an urgent need for their high reliability and high efficiency in converter applications. Therefore, research on quantitatively suppressing SiC MOSFET turn-off voltage overshoot peaks, optimizing switching losses under low loads, suppressing voltage overshoot peaks under high loads, and improving device reliability and efficiency is of great significance for practical operating conditions. Summary of the Invention

[0005] The purpose of this invention is to provide a SiC MOSFET driving method and system for quantitative suppression of voltage overshoot spikes. This method achieves quantitative suppression of voltage overshoot spikes, reduces switching losses under low current loads, improves system efficiency, and quantitatively suppresses voltage overshoot spikes under high current loads, thereby improving device operational reliability.

[0006] A method for quantitatively suppressing voltage overshoot spikes in a SiC MOSFET driving system, wherein the gate of the SiC MOSFET is connected to the output terminal of a voltage-controlled current source, and the specific steps of the method are as follows:

[0007] S1: Reduce the drain-source voltage of the SiC MOSFET to a voltage range that can be detected by the subsequent circuitry;

[0008] S2: Detect the output of drain-source voltage after degradation, maintain the overshoot peak value of drain-source voltage and output it;

[0009] S3: Sample the peak value of the drain-source voltage overshoot output in step S2;

[0010] S4: Identify the current drop phase during device turn-off based on drain-source voltage and output a pulse signal;

[0011] S5: Run the PI control module to obtain the voltage control reference voltage at the input terminal of the voltage-controlled current source;

[0012] S6: The voltage-controlled current source takes the voltage-controlled reference voltage in step S5 as input, and triggers the voltage-controlled current source to output with a pulse signal, injecting additional drive current into the gate of the SiC MOSFET to regulate the voltage overshoot spike.

[0013] Optionally, the specific steps for outputting the pulse signal in step S4 are as follows:

[0014] S4.1: Compare the stepped-down drain-source voltage with the first reference voltage, output a pulse signal, latch the first rising edge of the pulse signal, and output a start signal;

[0015] S4.2: Input the drain-source voltage of the SiC MOSFET into the differentiating circuit to obtain the differential signal, compare the differential signal with the second reference voltage, output a pulse signal and invert it, latch the first rising edge of the signal, and output the end signal;

[0016] S4.3: Perform an XOR operation between the start signal and the end signal to generate a trigger signal.

[0017] Optionally, the specific steps in step S5 are as follows:

[0018] S5.1: The peak value of the SiC MOSFET turn-off voltage overshoot sampled in step S3 is used as the feedback input of the PI control module;

[0019] S5.2: Compare the feedback input of the PI control module with the preset upper limit of the overshoot peak value of the PI control module, and perform the PI control algorithm calculation once in each switching cycle;

[0020] S5.3: Output the calculated value of the PI control module in the form of voltage, and output the voltage-controlled reference voltage.

[0021] Optionally, the specific method for regulating the voltage overshoot spike in step S6 is as follows:

[0022] When the drain current of the SiC MOSFET decreases during turn-off, a pulse signal controls the input of the voltage-controlled reference voltage to the voltage-controlled current source. The output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET, adjusting the overshoot peak value of the SiC MOSFET turn-off voltage. Combined with step S5, the overshoot peak value of the SiC MOSFET turn-off voltage is controlled in a closed loop.

[0023] A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes includes a voltage-controlled current source, an RC voltage divider circuit, a peak hold circuit, a stage recognition circuit, a microcontroller, and a SiC MOSFET.

[0024] The output terminal of the voltage-controlled current source is connected to the gate of the SiC MOSFET. The voltage-controlled current source is connected to the microcontroller through the multiplexer S1. The drain of the SiC MOSFET is connected to the input terminal of the RC voltage divider circuit. The output terminal of the RC voltage divider circuit is connected to the peak hold circuit and the stage recognition circuit.

[0025] The microcontroller is used to acquire the output of the peak hold circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input, takes the pulse signal of the stage recognition circuit as the trigger signal and outputs it to inject additional drive current into the gate of the SiCMOSFET to regulate the voltage overshoot spike.

[0026] Optionally, the voltage-controlled current source further includes a reference current source, a current mirror circuit, and a power supply V. CC ;

[0027] One end of the reference current source is connected to the microcontroller via a multiplexer S1. The reference current source is connected to a current mirror circuit, and the input terminal of the current mirror circuit is connected to the power supply V. CC The output terminal of the current mirror circuit is connected to the gate of the SiC MOSFET.

[0028] Optionally, the RC voltage divider circuit includes a first RC parallel module and a second RC parallel module connected at one end;

[0029] The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, and the other end of the second RC parallel module is grounded. The connection point of the first RC parallel module and the second RC parallel module is connected to the peak hold circuit and the stage recognition circuit.

[0030] Optionally, the peak hold circuit includes a transconductance operational amplifier, a charging diode, a clamping diode, a reset MOSFET, a hold capacitor, and a high-bandwidth operational amplifier;

[0031] The non-inverting input of the transconductance operational amplifier is connected to the output of the RC voltage divider circuit, the inverting input of the transconductance operational amplifier is connected to the inverting input of the high-bandwidth operational amplifier, and the output of the transconductance operational amplifier is connected to the anode of the charging diode and the cathode of the clamping diode.

[0032] The cathode of the charging diode, one end of the holding capacitor, and the drain of the reset MOS transistor are connected to the non-inverting input of the high-bandwidth operational amplifier. The source of the reset MOS transistor, the other end of the holding capacitor, and the anode of the clamping diode are all grounded. The output of the high-bandwidth operational amplifier is connected to the microcontroller.

[0033] Optionally, the stage identification circuit includes a differential resistor, a differential capacitor, a first comparator, a second comparator, an inverter, a first D flip-flop, a second D flip-flop, and an XOR gate module.

[0034] The non-inverting input of the first comparator is connected to the RC voltage divider circuit, the inverting input of the first comparator is connected to the first reference voltage, the output of the first comparator is connected to the CLK pin of the first D flip-flop, and the output of the first D flip-flop is connected to the first input of the XOR gate module.

[0035] The differential resistor and differential capacitor are connected in series. The other end of the differential resistor is grounded, and the other end of the differential capacitor is connected to the drain of the SiC MOSFET. The connection point of the differential resistor and differential capacitor is connected to the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the second reference voltage. The output of the second comparator is connected to the input of the inverter. The output of the inverter is connected to the CLK pin of the second D flip-flop. The output of the second D flip-flop is connected to the second input of the XOR gate module. The CLR pins of the first and second D flip-flops are connected to the drive signal.

[0036] Optionally, the microcontroller includes an ADC module, a PI control module, and a DAC module;

[0037] The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak hold circuit. The PI control module is used to compare the SiC MOSFET turn-off voltage overshoot peak value with the preset upper limit value of the overshoot peak value of the PI control module. The DAC module is used to output the voltage-controlled reference voltage at the input terminal of the voltage-controlled current source.

[0038] Because of the adoption of the above technical solution, the present invention has the following advantages:

[0039] 1. This application realizes closed-loop control of voltage overshoot peak value, quantitatively suppresses voltage overshoot peak value. Compared with the existing methods, this invention has high control flexibility, reduces switching losses under low load current conditions, quantitatively suppresses voltage overshoot peak value under high load current conditions, avoids SiC MOSFET overvoltage breakdown, and improves reliability and efficiency.

[0040] 2. In this application, the peak value of the SiC MOSFET turn-off voltage overshoot is extracted by the peak hold circuit during the current switching cycle; then it is sampled by the ADC module of the microcontroller; then the sampled value of the ADC module is used as the feedback input of the PI control algorithm running inside the microcontroller, and a calculation is performed with the voltage overshoot control target preset by the microcontroller as the set value; then the voltage-controlled current source output current value injected into the gate of the SiC MOSFET in the next switching cycle is output by the DAC module of the microcontroller; then in the next switching cycle, the drain current of the SiC MOSFET is identified by the stage recognition circuit, and the voltage-controlled current mirror is triggered to inject the voltage-controlled current source output current value into the gate of the SiC MOSFET to control the voltage overshoot peak value.

[0041] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0042] The accompanying drawings of this invention are described below.

[0043] Figure 1 This is a circuit diagram of the SiC MOSFET driving system of the present invention.

[0044] Figure 2 This is a circuit diagram of the voltage divider circuit of the present invention.

[0045] Figure 3 This is a circuit diagram of the peak hold circuit of the present invention.

[0046] Figure 4 This is a circuit structure diagram of the stage identification circuit of the present invention.

[0047] Figure 5 This is a circuit diagram of the voltage-controlled current source of the present invention.

[0048] Figure 6 For the current i of this invention ctrl Simplified circuit diagram when injecting SiC MOSFET gate.

[0049] Figure 7 This is a diagram showing the key signals output by each circuit in this invention.

[0050] Figure 8 This is a schematic diagram of the delay time compensation of the present invention.

[0051] Figure 9 This is a comparison chart of the turn-off losses of the present invention and the method of increasing gate resistance.

[0052] Figure 10 This is an experimental diagram showing the quantitative suppression of the turn-off voltage overshoot spike in the SiC MOSFET of this invention. Detailed Implementation

[0053] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0054] Example 1:

[0055] like Figure 1 The SiC MOSFET driving system shown includes a voltage-controlled current source, an RC voltage divider circuit, a peak hold circuit, a stage recognition circuit, and a microcontroller.

[0056] The output terminal of the voltage-controlled current source is connected to the gate of the SiC MOSFET. The voltage-controlled current source is connected to the microcontroller through the multiplexer S1. The drain of the SiC MOSFET is connected to the input terminal of the RC voltage divider circuit. The output terminal of the RC voltage divider circuit is connected to the peak hold circuit and the stage recognition circuit.

[0057] The microcontroller is used to acquire the output of the peak hold circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input, takes the pulse signal of the stage recognition circuit as the trigger signal and outputs it to inject additional drive current into the gate of the SiCMOSFET to regulate the voltage overshoot spike.

[0058] like Figure 5 As shown, the voltage-controlled current source includes an operational amplifier OP3, a multiplexer S1, and a feedback resistor R. fN-type MOSFET Q2, P-type MOSFET Q3, P-type MOSFET Q4, P-type MOSFET Q5, and P-type MOSFET Q6; the feedback resistor R f One end is connected in series with the source of the N-type MOS transistor Q2, and the feedback resistor R f The other end is grounded. The output of the operational amplifier OP3 is connected to the gate of the N-type MOS transistor Q2, and the inverting input of the operational amplifier OP3 is connected to the feedback resistor R. f One end of the multiplexer S1 is connected to the non-inverting input of the operational amplifier OP3, and the other end of the multiplexer S1 is connected to the microcontroller.

[0059] The gate of P-type MOSFET Q3 is connected to the gate of P-type MOSFET Q4, and the drains of both P-type MOSFET Q3 and P-type MOSFET Q4 are connected to the power supply V. CC The gate of the P-type MOSFET Q5 is connected to the gate of the P-type MOSFET Q6, the source of the P-type MOSFET Q5 is connected to the drain of the N-type MOSFET Q2, the drain of the P-type MOSFET Q5 is connected to the source of the P-type MOSFET Q3, the drain of the P-type MOSFET Q6 is connected to the source of the P-type MOSFET Q4, and the source of the P-type MOSFET Q6 is connected to the gate of the SiC MOSFET.

[0060] In this embodiment, operational amplifier OP3 and feedback resistor R f N-type MOSFET Q2 forms a reference current source, while P-type MOSFETs Q3, Q4, Q5, and Q6 form a current mirror circuit.

[0061] like Figure 2 As shown, the RC voltage divider circuit includes a first RC parallel module and a second RC parallel module connected at one end; the first RC parallel module includes a voltage divider resistor R1 and a voltage divider capacitor C1, and the second RC parallel module includes a voltage divider resistor R2 and a voltage divider capacitor C2.

[0062] The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, and the other end of the second RC parallel module is grounded. The connection point of the first RC parallel module and the second RC parallel module is connected to the peak hold circuit and the stage recognition circuit.

[0063] like Figure 3 As shown, the peak hold circuit includes a transconductance operational amplifier OP1, a charging diode D1, a clamping diode D2, a reset MOSFET Q1, and a holding capacitor C. P and high-bandwidth operational amplifier OP2;

[0064] The non-inverting input terminal of the transconductance operational amplifier OP1 is connected to the connection terminal of the first parallel module and the second parallel module. The inverting input terminal of the transconductance operational amplifier OP1 is connected to the inverting input terminal of the high-bandwidth operational amplifier OP2. The output terminal of the transconductance operational amplifier OP1 is connected to the anode of the charging diode D1 and the cathode of the clamping diode D2.

[0065] The cathode of the charging diode D1 and the holding capacitor C P One end of the circuit and the drain of the reset MOSFET Q1 are connected to the non-inverting input of the high-bandwidth operational amplifier OP2. The source of the reset MOSFET Q1 and the holding capacitor C are connected to the non-inverting input of the high-bandwidth operational amplifier OP2. P The other end of the high-bandwidth operational amplifier OP2 and the anode of the clamping diode D2 are both grounded, and the output of the high-bandwidth operational amplifier OP2 is connected to the microcontroller.

[0066] like Figure 4 As shown, the stage identification circuit includes a differential resistor R3, a differential capacitor C3, a first comparator, a second comparator, an inverter INV1, a first D flip-flop, a second D flip-flop, and an XOR gate module XOR1; the differential resistor R3 and the differential capacitor C3 are connected in series, the other end of the differential resistor R3 is grounded, and the other end of the differential capacitor C3 is connected to the drain of the SiC MOSFET.

[0067] The non-inverting input of the first comparator is connected to an RC voltage divider circuit, and the inverting input of the first comparator is connected to the first reference voltage V. ref1 The first comparator's output is connected to the CLK pin of the first D flip-flop, and the output of the first D flip-flop is connected to the first input of the XOR gate module XOR1. The connection point of the differential resistor R3 and the differential capacitor C3 is connected to the non-inverting input of the second comparator, and the inverting input of the second comparator is connected to the second reference voltage V. ref2 The output of the second comparator is connected to the input of the inverter INV1. The output of the inverter INV1 is connected to the CLK pin of the second D flip-flop. The output of the second D flip-flop is connected to the second input of the XOR gate module XOR1. The data pin D of the first and second D flip-flops is connected to +5V. The CLR pins of the first and second D flip-flops are connected to the drive signal.

[0068] like Figure 1 As shown, the microcontroller includes an ADC module, a PI control module, and a DAC module. The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak hold circuit. The PI control module is used to compare the SiC MOSFET turn-off voltage overshoot peak value with the preset upper limit value of the overshoot peak value of the PI control module. The DAC module is used to output the voltage-controlled reference voltage at the input terminal of the voltage-controlled current source.

[0069] In this embodiment, the ADC module is used to sample the low-impedance peak voltage output of the high-bandwidth operational amplifier OP2. The microcontroller (MCU) uses STMicroelectronics' STM32G474CET6, which integrates a 12-bit ADC module. The peak voltage v is acquired in the peak hold circuit. ds_peak The conversion will begin immediately afterwards.

[0070] Example 2:

[0071] A SiC MOSFET driving method for quantitative suppression of voltage overshoot spikes, employing the SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes described in Example 1, includes the following specific steps:

[0072] S1: Reduce the drain-source voltage of the SiC MOSFET to a voltage range that can be detected by the subsequent circuitry;

[0073] In this embodiment, as Figure 2 The RC voltage divider circuit shown is used because the bus voltage of the SiC MOSFET is as high as several hundred volts, making it difficult for the stage detection circuit and peak detection circuit to detect it directly. Therefore, the RC voltage divider circuit is used to divide the several hundred volts. ds The voltage is reduced to a range detectable by the subsequent circuitry. Furthermore, to minimize the impact of parasitic capacitance, voltage divider capacitors C1 and C2 are used to improve the dynamic performance of the voltage divider network. The voltage division ratio is determined by R2 / (R1+R2), and the values ​​of voltage divider capacitors C1 and C2 satisfy the following relationship:

[0074]

[0075] S2: Detect the output of drain-source voltage after degradation, maintain the overshoot peak value of drain-source voltage and output it;

[0076] In this embodiment, as Figure 3 The peak hold circuit shown has a drain-source voltage v ds The changes are very rapid; directly detecting the peak value requires an ADC conversion chip with a very high sampling speed, and the sampled data needs to be processed, resulting in a complex and relatively low-precision implementation. A peak hold circuit can maintain v... ds Overshoot peak values ​​can be converted using a conventional ADC converter. In this embodiment, when the input voltage v of the transconductance operational amplifier OP1... ds_d Greater than peak voltage v ds_peak At that time, the output current of the transconductance operational amplifier OP1 supplies the holding capacitor C. P Charging, input voltage V ds_d After reaching its maximum value, the value begins to decrease. At this point, the charging diode D1 is cut off, and the capacitor C remains in place. PWith the voltage remaining constant, the large input impedance of the high-bandwidth operational amplifier OP2 reduces the holding capacitor C. p Voltage sag rate. When the input voltage v of the transconductance operational amplifier OP1... ds_d Less than peak voltage v ds_peak At this time, clamping diode D2 provides a current path for transconductance operational amplifier OP1, clamping the output of transconductance operational amplifier OP1 to 0V. In addition, to prevent excessive reverse recovery current from charging diode D1 from affecting the holding capacitor C... p The voltage drops significantly, and the charging diode D1 uses a Schottky diode. After the ADC sampling is complete, the holding capacitor C is reset via the reset MOSFET Q1. p Discharge causes the holding capacitor C to... p The drain-source voltage V can be maintained normally in the next cycle. ds_d The peak value.

[0077] S3: Sample the peak value of the drain-source voltage overshoot output in step S2;

[0078] In this embodiment, the drain voltage v after attenuation by the RC voltage divider circuit is used. ds As the input source, a slowly rising ramp signal is obtained through an RC low-pass filter circuit. After passing through a hysteresis comparator, a reference voltage v is set. ds_peak_lim Compared to a slowly rising ramp signal, at v ds After a fixed delay following the start of the rise, a rising edge is output, triggering the ADC module to sample the peak hold circuit output.

[0079] S4: Identify the current drop phase during device turn-off based on the drain-source voltage, and output a pulse signal. The specific steps are as follows:

[0080] S4.1: The output of the RC voltage divider circuit is compared with the first reference voltage V through a high-speed hysteresis comparator. ref1 The comparison is performed, and a pulse signal is output. The first D flip-flop latches the first rising edge of the pulse signal and outputs a start signal.

[0081] In this embodiment, the current and voltage waveforms and key signals when the device is turned off are as follows: Figure 7 As shown, the drain-source voltage v ds First rise to bus flow i d Then begin the descent, using the first comparator to identify the bus current i. d The moment t3 begins to decrease. The reference voltage V of the first comparator. ref1 The theoretical value is V DC When v ds_d Rise to V ref1 When the first comparator outputs a high level, to avoid v ds_dThe oscillation causes the level of the first comparator to jump repeatedly. The first rising edge of the output of the first comparator is synchronized by the first D flip-flop, and finally a stable trigger signal is output.

[0082] S4.2: Set the drain-source voltage v of the SiC MOSFET to... ds The input is fed into the differentiating circuit of the stage identification circuit to obtain the differential signal of the drain-source voltage, which is then compared with the second reference voltage V by a high-speed hysteresis comparator. ref2 The signal is compared and output as a pulse signal; then, it is inverted by an inverter, and finally, the first rising edge of the signal is latched by a second D flip-flop to output an end signal.

[0083] In this embodiment, a differentiating circuit composed of R3 and C3 is used to measure v. ds Differential, when the drain-source voltage v ds When it rises to its peak v ds_dif When the current drops to zero, the current i is no longer controlled. d Descending speed. V ref2 Setting it to 0.1V thus constructs the second comparator as a zero-crossing comparator, at v ds_dif The signal outputs a negative edge signal when it drops to zero, and then inverts it through inverter INV1 to avoid v ds_dif The oscillation causes the output of inverter INV1 to repeatedly change. Similarly, the first rising edge of inverter INV1 is synchronized using a second D flip-flop. Where v ds_dif for:

[0084]

[0085] S4.3: Use an XOR gate module to perform an XOR operation on the start signal and the end signal, ultimately generating the trigger signal v. trig This indicates the drain current decrease phase of the SiC MOSFET, during which the trigger signal v is generated. trig As a control signal for the voltage-controlled current source, the current mirror circuit outputs a drive current to the gate of the SiC MOSFET.

[0086] In this embodiment, the trigger signal v trig Triggering a voltage-controlled current source injects additional gate current during the drain current decline phase of the SiC MOSFET, reducing switching losses. However, this is due to delays in actual circuits. For example... Figure 8 As shown, when positioning at time t3, the reference voltage V of the first comparator needs to be appropriately reduced. ref1 Triggered at t'3, V ref1 The value of can be calculated as follows:

[0087]

[0088] Furthermore, due to the approximately 10ns delay between the second comparator and the current mirror output when the drain-source voltage rises to its peak, i ctrl The effective range lasts exactly up to i d The descent phase ends or even lasts longer, and i d After the descent phase ends, i d Since it is 0A, i ctrl in i d Continuing to output after the descent phase ends will not increase device losses, V ref2 No special design is needed.

[0089] S5: Run the PI control module to obtain the voltage control reference voltage at the input terminal of the voltage-controlled current source;

[0090] S5.1: The overshoot peak value of the SiC MOSFET turn-off voltage sampled by the ADC module is used as the feedback input of the PI control module;

[0091] S5.2: The feedback input of the PI control module is compared with the preset upper limit value V of the overshoot peak value of the PI control module. ds_peak_lim The comparison is performed, and the PI control algorithm is executed once in each switching cycle.

[0092] S5.3: The DAC module of the microcontroller outputs the calculated value of the PI control module as a voltage, resulting in the output voltage-controlled reference voltage V. ctrl .

[0093] In this embodiment, the DAC module of the microcontroller MCU updates v ctrl The value of (i+1) controls the output current i of the current mirror circuit. ctrl The magnitude of the value ultimately achieves overshoot peak control of the drain-source voltage.

[0094] S6: The voltage-controlled current source takes the voltage-controlled reference voltage in step S5 as input, and triggers the voltage-controlled current source to output with a pulse signal, injecting additional drive current into the gate of the SiC MOSFET to regulate the voltage overshoot spike.

[0095] In this embodiment, the DAC module of the microcontroller outputs the calculated value of the PI control algorithm in voltage form before the device is turned off. When the drain current of the SiC MOSFET decreases during turn-off, a pulse signal controls the input of the voltage-controlled reference voltage to the voltage-controlled current source. The output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET, adjusting the overshoot peak value of the SiC MOSFET turn-off voltage. Combined with step S5, the overshoot peak value of the SiC MOSFET turn-off voltage is controlled in a closed loop.

[0096] In this embodiment, as Figure 5 The voltage-controlled current source circuit shown includes OP3, Q2, and R. fQ3~Q6 form a reference current source, and Q3~Q6 form a current mirror circuit, with the reference current i ref for:

[0097]

[0098] A Cascode structure is used to increase the output impedance of the current mirror, providing stable i-values ​​even when the gate-source voltage changes rapidly. ctrl At this time i ctrl with i ref They are approximately equal.

[0099] When in i d The current i will decrease during the descent phase. ctrl When the gate is injected, the present application can simplify the SiC MOSFET and the proposed circuit during operation. Figure 6 The gate-source voltage v of a SiC MOSFET gs for:

[0100]

[0101] τ is the RC constant of the SiC MOSFET gate:

[0102]

[0103] i at this stage d It can be approximated by the following formula:

[0104]

[0105] di d The expression for / dt can be further derived as follows:

[0106]

[0107] The peak value of the turn-off voltage overshoot of a SiC MOSFET is calculated by the following formula:

[0108]

[0109] Therefore, the present invention controls i ctrl Adjusting the overshoot peak value of the SiC MOSFET turn-off voltage, combined with step S5, forms a closed-loop control system to effectively regulate the overshoot peak value of the SiC MOSFET turn-off voltage.

[0110] S7: Experiments and Simulations: such as Figure 9 As shown, tests were conducted under 600 V / 40 A conditions, reducing the peak turn-off voltage overshoot of the SiC MOSFET from 868 V to 764 V. Compared to the traditional method of increasing the gate resistance, this resulted in a 41.23% reduction in turn-off loss and a significant reduction in turn-off delay time. Furthermore, as... Figure 10 This invention can quantitatively suppress the overshoot peak value of the turn-off voltage of SiC MOSFET under 800 V voltage and variable load current conditions. Figure 10 (a) shows that under conventional drive, the peak voltage overshoot rises to 1060V as the load current increases. Figure 10 (b) demonstrates that, under this invention, voltage overshoot peaks are quantitatively suppressed to 950 V.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A SiC MOSFET driving method for quantitative suppression of voltage overshoot spikes, characterized in that, The gate of the SiC MOSFET is connected to the output terminal of the voltage-controlled current source. The specific steps are as follows: S1: Reduce the drain-source voltage of the SiC MOSFET to a voltage range that can be detected by the subsequent circuitry; S2: Detect the output of drain-source voltage after degradation, maintain the overshoot peak value of drain-source voltage and output it; S3: Sample the peak value of the drain-source voltage overshoot output in step S2; S4: Identify the current drop phase during device turn-off based on the drain-source voltage and output a pulse signal; S5: Run the PI control module to obtain the voltage control reference voltage at the input terminal of the voltage-controlled current source; S6: The voltage-controlled current source takes the voltage-controlled reference voltage in step S5 as input, and triggers the voltage-controlled current source to output with a pulse signal, injecting additional drive current into the gate of the SiC MOSFET to regulate the voltage overshoot spike. The specific steps in step S5 are as follows: S5.1: The peak value of the SiC MOSFET turn-off voltage overshoot sampled in step S3 is used as the feedback input of the PI control module; S5.2: Compare the feedback input of the PI control module with the preset upper limit of the overshoot peak value of the PI control module, and perform the PI control algorithm calculation once in each switching cycle; S5.3: Output the calculated value of the PI control module in the form of voltage, and output the voltage-controlled reference voltage; The specific method for controlling the voltage overshoot spike in step S6 is as follows: When the drain current of the SiC MOSFET decreases during turn-off, a pulse signal controls the input of the voltage-controlled reference voltage to the voltage-controlled current source. The output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET, adjusting the overshoot peak value of the SiC MOSFET turn-off voltage. Combined with step S5, the overshoot peak value of the SiC MOSFET turn-off voltage is controlled in a closed loop.

2. The SiC MOSFET driving method for quantitative suppression of voltage overshoot spikes according to claim 1, characterized in that, The specific steps for outputting the pulse signal in step S4 are as follows: S4.1: Compare the stepped-down drain-source voltage with the first reference voltage, output a pulse signal, latch the first rising edge of the pulse signal, and output a start signal; S4.2: Input the drain-source voltage of the SiC MOSFET into the differentiating circuit to obtain the differential signal, compare the differential signal with the second reference voltage, output a pulse signal and invert it, latch the first rising edge of the signal, and output the end signal; S4.3: Perform an XOR operation between the start signal and the end signal to generate a trigger signal.

3. A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes, used to implement the SiC MOSFET driving method for quantitative suppression of voltage overshoot spikes as described in claim 1 or 2, characterized in that, It includes a voltage-controlled current source, an RC voltage divider circuit, a peak hold circuit, a stage recognition circuit, a microcontroller, and a SiC MOSFET; The output terminal of the voltage-controlled current source is connected to the gate of the SiC MOSFET. The voltage-controlled current source is connected to the microcontroller through the multiplexer S1. The drain of the SiC MOSFET is connected to the input terminal of the RC voltage divider circuit. The output terminal of the RC voltage divider circuit is connected to the peak hold circuit and the stage recognition circuit. The microcontroller is used to acquire the output of the peak hold circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input, takes the pulse signal of the stage recognition circuit as the trigger signal and outputs it to inject additional drive current into the gate of the SiCMOSFET to regulate the voltage overshoot spike.

4. The SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes according to claim 3, characterized in that, The voltage-controlled current source also includes a reference current source, a current mirror circuit, and a power supply V. CC ; One end of the reference current source is connected to the microcontroller via a multiplexer S1. The reference current source is connected to a current mirror circuit, and the input terminal of the current mirror circuit is connected to the power supply V. CC The output terminal of the current mirror circuit is connected to the gate of the SiC MOSFET.

5. A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes according to claim 3, characterized in that, The RC voltage divider circuit includes a first RC parallel module and a second RC parallel module connected at one end; The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, and the other end of the second RC parallel module is grounded. The connection point of the first RC parallel module and the second RC parallel module is connected to the peak hold circuit and the stage recognition circuit.

6. A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes according to claim 5, characterized in that, The peak hold circuit includes a transconductance operational amplifier, a charging diode, a clamping diode, a reset MOSFET, a hold capacitor, and a high-bandwidth operational amplifier. The non-inverting input of the transconductance operational amplifier is connected to the output of the RC voltage divider circuit, the inverting input of the transconductance operational amplifier is connected to the inverting input of the high-bandwidth operational amplifier, and the output of the transconductance operational amplifier is connected to the anode of the charging diode and the cathode of the clamping diode. The cathode of the charging diode, one end of the holding capacitor, and the drain of the reset MOS transistor are connected to the non-inverting input of the high-bandwidth operational amplifier. The source of the reset MOS transistor, the other end of the holding capacitor, and the anode of the clamping diode are all grounded. The output of the high-bandwidth operational amplifier is connected to the microcontroller.

7. A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes according to claim 5, characterized in that, The stage identification circuit includes a differential resistor, a differential capacitor, a first comparator, a second comparator, an inverter, a first D flip-flop, a second D flip-flop, and an XOR gate module; The non-inverting input of the first comparator is connected to the RC voltage divider circuit, the inverting input of the first comparator is connected to the first reference voltage, the output of the first comparator is connected to the CLK pin of the first D flip-flop, and the output of the first D flip-flop is connected to the first input of the XOR gate module. The differential resistor and differential capacitor are connected in series. The other end of the differential resistor is grounded, and the other end of the differential capacitor is connected to the drain of the SiC MOSFET. The connection point of the differential resistor and differential capacitor is connected to the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the second reference voltage. The output of the second comparator is connected to the input of the inverter. The output of the inverter is connected to the CLK pin of the second D flip-flop. The output of the second D flip-flop is connected to the second input of the XOR gate module. The CLR pins of the first and second D flip-flops are connected to the drive signal.

8. A SiC MOSFET driving system for quantitative suppression of voltage overshoot spikes according to claim 3, characterized in that, The microcontroller includes an ADC module, a PI control module, and a DAC module; The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak hold circuit. The PI control module is used to compare the SiC MOSFET turn-off voltage overshoot peak value with the preset upper limit value of the overshoot peak value of the PI control module. The DAC module is used to output the voltage-controlled reference voltage at the input terminal of the voltage-controlled current source.

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