Multi-level bridgeless boost power factor correction device capable of suppressing zero crossover distortion of line current

Abstract

The invention relates to a multi-level bridgeless boost power factor correction device capable of suppressing zero crossover distortion of line current. The invention provides a multi-level bridgeless boost PFC device which comprises a circuit and a control circuit, and the circuit comprises an inductor with flying capacitor totem pole configuration, two pairs of switches and a capacitor. The control circuit is configured to drive the first pair of switches and the second pair of switches in a manner that reduces line current distortion. For the first pair of switches and the second pair of switches, the control circuit is configured to drive a first switch of the first pair of switches and the second pair of switches during a complete period equal to the first half-line period and a second switch of the first pair of switches and the second pair of switches during a portion period shorter than the first half-line period in the first half-line period; and in the second half-line period, driving the first switch in a partial period shorter than the second half-line period, and driving the second switch in a complete period equal to the second half-line period.

Description

Technical Field

[0001] The present invention relates to a power factor correction (PFC) converter, and more particularly to a multi-level bridgeless totem pole boost PFC converter with a flying capacitor. Background Art

[0002] Today's data centers have an increasing demand for energy due to increased data usage. Therefore, the efficiency and power density of power supplies in data centers are becoming increasingly important.

[0003] In data centers, traditional power supplies use a two-stage topology, including a non-isolated boost PFC front stage and an isolated LLC DC / DC converter. Figure 1 As shown, the boost PFC front stage 10 can be a two-stage bridgeless totem pole CCM (continuous conduction mode) PFC with Gallium Nitride (GaN) switches, which has an efficiency of more than 99% and can meet high efficiency requirements. However, operation in CCM mode usually requires totem pole switches (e.g. Figure 1 S a and S b ) to perform hard switching. To keep the switching loss low, the switching frequency must be maintained at a low frequency, usually 65kHz. However, because the switching frequency is too low, the advantages of GaN devices in the totem pole PFC circuit cannot be fully utilized, and the PFC inductor and electromagnetic interference (EMI) filter will be larger in size.

[0004] In order to simultaneously achieve high efficiency and high power density of the boost PFC front stage, a flying-capacitor multi-level (FCML) converter for the PFC front stage has been recently proposed (e.g., TTVu and G. Young, “Implementation of multi-level bridgeless PFC rectifiers for mid-power single-phase applications,” Proc. IEEE Applied Power Electronics Conf. (APEC), 2016, pp. 1835-1841). Figure 2 In the figure, a three-level FCML bridgeless totem pole boost PFC device 20 is illustrated, wherein the switch S 1a , S 2a , S 1b and S2b For totem pole switch, C FL is the flying capacitor, switch S p and S n The switch is selected for half line cycle (also called unfolder switch). When the instantaneous line voltage is greater than half of the output voltage, the three-level FCML bridgeless totem pole boost PFC device (e.g. Figure 2 The gate drive voltage v during the positive half line cycle is shown in GS1a 、v GS2a 、v GS1b and v GS2b , Totem pole midpoint voltage v M , boost inductor current i LB and the flying capacitor voltage v CFL The typical waveform of 30 Figure 3 In addition, Figure 3 It also includes a triangular carrier signal v that determines the gate drive voltage. CAR1 and v CAR2 and control voltage v CTRL The waveform of Figure 3 It can be seen that the inner switch S 1a and S 1b Complementary, outer switch S 2a and S 2b The gate drive voltages of the inner and outer switches are complementary, and there is a 180-degree phase shift between them. Figure 3 It can also be seen that the ripple frequency of the boost inductor current is twice the switching frequency, which can reduce the size of the boost inductor and EMI filter. Figure 3 It is also shown that the average voltage on the flying capacitor is half of the output voltage, and the voltage amplitude on the totem pole switch is equal to half of the output voltage. Therefore, switches with lower rated voltages can be used, which have lower parasitic capacitances than switches with higher rated voltages, thus reducing switching losses. Finally, the efficiency of the FCML bridgeless totem pole CCM boost PFC device can be even higher than that of the corresponding two-level boost PFC device.

[0005] Figure 4 A common multi-level (eg, n-level) FCML bridgeless totem pole boost PFC device 40 is shown, wherein the switch S 1a To S (n-1)a and switch S 1b To S (n-1)b For totem pole switch, C FL1 To C FL(n-2) is the flying capacitor, switch S p and S nThe switch is selected for half the line cycle. The ripple frequency of the boost inductor current is equal to n-1 times the switching frequency. The average voltage on the flying capacitor can be expressed as V CFL1 =V O / (n-1),…,V CFL(n-2) =(n-2)V O / (n-1). Therefore, the voltage amplitude on the totem pole switch is equal to 1 / (n-1) of the output voltage. The so-called multi-level here is n-level, where n is an integer greater than or equal to 3. The multi-level FCML bridgeless totem pole boost PFC device includes at least two upper switches (for example, located at the input node of the totem pole, where the input node can be Figure 4 Connected to the inductor L B After and at switch S 1a and S 1b ) and two lower switches, or may be referred to as comprising at least two pairs of totem pole switches. For example, in a three-level configuration (e.g., n=3), there are at least two pairs of totem pole switches (e.g., switches S 1a and S 1b The first pair is formed by switch S 2a and S 2b As described above, a multi-level configuration has certain advantages over a non-multi-level (eg, two-level) configuration, such as a higher ripple frequency and the ability to use switches with lower voltage ratings.

[0006] Currently, a variety of technologies have been developed to achieve control of boost PFC devices. Typically, a feedback control loop is used to regulate the boost PFC device and achieve the control target. Specifically, the output of the boost PFC device is sensed and compared with a reference value, and the error is then passed to the control circuit, which generates a duty cycle command to the pulse width modulator, which generates a switch control signal accordingly. In the totem pole configuration, the drive signals of each pair of switches are complementary. Figure 2 For example, in the positive half line cycle, switch S 1a As a boost switch (duty cycle D) controlled by a duty cycle command from a control loop, the switch S 1b The boost switch and the synchronous rectifier are used as fast synchronous rectifiers with a duty cycle of 1-D. In the negative half-line cycle, the switches (and their corresponding duty cycles) acting as boost switches and synchronous rectifiers are swapped. Although there have been advances in improving power factor and reducing zero-crossing distortion, zero-crossing distortion still exists in multi-level boost PFC devices in some cases. Therefore, there is still a need for improved control of such devices. Summary of the invention

[0007] In one embodiment of the present case, a multi-level bridgeless boost PFC device includes a circuit and a control circuit, wherein the circuit includes an inductor having a flying capacitor totem pole configuration, at least a first pair of switches and a second pair of switches, and a capacitor. The control circuit is configured to drive the first pair of switches and the second pair of switches in a manner that reduces line current distortion. For the first pair of switches and the second pair of switches, the control circuit is configured to: in a first half-line cycle, drive the first switch of the first pair of switches and the second pair of switches during a full period equal to the first half-line cycle, and drive the second switch of the first pair of switches and the second pair of switches during a partial period shorter than the first half-line cycle; and in a second half-line cycle, drive the first switch of the first pair of switches and the second pair of switches during a partial period shorter than the second half-line cycle, and drive the second switch of the first pair of switches and the second pair of switches during a full period equal to the second half-line cycle.

[0008] In one embodiment of the present case, a multi-level bridgeless boost PFC device includes a circuit and a control circuit. The circuit includes an inductor, at least a first pair of switches and a second pair of switches, a capacitor, and a plurality of slow bridge arm synchronous rectification switches, wherein the inductor, the first pair of switches, the second pair of switches, and the capacitor have a flying capacitor totem pole configuration. Each of the first pair of switches and the second pair of switches includes a fast bridge arm boost switch and a fast bridge arm synchronous rectification switch. The control circuit is configured to disable the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch, and the plurality of slow bridge arm synchronous rectification switches near the zero crossing point of the line voltage.

[0009] In one embodiment of the present invention, a multi-level bridgeless boost PFC device includes a circuit and a control circuit. The circuit includes an inductor having a flying capacitor totem pole configuration, at least a first pair of switches and a second pair of switches, and a capacitor. The control circuit includes a feedforward control element, wherein the feedforward control element is configured to provide pre-calculated values ​​of duty cycles of a continuous conduction mode and two different discontinuous conduction modes to control the first pair of switches and the second pair of switches.

[0010] Various aspects of the present invention will be further described in the embodiments shown below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention can be better understood by referring to the following schematic diagrams. The components in the schematic diagrams are not and need not be drawn to scale. The focus is on clearly illustrating the principles of the present invention. In addition, in each schematic diagram, similar numbers represent corresponding parts.

[0012] Figure 1 The schematic diagram of the circuit structure of a two-level bridgeless totem pole boost PFC converter is shown in FIG.

[0013] Figure 2 The circuit structure diagram of a three-level FCML bridgeless totem pole boost PFC converter is shown in FIG.

[0014] Figure 3 Show Figure 2 Key voltage and current waveforms of a three-level FCML bridgeless totem-pole boost PFC converter.

[0015] Figure 4 The circuit structure diagram of an n-level FCML bridgeless totem pole boost PFC converter is shown in FIG.

[0016] Figure 5 Schematic diagram of the architecture of a three-level FCML bridgeless totem pole boost PFC device in one embodiment of the present case, wherein the control circuit adopts average current control.

[0017] Fig. 6A Key waveforms showing the operation of a three-level FCML bridgeless totem-pole boost PFC device at 50% load and without duty cycle limitation.

[0018] Figure 6B Middle Pair Fig. 6A The waveform near the zero crossing point of the line voltage is enlarged.

[0019] Fig. 7A Key waveforms showing the operation of a three-level FCML bridgeless totem-pole boost PFC device at 50% load and duty cycle limited.

[0020] Figure 7B Middle Pair Fig. 7A The waveform near the zero crossing point of the line voltage is enlarged.

[0021] Fig. 8A Schematic diagram of key waveforms of a three-level FCML bridgeless totem pole boost PFC device operating at 50% load in an embodiment of the present invention.

[0022] Figure 8B Middle Pair Fig. 8A The waveform near the zero crossing point of the line voltage is enlarged.

[0023] Fig.9A FIG. 1 is a schematic diagram of key waveforms of a three-level FCML bridgeless totem pole boost PFC device operating at 50% load in another embodiment of the present invention.

[0024] Fig. 9B Middle Pair Fig.9A The waveform near the zero crossing point of the line voltage is enlarged.

[0025] Fig. 9C FIG. 1 is a schematic diagram of key waveforms of a three-level FCML bridgeless totem pole boost PFC device operating at 50% load in another embodiment of the present invention.

[0026] Fig.10Schematic diagram of the architecture of a three-level FCML bridgeless totem pole boost PFC device in one embodiment of the present case, wherein the control circuit adopts average current control and blocking control, wherein the blocking control blocks all switches near the zero crossing point of the line voltage.

[0027] Fig.11 Schematic diagram of key waveforms of a three-level FCML bridgeless totem-pole boost PFC device operating at 10% load.

[0028] Fig.12 Schematic diagram of the architecture of a three-level FCML bridgeless totem pole boost PFC device in one embodiment of the present case, wherein the control circuit adopts average current control and mixed duty cycle feedforward control.

[0029] Fig.13A , Fig. 13B , Fig. 13C The feedforward duty cycle D in another embodiment of the present invention is shown as follows: FF,CCM , D FF,DCM1 and D FF,DCM2 Changes at 10% load, 5% load and 2.5% load.

[0030] Fig.14A Schematic diagram of key waveforms of a three-level FCML bridgeless totem-pole boost PFC device operating at 10% load.

[0031] Fig. 14B Middle Pair Fig.14A The waveform near the zero crossing point of the line voltage is enlarged.

[0032] Fig.15A Schematic diagram of key waveforms of a three-level FCML bridgeless totem-pole boost PFC device operating at 5% load.

[0033] Fig. 15B Middle Pair Fig.15A The waveform near the zero crossing point of the line voltage is enlarged.

[0034] Fig.16A Schematic diagram of the key waveforms of a three-level FCML bridgeless totem-pole boost PFC device operating at 2.5% load.

[0035] Fig. 16B Middle Pair Fig.16A The waveform near the zero crossing point of the line voltage is enlarged.

[0036] Fig. 16C Middle Pair Fig.16A The waveform near the positive peak of the line voltage is amplified.

[0037] Fig.171 is a flow chart of a control method for a three-level FCML bridgeless totem pole boost PFC device in one embodiment of the present invention.

[0038] Fig.18 FIG. 4 is a flow chart of a control method for a three-level FCML bridgeless totem pole boost PFC device in another embodiment of the present invention.

[0039] Fig.19 FIG. 4 is a flow chart of a control method for a three-level FCML bridgeless totem pole boost PFC device in another embodiment of the present invention.

[0040] Explanation of symbols

[0041] 10: Boost PFC pre-stage

[0042] C O :capacitance

[0043] V O :Voltage

[0044] 20: Three-level FCML bridgeless totem pole boost PFC device

[0045] S 1a , S 2a , S ka , S (n-1)a , S 1b , S 2b , S kb , S (n-1)b :switch

[0046] C FL , C FL(k-1) , C FLk , C FL(n-2) :Flying capacitor

[0047] S p , S n , S a , S b :switch

[0048] 30: Waveform

[0049] v GS1a 、v GS2a 、v GS1b 、v GS2b : Gate drive voltage

[0050] v M : Totem pole midpoint voltage

[0051] v CFL : Flying capacitor voltage

[0052] v CAR1 、vCAR2 : Triangular carrier signal

[0053] v CTRL : Control voltage

[0054] 40: FCML bridgeless totem pole boost PFC device

[0055] L B :inductance

[0056] 50: FCML bridgeless totem pole boost PFC device

[0057] 51: Inductor

[0058] 52: FCML bridgeless totem pole boost PFC circuit

[0059] 53a, 53b, 55a, 55b, 57a, 57b: switch

[0060] 54: Control circuit

[0061] 56: Control elements

[0062] 58: Input

[0063] 59: Flying capacitor

[0064] V car1 、V car2 : Carrier

[0065] V AC :Voltage

[0066] V AC,Filt , 60, 70, 80: Line voltage after filtering

[0067] i- Line , 61, 71, 83: Line current

[0068] i- LB , 62, 72, 84: boost inductor current

[0069] V OUT , 63, 73, 85: Output voltage

[0070] V CFL , 64, 74, 86: Flying capacitor voltage

[0071] V in,Boost , 65, 75, 87: Boost input voltage

[0072] 76: Current out of control

[0073] T SW : Switching cycle

[0074] 81, 82: Gate drive pulse

[0075] 88a, 88b: Period

[0076] 90: Filtered line voltage

[0077] 91: Blocking Pulse

[0078] 92: Line current

[0079] 93, 93a: Boost inductor current

[0080] 94: Output voltage

[0081] 95: Flying capacitor voltage

[0082] 96, 96a: Boost input voltage

[0083] 97: Zero level period

[0084] 101a, 101b, 101c, 101d, 101e, 101f: Gate drive pulses

[0085] V GSn 、V GSp 、V GS2b 、V GS1b 、V GS1a 、V GS2a : Gate drive pulse

[0086] 98: Boost soft start pulse

[0087] 56a: Lockout control and boost soft start element

[0088] 110: Filtered line voltage

[0089] 111: Line current

[0090] 112: Boost inductor current

[0091] 113: Output voltage

[0092] 114: Flying capacitor voltage

[0093] 115: Boost input voltage

[0094] 1202: Duty cycle feedforward control element

[0095] 56b: Lock control element

[0096] 140, 150, 160: Line voltage

[0097] 141a, D FF,CCM , 151a, 161a: CCM feedforward duty cycle

[0098] 141b, D FF,Mixed , 151b, 161b: MCM feedforward duty cycle

[0099] 142, 152, 162: Line current

[0100] 143, 153, 163: Boost inductor current

[0101] 144, 154, 164: Output voltage

[0102] 145, 155, 165: Flying capacitor voltage

[0103] 146, 156, 166: Boost input voltage

[0104] 170, 180, 190: Control methods

[0105] 172, 174, 182, 184, 192, 194: Steps DETAILED DESCRIPTION

[0106] The present invention discloses some embodiments of a flying capacitor multi-level (FCML) bridgeless totem pole boost PFC converter. For example, the FCML bridgeless totem pole boost PFC converter can reduce line current distortion near the zero crossing point of the line voltage. In one embodiment, the control circuit of the converter reduces line current distortion by prohibiting the totem pole synchronous rectifier from turning on near the zero crossing point of the line voltage. In some embodiments, the control circuit of the converter reduces line current distortion by prohibiting the unfolding synchronous rectifier, the totem pole boost switch and the synchronous rectifier from turning on near the zero crossing point of the line voltage. In some embodiments, the control circuit of the converter reduces line current distortion by adopting a feed-forward duty cycle control of a mixed conduction mode (e.g., a mixture of continuous conduction mode (CCM) and discontinuous conduction mode (DCM)), especially under light load conditions.

[0107] After briefly summarizing certain features of the FCML bridgeless totem pole boost PFC converter of the present case, the FCML bridgeless totem pole boost PFC converter shown in the schematic diagram will be described in detail. Although the FCML bridgeless totem pole boost PFC converter will be described according to the schematic diagram (with particular emphasis on the three-level configuration), the present case is not limited to the illustrated embodiment. For example, the illustrated embodiment can also be applied to a multi-level or n-level configuration, where n is greater than three. In addition, although the specific details of one or more embodiments are described, these specific details are not necessary parts of each embodiment, and not all advantages are achieved by a single embodiment. It should be understood that the present case can have various changes in different implementations without departing from the scope of the present case, and the description and drawings therein are essentially used for illustrative purposes rather than for limiting the present case.

[0108] Figure 5 FIG. 1 is a schematic diagram of a multi-level (e.g., three-level) FCML bridgeless totem pole boost PFC device 50 in one embodiment of the present invention. The FCML bridgeless totem pole boost PFC device 50 includes a three-level FCML bridgeless totem pole boost PFC circuit 52 and a control circuit 54. Figure 3 In the illustrated embodiment, the FCML bridgeless totem pole boost PFC circuit 52 includes an inductor 51, a first pair of switches (eg, inner switches 53a and 53b, i.e., switches S 1a and S 1b ), a second pair of switches (e.g., outer switches 55a and 55b, i.e., switches S 2a and S 2b ) and a flying capacitor 59, wherein the flying capacitor 59 is located between the first pair of switches and the second pair of switches. The first pair of switches and the second pair of switches are arranged in a totem pole configuration, and when coupled to the flying capacitor 59, can together form a flying capacitor totem pole configuration. The FCML bridgeless totem pole boost PFC circuit 52 further includes a half-line cycle selection switch (e.g., switches 57a and 57b, i.e., switches S p and S n). The FCML bridgeless totem pole boost PFC device 50 operates in part based on average current mode control and duty cycle feed-forward control. Generally speaking, in average current mode control, a current controller is used in the feedback control loop, and the line current leads the line voltage. However, since the line current leads the line voltage, the power factor may not be 1 and zero crossing distortion of the line current may be caused. Duty cycle feed-forward control attempts to overcome the aforementioned shortcomings by using a duty cycle value determined outside the loop (i.e., outside the feedback control loop) (for example, based on the rectified line voltage and the output voltage of the boost PFC device), where the duty cycle value determined outside the loop is also referred to as a pre-calculated duty cycle value. In terms of efficiency, duty cycle feed-forward control reduces the burden of the feedback control loop to perform this task. In addition, the pre-calculated duty cycle value is combined with the value of the current control loop to control the switch in the FCML bridgeless totem pole boost PFC circuit 52. For example, the pre-calculated duty cycle value from the duty cycle feed-forward control is combined with the output of the current controller to generate a PWM waveform for controlling the switches in the FCML bridgeless totem pole boost PFC circuit 52. It should be noted that unlike the two-level boost PFC circuit using a single carrier, the three-level FCML bridgeless totem pole boost PFC circuit 52 uses two carriers V car1 and V car2 In general, a multi-level topology uses multiple phase-shifted carriers, or one less carrier than the number of levels. In this example, n is equal to three (i.e., three levels), so two carriers are used. In some embodiments, the input of the control circuit 54 includes the rectified voltage V AC , rectified current I LB and voltage V OUT .

[0109] For operation in CCM, the duty cycle feed-forward control pre-calculates the CCM duty cycle of the boost switch according to the following equation (1):

[0110]

[0111] In equation (1), |v IN | is the line voltage after rectification, V O is the output voltage of the PFC converter. In some embodiments, the duty cycle feed-forward control may include an additional input 58, Figure 5 Input 58 is shown as a dotted line connecting the low-pass filter and the duty cycle feedforward module, and will be further described later. Figure 5 As can be seen from the above, the pre-calculated duty cycle is added to the output of the current controller. Therefore, in steady-state operation, the duty cycle of the boost switch is mainly determined by the pre-calculated duty cycle D FF,CCMThe influence of the current controller on the duty cycle of the boost switch is significantly reduced, so the phase offset between the line voltage and the line current under duty cycle feedforward control is significantly smaller than the phase offset when duty cycle feedforward control is not adopted. In this way, the power factor can be improved and the zero crossing distortion of the line current can be reduced. For more information about duty cycle feedforward control under CCM operation, refer to DMVD Sype, KD Gusseme, APVD Bossche, and JAMelkebeek, entitled "Duty-ratio feedforward for digitally controlled boost PFC converters," Proc. IEEE Applied Power Electronics Conf. (APEC), 2003, pp. 396-402.

[0112] In some embodiments, the control circuit 54 further includes a control element 56 to provide additional functionality to the duty cycle feed-forward module. Figure 5 The control circuit 54 (and Fig.10 and Fig.12 The control circuit 54 shown in FIG. 5 includes exemplary functional blocks, but in practice, multiple components shown individually in the figure may be combined in practice, or a single component may also include multiple independent components in practice. Before describing the control component 56, it is first necessary to understand the problem caused by the duty cycle limitation that affects the performance of the existing bridgeless totem pole boost PFC device. It can be seen from the above equation (1) that at the zero crossing point of the line voltage (v IN =0), the duty cycle of the boost switch is equal to 1. However, due to the limitation of the actual duty cycle (for example, the actual duty cycle is less than 100% due to delay or voltage drop in the circuit, etc.), the line current of the existing bridgeless totem pole boost PFC device will have a peak at the zero crossing point of the line voltage. In fact, since the synchronous rectifier (SR) switch in the totem pole bridge arm allows the boost inductor current to flow in both directions, there will be a current runaway phenomenon near the zero crossing point of the line voltage.

[0113] The invention of this case can reduce the zero-crossing distortion of line current under different load levels. Figure 5 5. The FCML bridgeless totem pole boost PFC circuit 52 shown in FIG. 5 is used to illustrate the circuit topology of the present invention. It should be noted that the circuit topology of the present invention is not limited to the various transistor types mentioned below and illustrated in the figure. For example, the transistor may include MOSFET (such as silicon carbide MOSFET) or GaN, etc., which are all within the scope of the embodiments shown in the present invention. In addition, although some embodiments of the present invention are based on Figure 5The three-level FCML bridgeless totem pole boost PFC device 50 (and Fig.10 and Fig.12 However, for those skilled in the art, the description of the illustrated embodiment can be easily extended to other FCML bridgeless totem pole boost PFC devices with multiple levels (for example, the number of levels is greater than three), so they should all be included in the scope of this case.

[0114] Fig. 6A and Figure 6B Figure 2 shows the key voltage and current waveforms of the flying capacitor three-level bridgeless totem pole boost PFC device operating without duty cycle limitation. Fig. 7A and Figure 7B The key voltage and current waveforms of the flying capacitor three-level bridgeless totem pole boost PFC device operating under duty cycle limitation are shown. It should be noted that the waveforms shown in the figure are all simulated waveforms. Fig. 6A and Figure 6B In FIG. 1 , the waveforms shown are, from top to bottom, the line voltage 60 after EMI filter filtering, the line current 61, the boost inductor current 62 (the ripple in the boost inductor current is indicated by alternating wide and narrow lines in the figure), the output voltage 63, the flying capacitor voltage 64, and the boost input voltage 65. The waveforms shown are the voltage and current waveforms obtained by a 2.5kW boost PFC converter under the conditions of a line voltage of 220-Vrms / 50-Hz, an output voltage of 385-V, and a load of 50%. Similarly, in FIG. Fig. 7A and Figure 7B , the waveforms shown are, from top to bottom, the line voltage 70, line current 71, boost inductor current 72, output voltage 73, flying capacitor voltage 74, and boost input voltage 75 after filtering by the EMI filter, and the waveforms shown are voltage and current waveforms obtained when the line voltage of a 2.5kW boost PFC converter is 220-Vrms / 50-Hz, the output voltage is 385-V, and the load is 50%. It should be noted that the waveforms shown are waveforms of a three-level FCML bridgeless totem pole boost PFC circuit. For example, by observing the boost inductor current waveform 62, it can be clearly seen that it is different from the waveform of a two-level PFC circuit. For example, in a three-level bridgeless totem pole boost PFC circuit, there are four time points in each half cycle where the ripple is zero (i.e., two zero crossing points of the line voltage and two time points when the line voltage is equal to half of the output voltage), which is obviously different from the two-level boost PFC circuit where the ripple is zero only at the two zero crossing points of the line voltage. As Fig. 7A As shown, when operating under duty cycle limitation, the line current is significantly distorted near the zero crossing point of the line voltage (e.g. Fig. 7A The distortion rate is 5.2%, while Fig. 6A The distortion rate in is 0.43%). Figure 6B and Figure 7B In Fig. 6A and Fig. 7A The waveform of the neutral line voltage near the zero crossing point from the negative half line cycle to the positive half line cycle is amplified. Figure 7B As shown, the boost inductor current 72 has an obvious current runaway 76 phenomenon near the zero crossing point of the line voltage 70. In fact, near the zero crossing point of the line voltage, the boost inductor current is (1-D)T SW During the period (i.e. during the period when the synchronous rectifier conducts current), the slope changes greatly, where T SW is the switching period. Due to the duty cycle limitation, (1-D)T SW As the duration of the period increases, the variation in the boost inductor current also increases (for example, to account for the current through the synchronous rectifier that can change direction). The increased variation in the boost inductor current will result in current runaway during several consecutive CCM switching cycles.

[0115] According to an embodiment of the present invention, near the zero crossing point of the line voltage, in order to eliminate the line current peak caused by the duty cycle limitation, the gate drive pulse of the totem pole SR switch can be blocked (e.g., disabled), thereby stopping the operation of the boost inductor in CCM (e.g., changing the operation of the boost inductor from CCM to DCM). In one embodiment, the control element 56 (e.g., Figure 5 As shown in the figure, the gate drive pulse is blocked. For example, when the zero crossing of the line voltage is sensed (for example, by using a voltage comparator or any existing method), the control element 56 can output a blocking pulse, so that the blocking pulse is multiplied with the gate drive pulse (for example, the two pulses are input into an AND gate). When the blocking pulse is zero, the output of the AND gate is zero, thereby disabling the gate drive pulse and forming a corresponding blocking period. Under light load conditions (for example, less than 10% of full load), the totem pole SR switch is disabled throughout the entire half line cycle. For example, as the load decreases, the blocking period gradually increases until it covers the entire half line cycle. Fig. 8A and Figure 8B A flying capacitor three-level bridgeless totem pole boost PFC device (eg Figure 5 The key voltage and current waveforms of the FCML bridgeless totem pole boost PFC device 50 shown in FIG. 5 when the gate drive pulse of the totem pole SR switch is blocked near the zero crossing point of the line voltage. Fig. 8A and Figure 8B The waveforms shown from top to bottom are the line voltage 80 after being filtered by the EMI filter, the inner switch S 1a He He S 1b81 and 82 (each individual pulse in the gate drive pulse is omitted in the figure, and the whole is represented by a dark block), line current 83, boost inductor current 84, output voltage 85, flying capacitor voltage 86 and boost input voltage 87, and the waveforms shown are the voltage and current waveforms obtained under the conditions of a 2.5kW boost PFC converter with a line voltage of 220-Vrms / 50-Hz, an output voltage of 385-V and a load of 50%.

[0116] There are several points worth noting about the waveforms of the gate drive pulses 81 and 82. For simplicity, the focus is on the positive half-line cycle (which is similar in principle to the negative half-line cycle). In this example, the switch (e.g. Figure 5 Switch S in 1a ) covers the entire half line cycle (positive half line cycle) (e.g., from 60ms to 70ms). In other words, the switch S 1a is driven during the entire positive half-line cycle. In contrast, switches acting as synchronous rectifiers (e.g. Figure 5 Switch S in 1b ) The gate drive pulse 82 in the positive half-line cycle occupies less than the entire positive half-line cycle period. In other words, the gate drive pulse 82 is blocked during a period 88a close to the zero crossing point (e.g., after the zero crossing point), and is blocked during another period 88b close to the zero crossing point (e.g., before the zero crossing point), that is, the two blocked periods are located on different sides of the zero crossing point (e.g., period 88a is after the zero crossing point, and period 88b is before the zero crossing point). Disabling the synchronous rectifier prevents the current direction from changing, thereby avoiding current runaway. Similarly, in the second half-line cycle (i.e., the negative half-line cycle), the switches serving as the boost switch and the synchronous rectifier are swapped, and at this time the switch S 1a Operates as a synchronous rectifier, while the switch S 1b It operates as a boost switch. Fig. 8A As shown, the gate drive pulse 81 drives the switch S 1a The time of the gate drive pulse 82 driving the switch S is less than the entire half line cycle (negative half line cycle) period (due to blocking the gate drive pulse 81 at the zero crossing points near the beginning and end of the half line cycle). 1b The time is the entire negative half line cycle. Fig. 8A As shown, the blockade period is repeated alternately. Fig. 7A and Figure 7B The waveform shown in Fig. 8A The waveform of line current 83 has no current peak at the zero crossing point of line voltage, and its distortion rate at the zero crossing point is 0.46%, which is significantly lower than Fig. 7A The waveform shown in is distorted. Figure 8B In, yes Fig. 8A The waveforms of the line current 83, the boost inductor current 84, the output voltage 85, the flying capacitor voltage 86 and the boost input voltage 87 near the zero crossing point of the line voltage from the negative half-line cycle to the positive half-line cycle are amplified. Figure 8B As shown, due to the aforementioned blocking operation, the boost inductor current can smoothly transition from a negative value to a positive value at the zero crossing point of the line voltage.

[0117] In another embodiment of the present invention, near the zero crossing point of the line voltage, in order to eliminate the line current peak caused by the duty cycle limitation, all switches (eg Figure 5 The gate drive pulses of all six switches in the embodiment of the present invention can be realized by blocking the gate drive pulses of the fast bridge arm switch and the slow bridge arm switch, thereby making the boost inductor current zero during the blocking period. In one embodiment, similar to the above, the control element 56 (such as Figure 5 As shown) a blocking pulse is used to block the gate drive pulse. Fig.9A , Fig. 9B and Fig. 9C A flying capacitor three-level bridgeless totem pole boost PFC device (eg Figure 5 The key voltage and current waveforms of the FCML bridgeless totem pole boost PFC device 50 shown in FIG. 5 when the gate drive pulses of all switches are blocked near the zero crossing point of the line voltage. Fig.9A and Fig. 9B In FIG. 1 , the waveforms shown are, from top to bottom, the line voltage 90 after filtering by the EMI filter, the blocking pulse 91 (please note that the blocking occurs at the zero level of the blocking pulse), the line current 92, the boost inductor current 93, the output voltage 94, the flying capacitor voltage 95, and the boost input voltage 96. The waveforms shown are the voltage and current waveforms obtained by a 2.5kW boost PFC converter under the conditions of a line voltage of 220-Vrms / 50-Hz, an output voltage of 385-V, and a load of 50%. Fig. 9B As shown, in one embodiment, the zero level period 97 of the blocking pulse 91 spans or extends to both sides of the zero crossing point of the line voltage (including the zero crossing point), which is different from the blocking period only located before or after the zero crossing point in the previous embodiment. Fig. 9B The zero-level period 97 illustrated in the figure is depicted as lasting 102 microseconds. It should be noted that this value is only an application example and can actually be adjusted as needed. In one embodiment, the width or duration of the zero-level period 97 can be adjusted based on the required voltage range when the sensing line voltage crosses the zero point, such as by using a comparator logic unit. For example, a narrower zero-level period can be set based on a narrower comparison range, and a wider zero-level period can be set based on a wider comparison range. In some embodiments, different switches can use different zero-level periods, which will be explained later. Fig.9AAs shown, the line current 92 has no current peak at the zero crossing point of the line voltage, and the distortion rate is extremely low (for example Fig.9A 0.6% as shown). Fig. 9B In, yes Fig.9A The waveform near the zero crossing point of the neutral voltage is amplified. Fig. 9B As shown, due to the aforementioned blocking operation, the boost inductor current is zero during the blocking period near the zero crossing point of the line voltage (including at the zero crossing point and before and after the zero crossing point).

[0118] although Fig.9A and Fig. 9B The blocking period shown is the same for all fast bridge arm switches and slow bridge arm switches, but in some embodiments, a more flexible blocking method can be used to further improve performance. According to another embodiment of the present invention, for the slow bridge arm SR switch (e.g. Figure 5 Switch S in n and S p ), the fast bridge arm boost switch and the fast bridge arm SR switch have different blocking periods. Fig. 9C The waveforms shown from top to bottom are the line voltage 90 after being filtered by the EMI filter, the switch S n , S p , S 2b , S 1b , S 1a and S 2a (For example, using Figure 5 101a, 101b, 101c, 101d, 101e and 101f, boost inductor current 93a, output voltage 94, flying capacitor voltage 95 and boost input voltage 96a of the FCML bridgeless totem pole boost PFC circuit 52, and the waveforms shown are voltage and current waveforms obtained under the conditions of a 2.5kW boost PFC converter with a line voltage of 220-Vrms / 50-Hz, an output voltage of 385-V and a load of 50%. Roughly, at Fig. 9C In the example, the blocking period of the fast bridge arm boost switch is slightly narrower than the blocking period of the slow bridge arm SR switch, and the blocking period of the fast bridge arm SR switch is slightly wider than the blocking period of the slow bridge arm SR switch. For example, after the line voltage crosses the zero point, the switch S 1a and S 2a The switch S is the fast bridge arm boost switch. p The slow bridge arm SR switch, switch S 1b and S 2b It is a fast bridge arm SR switch. It should be noted that different lockout periods with different relative widths may be used in different embodiments, and different lockout periods may be used in different types of switches in various combinations. Fig. 9CDifferent blocking periods of the slow bridge arm SR switch, the fast bridge arm boost switch and the fast bridge arm SR switch are illustrated. Figure 5 Switch S in n ) of the gate drive pulse 101a (i.e., V GSn ) has a blocking period starting near (e.g., before) the time mark 79.96, wherein the blocking period starts before the zero crossing of the line voltage 90 (approximately at the time mark 80.00) and extends beyond the zero crossing (i.e., to the right of the zero crossing). The slow bridge arm SR switch (e.g., switch S p ) of the gate drive pulse 101b (i.e., V GSp ) also spans both sides of the zero crossing and ends near the time mark 80.07 (e.g., after the time mark). Gate drive pulses 101c and 101d are respectively Figure 5 The two switches on the totem pole (i.e. switch S 2b and S 1b ) of the gate drive pulse (i.e. V GS2b and V GS1b ), where in the negative half line cycle (i.e., on the left side of the zero crossing), the two totem pole switches act as fast bridge arm boost switches, and in the positive half line cycle (i.e., on the right side of the zero crossing), the two totem pole switches act as fast bridge arm SR switches. Among all the switches, gate drive pulses 101c and 101d have the longest blocking period, and their blocking periods also span both sides of the zero crossing. It should be noted that the gate drive pulse V GS2b and V GS1b There is a phase shift between them. The gate drive pulses 101e and 101f are Figure 5 The two switches under the totem pole (i.e. switch S 1a and S 1a ) of the gate drive pulse (i.e. V GS1a and V GS2a ), where in the negative half line cycle (i.e., on the left side of the zero crossing), the two totem pole switches act as fast bridge arm SR switches, and in the positive half line cycle (i.e., on the right side of the zero crossing), the two totem pole switches act as fast bridge arm boost switches. Among all the switches, the gate drive pulses 101e and 101f have the shortest blocking period, and their blocking periods also span both sides of the zero crossing. It should be noted that in the two-level configuration, there is no Figure 5 Switch S located outside 2a and S 2b, so the gate drive pulses 101f and 101c do not exist. Furthermore, one of the functions of the different blocking periods in each switch is to eliminate the current spikes near the zero crossing point and keep the inductor current at zero during the blocking period. As described above, in some embodiments, all switches have the same blocking period, while in other embodiments, different blocking periods may be used for different types of switches (such as fast bridge arm switches, slow bridge arm switches, and boost switches). Generally speaking, the switch plays different roles (such as boost switch, fast bridge arm SR switch, or slow bridge arm SR switch) depending on whether the current interval is on different sides of the zero crossing point (i.e., different half-line cycles), and the blocking periods before and after the zero crossing point are not the same. It should be noted that the aforementioned examples are for illustration only, and in fact any appropriate combination of blocking periods may be used. For example, in Fig. 9C In the circuit, before the line voltage crosses zero, the slow bridge arm SR switch (switch S n ) and the fast bridge arm boost switch (switch S 1b and S 2b ).

[0119] Fig. 9C Also shown is the use of a boost soft start pulse 98. Fig. 9B , in the waveform of the slow bridge arm midpoint voltage (corresponding to the boost input voltage 96), it changes accordingly during the duration of the zero level period 97, and then changes sharply (dv / dt is large) at the end of the blocking period or at the start of the boost gate drive pulse. Since a large dv / dt may cause electromagnetic interference, a boost soft start pulse 98 is used in some embodiments to achieve controllable dv / dt. Specifically, the drop of the slow bridge arm midpoint voltage (boost input voltage 96a) is controlled by a short boost soft start pulse 98 to reduce dv / dt (for example, to about 11 volts / microseconds, and dv / dt should generally not exceed 20 volts / microseconds), thereby improving EMI. The boost soft start pulse 98 is applied after the blocking interval of the fast bridge arm boost switch ends, and is generated by open-loop control (for example, by a pulse generator instead of using a closed-loop gate drive pulse). By using open-loop control, the boost soft-start pulse can be flexibly configured to achieve better performance as required, such as by changing the number of pulses, frequency, and pulse width. Fig. 9CIn the example of , the width of the boost soft start pulse gradually becomes wider, but its frequency is higher than that of the general boost pulse. In some embodiments, the width of the boost soft start pulse can also remain unchanged during the entire soft start period. It should be noted that the boost soft start pulse 98 is the same for both the inner and outer boost switches (e.g., has the same frequency, voltage and pulse width), and has no phase offset (i.e., synchronous control), which is different from the gate drive pulses with phase offset in the aforementioned inner and outer switches. The phase offset between the gate drive pulses is intended to increase (e.g., double) the ripple frequency, thereby reducing the size of the inductor. On the other hand, one of the goals of the boost soft start pulse 98 is to reduce the boost inductor current i LB One mechanism to achieve this goal is to reduce the width of the first boost soft start pulse (such as Fig. 9C The boost inductor current i is shown as LB ), even though the width of each soft start pulse may remain constant as described above. Another and / or additional mechanism to achieve this goal is to increase the frequency of the boost soft start pulse 98 (e.g., to have a frequency much higher than the gate drive pulse), so that the soft start pulse can be narrower and thus limit the boost inductor current i LB The peak value (such as Fig. 9C As shown, the boost inductor current i LB The peak value gradually decreases).

[0120] It should be noted that during the boost soft-start period, no current flows through the flying capacitor. Figure 5 As shown, the switch S as a boost switch 1a and S 2a (or by switch S 1b and S 2b As the boost switches) are turned on simultaneously and thus provide a short circuit configuration, the current naturally flows through these switches instead of being bypassed via the flying capacitor. Therefore, during the boost soft start period, the voltage of the flying capacitor does not change and the closed loop boost pulse is disabled. At the end of the boost soft start period, the slow bridge arm SR switch is turned on, and then the fast bridge arm SR switch is enabled after a short delay. As mentioned above, Fig. 9C The waveform of the line voltage at the zero-crossing point from the negative half-line cycle to the positive half-line cycle is shown in FIG. The waveform of the line voltage at the zero-crossing point from the positive half-line cycle to the negative half-line cycle is shown in FIG. Fig. 9C The waveforms shown in are similar to those shown in 1b and S 2b ), while the fast bridge arm SR switch is a totem pole down switch (i.e. switch S 1a and S 2a ). In addition, the slow bridge arm SR switch is switch S n , the midpoint voltage of the slow bridge arm (i.e. the boost input voltage Vin,Boost ) increases as the dv / dt slope decreases, where the dv / dt slope is controlled by the boost soft-start pulse.

[0121] Fig.10 The FCML bridgeless totem pole boost PFC device 50 of an embodiment of the present invention is shown, wherein Figure 5 Similar components are marked with the same reference numerals and will not be described again. Fig.10 The FCML bridgeless totem pole boost PFC device 50 in the embodiment includes a three-level FCML bridgeless totem pole boost PFC circuit 52 and a control circuit 54, wherein the control element 56 includes a blocking control and a boost soft start function, and is hereinafter referred to as a blocking control and a boost soft start element 56a. It should be noted that the additional input 58 indicated by the dotted line is optional. The blocking control and the boost soft start function have been supplemented by Fig.9A , Fig. 9B and Fig. 9C Explanation, so no more elaboration here.

[0122] As the load decreases, the boost inductor will operate in DCM for a wider period near the zero crossing of the line voltage, and Fig.11 As shown in Figure 1, the CCM duty cycle feed-forward control based on equation (1) may cause additional line current distortion. Fig.11 In FIG. 1 , the waveforms shown are respectively the line voltage 110 after filtering by the EMI filter, the line current 111, the boost inductor current 112, the output voltage 113, the flying capacitor voltage 114 and the boost input voltage 115 from top to bottom, and the waveforms shown are the voltage and current waveforms obtained by the 2.5kW flying capacitor three-level bridgeless totem pole boost PFC converter under the conditions of 220-Vrms / 50-Hz line voltage, 385-V output voltage and 10% load. Fig.11 As shown in FIG. 1 , the boost inductor operates in DCM during a wider period near the line voltage zero crossing point (the current will reach zero in DCM, but cannot reach zero in CCM), which increases the instantaneous absolute value of the line current during the period when the boost inductor current operates in DCM, and thus causes an increase in the distortion of the line current (e.g., 9.76% distortion rate). In addition, as the load decreases, operation in DCM becomes more common, and when it mainly operates in DCM, using CCM duty cycle feed-forward control will result in increased distortion.

[0123] According to another embodiment of the present invention, in order to make the boost inductor operate properly in DCM, the CCM duty cycle feedforward control based on equation (1) is replaced by the DCM duty cycle feedforward control based on equations (2) and (3).

[0124]

[0125] In equations (2) and (3), L B represents the boost inductor, f SW represents the switching frequency, |v IN | represents the rectified line voltage, I IN,RMS Represents the RMS value of the line current, V IN,RMS Represents the RMS value of the line voltage, V O represents the output voltage of the PFC converter. The RMS value is obtained by sampling and accumulating samples over a certain period of time (e.g., half a line cycle or a full cycle) and dividing the result by the number of samples. It should be noted that although the expressions of equations (2) and (3) are more complicated than the expression of equation (1), they are not difficult to implement. Specifically, as in CCM, V is also required in DCM. O and V IN In addition, L B and f SW Parameters such as L are usually fixed values ​​and therefore do not need to be measured. However, in some embodiments, L may need to be measured during initialization or calibration. B Parameters such as V O and V IN The input current V can be measured by conventional control circuits (such as control circuit 54). Alternatively, the filtered input current can be measured by any conventional technology (such as a Hall sensor), wherein the measured input current can be used to determine the RMS value. O and V IN Parameters such as and the measured filtered input current are used as inputs for the DCM duty cycle feedforward control 58. According to the DCM duty cycle feedforward control based on equations (2) and (3), Figure 5 The control circuit 54 is modified as follows: Fig.12 As shown in Figure 5 and Fig.12 Similar components in the same manner are marked with the same reference numerals and will not be described in detail herein. Fig.12 In the control circuit 54, the measured filtered current (derived from the low pass filter) is used as the input 58 of the duty cycle feed forward control element 1202. Fig.12 In the figure, the FCML bridgeless totem pole boost PFC device 50 shown includes a three-level FCML bridgeless totem pole boost PFC circuit 52 (with Figure 5 As described above, for Figure 5 The modification of the control circuit 54 mainly includes: the control element 56 is changed to a blocking control element 56b; and an additional input 58 for duty cycle feedforward control (that is, the input 58 includes V O and V IN In addition, it also includes the measured input current (i.e., the boost inductor current i LBIn some embodiments, the lockout control element 56b may include a soft start function (e.g., similar to Fig.10 In some embodiments, the blocking control and boost soft start element 56a are included, while in other embodiments, the blocking control element 56b may not include the soft start function. In fact, in the case of extremely light load (e.g., 10% load), the soft start can be omitted because the distortion near the zero crossing point is mainly caused by the interlaced operation of CCM during the DCM operation. In addition, in some embodiments, since the duty cycle feedforward control includes pre-calculating the required value of DCM (according to equations (2) and (3)), the soft start can be omitted in light load conditions.

[0126] Generally speaking, in a half line cycle, the boost inductor operates in both DCM and CCM modes, which is also called mixed conduction mode (MCM). Fig.13A , Fig. 13B , Fig. 13C Three feedforward duty cycles D based on equations (1), (2) and (3) are shown: FF The variation of the feedforward duty cycle in three different load conditions during a half line cycle. If operating in CCM, the duty cycle is pre-calculated according to equation (1), and the feedforward duty cycle is D FF,CCM When operating in DCM, if the instantaneous input voltage is less than or equal to half of the output voltage, equation (2) is used (operating mode is DCM1), and the feedforward duty cycle is D FF,DCM1 When operating in DCM, if the instantaneous input voltage is greater than half of the output voltage, equation (3) is used (operating mode is DCM2), and the feedforward duty cycle is D FF,DCM2 In this way, the minimum value of the feedforward duty cycle obtained according to equations (1), (2) and (3) is selected as the exact value of the feedforward duty cycle. Therefore, switching between different conduction modes does not cause the feedforward duty cycle to jump. It should be noted that if Fig.13A , Fig. 13B , Fig. 13C As shown, the feedforward duty cycle D of CCM under three different load conditions FF,CCM are the same. Fig.13A As shown in the figure, under 10% load, the MCM operation of the boost inductor only includes two modes, CCM and DCM1, where DCM1 has a lower feedforward duty cycle near the zero crossing point. Under 5% and 2.5% load, MCM includes all three modes (i.e., CCM, DCM1, and DCM2), where DCM2 has the lowest feedforward duty cycle for most of the time within the half-line cycle under 2.5% load, so DCM2 is more important; and under 5% load, during the overlap period of CCM and DCM2, the feedforward duty cycle corresponding to DCM1, CCM, or DCM1 can be selected in sequence as the minimum value.

[0127] according to Figure 13A-13C , it is clear that there is at least one difference between the two-level and three-level (i.e., multi-level) boost PFC operation. For example, even if the two-level configuration is assumed to operate in MCM, in the best case, only DCM1 is close to the zero crossing point in addition to CCM. It should be noted that in the two-level configuration, the ripple is zero only at the zero crossing point of the line voltage. In addition, in the existing two-level boost PFC device, even if there is a need to operate in DCM (e.g. Fig.11 In contrast, some embodiments of the flying capacitor three-level bridgeless totem pole boost PFC device disclosed in this case can operate in DCM (e.g., DCM2) even near the peak of the line voltage, such as Figure 13A-13C In other words, when using MCM, it is possible to operate in DCM2 in some embodiments (especially under light load conditions), which enables operation with an appropriate feedforward duty cycle under certain conditions (such as D FF,DCM2 ) without insisting on enforcing an inappropriate CCM.

[0128] Fig.14A and Fig. 14B Figure 2 shows the key voltage and current waveforms of the flying capacitor three-level bridgeless totem pole boost PFC device operating in MCM at 10% load. Fig.15A and Fig. 15B The key voltage and current waveforms of the flying capacitor three-level bridgeless totem pole boost PFC device operating in MCM at 5% load are shown. Fig.16A , Fig. 16B and Fig. 16C Figure 2 shows the key voltage and current waveforms of a flying capacitor three-level bridgeless totem pole boost PFC device operating in MCM at 2.5% load. Fig.14A In FIG. 1 , the waveforms shown are, from top to bottom, the line voltage 140 after EMI filter filtering, the CCM feedforward duty cycle 141a, the MCM feedforward duty cycle 141b, the line current 142, the boost inductor current 143, the output voltage 144, the flying capacitor voltage 145, and the boost input voltage 146, and the waveforms shown are the voltage and current waveforms obtained when the line voltage of the 2.5kW boost PFC converter is 220-Vrms / 50-Hz and the output voltage is 385-V. Fig.15A, the waveforms shown are, from top to bottom, the line voltage 150 after EMI filter filtering, CCM feedforward duty cycle 151a, MCM feedforward duty cycle 151b, line current 152, boost inductor current 153, output voltage 154, flying capacitor voltage 155, and boost input voltage 156, and the waveforms shown are the voltage and current waveforms obtained when the line voltage of a 2.5kW boost PFC converter is 220-Vrms / 50-Hz and the output voltage is 385-V. Fig.16A , the waveforms shown are, from top to bottom, the line voltage 160 filtered by the EMI filter, the CCM feedforward duty cycle 161a, the MCM feedforward duty cycle 161b, the line current 162, the boost inductor current 163, the output voltage 164, the flying capacitor voltage 165, and the boost input voltage 166, and the waveforms shown are the voltage and current waveforms obtained when the line voltage of the 2.5kW boost PFC converter is 220-Vrms / 50-Hz and the output voltage is 385-V. Fig.14A As shown, under 10% load and operating with MCM feed-forward duty cycle, the distortion of line current 142 waveform near the line voltage zero crossing is significantly reduced (compared to operating with CCM feed-forward duty cycle only). It should be noted that the distortion percentage corresponds to total harmonic distortion (THD), which is generally understood in the art as the ratio of harmonic current to fundamental current. Fig.14A (distortion rate is 1.7%), Fig.15A (distortion rate 5.5%) to Fig.16A The gradually increasing distortion rate in (distortion rate is 10.4%) reflects the gradual decrease in the fundamental current value. Fig. 14B , Fig. 15B and Fig. 16B In Fig.14A , Fig.15A and Fig.16A The waveform of the neutral line voltage near the zero-crossing point from the negative half-line cycle to the positive half-line cycle is amplified; Fig. 16C In, yes Fig.16A The waveform near the positive peak of the line voltage is amplified. Fig. 14B , Fig. 15B and Fig. 16B In Figure 1, it is clearly shown that the boost inductor operates in DCM near the zero crossing of the line voltage, which corresponds to Fig.13A , Fig. 13B and Fig. 13C The feedforward duty cycle in Fig. 16C It is also clearly shown that the boost inductor operates in DCM near the positive peak of the line voltage, which corresponds to Fig. 13C The feedforward duty cycle in .

[0129] The aforementioned implementation method for reducing the zero crossover distortion of the three-level FCML bridgeless totem pole boost PFC device in this case can also be extended to Figure 4 The n-level FCML bridgeless totem-pole boost PFC converter shown.

[0130] The control circuit 54 can be implemented using hardware, software (including firmware), or a combination of hardware and software. For example, the control circuit 54 can be implemented using a digital signal processor or a microcontroller, wherein the microcontroller can include at least one of a discrete logic circuit (having logic gates that can perform logic operations on information signals), an application specific integrated circuit, a programmable gate array, and a field programmable gate array. In addition, the control circuit 54 also includes one or more pulse generators.

[0131] According to the aforementioned embodiments of the three-level FCML bridgeless totem pole boost PFC converter, it can be understood that the present invention has disclosed a corresponding control method, such as Fig.17 A control method 170 of an embodiment is shown. The control method 170 is applicable to a multi-level bridgeless boost PFC device, wherein the circuit of the multi-level bridgeless boost PFC device includes an inductor having a flying capacitor totem pole configuration, a first pair of switches, a second pair of switches, and a capacitor. The control method 170 is performed by a control circuit, wherein the control circuit is configured to drive the first pair of switches and the second pair of switches in a manner that reduces line current distortion. In one embodiment, the control method 170 includes: in a first half line cycle, driving the first switch of the first pair of switches and the second pair of switches during a full period equal to the first half line cycle, and driving the second switch of the first pair of switches and the second pair of switches during a partial period shorter than the first half line cycle (as shown in step 172). In addition, the control method 170 also includes: in a second half line cycle, driving the first switch of the first pair of switches and the second pair of switches during a partial period shorter than the second half line cycle, and driving the second switch of the first pair of switches and the second pair of switches during a full period equal to the second half line cycle (as shown in step 174).

[0132] According to the above embodiments, it should be understood that the present invention has disclosed the corresponding control method, for example Fig.18A control method 180 of an embodiment is shown. The control method 180 is applicable to a multi-level bridgeless boost PFC device, wherein the circuit of the multi-level bridgeless boost PFC device includes an inductor having a flying capacitor totem pole configuration, a first pair of switches, a second pair of switches and a capacitor, and a slow bridge arm synchronous rectification switch, wherein the first pair of switches and the second pair of switches both include a fast bridge arm boost switch and a fast bridge arm synchronous rectification switch. The control method 180 can be performed by a control circuit. The control method 180 includes determining a zero crossing point of a line voltage (as shown in step 182). In addition, the control method 180 also includes: disabling the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch, and the slow bridge arm synchronous rectification switch near the zero crossing point of the line voltage (as shown in step 184).

[0133] According to the above embodiments, it should be understood that the present invention has disclosed the corresponding control method, for example Fig.19 A control method 190 of another embodiment is shown. The control method 190 is applicable to a multi-level bridgeless boost PFC device, wherein the circuit of the multi-level bridgeless boost PFC device includes an inductor having a flying capacitor totem pole configuration, a first pair of switches, a second pair of switches, and a capacitor. The control method 190 can be performed by a control circuit including a feedforward control element. The control method 190 includes: providing a pre-calculated value of a duty cycle of a continuous conduction mode to control the first pair of switches and the second pair of switches (as shown in step 192). In addition, the control method 190 also includes: providing two different pre-calculated values ​​of the duty cycle of a discontinuous conduction mode to control the first pair of switches and the second pair of switches (as shown in step 194)

[0134] According to some embodiments of the multi-level bridgeless boost PFC device and control method thereof, and referring to at least Figure 5 , Fig. 8A and Fig.17 After that, it should be understood that in the first embodiment shown in this case, the multi-level bridgeless boost PFC device 50 includes a circuit 52 and a control circuit 54, wherein the circuit 52 includes an inductor 51 having a flying capacitor totem pole configuration, at least a first pair of switches 53a, 53b and a second pair of switches 55a, 55b and a capacitor 59. The control circuit is configured to drive the first pair of switches and the second pair of switches in a manner that reduces line current distortion. For the first pair of switches and the second pair of switches, the control circuit is configured to: in a first half line cycle, drive the first switch 53a, 55a of the first pair of switches and the second pair of switches during a full period equal to the first half line cycle, and drive the second switch 53b, 55b of the first pair of switches and the second pair of switches during a partial period shorter than the first half line cycle (step 172); and in a second half line cycle, drive the first switch of the first pair of switches and the second pair of switches during a partial period shorter than the second half line cycle, and drive the second switch of the first pair of switches and the second pair of switches during a full period equal to the second half line cycle (step 174).

[0135] The first embodiment may include any one or a combination of the following technical features.

[0136] For the multi-level bridgeless boost PFC device in the first embodiment, in the first half line cycle, the first switch of the first pair of switches and the second pair of switches operates as a boost switch, and the second switch of the first pair of switches and the second pair of switches operates as a synchronous rectification switch, wherein the control circuit is configured with a gate drive pulse V GS1a 、V GS1b The boost switch is driven and the synchronous rectification switches are disabled during a period 88a, 88b at least close to the zero crossing of the line voltage.

[0137] For the multi-level bridgeless boost PFC device in the first embodiment, in the first half line cycle, the control circuit blocks the gate driving pulse of the synchronous rectification switch on both sides of the zero crossing point of the line voltage to disable the synchronous rectification switch.

[0138] For the multi-level bridgeless boost PFC device in the first embodiment, in the first half line cycle, the control circuit blocks the gate driving pulse of the synchronous rectification switch during the entire first half line cycle to disable the synchronous rectification switch.

[0139] For the multi-level bridgeless boost PFC device in the first embodiment, in the second half line cycle, the first pair of switches and the second switch of the second pair of switches operate as a boost switch, and the first pair of switches and the first switch of the second pair of switches operate as a synchronous rectification switch, wherein the control circuit is configured to drive the boost switch with a gate drive pulse and disable the synchronous rectification switch during a period at least close to the zero crossing point of the line voltage.

[0140] For the multi-level bridgeless boost PFC device in the first embodiment, in the second half line cycle, the control circuit blocks the gate driving pulse of the synchronous rectification switch on both sides of the zero crossing point of the line voltage to disable the synchronous rectification switch.

[0141] For the multi-level bridgeless boost PFC device in the first embodiment, in the second half line cycle, the control circuit blocks the gate driving pulse of the synchronous rectification switch during the entire second half line cycle to disable the synchronous rectification switch.

[0142] For the multi-level bridgeless boost PFC device in the first embodiment, the first pair of switches and the second pair of switches are fast bridge arm switches, and the multi-level bridgeless boost PFC device further includes a pair of slow bridge arm synchronous rectification switches 57a, 57b.

[0143] See at least Figure 9A-Figure 10 and Fig.18After that, it should be understood that in the second embodiment illustrated in this case, the multi-level bridgeless boost PFC device 50 includes a circuit 52 and a control circuit 54, wherein the circuit 52 includes an inductor 51, at least a first pair of switches and a second pair of switches, a capacitor 59, and a plurality of slow bridge arm synchronous rectification switches, wherein the inductor, the first pair of switches, the second pair of switches, and the capacitor have a flying capacitor totem pole configuration. Each of the first pair of switches and the second pair of switches includes a fast bridge arm boost switch and a fast bridge arm synchronous rectification switch. The control circuit is configured to disable the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch, and the slow bridge arm synchronous rectification switch near the zero crossing point of the line voltage (step 184).

[0144] The second embodiment may include any one or a combination of the following technical features.

[0145] For the multi-level bridgeless boost PFC device in the second embodiment, the control circuit is configured to block the corresponding gate drive pulses during the blocking period on both sides of the zero crossing point of the line voltage to disable the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the slow bridge arm synchronous rectification switch.

[0146] For the multi-level bridgeless boost PFC device in the second embodiment, the lockout periods corresponding to the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the slow bridge arm synchronous rectification switch are all the same.

[0147] For the multi-level bridgeless boost PFC device in the second embodiment, the lockout periods (101a-101f) corresponding to the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the slow bridge arm synchronous rectification switch are not the same.

[0148] For the multi-level bridgeless boost PFC device in the second embodiment, the blocking period before the zero crossing point of the line voltage and the blocking period after the zero crossing point of the line voltage have different durations.

[0149] For the multi-level bridgeless boost PFC device in the second embodiment, the control circuit is configured to provide a first lockout period (101e, 101f) for the fast bridge arm boost switch, a second lockout period (101c, 101d) for the fast bridge arm synchronous rectification switch, and a third lockout period (101a, 101b) for the slow bridge arm synchronous rectification switch, wherein the first lockout period, the second lockout period, and the third lockout period are different.

[0150] For the multi-level bridgeless boost PFC device in the second embodiment, the control circuit is also configured to provide a boost soft start pulse 98 when the gate drive pulse is disabled, wherein the control circuit provides the boost soft start pulse using an open-loop control 56a and disables the gate drive pulse based on a closed-loop control, and the control circuit provides the boost soft start pulse at the end of the lockout period of the fast bridge arm boost switch.

[0151] For the multi-level bridgeless boost PFC device in the second embodiment, after the boost soft start pulse is provided, the control circuit is further configured to turn on one of the slow bridge arm synchronous rectification switches, and turn on all the fast bridge arm synchronous rectification switches after a delay.

[0152] See at least Figure 12-13C and Fig.19 After that, it should be understood that in the third embodiment illustrated in this case, the multi-level bridgeless boost PFC device 50 includes a circuit 52 and a control circuit 54, wherein the circuit includes an inductor 51 with a flying capacitor totem pole configuration, at least a first pair of switches and a second pair of switches, and a capacitor 59. The control circuit includes a feedforward control element 1202, wherein the feedforward control element is configured to provide pre-calculated values ​​of duty cycles of a continuous conduction mode and two different discontinuous conduction modes to control the first pair of switches and the second pair of switches (steps 192 and 194).

[0153] The third embodiment may include any one or a combination of the following technical features.

[0154] For the multi-level bridgeless boost PFC device in the third embodiment, the control circuit is configured to switch between the continuous conduction mode and two different discontinuous conduction modes within a whole half line cycle between zero crossings of the line voltage.

[0155] For the multi-level bridgeless boost PFC device in the third embodiment, the control circuit is configured to select the continuous conduction mode and one of the two different discontinuous conduction modes according to the minimum value of the duty cycle.

[0156] For the multi-level bridgeless boost PFC device in the third embodiment, the pre-calculated values ​​of the duty cycles of the two different discontinuous conduction modes are obtained based on two different calculation methods, and the control circuit selects one of the discontinuous conduction modes by comparing the input voltage and the output voltage of the circuit.

[0157] It should be noted that in some embodiments, the first, second and third embodiments may be combined in any manner.

[0158] It should be noted that the above are only preferred embodiments proposed for the purpose of illustrating the present invention. The present invention is not limited to the embodiments described. The scope of the present invention is determined by the scope of the patent application as attached. The present invention may be modified in various ways by a person skilled in the art, but all of them are within the scope of the patent application as attached. In addition, the disclosed embodiments may be combined arbitrarily, and reference to one embodiment does not mean the exclusion of features in other embodiments. In the patent application, the word "comprising" does not exclude other elements or steps, and the word "a" before the element name does not exclude multiple elements.

Claims

1. A multi-level bridgeless boost power factor correction device, comprising: A circuit comprising an inductor having a flying capacitor totem pole configuration, at least a first pair of switches and a second pair of switches, and a capacitor; and a control circuit configured to drive the first pair of switches and the second pair of switches in a manner to reduce line current distortion, wherein for the first pair of switches and the second pair of switches, the control circuit is configured to: In a first half line cycle, driving the first switch of the first pair of switches and the second pair of switches during a full period equal to the first half line cycle, and driving the second switch of the first pair of switches and the second pair of switches during a partial period shorter than the first half line cycle; and In a second half line cycle, the first switch is driven during a partial period shorter than the second half line cycle, and the second switch is driven during a full period equal to the second half line cycle.

2. A multi-level bridgeless boost power factor correction device as described in claim 1, wherein in the first half line cycle, the first switch of the first pair of switches and the second pair of switches operates as a boost switch, and the second switch of the first pair of switches and the second pair of switches operates as a synchronous rectification switch, and the control circuit is configured to drive the boost switch with a gate drive pulse and disable the synchronous rectification switch during a period at least close to a zero crossing point of the line voltage.

3. A multi-level bridgeless boost power factor correction device as described in claim 2, wherein in the first half-line cycle, the control circuit blocks the gate drive pulse of the synchronous rectification switch on both sides of the zero crossing point of the line voltage or blocks the gate drive pulse of the synchronous rectification switch throughout the first half-line cycle to disable the synchronous rectification switch.

4. A multi-level bridgeless boost power factor correction device as described in claim 1, wherein in the second half-line cycle, the second switch of the first pair of switches and the second pair of switches operates as a boost switch, and the first switch of the first pair of switches and the second pair of switches operates as a synchronous rectification switch, wherein the control circuit is configured to drive the boost switch with a gate drive pulse and disable the synchronous rectification switch during a period at least close to a zero crossing point of the line voltage.

5. A multi-level bridgeless boost power factor correction device as described in claim 4, wherein in the second half-line cycle, the control circuit blocks the gate drive pulse of the synchronous rectification switch on both sides of the zero crossing point of the line voltage or blocks the gate drive pulse of the synchronous rectification switch throughout the second half-line cycle to disable the synchronous rectification switch.

6. The multi-level bridgeless boost power factor correction device as described in claim 1, wherein the first pair of switches and the second pair of switches are fast bridge arm switches, and the multi-level bridgeless boost power factor correction device further comprises a pair of slow bridge arm synchronous rectification switches.

7. A multi-level bridgeless boost power factor correction device, comprising: A circuit comprising an inductor, at least a first pair of switches and a second pair of switches, a capacitor and a plurality of slow bridge arm synchronous rectification switches, wherein the inductor, the first pair of switches, the second pair of switches and the capacitor have a flying capacitor totem pole configuration, and each of the first pair of switches and the second pair of switches comprises a fast bridge arm boost switch and a fast bridge arm synchronous rectification switch; and A control circuit is configured to disable the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the plurality of slow bridge arm synchronous rectification switches near a zero crossing point of the line voltage.

8. A multi-level bridgeless boost power factor correction device as described in claim 7, wherein the control circuit is configured to block the corresponding gate drive pulse during the blocking period on both sides of the zero crossing point of the line voltage to disable the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the multiple slow bridge arm synchronous rectification switches.

9. The multi-level bridgeless boost power factor correction device as described in claim 8, wherein the lockout periods corresponding to the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the plurality of slow bridge arm synchronous rectification switches are all the same.

10. The multi-level bridgeless boost power factor correction device as claimed in claim 8, wherein the lockout periods corresponding to the fast bridge arm boost switch, the fast bridge arm synchronous rectification switch and the plurality of slow bridge arm synchronous rectification switches are not completely the same.

11. The multi-level bridgeless boost power factor correction device as claimed in claim 8, wherein the blocking period before the zero-crossing point of the line voltage and the blocking period after the zero-crossing point of the line voltage have different durations.

12. A multi-level bridgeless boost power factor correction device as described in claim 8, wherein the control circuit is further configured to provide a boost soft start pulse when the gate drive pulse is disabled, the control circuit provides the boost soft start pulse using open-loop control, and disables the gate drive pulse based on closed-loop control, and the control circuit provides the boost soft start pulse at the end of the blocking period of the fast bridge arm boost switch, wherein after the end of providing the boost soft start pulse, the control circuit is further configured to turn on one of the slow bridge arm synchronous rectification switches, and turn on all of the fast bridge arm synchronous rectification switches after a delay time.

13. A multi-level bridgeless boost power factor correction device, comprising: A circuit comprising an inductor having a flying capacitor totem pole configuration, at least a first pair of switches and a second pair of switches, and a capacitor; and A control circuit includes a feed-forward control element, wherein the feed-forward control element is configured to provide pre-calculated values ​​of duty cycles of a continuous conduction mode and two different discontinuous conduction modes to control the first pair of switches and the second pair of switches.

14. A multi-level bridgeless boost power factor correction device as described in claim 13, wherein the control circuit is configured to switch between the continuous conduction mode and the two different discontinuous conduction modes within the entire half-line cycle between the zero crossing points of the line voltage, and the control circuit is configured to select the continuous conduction mode and one of the two different discontinuous conduction modes according to the minimum value of the duty cycle.

15. A multi-level bridgeless boost power factor correction device as described in claim 13, wherein the pre-calculated value of the duty cycle of the two different discontinuous conduction modes is obtained based on two different calculation methods, and the control circuit selects one of the discontinuous conduction modes by comparing the input voltage and output voltage of the circuit.

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