High-voltage integrated circuit, intelligent power module and electrical equipment

Abstract

The invention discloses a high-voltage integrated circuit, an intelligent power module and electrical equipment. The high-voltage integrated circuit comprises a high-voltage driving sub-circuit which is provided with a high-voltage input end, a high-voltage output end, a first power supply end and a second power supply end and is connected with a high-voltage area input end, a high-voltage area output end, a high-voltage area power supply positive end and a high-voltage area ground end of the high-voltage integrated circuit in a one-to-one correspondence manner, the external bootstrap capacitor is connected between the positive end of the high-voltage area power supply and the ground end of the high-voltage area; the switch sub-circuit is connected with the resistor sub-circuit in parallel, the first end of the switch sub-circuit is connected with the high-voltage area ground end, the second end of the switch sub-circuit is connected with the high-voltage inverter half-bridge floating node, and the control end of the switch sub-circuit is used for inputting a target control signal. According to the high-voltage integrated circuit, the negative voltage overshoot resistance of the high-voltage inverter half-bridge floating node can be improved, the high-voltage integrated circuit is not limited by an equivalent bootstrap resistor, direct connection during circuit starting cannot be caused, and the influence on the charging and discharging speed of the bootstrap capacitor is small.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent power modules, and in particular to a high-voltage integrated circuit, an intelligent power module and an electrical device. Background Art

[0002] Figure 1 This is a schematic diagram of the application of HVIC (High Voltage Integrated Circuit) in a power inverter system. The influence of parasitic inductances L1 and L2 is taken into account in this power inverter system. When the upper bridge power switch device T2 is turned off and the lower bridge power switch device T1 is not turned on, the inductive load L LOAD To maintain the direction and magnitude of the current, the freewheeling diode D1 connected in parallel with T1 begins to conduct. Due to the presence of parasitic inductances L1 and L2, the potential of the negative end of the HVIC high-voltage area power supply (i.e., the high-voltage inverter half-bridge floating node VS) will be rapidly pulled down, generating a large negative overshoot voltage.

[0003] To this end, the related art proposes to connect a resistor Re in series between the VS terminal and the half-bridge node A. Re is located between the external bootstrap capacitor C1 and the half-bridge node A, and forms an RC filter with C1. The overshoot voltage at the VS terminal can be limited. The larger Re is, the better the effect is. However, if Re is too large, it may cause direct conduction when the high-voltage integrated circuit is started. Therefore, Re needs to satisfy the following formula:

[0004]

[0005] Among them, RB represents the bootstrap resistor, VCE1 and VDB represent the conduction voltage drop of the lower bridge power switch device T1 and the bootstrap diode DB respectively, and Vth represents the turn-on voltage of the upper bridge power switch device T2. At the same time, the margin also needs to be considered.

[0006] However, the above technology is mainly suitable for the scenario where the HVIC and the power device are separated so that the resistor Re can be added. It can basically not be used in IPM (Intelligent Power Module). In most IPMs, because the bootstrap capacitor is not integrated, the resistor Re cannot be integrated. Generally speaking, IPM does not have space to integrate the bootstrap capacitor and the resistor Re. And, in terms of effect, the larger the resistor Re, the better. However, Re is limited by the equivalent bootstrap resistor RB and cannot be too large, otherwise it will cause the circuit to be directly connected when it starts, and at the same time limit the speed of charging and discharging the bootstrap capacitor, thereby affecting the performance of the overall circuit. Summary of the invention

[0007] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present invention is to provide a high-voltage integrated circuit, an intelligent power module and an electrical device to enhance the VS's ability to resist negative voltage overshoot, improve the performance of the intelligent power module, and not cause the upper bridge and the lower bridge to be directly connected during startup, and have little effect on the speed of charging and discharging the bootstrap capacitor.

[0008] In order to solve the above technical problems, the first aspect of the present invention proposes a high-voltage integrated circuit, including: a high-voltage driving sub-circuit, a resistor sub-circuit and a switch sub-circuit; the high-voltage driving sub-circuit has a high-voltage input terminal, a high-voltage output terminal, a first power supply terminal and a second power supply terminal, and the high-voltage input terminal, the high-voltage output terminal, the first power supply terminal and the second power supply terminal are connected one-to-one with the high-voltage area input terminal, the high-voltage area output terminal, the high-voltage area power supply positive terminal and the high-voltage area ground terminal of the high-voltage integrated circuit, wherein, when applied, an external bootstrap capacitor is connected between the positive terminal of the high-voltage area power supply and the high-voltage area ground terminal; the switch sub-circuit is connected in parallel with the resistor sub-circuit, the first end of the switch sub-circuit is connected to the high-voltage area ground terminal, the second end of the switch sub-circuit is connected to the high-voltage inverter half-bridge floating node of the high-voltage integrated circuit, and the control end of the switch sub-circuit is used to input the target control signal.

[0009] In addition, the high voltage integrated circuit of the embodiment of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, the high-voltage driving sub-circuit includes a logic processing unit, a pulse generating unit, a high-voltage level shifting unit, a filtering unit, an RS trigger and a driving unit connected in sequence, the high-voltage input terminal of the logic processing unit is connected to the high-voltage area input terminal, and the high-voltage output terminal of the driving unit is connected to the high-voltage area output terminal. The circuit also includes: a control sub-circuit, a first input terminal of the control sub-circuit is connected to the output terminal or the R input terminal of the RS trigger, a second input terminal of the control sub-circuit is connected to the output terminal of the driving unit, and the output terminal of the control sub-circuit is connected to the control terminal of the switch sub-circuit. The control sub-circuit is configured to output a target control signal for controlling the switch sub-circuit to disconnect when the input signal of the first input terminal is a shutdown signal and the voltage value of the input signal of the second input terminal is within a preset voltage range.

[0011] According to an embodiment of the present invention, the resistor subcircuit includes a first resistor, a first end of the first resistor is connected to the high voltage region ground terminal, and a second end of the first resistor is connected to the high voltage inverter half-bridge floating node.

[0012] According to one embodiment of the present invention, the switch subcircuit includes a first NMOS tube, the drain of the first NMOS tube serves as the first end of the switch subcircuit, the source of the first NMOS tube serves as the second end of the switch subcircuit, and the gate of the first NMOS tube serves as the control end of the switch subcircuit.

[0013] According to an embodiment of the present invention, the preset voltage range includes greater than or equal to a first preset voltage, or greater than or equal to the first preset voltage and less than or equal to a second preset voltage, wherein the first preset voltage is less than the second preset voltage.

[0014] According to one embodiment of the present invention, the control subcircuit includes: a first control unit and a second control unit; a power supply end of the first control unit is connected to the positive end of the high-voltage area power supply, a ground end of the first control unit is connected to the ground end of the high-voltage area, a first input end of the first control unit is connected to the output end of the RS trigger, and a second input end of the first control unit is connected to the output end of the drive unit, and the first control unit is configured to generate complementary first and second signals according to the output signal of the RS trigger and the output signal of the drive unit; a power supply end of the second control unit is connected to the positive end of the high-voltage area power supply, a ground end of the second control unit is connected to the high-voltage inverter half-bridge floating node, a first input end of the second control unit is connected to the first output end of the first control unit, a second input end of the second control unit is connected to the second output end of the first control unit, an output end of the second control unit is connected to the control end of the switch subcircuit, and the second control unit is configured to generate the target control signal according to the first signal and the second signal.

[0015] According to one embodiment of the present invention, the first control unit includes: a first NOT gate, a first NAND gate, a comparator, a second NOT gate, a third NOT gate and a fourth NOT gate; the input end of the first NOT gate is connected to the output end of the RS trigger, and the output end of the first NOT gate is connected to the first input end of the first NAND gate; the inverting input end of the comparator is connected to the output end of the driving unit, the non-inverting input end of the comparator is connected to the positive pole of the preset power supply, the power supply end of the comparator is connected to the positive end of the power supply of the high-voltage area, and the output end of the comparator is connected to the input end of the second NOT gate, wherein the negative pole of the preset power supply is connected to the ground end of the high-voltage area, and the preset power supply is used to provide the first preset voltage; the output end of the second NOT gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the third NOT gate, the output end of the third NOT gate is connected to the input end of the fourth NOT gate and serves as the first output end of the first control unit, and the output end of the fourth NOT gate serves as the second output end of the first control unit.

[0016] According to one embodiment of the present invention, the second control unit includes: a first N-type switch tube, a second N-type switch tube, a first P-type switch tube, a second P-type switch tube and a fifth NOT gate; the gate of the first N-type switch tube serves as the first input end of the second control unit, the drain of the first N-type switch tube is connected to the drain of the first P-type switch tube and the gate of the second P-type switch tube respectively, the gate of the second N-type switch tube serves as the second input end of the second control unit, the drain of the second N-type switch tube is connected to the gate of the first P-type switch tube, the drain of the second P-type switch tube and the input end of the fifth NOT gate respectively, the source of the first N-type switch tube and the source of the second N-type switch tube are connected to the high-voltage inverter half-bridge floating node, the source of the first P-type switch tube and the source of the second P-type switch tube are connected to the positive end of the high-voltage area power supply, and the output end of the fifth NOT gate serves as the output end of the second control unit.

[0017] According to an embodiment of the present invention, the first control unit further includes: a Zener diode, an anode of the Zener diode is connected to the floating node of the high-voltage inverter half-bridge, and a cathode of the Zener diode is connected to the ground terminal of the high-voltage region.

[0018] According to one embodiment of the present invention, the first control unit also includes: a delay filter, the delay filter includes a filter resistor and a filter capacitor, the first end of the filter resistor is connected to the output end of the driving unit, the second end of the filter resistor is connected to the inverting input end of the comparator, the first end of the filter capacitor is connected to the second end of the filter resistor, and the second end of the filter capacitor is connected to the ground end of the high-voltage area.

[0019] In order to solve the above technical problem, a second embodiment of the present invention proposes an intelligent power module, characterized in that it includes the high-voltage integrated circuit described in the first embodiment.

[0020] In order to solve the above technical problem, a third embodiment of the present invention provides an electrical device, including the intelligent power module described in the above second embodiment.

[0021] The high-voltage integrated circuit, intelligent power module and electrical equipment of the embodiment of the present invention can improve the VS's ability to resist negative voltage overshoot through the setting of the resistance subcircuit and the switch subcircuit, and the resistance subcircuit and the switch subcircuit are integrated into the high-voltage integrated circuit, which can be easily applied in the intelligent power module to improve the performance of the intelligent power module, and can also be used in a discrete power inverter system. At the same time, the resistance subcircuit is not limited to the bootstrap resistor, and has a larger value range, which will not cause the circuit to be directly connected when starting, and makes the VS better in resisting negative voltage overshoot; it has little effect on the speed of charging and discharging the bootstrap capacitor, and even because it is integrated in the high-voltage integrated circuit, it can not affect the charging and discharging speed of the bootstrap capacitor.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the application of high voltage integrated circuits in power inverter systems;

[0024] Figure 2 is a schematic structural diagram of a high voltage integrated circuit according to an embodiment of the present invention;

[0025] Figure 3 is a schematic structural diagram of a high-voltage drive subcircuit according to an embodiment of the present invention;

[0026] Figure 4 is a schematic structural diagram of a high voltage integrated circuit according to a specific embodiment of the present invention;

[0027] Figure 5 is a schematic structural diagram of a high voltage integrated circuit according to a specific embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of the structure of a control subcircuit according to an embodiment of the present invention;

[0029] Figure 7 is a structural schematic diagram of a control subcircuit according to another embodiment of the present invention;

[0030] Figure 8 is a structural schematic diagram of a control subcircuit of yet another embodiment of the present invention;

[0031] Fig. 9 is a control logic timing diagram of an embodiment of the present invention;

[0032] Fig.10 is a control logic timing diagram of another embodiment of the present invention;

[0033] Fig.11 is a structural block diagram of an intelligent power module according to an embodiment of the present invention;

[0034] Fig.12 It is a structural block diagram of an electrical device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0036] The following describes a high-voltage integrated circuit, an intelligent power module, and an electrical device according to embodiments of the present invention with reference to the accompanying drawings.

[0037] Figure 2 It is a schematic diagram of the structure of a high-voltage integrated circuit according to an embodiment of the present invention.

[0038] like Figure 2 As shown, the high voltage integrated circuit 100 includes: a high voltage driving sub-circuit 110 , a resistance sub-circuit 120 and a switch sub-circuit 130 .

[0039] See also Figure 2 The high-voltage driving sub-circuit 110 has a high-voltage input terminal, a high-voltage output terminal, a first power supply terminal and a second power supply terminal. The high-voltage input terminal, the high-voltage output terminal, the first power supply terminal and the second power supply terminal are connected one by one with the high-voltage region input terminal HIN, the high-voltage region output terminal HO, the high-voltage region power supply positive terminal VB and the high-voltage region ground terminal VS1 of the high-voltage integrated circuit 100. The high-voltage region ground terminal VS1 is a port newly added on the high-voltage side of the high-voltage integrated circuit 100. The external bootstrap capacitor C1 is connected between the high-voltage region power supply positive terminal VB and the high-voltage region ground terminal VS1. The switch sub-circuit 130 is connected in parallel with the resistor sub-circuit 120. The first end of the switch sub-circuit 130 is connected to the high-voltage region ground terminal VS1. The second end of the switch sub-circuit 130 is connected to the high-voltage region ground terminal VS1. The control end of the switch sub-circuit 130 is used to input the target control signal.

[0040] Specifically, see Figure 2A bootstrap subcircuit 140 is connected between the positive terminal VB of the high-voltage region power supply and the positive terminal VCC of the low-voltage region power supply of the high-voltage integrated circuit 100. The bootstrap subcircuit 140 may include a bootstrap resistor RB and a bootstrap diode DB. The cathode of the bootstrap diode DB is connected to the positive terminal VB of the high-voltage region power supply, and the anode of the bootstrap diode DB is connected to the positive terminal VCC of the low-voltage region power supply through the bootstrap resistor RB. The target control signal may be determined according to the input signal and / or output signal of the high-voltage driving subcircuit 110 to control the on and off of the switch subcircuit 130, wherein the output signal of the high-voltage driving subcircuit 110 is determined by the input signal.

[0041] When the inverter system is just started, the external bootstrap capacitor C1 will be charged. At this time, the input signal of the high-voltage drive subcircuit 110 is a shutdown signal, and the target control signal obtained according to the shutdown signal is a signal for controlling the switch subcircuit 130 to be turned on. After the switch subcircuit 130 is turned on, the on-resistance of the switch subcircuit 130 is connected in parallel with the resistor subcircuit 120, and the equivalent resistance Req of the two is small. The bootstrap charging path goes from VCC through the bootstrap resistor RB and the bootstrap diode DB to VB, and then through the external bootstrap capacitor C1 to VS1, and then through the smaller equivalent resistance Req to VS, and then through the turned-on lower bridge power switch device T1 (see Figure 1 ) reaches the ground terminal VSS of the high voltage integrated circuit 100. Since the equivalent resistance Req is relatively small, it will not cause the upper bridge and the lower bridge to be directly connected when the inverter system is started, and the impact on the charging efficiency is also very small.

[0042] For the time period when VS negative voltage overshoot occurs, the input signal of the high voltage driving subcircuit 110 is a shutdown signal. According to the shutdown signal and the HO signal, a target control signal for controlling the switch subcircuit 130 to shut down can be obtained. That is, when VS has a negative voltage overshoot, it can correspond to the time when the switch subcircuit 130 is shut down. At this time, the resistance subcircuit 120 and C1 form a negative voltage overshoot resistance structure. Because it is not limited by the bootstrap resistor RB, the resistance value of the resistance subcircuit 120 can be higher than Figure 1 The resistance value of Re added in the circuit will have a better effect in resisting negative pressure overshoot.

[0043] For other time periods when VS negative voltage overshoot does not occur, the switch subcircuit 130 is turned on, so that the on-resistance of the switch subcircuit 130 is connected in parallel with R3 to form a smaller equivalent circuit, which can reduce the impact of this time period on the circuit 100.

[0044] In some embodiments of the present invention, Figure 3As shown, the high-voltage driving sub-circuit 110 includes a logic processing unit 116, a pulse generating unit 111, a high-voltage level shifting unit 112, a filtering unit 113, an RS trigger 114 and a driving unit 115 which are connected in sequence. The high-voltage input terminal of the logic processing unit 116 is connected to the high-voltage area input terminal HIN, and the high-voltage output terminal of the driving unit 115 is connected to the high-voltage area output terminal HO. The pulse generating unit 111 converts the rising edge and falling edge of the HIN input signal processed by the logic processing unit 116 into two narrow pulse signals SET and RESET respectively and outputs them to the high-voltage level shifting unit 112. The high-voltage level shifting unit 112 converts the two narrow pulse signals SET and RESET into high-voltage area circuit signals VDS and VDR to respectively control two high-voltage power switching devices in the high-voltage level shifting unit 112. The two output signals of the high-voltage level shifting unit 112 are connected to the two input signal terminals of the filtering unit 113. The two output terminals of the filtering unit 113 are respectively connected to the set input terminal (i.e., the S terminal) and the reset input terminal (i.e., the R terminal) of the RS trigger 114. The output terminal of the RS trigger is connected to the input terminal of the driving unit 115. The output signal of the high-voltage output terminal of the driving unit 115 is used to drive the high-voltage area power switching device.

[0045] In this embodiment, if Figure 4 , Figure 5 As shown, the high-voltage integrated circuit 100 also includes a control subcircuit 150, a first input terminal of the control subcircuit 150 is connected to the output terminal Q or R input terminal of the RS trigger 114, a second input terminal of the control subcircuit 150 is connected to the output terminal of the driving unit 115, and the output terminal of the control subcircuit 150 is connected to the control terminal of the switch subcircuit 130. The control subcircuit 150 is configured to output a target control signal for controlling the switch subcircuit 130 to disconnect when the input signal at the first input terminal is a shutdown signal and the voltage value of the input signal at the second input terminal is within a preset voltage range.

[0046] The preset voltage range may be greater than or equal to a first preset voltage, or greater than or equal to the first preset voltage and less than or equal to a second preset voltage, wherein the first preset voltage is less than the second preset voltage.

[0047] It should be noted that the logic signal outputted from the high voltage side of the general high voltage integrated circuit 100 is transmitted from the low voltage side to the high voltage area, and is generally divided into two single pulse signals (or 1-2 pulse signals), which are then restored to a square wave control signal after being processed by circuits such as filtering. In this embodiment, the input signal of the control subcircuit can be the pulse signal after filtering.

[0048] In some examples, such as Figure 4 , Figure 5As shown, the resistor subcircuit 120 includes a first resistor R3, a first end of the first resistor R3 is connected to the high voltage region ground terminal VS1, and a second end of the first resistor R3 is connected to the high voltage inverter half bridge floating node VS.

[0049] The resistance value of the first resistor R3 can be set as required. The number of the first resistor R3 can be multiple, and the multiple first resistors R3 can be connected in series, in parallel, or in a combination of series and parallel connection.

[0050] In some examples, such as Figure 4 , Figure 5 As shown, the switch sub-circuit 130 includes a first NMOS tube MN3, the drain of the first NMOS tube MN3 serves as the first end of the switch sub-circuit 130, the source of the first NMOS tube MN3 serves as the second end of the switch sub-circuit 130, and the gate of the first NMOS tube MN3 serves as the control end of the switch sub-circuit 130.

[0051] It should be noted that the first NMOS tube MN3 can also be replaced by a PMOS tube, and the target control signal needs to be adaptively adjusted accordingly to meet the requirement of turning off the PMOS during the VS negative voltage overshoot period.

[0052] Specifically, see Figure 4 When the inverter system is just started, the external bootstrap capacitor C1 will be charged, and the control subcircuit 150 outputs the target control signal for controlling the conduction of MN3 according to the IN_A signal (which is the shutdown signal at this time) and the HO signal. MN3 is turned on, and the on-resistance of MN3 is connected in parallel with R3, and the equivalent resistance Req of the two is small. At startup, the bootstrap charging path goes from VCC through RB and DB to VB, then through the bootstrap capacitor C1 to VS1, and then through the smaller equivalent resistance Req to VS, and then through the turned-on lower bridge power switch device to VSS. Because the equivalent resistance Req is relatively small at this time, it will not cause direct conduction when the inverter system is started, and the impact on the charging efficiency is also very small.

[0053] For the time period when VS negative voltage overshoot occurs, the input signal of the high voltage driving sub-circuit 110 is a shutdown signal, and the control sub-circuit 150 is based on the IN_A signal (which is a shutdown signal at this time) and the HO signal (which is greater than the first preset voltage V TH,L ) outputs the target control signal for controlling MN3 to turn off. That is, when VS has a negative voltage overshoot, it can correspond to the time when MN3 is turned off. At this time, the first resistor R3 and C1 form a negative voltage overshoot resistance structure. Because it is not limited by the bootstrap resistor RB, the resistance value of the first resistor R3 can be higher than Figure 1 The resistance value of Re added in the circuit will have a better effect in resisting negative pressure overshoot.

[0054] For other time periods when VS negative voltage overshoot does not occur, MN3 is turned on, so that the on-resistance of MN3 is connected in parallel with R3 to form a smaller equivalent circuit, which can reduce the impact of this time period on the inverter system.

[0055] Furthermore, due to the effect of the body diode of MN3, when the upper bridge power switch device T2 is turned on, the driving loop passes through the parallel combination of the body diode of MN3 and R3, which has little influence on the driving effect.

[0056] In some examples, such as Figure 4 , Figure 5 As shown, the driving unit 115 includes a logic unit and a switch unit. The logic unit includes a first logic subunit and a second logic subunit, and the switch unit includes a first switch subunit and a second switch subunit. The input end of the first logic subunit is connected to the output end of the filter unit 114, the output end of the first logic subunit is connected to the control end of the first switch subunit, the input end of the second logic subunit is connected to the output end of the filter unit 114, and the output end of the second logic subunit is connected to the control end of the second switch subunit.

[0057] Specifically, see Figure 4 , Figure 5 , the first logic subunit and the second logic subunit both include a plurality of NOT gates connected in sequence. The first switch subunit includes: a first PMOS tube MP1 and a resistor Ron, the source of the first PMOS tube MP1 is connected to the positive terminal VB of the high-voltage region power supply, the drain of the first PMOS tube MP1 is connected to the first end of the resistor Ron, the gate of the first PMOS tube MP1 serves as the control terminal of the first switch subunit, and the second end of the resistor Ron is connected to the output terminal HO of the high-voltage region. The first switch subunit includes: a second NMOS tube MN2 and a resistor Roff, the source of the second NMOS tube MN2 is connected to the ground terminal VS1 of the high-voltage region, the drain of the second NMOS tube MN2 is connected to the first end of the resistor Roff, the gate of the second NMOS tube MN2 serves as the control terminal of the second switch subunit, and the second end of the resistor Roff is connected to the output terminal HO of the high-voltage region. When MP1 is turned on, HO outputs a high-level signal to control T2 to be turned on; when MN2 is turned on, HO outputs a low-level signal to control T2 to be turned off.

[0058] It should be noted that the above logic unit and switch unit may also have other structural forms, for example Figure 4 , Figure 5 Replace the three NOT gates in with 5, add NAND gates, etc. For example, Figure 4 , Figure 5 The three NOT gates in the circuit are replaced with four, and the positions of MP1 and MN2 are swapped. The signal for controlling T2 generated by the signal output by the RS trigger 114 is consistent with the control intention of the signal input by HIN. Figure 1To.

[0059] In some examples, such as Figure 4 , Figure 5 As shown, the driving unit 115 further includes a second resistor R0 connected between an output terminal of a NOT gate of the second logic subunit and the high voltage region ground terminal VS1, so as to enable the high voltage integrated circuit 100 to better control the power switch device.

[0060] In some embodiments of the present invention, Figure 6 As shown, the control subcircuit 150 includes: a first control unit 151 and a second control unit 152 .

[0061] The power supply end of the first control unit 151 is connected to the positive terminal VB of the high-voltage area power supply, the ground end of the first control unit 151 is connected to the ground terminal VS1 of the high-voltage area, the first input end of the first control unit 151 is connected to the output end Q of the RS trigger 114 (it can also be connected to the R end of the RS trigger 114), and the second input end of the first control unit 151 is connected to the output end of the driving unit 115. The first control unit 151 is configured to generate complementary first and second signals according to the output signal of the RS trigger 114 and the output signal of the driving unit 115.

[0062] The power supply end of the second control unit 152 is connected to the positive end VB of the high-voltage area power supply, the ground end of the second control unit 152 is connected to the high-voltage inverter half-bridge floating node VS, the first input end of the second control unit 152 is connected to the first output end of the first control unit 151, the second input end of the second control unit 152 is connected to the second output end of the first control unit 151, the output end of the second control unit 152 is connected to the control end of the switch sub-circuit 130, and the second control unit 152 is configured to generate a target control signal according to the first signal and the second signal.

[0063] In some embodiments of the present invention, Figure 6 As shown, the first control unit 151 includes: a first NOT gate 151a, a first NAND gate 151b, a comparator 151c, a second NOT gate 151d, a third NOT gate 151e and a fourth NOT gate 151f.

[0064] The input end of the first NOT gate 151a is connected to the output end of the RS trigger 114, and the output end of the first NOT gate 151a is connected to the first input end of the first NAND gate 151b; the inverting input end of the comparator 151c is connected to the output end of the driving unit 115, the non-inverting input end of the comparator 151c is connected to the positive electrode of the preset power supply V1, the power supply end of the comparator 151c is connected to the positive end VB of the high-voltage area power supply, and the output end of the comparator 151c is connected to the input end of the second NOT gate 151d, wherein the negative electrode of the preset power supply V1 is connected to the ground end VS1 of the high-voltage area, and the preset power supply V1 is used to provide a first preset voltage V TH,L The output end of the second NOT gate 151d is connected to the second input end of the first NAND gate 151b, the output end of the first NAND gate 151b is connected to the input end of the third NOT gate 151e, the output end of the third NOT gate 151e is connected to the input end of the fourth NOT gate 151f and serves as the first output end of the first control unit 151, and the output end of the fourth NOT gate 151f serves as the second output end of the first control unit 151.

[0065] The first NAND gate 151b is used to realize that IN_A is the upper bridge shutdown signal and the voltage of the HO terminal signal is greater than the threshold V TH，L When the comparator 151c is turned off, the output signal of MN3 is turned off, which can also be designed by using an RS trigger. The comparator 151c can be implemented by using an inverter or the like.

[0066] See also Figure 6 The second control unit 152 includes: a first N-type switch tube N1, a second N-type switch tube N2, a first P-type switch tube P1, a second P-type switch tube P2 and a fifth NOT gate 152a.

[0067] The gate of the first N-type switch tube N1 serves as the first input end of the second control unit 152, the drain of the first N-type switch tube N1 is connected to the drain of the first P-type switch tube P1 and the gate of the second P-type switch tube P2 respectively, the gate of the second N-type switch tube N2 serves as the second input end of the second control unit 152, the drain of the second N-type switch tube N2 is connected to the gate of the first P-type switch tube P1, the drain of the second P-type switch tube P1 and the input end of the fifth NOT gate 152a respectively, the source of the first N-type switch tube N1 and the source of the second N-type switch tube N2 are connected to the high-voltage inverter half-bridge floating node VS, the source of the first P-type switch tube P1 and the source of the second P-type switch tube P2 are connected to the positive end VB of the high-voltage area power supply, and the output end of the fifth NOT gate 152a serves as the output end of the second control unit 152.

[0068] Figure 6 The control logic implemented by the control subcircuit 150 is as follows: when it is detected that IN_A outputs a shutdown signal and the voltage of HO is greater than the first preset voltage V TH，LWhen MN3 is turned off, the target control signal is output, and MN3 is turned on at other times.

[0069] See also Figure 6 The signal at the HO terminal is input to the comparator 151c, V1 is the reference voltage, and is set to the threshold value V TH，L When the signal voltage at the HO terminal is higher than V TH，L When , the comparator 151c outputs a low level. After the output signal of the comparator 151c is processed by logic, it is combined with the logic-processed upper bridge shutdown logic control signal IN_A to realize that IN_A is the upper bridge shutdown signal, and at the same time, the voltage of the HO terminal signal is greater than the threshold value V TH，L When , the target control signal to turn off MN3 is output. This signal is transferred from the first control unit 151 to the second control unit 152 through level shift, and finally outputs a low level, that is, the OUT terminal outputs a low level (VS), controlling MN3 to turn off. If it is other cases, that is, IN_A is the upper bridge opening signal, or HO is lower than V TH，L When , the OUT terminal outputs a high level, controlling MN3 to turn on.

[0070] In some embodiments of the present invention, Figure 7 As shown, the first control unit 151 further includes: a voltage regulator tube DZ, an anode of the voltage regulator tube DZ is connected to the high-voltage inverter half-bridge floating node VS, and a cathode of the voltage regulator tube DZ is connected to the high-voltage region ground terminal VS1.

[0071] Specifically, the number of the voltage regulator tubes DZ can be one or more. Figure 7 In the figure, two voltage regulator tubes DZ (respectively denoted as DZ1 and DZ2) are connected in series as an example. Voltage clamping can be achieved through the voltage regulator tube DZ to prevent overvoltage of the components in the circuit and play a protective role.

[0072] In some embodiments of the present invention, Figure 8 As shown, the first control unit 151 further includes: a delay filter 151g, the delay filter 151g includes a filter resistor R4 and a filter capacitor C4, the first end of the filter resistor R4 is connected to the output end of the driving unit 115, the second end of the filter resistor R4 is connected to the inverting input end of the comparator 151c, the first end of the filter capacitor C4 is connected to the second end of the filter resistor R4, and the second end of the filter capacitor C4 is connected to the high-voltage area ground terminal VS1. Therefore, the filter delay can be realized through the four resistors R4 and the filter capacitor C4, and the anti-interference ability of the signal can be improved.

[0073] In some embodiments of the present invention, a delay filter may be provided after the first NAND gate 151b in the control subcircuit 150, and the delay time may be set as required, thereby further improving the anti-interference capability and performing delay control on the on and off time of MN3.

[0074] Figure 8 The corresponding logic sequence is as follows Fig. 9 As shown, an upper bridge shutdown signal is input at the HIN port, and is transmitted to IN_A after a delay time td1. After a delay time td2, the HO terminal signal starts to drop from a high level to V TH，L When IN_A is low and the voltage of the HO signal is higher than V TH，L When OUT is on, OUT outputs a low level and MN3 is turned off. In other time periods, OUT outputs a high level and MN3 is turned on.

[0075] Another control logic mode of the control sub-circuit 150 is: only when it is detected that IN_A is an output shutdown signal and it is detected that the voltage of the HO terminal signal is between the first preset voltage V TH，L and the second preset voltage V TH，H MN3 is turned off when the time is between 1 and 2, and turned on at other times. The corresponding logic sequence is as follows: Fig.10 shown.

[0076] The high-voltage integrated circuit of the embodiment of the present invention can improve the VS's ability to resist negative voltage overshoot through the setting of the resistor subcircuit and the switch subcircuit, and the resistor subcircuit and the switch subcircuit are integrated into the high-voltage integrated circuit, which can be easily applied in the intelligent power module to improve the performance of the intelligent power module, and can also be used in a discrete power inverter system. At the same time, the resistor subcircuit is not limited to the bootstrap resistor, and has a larger value range, which will not cause the circuit to be directly connected when it starts, and makes the VS better in resisting negative voltage overshoot; it has little effect on the speed of charging and discharging the bootstrap capacitor, and even because it is integrated in the high-voltage integrated circuit, it can not affect the charging and discharging speed of the bootstrap capacitor.

[0077] Fig.11 4 is a structural block diagram of an intelligent power module according to an embodiment of the present invention.

[0078] like Fig.11 As shown, the intelligent power module 200 includes the high voltage integrated circuit 100 of the above embodiment.

[0079] In this embodiment, see Figure 2 The intelligent power module 200 also includes a high-voltage region power switch device and a low-voltage region power switch device.

[0080] The intelligent power module of the embodiment of the present invention can enhance the VS's ability to resist negative voltage overshoot and improve its own performance through the above-mentioned high-voltage integrated circuit, and will not cause the upper bridge and the lower bridge to be directly connected when the high-voltage integrated circuit is started, and has little or no effect on the charging and discharging speed of the bootstrap capacitor.

[0081] Fig.12 It is a structural block diagram of an electrical device according to an embodiment of the present invention.

[0082] like Fig.12 As shown, the electrical device 1000 includes the intelligent power module 200 of the above embodiment.

[0083] In this embodiment, the electrical device 1000 may be, but is not limited to, an air conditioner, a refrigerator, a washing machine, or other device including a three-phase motor, and the intelligent power module 100 may be used to drive the three-phase motor.

[0084] The electrical equipment of the embodiment of the present invention can enhance the VS's ability to resist negative voltage overshoot and improve its own performance through the above-mentioned high-voltage integrated circuit, and will not cause the upper bridge and the lower bridge to be directly connected when the high-voltage integrated circuit is started, which has little or no effect on the charging and discharging speed of the bootstrap capacitor.

[0085] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0086] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0087] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0088] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0089] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0090] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A high voltage integrated circuit, characterized in that: include: A high voltage driver subcircuit, a resistor subcircuit and a switch subcircuit; The high-voltage driving sub-circuit has a high-voltage input terminal, a high-voltage output terminal, a first power supply terminal and a second power supply terminal, wherein the high-voltage input terminal, the high-voltage output terminal, the first power supply terminal and the second power supply terminal are connected one-to-one with the high-voltage region input terminal, the high-voltage region output terminal, the positive terminal of the high-voltage region power supply and the high-voltage region ground terminal of the high-voltage integrated circuit, wherein when applied, an external bootstrap capacitor is connected between the positive terminal of the high-voltage region power supply and the high-voltage region ground terminal; The switch subcircuit is connected in parallel with the resistor subcircuit, the first end of the switch subcircuit is connected to the ground end of the high-voltage area, the second end of the switch subcircuit is connected to the high-voltage inverter half-bridge floating node of the high-voltage integrated circuit, and the control end of the switch subcircuit is used to input the target control signal.

2. The high voltage integrated circuit according to claim 1, characterized in that: The high-voltage driving subcircuit comprises a logic processing unit, a pulse generating unit, a high-voltage level shifting unit, a filtering unit, an RS trigger and a driving unit connected in sequence, the high-voltage input terminal of the logic processing unit is connected to the high-voltage area input terminal, the high-voltage output terminal of the driving unit is connected to the high-voltage area output terminal, and the circuit further comprises: A control subcircuit, wherein a first input terminal of the control subcircuit is connected to the output terminal or the R input terminal of the RS trigger, a second input terminal of the control subcircuit is connected to the output terminal of the driving unit, and an output terminal of the control subcircuit is connected to the control terminal of the switch subcircuit, and the control subcircuit is configured to output a target control signal for controlling the switch subcircuit to disconnect when the input signal at the first input terminal is a shutdown signal and the voltage value of the input signal at the second input terminal is within a preset voltage range.

3. The high voltage integrated circuit according to claim 1 or 2, characterized in that: The resistance subcircuit includes a first resistor, a first end of the first resistor is connected to the ground end of the high voltage region, and a second end of the first resistor is connected to the floating node of the high voltage inverter half bridge.

4. The high voltage integrated circuit according to claim 1 or 2, characterized in that: The switch subcircuit includes a first NMOS tube, the drain of the first NMOS tube serves as the first end of the switch subcircuit, the source of the first NMOS tube serves as the second end of the switch subcircuit, and the gate of the first NMOS tube serves as the control end of the switch subcircuit.

5. The high voltage integrated circuit according to claim 2, characterized in that: The preset voltage range includes greater than or equal to a first preset voltage, or greater than or equal to the first preset voltage and less than or equal to a second preset voltage, wherein the first preset voltage is less than the second preset voltage.

6. The high voltage integrated circuit according to claim 5, characterized in that: The control subcircuit comprises: a first control unit and a second control unit; The power supply terminal of the first control unit is connected to the positive terminal of the power supply in the high-voltage area, the ground terminal of the first control unit is connected to the ground terminal of the high-voltage area, the first input terminal of the first control unit is connected to the output terminal of the RS trigger, and the second input terminal of the first control unit is connected to the output terminal of the driving unit, and the first control unit is configured to generate a complementary first signal and a second signal according to the output signal of the RS trigger and the output signal of the driving unit; The power supply end of the second control unit is connected to the positive end of the high-voltage area power supply, the ground end of the second control unit is connected to the high-voltage inverter half-bridge floating node, the first input end of the second control unit is connected to the first output end of the first control unit, the second input end of the second control unit is connected to the second output end of the first control unit, the output end of the second control unit is connected to the control end of the switch sub-circuit, and the second control unit is configured to generate the target control signal according to the first signal and the second signal.

7. The high voltage integrated circuit according to claim 6, characterized in that: The first control unit includes: a first NOT gate, a first NAND gate, a comparator, a second NOT gate, a third NOT gate and a fourth NOT gate; The input end of the first NOT gate is connected to the output end of the RS trigger, and the output end of the first NOT gate is connected to the first input end of the first NAND gate; The inverting input terminal of the comparator is connected to the output terminal of the driving unit, the non-inverting input terminal of the comparator is connected to the positive electrode of the preset power supply, the power supply terminal of the comparator is connected to the positive terminal of the power supply of the high-voltage area, and the output terminal of the comparator is connected to the input terminal of the second NOT gate, wherein the negative electrode of the preset power supply is connected to the ground terminal of the high-voltage area, and the preset power supply is used to provide the first preset voltage; The output end of the second NOT gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the third NOT gate, the output end of the third NOT gate is connected to the input end of the fourth NOT gate and serves as the first output end of the first control unit, and the output end of the fourth NOT gate serves as the second output end of the first control unit.

8. The high voltage integrated circuit according to claim 6, characterized in that: The second control unit includes: a first N-type switch tube, a second N-type switch tube, a first P-type switch tube, a second P-type switch tube and a fifth NOT gate; The gate of the first N-type switch tube serves as the first input end of the second control unit, the drain of the first N-type switch tube is connected to the drain of the first P-type switch tube and the gate of the second P-type switch tube respectively, the gate of the second N-type switch tube serves as the second input end of the second control unit, the drain of the second N-type switch tube is connected to the gate of the first P-type switch tube, the drain of the second P-type switch tube and the input end of the fifth NOT gate respectively, the source of the first N-type switch tube and the source of the second N-type switch tube are connected to the high-voltage inverter half-bridge floating node, the source of the first P-type switch tube and the source of the second P-type switch tube are connected to the positive end of the high-voltage area power supply, and the output end of the fifth NOT gate serves as the output end of the second control unit.

9. The high voltage integrated circuit according to claim 7, characterized in that: The first control unit further includes: a voltage regulator tube, wherein an anode of the voltage regulator tube is connected to the floating node of the high-voltage inverter half-bridge, and a cathode of the voltage regulator tube is connected to the ground end of the high-voltage region.

10. The high voltage integrated circuit according to claim 7, characterized in that: The first control unit also includes: a delay filter, the delay filter includes a filter resistor and a filter capacitor, the first end of the filter resistor is connected to the output end of the driving unit, the second end of the filter resistor is connected to the inverting input end of the comparator, the first end of the filter capacitor is connected to the second end of the filter resistor, and the second end of the filter capacitor is connected to the ground end of the high voltage area.

11. An intelligent power module, characterized in that: Comprising the high voltage integrated circuit as claimed in any one of claims 1 to 10.

12. An electrical device, characterized in that: Comprising the intelligent power module as claimed in claim 11.

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