Six-bit ultra-wideband active numerical control phase shifter with low root-mean-square phase and gain error

Abstract

The invention provides a 6-bit ultra-wideband low-root-mean-square phase and gain error active numerical control phase shifter, which adopts a TSMC 180nm RF CMOS (Radio Frequency Complementary Metal-Oxide-Semiconductor Transistor) process, and mainly comprises an orthogonal decomposition network and a vector synthesizer, the orthogonal decomposition network is used for generating signals with a phase difference of 90 degrees, and the vector synthesizer is used for carrying out polarity selection and gain control on orthogonal signals. Wherein the vector synthesizer comprises an analog adder and a current mirror array control circuit. The orthogonal decomposition network adopts an RC-RL multi-phase filter structure, and the vector synthesizer comprises an analog adder based on a Gilbert unit and a control circuit based on a dual-path current mirror array. The differential signals are converted into two paths of orthogonal signals through an orthogonal decomposition network, wherein the amplitudes of the two paths are equal and the phase difference is 90 degrees. In a vector synthesizer, a quadrant of vector synthesis is selected by polarity selection of an orthogonal differential signal. And the synthesized output signal has an expected phase and a constant amplitude through amplitude modulation of the two paths of orthogonal signals.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a design of a 6-bit ultra-wideband low root mean square phase and gain error active digital controlled phase shifter. Background Art

[0002] The phased array system is a multi-array antenna system that realizes electronic scanning by changing the amplitude or phase information of the electrical signal transmitted or received by each antenna in the array to change the direction and intensity of the array equivalent beam. With the continuous development of microwave millimeter wave integrated circuit technology, the phased array system is also constantly developing towards higher frequency bands, multi-functions, high integration, high performance, low power consumption and small size. The phase shifter is the core unit that can change the phase of the signal in the phased array system. Its research and design have important academic significance and application value for the development of the phased array system. The digitally controlled phase shifter can be divided into passive and active types. In order to achieve higher phase shifting accuracy over an ultra-wide operating bandwidth, the scale of the passive phase shifter has increased dramatically and is not suitable for integrated phased array systems on chips. In contrast, the active digitally controlled phase shifter has a wider operating frequency band, higher phase shifting accuracy and smaller size, which can achieve low cost and high integration. However, there are problems of low accuracy, large root mean square phase error and root mean square gain error. Summary of the invention

[0003] The technical problem to be solved by the present invention is to solve the problems of low-quality orthogonal signals and high insertion loss in the ultra-wide band of the current mainstream orthogonal decomposition network and to improve the control accuracy of the control circuit in the vector synthesizer. In order to solve the above problems, a 6-bit ultra-wideband low root mean square phase and gain error active digital controlled phase shifter is provided.

[0004] The object of the present invention is achieved in the following manner:

[0005] A 6-bit ultra-wideband low root mean square phase and gain error active digital controlled phase shifter comprises an orthogonal decomposition network and a vector synthesizer. The orthogonal decomposition network adopts an RC-RL multiphase filter structure. The vector synthesizer comprises an analog adder based on a Gilbert unit and a control circuit based on a dual-channel current mirror array. The analog adder module is composed of two-channel I and Q Gilbert units introduced with a switch tube. The input ends of the I and Q Gilbert unit circuits are respectively connected to the in-phase differential signals I+ and I- and the orthogonal differential signals Q+ and Q- generated by the orthogonal decomposition network. The tail current I of the two Gilbert units is changed by the current mirror array control circuit. I with I Q The proportional relationship between the sizes of can be used to synthesize signals with different phase shifts at the output end.

[0006] The RC-RL polyphase filter comprises four-stage circuits, namely, first-stage, third-stage, fourth-stage RC polyphase filters and a second-stage RL polyphase filter.

[0007] The RC-RL multiphase filter includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R41, a resistor R42, a resistor R43, and a resistor R44; a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C41, a capacitor C42, a capacitor C43, a capacitor C44 and an inductor L12, an inductor L12, an inductor L13, and an inductor L14; an input signal IN+ is connected to the left end of the resistor R11, the left plate of the capacitor C11, the resistor R12 The left end of the resistor R13 and the left plate of the capacitor C12; the input signal IN- is connected to the left end of the resistor R13, the left plate of the capacitor C13, the left end of the resistor R14, and the left plate of the capacitor C14; the right plate of the capacitor C11 is connected to the right end of the resistor R12, the right plate of the capacitor C12 is connected to the right end of the resistor R13, the right plate of the capacitor C13 is connected to the right end of the resistor R14, and the right plate of the capacitor C14 is connected to the right end of the resistor R11; the right end of the resistor R11 is connected to the left end of the resistor R21, the right end of the resistor R21 is connected to the left end of the resistor R22, the right end of the resistor R13 is connected to the left end of the resistor R23, and the right end of the resistor R14 is connected to the left end of the resistor R24; the right end of the inductor L11 is connected to the right end of the resistor R21, and the left end is connected to the resistor R The left end of the inductor L12 is connected to the right end of the resistor R22, and the left end is connected to the left end of the resistor R23. The right end of the inductor L13 is connected to the right end of the resistor R23, and the left end is connected to the left end of the resistor R24. The right end of the inductor L14 is connected to the right end of the resistor R24, and the left end is connected to the left end of the resistor R21. The right end of the resistor R21 is connected to the left end of the resistor R31 and the left plate of the capacitor C31. The right end of the resistor R22 is connected to the left end of the resistor R32 and the left plate of the capacitor C32. The right end of the resistor R23 is connected to the left end of the resistor R33 and the left plate of the capacitor C33. The right end of the resistor R24 ​​is connected to the left end of the resistor R34 and the left plate of the capacitor C34. The right plate of the capacitor C31 is connected to the right end of the resistor R32, and the right end of the capacitor C32 is connected to the left end of the resistor R32. The plate is connected to the right end of the resistor R33, the right plate of the capacitor C33 is connected to the right end of the resistor R34, and the right plate of the capacitor C34 is connected to the right end of the resistor R31; the right end of the resistor R31 is connected to the left end of the resistor R41 and the left plate of the capacitor C41, the right end of the resistor R32 is connected to the left end of the resistor R42 and the left plate of the capacitor C42, the right end of the resistor R33 is connected to the left end of the resistor R43 and the left plate of the capacitor C43, and the right end of the resistor R34 is connected to the left end of the resistor R44 and the left plate of the capacitor C44; the right plate of the capacitor C41 is connected to the right end of the resistor R42, the right plate of the capacitor C42 is connected to the right end of the resistor R43, the right plate of the capacitor C43 is connected to the right end of the resistor R44, and the right plate of the capacitor C44 is connected to the right end of the resistor R41;The right end of the resistor R41 is connected to the I+ signal output, the right end of the resistor R42 is connected to the Q+ signal output, the right end of the resistor R43 is connected to the I- signal output, and the right end of the resistor R44 is connected to the Q- signal output. ;

[0008] The analog adder includes a third-layer amplification synthesis NMOS tubes M3, M4, M5, M6, M7, M8, M9, M10, a second-layer quadrant selection NMOS tubes M11, M12, M13, M14, a first-layer tail current NMOS tubes M15, M16; and NMOS tubes M1, M2 acting as active inductors, resistors R1, R2, switches SI, SIB, SQ, SQB; in the I path, a 1.8V power supply is connected to the upper end of R1 and the drain of M1, and the The lower end is connected to the gate of M1, and the source of M1 is connected to the OUT+ output signal; the OUT+ output signal is connected to the drains of M4, M6, M8, and M10; the I+ input is connected to the gates of M3 and M6, and the I- input is connected to the gates of M4 and M5; the sources of M3 and M4 are connected to the drain of M11, and the gate of M11 is connected to the left end of SI on the left and the upper end of SIB; the sources of M5 and M6 are connected to the drain of M12, and the gate of M12 is connected to the right end of SIB on the right and the upper end of SI; the bias voltage V bias，I Connect the right end of SI on the upper side and the left end of SIB, and the ground is connected to the lower end of SIB on the lower side and the lower end of SI; the source of M11 and M12 is connected to the drain of M15, and the gate of M15 is connected to V mirror，I Bias voltage, source connected to ground; in the Q path, the 1.8V power supply is connected to the upper end of R2 and the drain of M2, the lower end of R2 is connected to the gate of M2, and the source of M2 is connected to the OUT- output signal; the OUT- output signal is connected to the drain of M3, M5, M7, and M9; the Q+ input is connected to the gate of M7 and M10, and the Q- input is connected to the gate of M8 and M9; the source of M7 and M8 is connected to the drain of M13, and the gate of M13 is connected to the left end of SQ on the left and the upper end of SQB; the source of M9 and M10 is connected to the drain of M14, and the gate of M14 is connected to the right end of SQB on the right and the upper end of SQ; the bias voltage V bias，Q Connect the right end of the upper side SQ and the left end of SQB, and the ground is connected to the lower end of the lower side SQB and the lower end of SQ; the source of M13 and M14 is connected to the drain of M16, and the gate of M16 is connected to V mirror，Q Bias voltage, source connected to ground.

[0009] The current mirror array circuit includes two current mirror arrays, I and Q. The I path includes PMOS tubes M01, M02, M11, M12, M21, M22, M31, M32, M41, M42, M51, M52, M61, M62, switches S0, S0N, S1, S1N, S2, S2N, S3, S3N, S4, S4N, S5, S5N, S6, S6N; the Q path includes PMOS tubes M71, M72, M81, M 82, M91, M92, M101, M102, M111, M112, M121, M122, M131, M132, switches S7, S7N, S8, S8N, S9, S9N, S10, S10N, S11, S11N, S12, S12N, S13, S13N; current synthesis PMOS tubes MI1, MI2, MQ1, MQ2 and current source IREF, PMOS tubes MREF1, MREF2;

[0010] The 1.8V power supply is connected to the drain of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131, MREF1 and the upper end of S0N, S1N, S2N, S3N, S4N, S5N, S6N, S7N, S8N, S9N, S10N, S11N, S12N, S13N; the gate of MREF1 is connected to the source of MREF1 and the gates of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131; the source of M01 is connected to the drain of M02, M11 The source of MREF1 is connected to the drain of MREF2; the source of M21 is connected to the drain of M22; the source of M31 is connected to the drain of M32; the source of M41 is connected to the drain of M42; the source of M51 is connected to the drain of M52; the source of M61 is connected to the drain of M62; the source of M71 is connected to the drain of M72; the source of M81 is connected to the drain of M82; the source of M91 is connected to the drain of M92; the source of M101 is connected to the drain of M102; the source of M111 is connected to the drain of M112; the source of M121 is connected to the drain of M122; the source of M131 is connected to the drain of M132; the source of MREF1 is connected to the drain of MREF2; the gate of M02 is connected to the lower end of S0N and the upper end of S0; The gate of M12 is connected to the lower end of S1N and the upper end of S1, the gate of M22 is connected to the lower end of S2N and the upper end of S2, the gate of M32 is connected to the lower end of S3N and the upper end of S3, the gate of M42 is connected to the lower end of S4N and the upper end of S4, the gate of M52 is connected to the lower end of S5N and the upper end of S5, the gate of M62 is connected to the lower end of S6N and the upper end of S6, the gate of M72 is connected to the lower end of S7N and the upper end of S7, the gate of M82 is connected to the lower end of S8N and the upper end of S8, the gate of M92 is connected to the lower end of S9N and the upper end of S9, the gate of M102 is connected to the lower end of S10N and the upper end of S10, the gate of M112 is connected to the lower end of S11N and the upper end of S11, and the gate of M12 is connected to the lower end of S1 The gate of 2 is connected to the lower end of S12N and the upper end of S12, and the gate of M132 is connected to the lower end of S13N and the upper end of S13; the gate of MREF2 is connected to the source of MREF2 and the lower ends of S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, and S13; the source of MREF2 is connected to the upper end of the 100μA current source, and the lower end of the 100μA current source is connected to the ground; the source of M02, M12, M22, M32, M42, M52, and M62 is connected to the drain of MI1, the drain of MI1 is connected to the gate of MI1, the source of MI1 is connected to the drain of MI2, the drain of MI2 is connected to the gate of MI2, and the source of MI2 is grounded;The sources of M72, M82, M92, M102, M112, M122 and M132 are connected to the drain of MQ1, the drain of MQ1 is connected to the gate of MQ1, the source of MQ1 is connected to the drain of MQ2, the drain of MQ2 is connected to the gate of MQ2, and the source of MQ2 is grounded. ;

[0011] Beneficial effects of the present invention: In the present invention, the orthogonal decomposition network uses an RC-RL multiphase filter to generate two pairs of orthogonal vectors with high orthogonal accuracy over a wide frequency band, and reduces the insertion loss by reducing the inter-stage mismatch. The orthogonal signal is then input into an analog adder based on a Gilbert unit, and the tail current ratio of its I and Q paths is adjusted through a current mirror array control circuit to achieve a signal phase shift with a 6-bit phase resolution between 0-360°. The current array independently controls the currents of the I and Q paths, so that the two current paths can simultaneously meet the ratio that accurately approximates the theoretical value, thereby reducing the phase shift and gain errors of the phase shifter. The present invention solves the difficulty of generating high-quality orthogonal signals and performing more accurate vector synthesis over an ultra-wide operating frequency band, so as to meet the application requirements of ultra-wideband, low root mean square phase and gain errors of digitally controlled phase shifters. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The basic principle block diagram of the 6-bit ultra-wideband low root mean square phase and gain error active digital controlled phase shifter of the present invention is shown.

[0013] Figure 2 2 is a schematic diagram of an orthogonal decomposition network circuit of an embodiment.

[0014] Figure 3 FIG. 4 is a schematic diagram of an analog adder circuit of an embodiment.

[0015] Figure 4 2 is a schematic diagram of a control circuit of an embodiment.

[0016] Figure 5 The signal phase shift simulation diagram of 64 phase states of a 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter.

[0017] Figure 6 The signal gain simulation diagram of 64 phase states of the 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter.

[0018] Figure 7 This is the RMS phase error simulation diagram of a 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter.

[0019] Figure 8 The RMS gain error simulation diagram of the 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter. DETAILED DESCRIPTION

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0022] The present invention proposes a 6-bit ultra-wideband low root mean square phase and gain error active digital controlled phase shifter, which adopts TSMC 180nm RF CMOS process, and its main circuit includes two parts: an orthogonal decomposition network that mainly generates signals with a phase difference of 90 degrees and a vector synthesizer that performs polarity selection and gain control on the orthogonal signal, wherein the vector synthesizer includes an analog adder and a current mirror array control circuit. The orthogonal decomposition network adopts an RC-RL multi-phase filter structure, and the vector synthesizer includes an analog adder based on a Gilbert unit and a control circuit based on a dual-channel current mirror array. The differential signal is converted into two orthogonal signals with equal amplitudes and a phase difference of 90 degrees through the orthogonal decomposition network. In the vector synthesizer, the quadrant of vector synthesis is selected by selecting the polarity of the orthogonal differential signal. The synthesized output signal has a desired phase and a constant amplitude by amplitude modulation of the two-channel orthogonal signals.

[0023] The specific implementation example of the present invention is Figure 2 , Figure 3 , Figure 4 shown.

[0024] like Figure 2 As shown, the RC-RL multi-phase filter includes resistors R11, R12, R13, R14, R21, R22, R23, R24, R31, R32, R33, R34, R41, R42, R43, R44; capacitors C11, C12, C13, C14, C31, C32, C33, C34, C41, C42, C43, C44 and inductors L12, L12, L13, L14.

[0025] The input signal IN+ is connected to the left end of R11, the left plate of C11, the left end of R12, and the left plate of C12; the input signal IN- is connected to the left end of R13, the left plate of C13, the left end of R14, and the left plate of C14; the right plate of C11 is connected to the right end of R12, the right plate of C12 is connected to the right end of R13, the right plate of C13 is connected to the right end of R14, and the right plate of C14 is connected to the right end of R11; the right end of R11 is connected to the left end of R21, and the right end of R21 is connected to R22 The left end of L11 is connected to the right end of R21, and the left end is connected to the left end of R22. The right end of L12 is connected to the right end of R22, and the left end is connected to the left end of R23. The right end of L13 is connected to the right end of R23, and the left end is connected to the left end of R24. The right end of L14 is connected to the right end of R24, and the left end is connected to the left end of R21. The right end of R21 is connected to the left end of R31 and the left plate of C31. The right end of R22 is connected to the right end of R31 and the left plate of C31. The right end of R23 is connected to the left end of R33 and the left plate of C33, the right end of R24 is connected to the left end of R34 and the left plate of C34; the right plate of C31 is connected to the right end of R32, the right plate of C32 is connected to the right end of R33, the right plate of C33 is connected to the right end of R34, and the right plate of C34 is connected to the right end of R31; the right end of R31 is connected to the left end of R41 and the left plate of C41, and the right end of R32 is connected to the left end of R42 and the left plate of C42. , the right end of R33 is connected to the left end of R43 and the left plate of C43, the right end of R34 is connected to the left end of R44 and the left plate of C44; the right plate of C41 is connected to the right end of R42, the right plate of C42 is connected to the right end of R43, the right plate of C43 is connected to the right end of R44, and the right plate of C44 is connected to the right end of R41; the right end of R41 is connected to the I+ signal output, the right end of R42 is connected to the Q+ signal output, the right end of R43 is connected to the I- signal output, and the right end of R44 is connected to the Q- signal output.

[0026] The RC-RL multiphase filter designed by the present invention comprises a four-stage circuit, wherein the first, third and fourth stages are RC multiphase filter structures, and the second stage is RL multiphase filter structure, and the sizes of the resistors, capacitors and inductors in the same stage are equal. The impedance of the RC stage has an imaginary capacitive part, and the impedance of the RL stage has an imaginary inductor part. In order to minimize the impedance mismatch to obtain low insertion loss and orthogonal signal error at the fundamental frequency, R1 must be equal to R2. For a single-stage differential RL multiphase filter without capacitive load, the characteristics of the orthogonal phase difference and amplitude imbalance are similar to those of the RC multiphase filter. At the angular frequency of ω0=R2 / L1, the orthogonal signal amplitude mismatch is zero, and the insertion loss is estimated to be 3dB. This results in L1C1=1 / ω0 2 The bandwidth of the quadrature signals of the RC-RC and RC-RL polyphase filters is exactly the same. Figure 2 The I+, Q+, I-, Q- outputs in Figure 3 The I+, Q+, I-, and Q- inputs are connected one by one.

[0027] In the orthogonal decomposition network, the traditional RC multiphase filter has a high insertion loss, especially in the ultra-wideband. In order to meet the bandwidth requirements, multi-stage cascade is often required, and the insertion loss will increase with the increase of the number of stages. This insertion loss is attributed to the impedance mismatch between each stage. In order to reduce this huge insertion loss, we use an RC-RL multiphase filter structure. The first-order RL multiphase filter and the RC multiphase filter have the same working bandwidth, and can provide a capacitive imaginary part for the impedance of the RC stage, and the RL stage impedance can provide an inductor imaginary part, which can reduce the impedance mismatch between stages. The RC-RL multiphase filter of the present invention can generate high-quality orthogonal signals over an ultra-wideband, and greatly reduces the insertion loss compared to the fourth-order RC multiphase filter.

[0028] Figure 3 The analog adder module includes the third-layer amplification synthesis NMOS tubes M3, M4, M5, M6, M7, M8, M9, and M10, the second-layer quadrant selection NMOS tubes M11, M12, M13, and M14, and the first-layer tail current NMOS tubes M15 and M16. In addition, the NMOS tubes M1 and M2 acting as active inductors, resistors R1 and R2, and switches SI, SIB, SQ, and SQB.

[0029] In the I path, the 1.8V power supply is connected to the upper end of R1 and the drain of M1, the lower end of R1 is connected to the gate of M1, and the source of M1 is connected to the OUT+ output signal; the OUT+ output signal is connected to the drains of M4, M6, M8, and M10; the I+ input is connected to the gates of M3 and M6, and the I- input is connected to the gates of M4 and M5; the sources of M3 and M4 are connected to the drain of M11, and the gate of M11 is connected to the left end of SI on the left and the upper end of SIB; the sources of M5 and M6 are connected to the drain of M12, and the gate of M12 is connected to the right end of SIB on the right and the upper end of SI; the bias voltage V bias，I Connect the right end of SI on the upper side and the left end of SIB, and the ground is connected to the lower end of SIB on the lower side and the lower end of SI; the source of M11 and M12 is connected to the drain of M15, and the gate of M15 is connected to V mirror，IBias voltage, source connected to ground. In the Q path, the 1.8V power supply is connected to the upper end of R2 and the drain of M2, the lower end of R2 is connected to the gate of M2, and the source of M2 is connected to the OUT- output signal; the OUT- output signal is connected to the drains of M3, M5, M7, and M9; the Q+ input is connected to the gates of M7 and M10, and the Q- input is connected to the gates of M8 and M9; the sources of M7 and M8 are connected to the drain of M13, and the gate of M13 is connected to the left end of SQ on the left and the upper end of SQB; the sources of M9 and M10 are connected to the drain of M14, and the gate of M14 is connected to the right end of SQB on the right and the upper end of SQ; the bias voltage V bias，Q Connect the right end of the upper side SQ and the left end of SQB, and the ground is connected to the lower end of the lower side SQB and the lower end of SQ; the source of M13 and M14 is connected to the drain of M16, and the gate of M16 is connected to V mirror，Q Bias voltage, source connected to ground.

[0030] The analog adder designed by the present invention mainly includes two Gilbert units, and the quadrant of vector synthesis is selected by selecting the polarity of the orthogonal differential signal. The summed output signal has a desired phase and a constant amplitude by amplitude modulation of the two orthogonal signals. A three-layer NMOS tube design is required, and the voltage margin requirement is relatively high. The voltage distribution first satisfies that the third layer of NMOS tubes (M3-M10) for amplifying and synthesizing the signal is in the saturation region. The gate V of the second and first layer NMOS tubes (M11-M16) is bias，I 、V bias，Q 、V mirror，I 、V mirror，I and Figure 4 The output V of the control circuit bias，I 、V bias，Q 、V mirror，I 、V mirror，I Active inductance is used in analog adders to achieve inductance peaking, which improves the operating frequency and bandwidth of the analog adder and compensates for the decrease in high-frequency gain.

[0031] If the size of the MOS transistor used for signal amplification is W / L, and the secondary effect of the MOS tube is not considered, the transconductance of the MOS tube in the saturated state is in Vector synthesizer voltage output formula:

[0032]

[0033] If the orthogonal signals are completely orthogonal, the equation can be written as:

[0034]

[0035] Then the vector synthesizer output gain and phase can be obtained:

[0036]

[0037]

[0038] The analog adder module in the vector synthesizer of the present invention is mainly realized by two Gilbert units. The analog adder module is composed of two Gilbert units I and Q introduced with switch tubes. The input ends of the I and Q Gilbert unit circuits are respectively connected to the in-phase differential signals I+, I- and the orthogonal differential signals Q+, Q- generated by the orthogonal decomposition network. Since the output ends of the I and Q Gilbert units are connected to the same load, the tail current I of the two Gilbert units is changed by changing the tail current I I with I Q By controlling the switch tubes SI, SIB, SQ and SQB, the signal synthesis in four quadrants can be realized, so that the phase shifter can achieve a phase shift range of 360°.

[0039] The control circuit in the vector synthesizer uses a dual current mirror array. Considering various non-ideal effects of integrated circuits, including channel length modulation effect; threshold voltage deviation between two tubes; non-ideal geometric mismatch, the basic current mirror cannot produce accurate current values. Therefore, the designed current mirror array circuit is composed of common source and common gate current mirrors.

[0040] By ensuring that the sum of the tail currents of the two Gilbert units in the analog adder remains unchanged and adjusting the tail current ratio, the phase of the vector can be changed without changing the amplitude. We copy the current of each path to both I and Q paths at the same time, so that the current flowing into I I and I Q The currents of the two paths can be controlled independently, so that the two currents can simultaneously meet the two constraints that the ratio is accurately close to the theoretical value and the sum of the currents remains unchanged, which is very helpful in reducing the phase shift error and gain error of the phase shifter.

[0041] Figure 4The current mirror array control circuit includes two current arrays, I and Q. The I path includes PMOS tubes M01, M02, M11, M12, M21, M22, M31, M32, M41, M42, M51, M52, M61, M62, switches S0, S0N, S1, S1N, S2, S2N, S3, S3N, S4, S4N, S5, S5N, S6, S 6N; Q circuit includes PMOS tubes M71, M72, M81, M82, M91, M92, M101, M102, M111, M112, M121, M122, M131, M132, switches S7, S7N, S8, S8N, S9, S9N, S10, S10N, S11, S11N, S12, S12N, S13, S13N. Current synthesis PMOS tubes MI1, MI2, MQ1, MQ2, current source IREF, PMOS tubes MREF1, MREF2.

[0042] The 1.8V power supply is connected to the drain of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131, MREF1 and the upper end of S0N, S1N, S2N, S3N, S4N, S5N, S6N, S7N, S8N, S9N, S10N, S11N, S12N, S13N; the gate of MREF1 is connected to the source of MREF1 and the gates of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131; the source of M01 is connected to the drain of M02, M11 The source of MREF1 is connected to the drain of MREF2; the source of M21 is connected to the drain of M22; the source of M31 is connected to the drain of M32; the source of M41 is connected to the drain of M42; the source of M51 is connected to the drain of M52; the source of M61 is connected to the drain of M62; the source of M71 is connected to the drain of M72; the source of M81 is connected to the drain of M82; the source of M91 is connected to the drain of M92; the source of M101 is connected to the drain of M102; the source of M111 is connected to the drain of M112; the source of M121 is connected to the drain of M122; the source of M131 is connected to the drain of M132; the source of MREF1 is connected to the drain of MREF2; the gate of M02 is connected to the lower end of S0N and the upper end of S0; The gate of M12 is connected to the lower end of S1N and the upper end of S1, the gate of M22 is connected to the lower end of S2N and the upper end of S2, the gate of M32 is connected to the lower end of S3N and the upper end of S3, the gate of M42 is connected to the lower end of S4N and the upper end of S4, the gate of M52 is connected to the lower end of S5N and the upper end of S5, the gate of M62 is connected to the lower end of S6N and the upper end of S6, the gate of M72 is connected to the lower end of S7N and the upper end of S7, the gate of M82 is connected to the lower end of S8N and the upper end of S8, the gate of M92 is connected to the lower end of S9N and the upper end of S9, the gate of M102 is connected to the lower end of S10N and the upper end of S10, the gate of M112 is connected to the lower end of S11N and the upper end of S11, and the gate of M12 is connected to the lower end of S1 The gate of 2 is connected to the lower end of S12N and the upper end of S12, and the gate of M132 is connected to the lower end of S13N and the upper end of S13; the gate of MREF2 is connected to the source of MREF2 and the lower ends of S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, and S13; the source of MREF2 is connected to the upper end of the 100μA current source, and the lower end of the 100μA current source is connected to the ground; the source of M02, M12, M22, M32, M42, M52, and M62 is connected to the drain of MI1, the drain of MI1 is connected to the gate of MI1, the source of MI1 is connected to the drain of MI2, the drain of MI2 is connected to the gate of MI2, and the source of MI2 is grounded;The sources of M72, M82, M92, M102, M112, M122 and M132 are connected to the drain of MQ1, the drain of MQ1 is connected to the gate of MQ1, the source of MQ1 is connected to the drain of MQ2, the drain of MQ2 is connected to the gate of MQ2, and the source of MQ2 is grounded. ;

[0043] The current array control circuit designed in the present invention has six control bits. For the six-bit active digital phase shifter, the phase shift step is 5.625°. Due to the periodicity of trigonometric functions and the characteristics of tangent functions, the current array only needs to realize the ratio of 8 currents, so the current array only needs 7 channels to meet the application, and the current value ratio of the seven channels is 1:2:4:8:16:32:64. By ensuring that the sum of the tail currents of the two Gilbert units remains unchanged and adjusting the ratio of the tail currents, the phase of the vector can be changed without changing the amplitude. We optimize the circuit and copy the current of each channel to both I and Q channels at the same time, so that the current flowing into I I and I Q The currents of the two paths can be controlled independently, so that the two currents can simultaneously satisfy the two constraints that the ratio is accurately close to the theoretical value and the sum of the currents remains unchanged.

[0044] The current mirror array circuit and the switch of the analog adder tail current are combined to change the phase of the output signal. First, by selecting the on and off of switches SI, SIB, SQ and SQB, the presence or absence of tail currents in the I and Q paths is determined, and then the corresponding four quadrants of the output signal are controlled, which are 0~π / 2, π / 2~π, π~3π / 2, and 3π / 2~2π respectively; then, by controlling the on and off of the switches of the current mirror array circuit S0(N)~S13(N), different I and Q current ratios are generated, thereby subdividing the required phase shift states in the four quadrants, and finally achieving a 6-bit phase shift in the range of 0~2π.

[0045] Figure 5 This is a simulation diagram of the signal phase shift of 64 phases of a 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter. Figure 6 It is a signal gain simulation diagram of 64 phase states of a 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter. Figure 7 This is a simulation diagram of the RMS phase error of a 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter. Figure 8 The following is a simulation diagram of the RMS gain error of a 6-bit ultra-wideband low RMS phase and gain error active digital controlled phase shifter. The simulation results show that the RMS phase error is <5° at 2-18GHz (<3.5° at 2-10GHz), and the RMS gain error is <0.83dB at 2-18GHz. According to all the performance data, the proposed active digital controlled phase shifter has a wide operating bandwidth and has small low RMS phase error and gain error.

[0046] The above is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several changes and improvements can be made without departing from the overall concept of the present invention, which should also be regarded as the scope of protection of the present invention.

Claims

1. A 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter, comprising an orthogonal decomposition network and a vector synthesizer, characterized in that: The orthogonal decomposition network adopts an RC-RL multiphase filter structure, and the vector synthesizer includes an analog adder based on a Gilbert unit and a control circuit based on a dual-channel current mirror array; the analog adder module is composed of two-channel Gilbert units I and Q introduced into the switch tube, and the input ends of the two-channel Gilbert unit circuits I and Q are respectively connected to the in-phase differential signals I + , I - and the orthogonal differential signals Q + , Q - generated by the orthogonal decomposition network; The tail current I of two Gilbert cells is changed by the current mirror array control circuit I with I Q The proportional relationship between the sizes of can be used to synthesize signals with different phase shifts at the output end.

2. The 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter according to claim 1, characterized in that: The RC-RL polyphase filter comprises four-stage circuits, namely, first-stage, third-stage, fourth-stage RC polyphase filters and a second-stage RL polyphase filter.

3. The 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter according to claim 2, characterized in that: The RC-RL multiphase filter includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R41, a resistor R42, a resistor R43, and a resistor R44; a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C34, a capacitor C41, a capacitor C42, a capacitor C43, a capacitor C44 and an inductor L12, an inductor L12, an inductor L13, and an inductor L14; an input signal IN+ is connected to the left end of the resistor R11, the left plate of the capacitor C11, the resistor R12 The left end of the resistor R13 and the left plate of the capacitor C12; the input signal IN- is connected to the left end of the resistor R13, the left plate of the capacitor C13, the left end of the resistor R14, and the left plate of the capacitor C14; the right plate of the capacitor C11 is connected to the right end of the resistor R12, the right plate of the capacitor C12 is connected to the right end of the resistor R13, the right plate of the capacitor C13 is connected to the right end of the resistor R14, and the right plate of the capacitor C14 is connected to the right end of the resistor R11; the right end of the resistor R11 is connected to the left end of the resistor R21, the right end of the resistor R21 is connected to the left end of the resistor R22, the right end of the resistor R13 is connected to the left end of the resistor R23, and the right end of the resistor R14 is connected to the left end of the resistor R24; the right end of the inductor L11 is connected to the right end of the resistor R21, and the left end is connected to the resistor R The left end of the inductor L12 is connected to the right end of the resistor R22, and the left end is connected to the left end of the resistor R23. The right end of the inductor L13 is connected to the right end of the resistor R23, and the left end is connected to the left end of the resistor R24. The right end of the inductor L14 is connected to the right end of the resistor R24, and the left end is connected to the left end of the resistor R21. The right end of the resistor R21 is connected to the left end of the resistor R31 and the left plate of the capacitor C31. The right end of the resistor R22 is connected to the left end of the resistor R32 and the left plate of the capacitor C32. The right end of the resistor R23 is connected to the left end of the resistor R33 and the left plate of the capacitor C33. The right end of the resistor R24 ​​is connected to the left end of the resistor R34 and the left plate of the capacitor C34. The right plate of the capacitor C31 is connected to the right end of the resistor R32, and the right end of the capacitor C32 is connected to the left end of the resistor R32. The plate is connected to the right end of the resistor R33, the right plate of the capacitor C33 is connected to the right end of the resistor R34, and the right plate of the capacitor C34 is connected to the right end of the resistor R31; the right end of the resistor R31 is connected to the left end of the resistor R41 and the left plate of the capacitor C41, the right end of the resistor R32 is connected to the left end of the resistor R42 and the left plate of the capacitor C42, the right end of the resistor R33 is connected to the left end of the resistor R43 and the left plate of the capacitor C43, and the right end of the resistor R34 is connected to the left end of the resistor R44 and the left plate of the capacitor C44; the right plate of the capacitor C41 is connected to the right end of the resistor R42, the right plate of the capacitor C42 is connected to the right end of the resistor R43, the right plate of the capacitor C43 is connected to the right end of the resistor R44, and the right plate of the capacitor C44 is connected to the right end of the resistor R41;The right end of the resistor R41 is connected to the I+ signal output, the right end of the resistor R42 is connected to the Q+ signal output, the right end of the resistor R43 is connected to the I- signal output, and the right end of the resistor R44 is connected to the Q- signal output. ; 4. The 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter according to claim 1, characterized in that: The analog adder includes a third layer of amplification synthesis NMOS tubes M3, M4, M5, M6, M7, M8, M9, M10, a second layer of quadrant selection NMOS tubes M11, M12, M13, M14, a first layer of tail current NMOS tubes M15, M16; and NMOS tubes M1, M2 acting as active inductors, resistors R1, R2, switches SI, SIB , SQ, SQB; in the I path, the 1.8V power supply is connected to the upper end of R1 and the drain of M1, the lower end of R1 is connected to the gate of M1, and the source of M1 is connected to the OUT+ output signal; the OUT+ output signal is connected to the drain of M4, M6, M8, and M10; the I+ input is connected to the gate of M3 and M6, and the I- input is connected to the gate of M4 and M5; the source of M3 and M4 is connected to the drain of M11, and the gate of M11 is connected to the left end of SI on the left and the upper end of SIB; the source of M5 and M6 is connected to the drain of M12, and the gate of M12 is connected to the right end of SIB on the right and the upper end of SI; the bias voltage V bias，I Connect the right end of SI on the upper side and the left end of SIB, and the ground is connected to the lower end of SIB on the lower side and the lower end of SI; the source of M11 and M12 is connected to the drain of M15, and the gate of M15 is connected to V mirror，I Bias voltage, source connected to ground; in the Q path, the 1.8V power supply is connected to the upper end of R2 and the drain of M2, the lower end of R2 is connected to the gate of M2, and the source of M2 is connected to the OUT- output signal; the OUT- output signal is connected to the drain of M3, M5, M7, and M9; the Q+ input is connected to the gate of M7 and M10, and the Q- input is connected to the gate of M8 and M9; the source of M7 and M8 is connected to the drain of M13, and the gate of M13 is connected to the left end of SQ on the left and the upper end of SQB; the source of M9 and M10 is connected to the drain of M14, and the gate of M14 is connected to the right end of SQB on the right and the upper end of SQ; the bias voltage V bias，Q Connect the right end of the upper side SQ and the left end of SQB, and the ground is connected to the lower end of the lower side SQB and the lower end of SQ; the source of M13 and M14 is connected to the drain of M16, and the gate of M16 is connected to V mirror，Q Bias voltage, source connected to ground.

5. The 6-bit ultra-wideband low RMS phase and gain error active digitally controlled phase shifter according to claim 1, characterized in that: The current mirror array circuit includes two current mirror arrays, I and Q. The I path includes PMOS tubes M01, M02, M11, M12, M21, M22, M31, M32, M41, M42, M51, M52, M61, M62, switches S0, S0N, S1, S1N, S2, S2N, S3, S3N, S4, S4N, S5, S5N, S6, S6N; the Q path includes PMOS tubes M71, M72, M81, M 82, M91, M92, M101, M102, M111, M112, M121, M122, M131, M132, switches S7, S7N, S8, S8N, S9, S9N, S10, S10N, S11, S11N, S12, S12N, S13, S13N; current synthesis PMOS tubes MI1, MI2, MQ1, MQ2 and current source IREF, PMOS tubes MREF1, MREF2; The 1.8V power supply is connected to the drain of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131, MREF1 and the upper end of S0N, S1N, S2N, S3N, S4N, S5N, S6N, S7N, S8N, S9N, S10N, S11N, S12N, S13N; the gate of MREF1 is connected to the source of MREF1 and the gates of M01, M11, M21, M31, M41, M51, M61, M71, M81, M91, M101, M111, M121, M131; the source of M01 is connected to the drain of M02, M11 The source of MREF1 is connected to the drain of MREF2; the source of M21 is connected to the drain of M22; the source of M31 is connected to the drain of M32; the source of M41 is connected to the drain of M42; the source of M51 is connected to the drain of M52; the source of M61 is connected to the drain of M62; the source of M71 is connected to the drain of M72; the source of M81 is connected to the drain of M82; the source of M91 is connected to the drain of M92; the source of M101 is connected to the drain of M102; the source of M111 is connected to the drain of M112; the source of M121 is connected to the drain of M122; the source of M131 is connected to the drain of M132; the source of MREF1 is connected to the drain of MREF2; the gate of M02 is connected to the lower end of S0N and the upper end of S0; The gate of M12 is connected to the lower end of S1N and the upper end of S1, the gate of M22 is connected to the lower end of S2N and the upper end of S2, the gate of M32 is connected to the lower end of S3N and the upper end of S3, the gate of M42 is connected to the lower end of S4N and the upper end of S4, the gate of M52 is connected to the lower end of S5N and the upper end of S5, the gate of M62 is connected to the lower end of S6N and the upper end of S6, the gate of M72 is connected to the lower end of S7N and the upper end of S7, the gate of M82 is connected to the lower end of S8N and the upper end of S8, the gate of M92 is connected to the lower end of S9N and the upper end of S9, the gate of M102 is connected to the lower end of S10N and the upper end of S10, the gate of M112 is connected to the lower end of S11N and the upper end of S11, and the gate of M12 is connected to the lower end of S1 The gate of 2 is connected to the lower end of S12N and the upper end of S12, and the gate of M132 is connected to the lower end of S13N and the upper end of S13; the gate of MREF2 is connected to the source of MREF2 and the lower ends of S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, and S13; the source of MREF2 is connected to the upper end of the 100μA current source, and the lower end of the 100μA current source is connected to the ground; the source of M02, M12, M22, M32, M42, M52, and M62 is connected to the drain of MI1, the drain of MI1 is connected to the gate of MI1, the source of MI1 is connected to the drain of MI2, the drain of MI2 is connected to the gate of MI2, and the source of MI2 is grounded;The sources of M72, M82, M92, M102, M112, M122 and M132 are connected to the drain of MQ1, the drain of MQ1 is connected to the gate of MQ1, the source of MQ1 is connected to the drain of MQ2, the drain of MQ2 is connected to the gate of MQ2, and the source of MQ2 is grounded. ;

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