Driving method and equipment of power semiconductor device, storage medium and driving device

Abstract

The invention provides a driving method and equipment of a power semiconductor device, a storage medium and a driving device, and relates to the technical field of power semiconductor devices. The driving method of the power semiconductor device comprises the following steps: controlling an internal gate-source voltage value of the power semiconductor device to rise to a turn-on threshold voltage value; driving a grid electrode of the power semiconductor device by using a first voltage source, and controlling the internal grid source voltage value to rise to a set value which is less than or equal to a Miller platform voltage value; wherein the voltage value of the first voltage source is greater than the turn-on threshold voltage value. The embodiment of the invention provides a driving method and equipment of a power semiconductor device, a storage medium and a driving device, and aims to control energy storage of a parasitic inductor and a parasitic capacitor of the power semiconductor device, optimize a switching waveform of the power semiconductor device and reduce switching loss at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a driving method, equipment, storage medium and driving device of a power semiconductor device. Background Art

[0002] Power semiconductor devices are widely used in power supply, motor drive, new energy, energy storage and other fields. Commonly used power devices include silicon IGBT, silicon Mosfet, Sic Mosfet, etc.

[0003] The switching process of power semiconductor devices involves the switching of channels, changes in parasitic parameters, and the influence of external circuits. It is important to optimize the switching waveform and reduce switching losses, but the switching characteristics of devices and the influence of parasitic parameters are often contradictory. Summary of the invention

[0004] The embodiments of the present invention provide a driving method, device, storage medium and driving apparatus of a power semiconductor device, which control the energy storage of parasitic inductance and capacitance of the power semiconductor device, optimize the switching waveform of the power semiconductor device, and reduce the switching loss.

[0005] In a first aspect, an embodiment of the present invention provides a driving method of a power semiconductor device, comprising:

[0006] Controlling the internal gate-source voltage value of the power semiconductor device to rise to a turn-on threshold voltage value;

[0007] The gate of the power semiconductor device is driven by a first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value; wherein the voltage value of the first voltage source is greater than the turn-on threshold voltage value.

[0008] Optionally, a voltage value of the first voltage source is greater than or equal to a Miller platform voltage value of the power semiconductor device.

[0009] Optionally, before the gate of the power semiconductor device is driven by the first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value, the method further includes:

[0010] The voltage value of the first voltage source is obtained according to at least one of the internal gate resistance, gate-source capacitance, parasitic inductance, and initial current of the power loop of the power semiconductor device, as well as the turn-on threshold voltage value and the Miller platform voltage value.

[0011] Optionally, after connecting the gate of the power semiconductor device with a first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value, the method further includes:

[0012] The gate of the power semiconductor device is driven by a second voltage source, and the internal gate-source voltage value is controlled to rise to a driving voltage value during actual operation.

[0013] Optionally, a voltage value of the second voltage source is greater than or equal to a driving voltage value of the power semiconductor device during actual operation.

[0014] Optionally, the first voltage source drives the gate of the power semiconductor device for a maintenance time of less than 1 microsecond.

[0015] Optionally, the duration of applying the voltage value of the second voltage source is equal to a pulse width required for actual work.

[0016] In a second aspect, an embodiment of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the driving method as described in the first aspect when executing the program.

[0017] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the driving method as described in the first aspect.

[0018] In a fourth aspect, an embodiment of the present invention provides a driving device for a power semiconductor device, comprising a driving circuit for implementing the driving method as described in the first aspect.

[0019] In an embodiment of the present invention, the energy continuity at different stages of the switching process is controlled. A first voltage source is used to drive the gate of a power semiconductor device instead of a current source. The first voltage source does not limit the charging current like a current source, so that the corresponding parasitic capacitor can be charged to a preset charge amount in a shorter period of time. The energy storage of the parasitic inductance and capacitance of the power semiconductor device is controlled, the switching waveform of the power semiconductor device is optimized, and the switching loss is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a driving waveform of a gate-source voltage value of a power semiconductor device in the related art;

[0021] Figure 2 A schematic diagram of waveforms of source-drain voltage and drain current of a power semiconductor device in the related art;

[0022] Figure 3 is a schematic diagram of an equivalent circuit of a power semiconductor device;

[0023] Figure 4 A flow chart of a driving method for a power semiconductor device provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of a driving waveform of a gate-source voltage value of a power semiconductor device provided by an embodiment of the present invention;

[0025] Figure 6 A flow chart of another method for driving a power semiconductor device provided by an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0028] Figure 1 Schematic diagram of driving waveform of gate-source voltage value of power semiconductor device in related technology, Figure 2 Schematic diagram of waveforms of source-drain voltage and drain current of a power semiconductor device in the related art. Figure 2 The solid line in the figure represents the waveform of the source-drain voltage value, and the dotted line represents the waveform of the drain current. Figure 3 For the equivalent circuit diagram of power semiconductor devices, refer to Figure 1-Figure 3 , from t0 to t1, the gate-source voltage Vgs of the power semiconductor device rises to the turn-on threshold voltage Vth. Before the gate-source voltage Vgs of the power semiconductor device rises to the turn-on threshold voltage Vth, the gate current mainly charges the capacitor Cgs, and the channel also has only a partial leakage current. There is basically no energy in the parasitic inductance.

[0029] From t1 to t2, as the capacitor Cgs is charged, the gate-source voltage Vgs gradually rises to reach the turn-on threshold voltage Vth of the power semiconductor device. At this time, the power semiconductor device (such as MOS tube) is gradually turned on and begins to output current to the outside. The channel changes from a high-resistance state to a variable resistance zone. At this stage, the channel resistance of the power semiconductor device is still large, but there will be changes between the parasitic capacitance (including capacitance Cgs, capacitance Cgd and capacitance Cds), and there will be transient charging and discharging currents. Due to the existence of internal parasitic inductance (inductance Lg, inductance Ld and inductance Ls), the source-drain voltage Vds of the power semiconductor device does not change significantly from the outside, and the parasitic inductance begins to store energy.

[0030] From t2 to t3, as the capacitor Cgs charges, the voltage level continues to rise from the turn-on threshold voltage value Vth to the Miller platform voltage value Vg1. At this time, the gate-level charge mainly charges the capacitor Cgd, and the source-drain voltage value Vds changes from high to low, and the channel impedance becomes lower. Since the drain current Id changes at this stage, the energy stored in the parasitic inductance often changes dramatically.

[0031] At the time of t3 to t4, the channel has been opened and turned into a low resistance state. At this time, the energy stored in the parasitic inductance tends to change slowly with the power loop.

[0032] For example, reference Figure 3 , between the inductor Lg and the gate of the power semiconductor device, an equivalent resistance Rg is also included.

[0033] According to research, the stage from t0 to t1 has little effect on the loss and waveform, so it can be selected as fast as possible. The stage from t3 to t4 has little effect on the waveform, but has a slight effect on the loss, so it can be selected as fast as possible. The selection and processing of the switching speed in the stage from t1 to t3 are very critical.

[0034] Figure 4 A flow chart of a driving method for a power semiconductor device provided by an embodiment of the present invention, Figure 5 A schematic diagram of a driving waveform of a gate-source voltage value of a power semiconductor device provided by an embodiment of the present invention, Figure 5 The Figure 1 The driving waveform of the gate-source voltage value of the power semiconductor device in the similar related technology is used as a comparison. Figure 5 Indicated by light green lines. Figure 5 and Figure 1 The difference is that Figure 5 A schematic curve of the voltage applied from the outside is also given in Figure 5 The black line is used to illustrate this. The voltage applied from the outside refers to the voltage directly applied to the corresponding external port of the power semiconductor device. Figure 5 A schematic curve of the externally applied voltage is given in FIG. 1 , for which the moments (t0, t1, t2, t3, t4, t5) in the abscissa are adaptively arranged in sequence.

[0035] refer to Figure 4 and Figure 5 , the driving method of the power semiconductor device includes:

[0036] S101 , controlling the internal gate-source voltage value of the power semiconductor device to rise to a turn-on threshold voltage value.

[0037] like Figure 5As shown, from t0 to t1, the gate-source voltage Vgs of the power semiconductor device rises to the turn-on threshold voltage Vth. The internal gate-source voltage refers to the voltage difference between the gate and the source actually applied to the power semiconductor device after the parasitic parameters are offset.

[0038] S102, driving the gate of the power semiconductor device with a first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value; wherein the voltage value of the first voltage source is greater than the turn-on threshold voltage value.

[0039] As an example, the power semiconductor device includes a transistor, such as a MOS transistor or a triode. Figure 5 As shown, from time t1 to t2, the gate of the power semiconductor device is driven by the first voltage source to control the gate-source voltage value Vgs to rise to the set value set value. The set value is less than or equal to the Miller platform voltage value Vm. The voltage value Vg1 of the first voltage source is greater than the turn-on threshold voltage value Vth. The Miller platform voltage value Vm and the turn-on threshold voltage value Vth are voltage values ​​in the inherent properties of the power semiconductor device.

[0040] In an embodiment of the present invention, the energy continuity at different stages of the switching process is controlled. A first voltage source is used to drive the gate of a power semiconductor device instead of a current source. The first voltage source does not limit the charging current like a current source, so that the corresponding parasitic capacitance (for example, including capacitance Cgs) can be charged to a preset charge amount in a shorter period of time. The energy storage of the parasitic inductance and capacitance of the power semiconductor device is controlled, the switching waveform of the power semiconductor device is optimized, and the switching loss is reduced.

[0041] Optionally, the voltage value Vg1 of the first voltage source is greater than or equal to the Miller platform voltage value Vm. In step S102, the gate-source voltage value Vgs may be controlled to rise to a set value less than the Miller platform voltage value Vm, or the gate-source voltage value Vgs may be controlled to rise to the Miller platform voltage value Vm.

[0042] Figure 6 Another driving method flow chart of a power semiconductor device provided by an embodiment of the present invention is shown in FIG. Figure 5 and Figure 6 , the driving method of the power semiconductor device includes:

[0043] S201 , controlling the internal gate-source voltage value of the power semiconductor device to rise to a turn-on threshold voltage value.

[0044] S202, obtaining a voltage value of a first voltage source according to at least one of an internal gate resistance, a gate-source capacitance, a parasitic inductance, an initial current of a power loop, a turn-on threshold voltage value, and a Miller platform voltage value of the power semiconductor device.

[0045] For example, reference Figure 3 The internal gate resistance of the power semiconductor device is the equivalent resistance Rg, the gate-source capacitance is the capacitance Cgs, and the parasitic inductance includes the inductance Lg, the inductance Ld and the inductance Ls.

[0046] S203, driving the gate of the power semiconductor device with a first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value; wherein the voltage value of the first voltage source is greater than the turn-on threshold voltage value.

[0047] Optionally, the voltage value Vg1 of the first voltage source is greater than or equal to the Miller platform voltage value Vm of the power semiconductor device.

[0048] Optionally, the first voltage source drives the gate of the power semiconductor device for a duration of less than 1 microsecond, so that the gate-source voltage value Vgs can quickly rise to a set value less than or equal to the Miller platform voltage value.

[0049] Furthermore, the first voltage source drives the gate of the power semiconductor device for a duration shorter than 100 nanoseconds.

[0050] S204: driving the gate of the power semiconductor device with the second voltage source to control the internal gate-source voltage value to rise to the driving voltage value during actual operation.

[0051] like Figure 5 As shown, from time t1 to t2, the gate of the power semiconductor device is driven by the second voltage source to control the gate-source voltage value Vgs to rise to the driving voltage value during actual operation. The driving voltage value during actual operation is greater than the set value in the above embodiment.

[0052] Optionally, the voltage value Vg2 of the second voltage source is greater than or equal to the driving voltage value of the power semiconductor device during actual operation.

[0053] Exemplarily, the voltage value Vg2 of the second voltage source is greater than the voltage value Vg1 of the first voltage source.

[0054] Optionally, the duration of applying the voltage value Vg2 of the second voltage source is equal to the pulse width required for actual operation.

[0055] In the embodiment of the present invention, based on the above embodiment, a second voltage source is used to drive the gate of the power semiconductor device instead of a current source. The second voltage source does not limit the charging current like the current source, so that the corresponding parasitic capacitance (for example, including capacitance Cgd and capacitance Cds) can be charged to a preset charge amount in a shorter time. The energy storage of the parasitic inductance and capacitance of the power semiconductor device is controlled, the switching waveform of the power semiconductor device is optimized, and the switching loss is reduced.

[0056] The gate-source voltage driving waveform for turning off the power semiconductor device and the gate-source voltage driving waveform for turning on the power semiconductor device can be set symmetrically. Alternatively, in one embodiment, a different technical concept from turning on the power semiconductor device is used to turn off the power semiconductor device.

[0057] Figure 7 A schematic diagram of a computer device provided in an embodiment of the present invention, referring to Figure 7 The computer device 60 includes a memory 602, a processor 601, and a computer program stored in the memory 602 and executable on the processor. When the processor 601 executes the program, the method in the above embodiment is implemented. Figure 7 A block diagram of an exemplary computer device suitable for implementing embodiments of the present invention is shown. Figure 7 The computer device 60 shown is only an example and should not limit the functions and scope of use of the embodiments of the present invention. Figure 7 As shown, the computer device 60 is in the form of a general-purpose computing device. The components of the computer device 60 may include, but are not limited to: one or more processors 601, a system memory 602, and a bus 603 connecting different system components (including the system memory 602 and the processor 601).

[0058] Bus 603 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnect (PCI) bus.

[0059] The computer device 60 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computer device 60, including volatile and non-volatile media, removable and non-removable media.

[0060] System memory 602 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 604 and / or cache memory 605. Computer device 60 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 606 may be used to read and write non-removable, non-volatile magnetic media ( Figure 7 not shown, usually called a "hard drive"). Although Figure 7 Not shown in the figure, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 603 via one or more data medium interfaces. The system memory 602 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the embodiments of the present invention.

[0061] A program / utility 608 having a set (at least one) of program modules 607 may be stored, for example, in system memory 602, such program modules 607 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. Program modules 607 generally perform the functions and / or methods of the embodiments described herein.

[0062] The computer device 60 may also communicate with one or more external devices 609 (e.g., keyboard, pointing device, display 610, etc.), one or more devices that enable a user to interact with the device, and / or any device that enables the computer device 60 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 611. Furthermore, the computer device 60 may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 612. Figure 7 As shown, the network adapter 612 communicates with other modules of the computer device 60 via the bus 603. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the computer device 60, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0063] The processor 601 executes various functional applications and data processing by running programs stored in the system memory 602 .

[0064] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above embodiment can be implemented.

[0065] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0066] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0067] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0068] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0069] An embodiment of the present invention further provides a driving device for a power semiconductor device, and the driving device may include a driving circuit.

[0070] The driving circuit may include at least one element among an inductor, a capacitor, a resistor and a transistor. The driving circuit may also include other elements besides the inductor, the capacitor, the resistor and the transistor to implement the driving method in the above embodiment.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for driving a power semiconductor device, characterized in that: include: Controlling the internal gate-source voltage value of the power semiconductor device to rise to a turn-on threshold voltage value; The gate of the power semiconductor device is driven by a first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value; wherein the voltage value of the first voltage source is greater than the turn-on threshold voltage value.

2. The driving method according to claim 1, characterized in that: A voltage value of the first voltage source is greater than or equal to a Miller platform voltage value of the power semiconductor device.

3. The driving method according to claim 2, characterized in that: Before the gate of the power semiconductor device is driven by the first voltage source to control the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value, the method further includes: The voltage value of the first voltage source is obtained according to at least one of the internal gate resistance, gate-source capacitance, parasitic inductance, and initial current of the power loop of the power semiconductor device, as well as the turn-on threshold voltage value and the Miller platform voltage value.

4. The driving method according to claim 2, characterized in that: After connecting the gate of the power semiconductor device with a first voltage source and controlling the internal gate-source voltage value to rise to a set value less than or equal to the Miller platform voltage value, the method further includes: The gate of the power semiconductor device is driven by a second voltage source, and the internal gate-source voltage value is controlled to rise to a driving voltage value during actual operation.

5. The driving method according to claim 4, characterized in that: The voltage value of the second voltage source is greater than or equal to the driving voltage value of the power semiconductor device during actual operation.

6. The driving method according to claim 1, characterized in that: The first voltage source drives the gate of the power semiconductor device for a maintenance time of less than 1 microsecond.

7. The driving method according to claim 4, characterized in that: The duration of applying the voltage value of the second voltage source is equal to the pulse width required for actual operation.

8. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the driving method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the driving method as described in any one of claims 1 to 7 is implemented.

10. A driving device for a power semiconductor device, characterized in that: The invention comprises a driving circuit for implementing the driving method according to any one of claims 1 to 7.

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