Three-path high-linearity grid voltage bootstrapped switch

Abstract

The invention discloses a three-path high-linearity grid voltage bootstrap switch which comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a first transistor M1, a second transistor M21, a second transistor M22, a second transistor M23, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a bootstrap switch transistor MS. Three bootstrap capacitors are adopted to form two main paths and an auxiliary path respectively, so that the establishment of a gate end voltage is accelerated when an input signal is transmitted to the gate end of a switching tube through the two main paths, and meanwhile, the auxiliary path is utilized to drive a nonlinear capacitor, so that the influence of the nonlinear capacitor in the circuit on the linearity of a sampling circuit is reduced, and the reliability of the sampling circuit is improved. Therefore, the signal driving capability is enhanced and the precision of the whole circuit is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of wireless communication, and relates to a three-path high linearity gate voltage bootstrap switch, which is mainly applied to a high-speed and high-precision pipeline analog-to-digital converter (Pipeline ADC). Background Art

[0002] With the advent of the 5G era, people have higher and higher requirements for high-speed network transmission and massive terminal access rates, and the market demand for high-speed, high-precision analog-to-digital converters (ADC) is increasing.

[0003] As the input interface of the wireless communication sensor terminal, the analog-to-digital converter undertakes functions such as data sampling, analog-to-digital conversion, signal processing, and gain control. The pipeline analog-to-digital converter (Pipeline ADC) can achieve a balance between power consumption, speed, and accuracy due to its pipeline structure, and is a very promising converter type in the current medium-speed and high-precision application field.

[0004] Attached Figure 1 This is a schematic diagram of a traditional gate voltage bootstrap switch circuit. The VGS of the bootstrap switch tube MS is constant and independent of the input, so as to provide a constant switch conductance. Its working principle is as follows:

[0005] (1) Sampling stage: CLK is high level, CLKB is low level, at this time MS, M5, M6, M9 are turned on, M8 is turned off. V2 follows the input signal Vin, and V1 rises to VDD+Vin, so as to increase the gate voltage of the switching transistor in the sampling stage.

[0006] (2) Holding stage: CLK is low, M7 and M8 are turned on, and V1 and V2 are both set to GND. At this time, M1 and M2 are also turned on, and other MOS transistors remain in the off state. The capacitor CL stores a charge of VDD·C1. The gate VG of the bootstrap switch is pulled down to a low level, and the output Vout maintains the sampled voltage unchanged.

[0007] In the traditional gate voltage bootstrap switch circuit, the source N substrate of the PMOS transistors M2 and M5 is forward biased, and the substrate terminal is connected to the source instead of VDD. This will cause the N well of M2 and M5 to form a large nonlinear capacitor Cnwell to the V1 node, as shown in the attached figure. Figure 2 Attached Figure 3 The equivalent circuit diagram of the traditional bootstrap switch during sampling is shown in Figure 1. The transfer function from Vin to VG is:

[0008]

[0009] Among them, CG is the capacitance seen at the gate of MS; R5 = 1 / G5. It can be seen that the change of Cnwell will bring about the change of on-resistance and reduce the linearity. Summary of the invention

[0010] (I) Purpose of the invention

[0011] The purpose of the present invention is to improve the traditional gate voltage bootstrap switch circuit and propose a three-path high linearity gate voltage bootstrap switch.

[0012] (II) Technical solution

[0013] In order to solve the above technical problems, the present invention provides a three-path high linearity gate voltage bootstrap switch, which comprises:

[0014] A first capacitor C1, one end of which is connected to the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M21 and the source of the fifth transistor M51;

[0015] A second capacitor C2, one end of which is connected to the first capacitor C1, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M22 and the source of the fifth transistor M5;

[0016] A third capacitor C3, one end of which is connected to the first capacitor C1, the second capacitor C2, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M23, the substrate of the second transistor M23, and the substrate of the fifth transistor M5;

[0017] a first transistor M1, having a source connected to the ground, a gate connected to CLKB, and a drain connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9;

[0018] The second transistor M21 has a source connected to the first capacitor C1 and the source of the fifth transistor M51, a gate connected to the drain of the fifth transistor M51, the gate of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0019] The second transistor M22 has a source connected to the second capacitor C2 and the source of the fifth transistor M5, a gate connected to the drain of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0020] The second transistor M23 has a source connected to the third capacitor C3 and the substrate of the fifth transistor M5, a gate connected to the drain of the transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0021] a third transistor M3, having a source connected to VDD, a gate connected to CLK, and a drain connected to the drain of the fourth transistor M4, the gate of the fifth transistor M5, and the drain of the sixth transistor M6;

[0022] a fourth transistor M4, having a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, a gate connected to CLK, and a drain connected to the drain of the third transistor M3, the gate of the fifth transistor M5, and the drain of the sixth transistor M6;

[0023] a fifth transistor M5, having a source connected to the second capacitor C2 and the source of the second transistor M22, a gate connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the drain of the sixth transistor M6, and a drain connected to the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS;

[0024] a sixth transistor M6, whose source is connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, and the source of the ninth transistor M9, whose gate is connected to the drain of the fifth transistor M5, the source of the seventh transistor M7, and the gate of the transistor MS, and whose drain is connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the gate of the fifth transistor M5;

[0025] a seventh transistor M7, having a source connected to the drain of the fifth transistor M51, the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, a gate connected to VDD, and a drain connected to the source of the eighth transistor M8;

[0026] an eighth transistor M8, having a source connected to the drain of the seventh transistor M7, a gate connected to CLKB, and a drain grounded;

[0027] a ninth transistor M9, having a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, and the source of the sixth transistor M6, a gate connected to the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to Vin;

[0028] The bootstrap switch transistor MS has a source connected to Vin, a gate connected to the drain of the fifth transistor M5 , the gate of the sixth transistor M6 , and the source of the seventh transistor M7 , and a drain connected to Vout.

[0029] (III) Beneficial effects

[0030] The three-path high-linearity gate voltage bootstrap switch provided by the above technical solution utilizes two main paths and one auxiliary path, so that the input signal accelerates the establishment of the gate terminal voltage when it is transmitted to the gate terminal of the switch tube through the two main paths. At the same time, the auxiliary path drives Cnwell, reducing the influence of the nonlinear capacitance in the circuit on the linearity of the sampling circuit, thereby enhancing the signal driving capability and improving the accuracy of the overall circuit; the main path and the auxiliary path can be optimized independently to obtain maximum signal linearity and driving strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Attached Figure 1 Conventional gate voltage bootstrap switching circuit.

[0032] Attached Figure 2 Schematic diagram of the nonlinear N-well capacitor Cnwell.

[0033] Attached Figure 3 Equivalent circuit diagram of conventional bootstrap switch during sampling.

[0034] Attached Figure 4 A gate voltage bootstrap switch circuit diagram proposed by the present invention.

[0035] Attached Figure 5 Equivalent circuit diagram of the improved gate voltage bootstrap switch during sampling. DETAILED DESCRIPTION

[0036] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0037] like Figure 4 As shown, the high linearity gate voltage bootstrap switch of the three paths in this embodiment includes:

[0038] A first capacitor C1, one end of which is connected to the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M21 and the source of the fifth transistor M51;

[0039] A second capacitor C2, one end of which is connected to the first capacitor C1, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M22 and the source of the fifth transistor M5;

[0040] A third capacitor C3, one end of which is connected to the first capacitor C1, the second capacitor C2, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M23, the substrate of the second transistor M23, and the substrate of the fifth transistor M5;

[0041] a first transistor M1, having a source connected to the ground, a gate connected to CLKB, and a drain connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9;

[0042] The second transistor M21 has a source connected to the first capacitor C1 and the source of the fifth transistor M51, a gate connected to the drain of the fifth transistor M51, the gate of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0043] The second transistor M22 has a source connected to the second capacitor C2 and the source of the fifth transistor M5, a gate connected to the drain of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0044] The second transistor M23 has a source connected to the third capacitor C3 and the substrate of the fifth transistor M5, a gate connected to the drain of the transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD;

[0045] a third transistor M3, having a source connected to VDD, a gate connected to CLK, and a drain connected to the drain of the fourth transistor M4, the gate of the fifth transistor M5, and the drain of the sixth transistor M6;

[0046] a fourth transistor M4, having a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, a gate connected to CLK, and a drain connected to the drain of the third transistor M3, the gate of the fifth transistor M5, and the drain of the sixth transistor M6;

[0047] a fifth transistor M5, having a source connected to the second capacitor C2 and the source of the second transistor M22, a gate connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the drain of the sixth transistor M6, and a drain connected to the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS;

[0048] a sixth transistor M6, whose source is connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, and the source of the ninth transistor M9, whose gate is connected to the drain of the fifth transistor M5, the source of the seventh transistor M7, and the gate of the transistor MS, and whose drain is connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the gate of the fifth transistor M5;

[0049] a seventh transistor M7, having a source connected to the drain of the fifth transistor M51, the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, a gate connected to VDD, and a drain connected to the source of the eighth transistor M8;

[0050] an eighth transistor M8, having a source connected to the drain of the seventh transistor M7, a gate connected to CLKB, and a drain grounded;

[0051] The ninth transistor M9 has a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, and the source of the sixth transistor M6, a gate connected to the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to Vin.

[0052] The bootstrap switch transistor MS has a source connected to Vin, a gate connected to the drain of the fifth transistor M5 , the gate of the sixth transistor M6 , and the source of the seventh transistor M7 , and a drain connected to Vout.

[0053] In order to eliminate the influence of the N-well parasitic capacitance Cnwell, the present embodiment divides the bootstrap capacitor into a first capacitor C1, a second capacitor C2, and a third capacitor C3, so that two main signal paths consisting of the first capacitor C1 and the second transistor M21 and the second capacitor C2 and the second transistor M22 are formed, and an auxiliary signal path consisting of the third capacitor C3 and the second transistor M23 is formed. The substrates of the second transistors M21, M22, and M23 are connected to the substrate of the fifth transistor M5, and the nonlinear voltage is V1. The drain of the ninth transistor M9 is connected to the source of the bootstrap switch tube MS as the input end of the gate voltage bootstrap switch circuit, and the output signal end is connected to the load capacitor CL. The source of the first transistor M1 is connected to the ground, and the gate is connected to the eighth transistor M8, providing a clock inversion signal of the gate voltage bootstrap switch.

[0054] The working principle of the high linearity gate voltage bootstrap switch of the third path of this embodiment is as follows: when CLK is at a high level and CLKB is at a low level, the fourth transistor M4, the fifth transistor M5, the fifth transistor M51, and the ninth transistor M9 are turned on, the voltage of the lower plate of the capacitor changes with the change of Vin, and the voltage of the upper plate of the capacitor is equal to Vin plus the voltage stored on the original capacitor; the bootstrap switch MS is turned on, and the output voltage Vout is equal to the input voltage Vin; when CLK is at a low level and CLKB is at a high level, the first transistor M1, the seventh transistor M7, and the eighth transistor M8 are turned on, the drain voltage of the NMOS tube drops to GND, the negative ends of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are grounded, and the positive ends are charged to VDD due to the conduction of the second transistor M21, the second transistor M22, and the second transistor M23, and the bootstrap switch tube MS is disconnected due to the gate voltage being grounded, and the output signal is in a holding state. In the proposed bootstrap switch, the size ratio of the main path to the auxiliary path is set to 3:1, that is, 3W23 = W22 = W21, 3C3 = C1 = C2. The equivalent circuit of the proposed bootstrap switch during sampling is shown in the attached figure. Figure 4 shown.

[0055] The transfer function from Vin to VG is:

[0056]

[0057] Compared with equation (1), on the one hand, G5 is more linear in the proposed circuit than in the conventional circuit, and the nonlinear voltage V1 is connected to the substrate of the fifth transistor M5 instead of its source terminal. Therefore, G5 is proportional to the error of V1 in the conventional circuit, but only proportional to the square root of the error of V1 in the proposed circuit. On the other hand, the proposed switch slightly reduces the bootstrap capacitance to 6 / 7 of the original capacitance C1, and the main path removes the nonlinear parasitic capacitance Cnwell, so that the nonlinear voltage V1 is reconnected to the fifth transistor M5, thereby improving the overall linearity.

[0058] It can be seen from the above technical scheme that the present invention adopts three bootstrap capacitors to form two main paths and one auxiliary path respectively, so that the input signal can accelerate the establishment of the gate terminal voltage when it is transmitted to the gate terminal of the switch tube through the two main paths. At the same time, the auxiliary path is used to drive the nonlinear capacitor to reduce the influence of the nonlinear capacitor in the circuit on the linearity of the sampling circuit, thereby enhancing the signal driving capability and improving the accuracy of the overall circuit.

[0059] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A three-path high linearity gate voltage bootstrap switch, characterized in that: include: A first capacitor C1, one end of which is connected to the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M21 and the source of the fifth transistor M51; A second capacitor C2, one end of which is connected to the first capacitor C1, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M22 and the source of the fifth transistor M5; A third capacitor C3, one end of which is connected to the first capacitor C1, the second capacitor C2, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, and the other end of which is connected to the source of the second transistor M23, the substrate of the second transistor M23, and the substrate of the fifth transistor M5; a first transistor M1, having a source connected to the ground, a gate connected to CLKB, and a drain connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9; The second transistor M21 has a source connected to the first capacitor C1 and the source of the fifth transistor M51, a gate connected to the drain of the fifth transistor M51, the gate of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD; The second transistor M22 has a source connected to the second capacitor C2 and the source of the fifth transistor M5, a gate connected to the drain of the fifth transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD; The second transistor M23 has a source connected to the third capacitor C3 and the substrate of the fifth transistor M5, a gate connected to the drain of the transistor M5, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to VDD; a third transistor M3, having a source connected to VDD, a gate connected to CLK, and a drain connected to the drain of the fourth transistor M4, the gate of the fifth transistor M5, and the drain of the sixth transistor M6; a fourth transistor M4, having a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, the source of the sixth transistor M6, and the source of the ninth transistor M9, a gate connected to CLK, and a drain connected to the drain of the third transistor M3, the gate of the fifth transistor M5, and the drain of the sixth transistor M6; a fifth transistor M5, having a source connected to the second capacitor C2 and the source of the second transistor M22, a gate connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the drain of the sixth transistor M6, and a drain connected to the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS; a sixth transistor M6, whose source is connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the drain of the first transistor M1, the source of the fourth transistor M4, and the source of the ninth transistor M9, whose gate is connected to the drain of the fifth transistor M5, the source of the seventh transistor M7, and the gate of the transistor MS, and whose drain is connected to the drain of the third transistor M3, the drain of the fourth transistor M4, and the gate of the fifth transistor M5; a seventh transistor M7, having a source connected to the drain of the fifth transistor M51, the gate of the fifth transistor M51, the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, a gate connected to VDD, and a drain connected to the source of the eighth transistor M8; an eighth transistor M8, having a source connected to the drain of the seventh transistor M7, a gate connected to CLKB, and a drain grounded; a ninth transistor M9, having a source connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the source of the fourth transistor M4, and the source of the sixth transistor M6, a gate connected to the gate of the sixth transistor M6, the source of the seventh transistor M7, and the gate of the transistor MS, and a drain connected to Vin; The bootstrap switch transistor MS has a source connected to Vin, a gate connected to the drain of the fifth transistor M5 , the gate of the sixth transistor M6 , and the source of the seventh transistor M7 , and a drain connected to Vout.

2. The three-path high linearity gate voltage bootstrap switch according to claim 1, characterized in that: The first capacitor C1, the second capacitor C2 and the third capacitor C3 form two main signal paths consisting of the first capacitor C1 and the second transistor M21 and the second capacitor C2 and the second transistor M22, and an auxiliary signal path consisting of the third capacitor C3 and the second transistor M23.

3. The three-path high linearity gate voltage bootstrap switch according to claim 2, characterized in that: The substrates of the second transistors M21 , M22 , and M23 are connected to the substrate of the fifth transistor M5 , and the non-linear voltage is V1 .

4. The three-path high linearity gate voltage bootstrap switch according to claim 3, characterized in that: The drain of the ninth transistor M9 is connected to the source of the bootstrap switch tube MS, serving as the input end of the gate voltage bootstrap switch circuit, and the output signal end is connected to the load capacitor CL.

5. The three-path high linearity gate voltage bootstrap switch according to claim 4, characterized in that: The source of the first transistor M1 is connected to the ground, and the gate is connected to the eighth transistor M8, providing a clock inversion signal of the gate voltage bootstrap switch.

6. The three-path high linearity gate voltage bootstrap switch according to claim 5, characterized in that: When CLK is at a high level and CLKB is at a low level, the fourth transistor M4, the fifth transistor M5, the fifth transistor M51, and the ninth transistor M9 are turned on, the voltage on the lower plate of the capacitor changes with the change of Vin, and the voltage on the upper plate of the capacitor is equal to Vin plus the voltage originally stored on the capacitor; the bootstrap switch MS is turned on, and the output voltage Vout is equal to the input voltage Vin.

7. The three-path high linearity gate voltage bootstrap switch according to claim 6, characterized in that: When CLK is at a low level and CLKB is at a high level, the first transistor M1, the seventh transistor M7, and the eighth transistor M8 are turned on, the drain voltage of the NMOS tube drops to GND, the negative ends of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are grounded, and the positive ends are charged to VDD due to the conduction of the second transistor M21, the second transistor M22, and the second transistor M23. The bootstrap switch tube MS is turned off because the gate voltage is grounded, and the output signal is in a holding state.

8. The three-path high linearity gate voltage bootstrap switch according to claim 7, characterized in that: In the bootstrap switch, the size ratio of the main path to the auxiliary path is set to 3:1, that is, 3W23=W22=W21, 3C3=C1=C2.

9. The three-path high linearity gate voltage bootstrap switch according to claim 8, characterized in that: In the equivalent circuit of the bootstrap switch during sampling, the transfer function from Vin to VG is:

10. Application of a high linearity gate voltage bootstrap switch based on three paths according to any one of claims 1 to 9 in the field of wireless communication technology.

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