Low-power SAR ADC switch switching circuit and switching method
By adopting C-2C structure and capacitance splitting technology in SAR ADC analog-to-digital converter, the dependence problem on the intermediate common mode level during the CDAC switching process is solved, and switching switching is achieved that is low power consumption and suitable for low voltage processes.
Patent Information
- Application Number
- CN202411622469.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-04-15
AI Technical Summary
The dependence of existing SAR ADC analog-to-digital converters on the intermediate common mode level during the CDAC switching process makes it difficult to achieve effective switching in low-voltage processes and have high power consumption.
The capacitance splitting technology based on C-2C structure is adopted, combined with bootstrap switch and clock control comparator, CDAC switch switching is realized, get rid of the dependence on the intermediate common mode level, and reduce power consumption through capacitance splitting technology.
It realizes low power consumption SAR ADC switch switching under low voltage processes, and the output common mode level remains unchanged. It is suitable for low voltage processes and has a simple circuit structure.
Smart Images
Figure CN119834808A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of wireless communication, and relates to a low-power SAR ADC switch switching circuit and a switching method, which are mainly applied to a high-speed, low-power SAR ADC analog-to-digital converter. Background Art
[0002] With the advent of the 5G era, people have higher and higher requirements for high-speed network transmission and massive terminal access rates, and the market demand for high-speed, low-power analog to digital converters (ADC) is increasing.
[0003] As the input interface of wireless communication sensor terminals, analog-to-digital converters undertake functions such as data sampling, analog-to-digital conversion, signal processing, and gain control. The successive approximation analog-to-digital converter (SAR ADC) is a very promising converter type in current medium- and high-speed applications because of its simple structure and fewer analog modules, which makes it more suitable for advanced processes. Summary of the invention
[0004] (I) Purpose of the invention
[0005] The purpose of the present invention is to provide a low-power SAR ADC switch switching circuit and switching method based on capacitor splitting technology and combined with a C-2C structure, while reducing the power consumption of the CDAC switch, getting rid of the dependence on the intermediate common mode level during the CDAC switching process, so that the structure is suitable for low-voltage processes.
[0006] (II) Technical solution
[0007] In order to solve the above technical problems, the present invention provides a low-power SAR ADC switch switching circuit, which includes: a bootstrap switch, a capacitor array digital-to-analog converter CDAC, and a clock-controlled comparator; wherein the CDAC reference capacitors are from left to right and from high to low; in the sampling stage, the signal is sampled by the bootstrap switch and stored in the capacitor of the capacitor array digital-to-analog converter CDAC in the form of charge; in the comparison stage, the upper plate of the CDAC is connected to the clock-controlled comparator; the clock-controlled comparator compares the level of the upper plate of the CDAC, and controls the shift register to latch the comparison result, and flips the level of the lower plate of the CDAC bit by bit according to the comparison result; repeating the above process allows the ADC to complete successive approximation.
[0008] Among them, the capacitor array digital-to-analog converter CDAC includes four groups of C-2C structures. In the signal sampling stage, the two lower plates of each group of C-2C structures are connected to the Vcm=VDD / 2 level; in the level conversion stage, one end of the C-2C structure is fixed to keep the Vcm level unchanged, and the other end is flipped according to the output result of the comparator.
[0009] Among them, when the bias level point C of the C-2C structure capacitor in the third position of CDAC is flipped, when the level of point C is flipped from the Vcm level to VDD, the circuit from point C to ground includes: capacitor C1, capacitor C2, capacitor 2Cu, capacitor Ct, one end of capacitor C1 is point C, and the other end is connected to one end of capacitor C2 and one end of capacitor 2Cu, the other end of capacitor C2 is point M, point M is connected to one end of capacitor Ct, and the other end of capacitor 2Cu and the other end of capacitor Ct are grounded.
[0010] The value of the capacitor Ct is the sum of other remaining capacitors between point M and ground after removing the third C-2C capacitor, and Cu is the unit capacitance.
[0011] When the change of the bias level at point C is ΔVcm, the change of the output level at point M is ΔVout:
[0012]
[0013] When the bias level of the second bit of CDAC at point B changes by ΔVcm, the output ΔVout at point M is:
[0014]
[0015] Among them, when the bias level of the highest bit of CDAC at point A is ΔVcm, the output ΔVout at point M is:
[0016]
[0017] Among them, when the level of the lower plate of CDAC is flipped from low to high in sequence, the change in the output of point M on the upper plate is in a binary relationship, realizing the function of half-approximation; in the sampling stage, the lower plates of all capacitors are connected to Vcm; in the comparison stage, the bias end of the lower plate level of the positive and negative capacitors of the comparator is flipped from Vcm to VDD and GND respectively according to the comparison results; the common mode output of point M on the upper plate of CDAC maintains the Vcm level unchanged.
[0018] The present invention also provides a low-power SAR ADC switch switching method of a switch switching circuit, which comprises the following steps:
[0019] S1: Signal sampling stage, D1 and D2 in each C-2C structure are connected to VDD and GND respectively, and the other two split capacitors maintain fixed VDD and GND levels respectively;
[0020] S2: Level comparison stage, the two split capacitors at one end of the C-2C structure still maintain the VDD and GND levels unchanged, and the D1 and D2 ends are all switched to VDD or GND according to the judgment result of the comparator.
[0021] (III) Beneficial effects
[0022] The low-power SAR ADC switch switching circuit and switching method provided by the above technical solution is a dual-level high-efficiency switch control scheme with unchanged output common mode. While reducing the power consumption of the CDAC switch, it gets rid of the dependence on the intermediate common mode level during the CDAC switching process, making the structure suitable for low-voltage processes; it has the advantages of simple circuit structure, low power consumption, and unchanged output level. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Attached Figure 1 Schematic diagram of the Vcm-based classic switch switching method.
[0024] Attached Figure 2 Schematic diagram of the improved CDAC based on the C-2C structure.
[0025] Attached Figure 3 Simplified structure diagram of the circuit from point C to ground.
[0026] Attached Figure 4 Thevenin equivalent circuit diagram.
[0027] Attached Figure 5 Schematic diagram of capacitor splitting.
[0028] Attached Figure 6 Schematic diagram of the improvement based on capacitor splitting technology. DETAILED DESCRIPTION
[0029] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.
[0030] Attached Figure 1 Schematic diagram of the Vcm-based classic switch switching method. The classic switch switching method requires three levels of VDD, Vcm=VDD / 2, and GND for biasing, and the intermediate level VDD / 2 cannot be achieved under low voltage working conditions.
[0031] Reference Figures 2 to 6 As shown, the low-power SAR ADC switch switching circuit of this embodiment includes: a bootstrap switch, a capacitor array digital-to-analog converter CDAC, and a clock-controlled comparator; wherein the CDAC reference capacitors are from left to right and from high to low; in the sampling phase, the signal is sampled by the bootstrap switch and stored in the capacitor of the capacitor array digital-to-analog converter CDAC in the form of charge; in the comparison phase, the upper plate of CDAC is connected to the clock-controlled comparator; the clock-controlled comparator compares the level of the upper plate of CDAC, and controls the shift register to latch the comparison result, and flips the level of the lower plate of CDAC bit by bit according to the comparison result; repeating the above process allows the ADC to complete successive approximation.
[0032] Attached Figure 2 The present invention improves the CDAC structure based on the Vcm-based switching method, and uses C-2C capacitors to replace the reference capacitor C in CDAC except for the highest bit.
[0033] The capacitor array digital-to-analog converter CDAC includes four groups of C-2C structures. In the signal sampling stage, the two lower plates of each group of C-2C structures are connected to the Vcm=VDD / 2 level; in the level conversion stage, one end of the C-2C structure is fixed to keep the Vcm level unchanged, and the other end is flipped according to the output result of the comparator.
[0034] Take the case where the bias level (point C) of the third C-2C structure capacitor of CDAC is flipped as an example. When the level of point C flips from Vcm level to VDD, the simplified circuit diagram from point C to ground is as shown in the attached figure. Figure 3 As shown in the figure. Ct is the sum of the remaining capacitance between point M and ground after removing the third C-2C capacitor, and Cu is the unit capacitance. According to the Thevenin theorem, Figure 3 Can be equivalent to Figure 4 .from Figure 4 It can be deduced that when the bias level of the third bit (point C) changes by ΔVcm, the change in the output level at point M, ΔVout, is:
[0035]
[0036] Similarly, when the bias level of the second bit of CDAC (point B) changes by ΔVcm, the output ΔVout at point M is:
[0037]
[0038] The C-2C structure is not used for the highest bit of CDAC. When point A changes to ΔVcm, the output ΔVout at point M is:
[0039]
[0040] From the above derivation, it can be seen that when the CDAC lower plate flips from low to high, the change in the output of the upper plate (point M) is in a binary relationship, which can realize the function of half-approximation. Based on the Vcm-based switch switching method, the lower plates of all capacitors are connected to Vcm during the sampling phase. In the comparison phase, the bias end of the lower plate level of the positive and negative capacitors of the comparator flips from Vcm to VDD and GND respectively according to the comparison results. The output common mode of the CDAC upper plate (point M) maintains the Vcm level unchanged.
[0041] The CDAC switch method based on the C-2C structure improvement achieves the output common mode to maintain the Vcm level unchanged. However, under the low-voltage process 1.1V power supply, if the switch is connected to a voltage near Vcm=VDD / 2 and turned on, the gate voltage of the turn-on tube must be close to or even higher than 1.1V, which is difficult to achieve. Further, the present invention uses capacitor splitting technology for improvement.
[0042] Attached Figure 6 The improved schematic diagram of the present invention based on the capacitor splitting technology is shown in the figure. The capacitor value is halved and the Vcm level is replaced by the VDD and GND levels. The two levels are equivalent to the Thevenin level. Figure 5 shown.
[0043] Signal sampling stage, Figure 6 In each C-2C structure, the D1 and D2 terminals are connected to VDD and GND respectively, while the other two split capacitors maintain fixed VDD and GND levels. In the level comparison stage, the two split capacitors at one end of the C-2C structure still maintain the VDD and GND levels unchanged, while the D1 and D2 terminals are all switched to VDD or GND according to the judgment result of the comparator. Obviously, Figure 6 The improved structure in does not require Vcm level for biasing, which can be achieved Figure 2 The basic function of the structure.
[0044] Attached Figure 6 That is a schematic diagram of the switching method proposed by the present invention.
[0045] Dynamic power consumption, Figure 2 In the CDAC structure, the highest capacitor area is halved. Figure 6 The C2 capacitor in the C-2C structure acts as a buffer, reducing the charging current of the input terminal to the C1 capacitor. Both factors reduce the dynamic power consumption of the CDAC.
[0046] Based on the above switching device, the low power consumption SAR ADC switch switching method of this embodiment includes the following steps:
[0047] S1: In the signal sampling stage, the D1 and D2 terminals in each C-2C structure are connected to VDD and GND respectively, and the other two split capacitors maintain fixed VDD and GND levels respectively.
[0048] S2: Level comparison stage, the two split capacitors at one end of the C-2C structure still maintain the VDD and GND levels unchanged, and the D1 and D2 ends are all switched to VDD or GND according to the judgment result of the comparator.
[0049] The low-power SAR ADC switch switching method of this embodiment does not need to bias the Vcm level to achieve CDAC switch switching, while achieving low power consumption and being suitable for low-voltage processes.
[0050] In summary, the SAR ADC switch switching method provided by the present invention reduces the power consumption of the CDAC switch while getting rid of the dependence on the intermediate common mode level during the CDAC switch process, and is suitable for low voltage processes.
[0051] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A low power SARADC switch switching circuit, characterized in that: include: Bootstrap switch, capacitor array digital-to-analog converter CDAC, clock control comparator; wherein, CDAC reference capacitors are from left to right, from high to low; in the sampling phase, the signal is sampled by the bootstrap switch and stored in the capacitor array digital-to-analog converter CDAC capacitor in the form of charge; In the comparison stage, the upper plate of CDAC is connected to the clock-controlled comparator; the clock-controlled comparator compares the level of the upper plate of CDAC and controls the shift register to latch the comparison result, and flips the level of the lower plate of CDAC bit by bit according to the comparison result; the above process is repeated to enable the ADC to complete successive approximation.
2. The low power SARADC switch switching circuit according to claim 1, characterized in that: The capacitor array digital-to-analog converter CDAC includes four groups of C-2C structures. During the signal sampling phase, the two lower plates of each group of C-2C structures are connected to the Vcm=VDD / 2 level. In the level conversion stage, one end of the C-2C structure is fixed to keep the Vcm level unchanged, and the other end is flipped according to the output result of the comparator.
3. The low power SARADC switch switching circuit according to claim 2, characterized in that: When the bias level point C of the C-2C structure capacitor in the third position of CDAC is flipped, when the level of point C is flipped from the Vcm level to VDD, the circuit from point C to ground includes: capacitor C1, capacitor C2, capacitor 2Cu, capacitor Ct, one end of capacitor C1 is point C, and the other end is connected to one end of capacitor C2 and one end of capacitor 2Cu, the other end of capacitor C2 is point M, point M is connected to one end of capacitor Ct, and the other end of capacitor 2Cu and the other end of capacitor Ct are grounded.
4. The low power SARADC switch switching circuit according to claim 3, characterized in that: The value of capacitor Ct is the sum of other remaining capacitors between point M and ground after removing the third C-2C capacitor, and Cu is the unit capacitance.
5. The low power SARADC switch switching circuit according to claim 4, characterized in that: When the third-bit bias level at point C changes by ΔVcm, the change in the output level at point M is ΔVout:
6. The low power consumption SARADC switch switching circuit as claimed in claim 5, characterized in that: When the bias level of the second bit of CDAC at point B changes by ΔVcm, the output ΔVout at point M is:
7. The low power consumption SARADC switch switching circuit according to claim 6, characterized in that: When the bias level of the highest bit of CDAC at point A is ΔVcm, the output ΔVout at point M is:
8. The low power consumption SARADC switch switching circuit according to claim 7, characterized in that: When the level of the lower plate of CDAC is flipped from low to high in sequence, the change in the output of point M on the upper plate is in a binary relationship, realizing the function of half-approximation; in the sampling phase, the lower plates of all capacitors are connected to Vcm; in the comparison phase, the bias end of the lower plate level of the positive and negative capacitors of the comparator is flipped from Vcm to VDD and GND respectively according to the comparison results; the common mode output of point M on the upper plate of CDAC maintains the Vcm level unchanged.
9. A low power SARADC switching method based on the switching circuit of claim 8, characterized in that: The following steps are involved: S1: Signal sampling stage, D1 and D2 in each C-2C structure are connected to VDD and GND respectively, and the other two split capacitors maintain fixed VDD and GND levels respectively; S2: Level comparison stage, the two split capacitors at one end of the C-2C structure still maintain the VDD and GND levels unchanged, and the D1 and D2 ends are all switched to VDD or GND according to the judgment result of the comparator.
10. Application of the low power SARADC switch switching circuit according to any one of claims 1 to 8 in the field of wireless communication technology.