High-speed LVDS transmission system

Abstract

The invention discloses a high-speed LVDS (Low Voltage Differential Signaling) transmission system, which comprises a protocol layer and an implementation layer, and is characterized in that the protocol layer comprises a synchronization sequence and a transmission frame; the implementation layer comprises a sending end and a receiving end, wherein the sending end comprises a bit scrambling module, a framing module, a check value calculation module and an output parallel / serial conversion module; and the receiving end comprises an input delay adjustment module, an input serial / parallel conversion module, a single-path synchronization module, a check value verification module, a multi-path synchronization module, an output control module and a bit unwinding module. According to the invention, the transmission rate is high, and 8b / 10b coding is not needed; parallel and reliable transmission of any path of data is supported; the efficiency is high, all LVDS lines are used for transmitting data, and no state / control signals occupy extra LVDS lines; real-time dynamic self-adaptive training is carried out to adapt to rapid change of signal delay; resource consumption is low, only one point needs to be sampled for each path of data, and sampling and data delay resources are saved.

Description

Technical Field

[0001] The invention relates to a system for performing high-speed data transmission through LVDS, which is suitable for performing high-speed data transmission inside a device or between devices. Background Art

[0002] With the continuous improvement of the functional performance requirements of modern electronic devices and the continuous increase in the complexity of processing protocols, the data transmission rate within and between devices has gradually become a bottleneck in the design of electronic devices. The traditional synchronous data transmission scheme can only achieve a stable transmission of up to 150Mbps between chips, and can only reach a rate of about 75Mbps when crossing circuit boards. In addition, for synchronous transmission systems, the more parallel data paths there are, the worse the timing consistency is, and the lower the maximum rate that can be achieved is, which significantly reduces the communication efficiency between chips. In order to avoid the above problems caused by synchronous data transmission, the current mainstream solution is to use high-speed serial interfaces such as GTX to transmit data up to tens of Gbps through a pair of high-speed LVDS. However, the application of high-speed serial interfaces such as GTX requires the use of dedicated hardware resources, and the peripheral circuits also need to be designed accordingly, and their versatility and flexibility are poor.

[0003] In order to avoid the inconveniences caused by using dedicated high-speed serial interfaces, some FPGA manufacturers, literature and patents have discussed the use of chips with dynamic delay adjustment function for external pins to achieve high-speed communication through ordinary LVDS interfaces.

[0004] The principle of high-speed communication through ordinary LVDS is as follows Figure 1 As shown in the figure, due to factors such as circuit characteristics and clock phase noise, data will have a certain degree of uncertainty at the junction with other data, that is, the sampled data may be the data on the "left" side of the junction, or the data on the "right" side of the junction, or other "illegal" data. Therefore, the sampling result at the data junction is meaningless. In contrast, the data obtained at the best sampling point can be considered reliable. The solutions provided in the following materials all use various methods to find the best sampling point.

[0005] In the manual xapp585 "LVDS Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication", FPGA manufacturer Xilinx samples the input data at two sampling points with a phase difference of 1 / 2 data cycle, and performs statistics on the results. If the data is sufficiently random, if the data obtained at the two sampling points are significantly different, it is considered that the two sampling points have sampled different data; if the data obtained at the two sampling points are significantly the same, it is considered that the two sampling points have sampled the same data. Based on the above statistical rules, the positions of the two sampling points are synchronously adjusted, and finally one of the sampling points is located in the middle part of the transmitted data, and the other sampling point is located at the junction of the transmitted data. The sampling point located in the middle part of the transmitted data can be considered as the transmitted data. The disadvantages of this solution are: first, because it needs to sample twice in one symbol period, compared with the solution that only samples once in one symbol period, it consumes twice the hardware resources, especially for input delay adjustment resources, which are relatively scarce in general FPGAs or chips; second, the sampling data is unreliable when the algorithm adjusts the sampling point position, so the sampling position cannot be dynamically adjusted during the service data transmission process. Therefore, the transmitting and receiving ends must be of the same source, and the sampling position must remain unchanged, otherwise it cannot be used; third, this solution only synchronizes a single pair of LVDS lines, and does not involve the synchronization technology of parallel transmission of multiple pairs of LVDS lines; finally, in some scenarios, the randomness of the transmitted data cannot be guaranteed, which also limits the application of this solution. FPGA manufacturer Xilinx uses a solution similar to xapp585 in the manual xapp523 "LVDS 4x Asynchronous Oversampling Using 7SeriesFPGAs", setting 4 sampling points for the input data, each separated by 1 / 2 data period, and dynamically adjusting the sampling position through the algorithm. The disadvantage of this solution is that it uses more resources, consuming four times the hardware resources compared to the solution that only samples once in one symbol period.

[0006] The document "Implementation of High-Speed ​​LVDS Interface Based on FPGA", Li Dapeng et al., Aeronautical Computing Technology, presents a high-speed LVDS interface design based on FPGA. The disadvantages of this solution are: first, the clocks of both ends of the transmitter and receiver must be the same source; second, training is only performed during initialization, which cannot adapt to the dynamic changes of data delay; third, there are additional control signals at both ends of the transmitter and receiver; finally, although it supports parallel transmission of multiple pairs of LVDS lines, the synchronization between multiple channels only depends on the delay control word, and its synchronization is relatively fragile. The document "FPGA Design and Implementation of High-Speed ​​LVDS Interface", Liu Huafeng, Science and Technology Vision, presents a high-speed LVDS interface with automatic alignment function based on 8B / 10B encoding. The disadvantages of this solution are: first, the clocks of both ends of the transmitter and receiver must be the same source; second, 8b / 10b encoding is used, which reduces the transmission rate; finally, it does not support parallel transmission of multiple pairs of LVDS lines. The document "Application of SERDES Technology with Adaptive Dynamic Delay Adjustment in Broadband Data Transmission", Zhang Feng, Telecommunications Technology, proposed a solution based on SERDES technology to achieve high-speed transmission in response to the demand for broadband high-speed data transmission. The disadvantages of this solution are: first, the clocks at both ends of the transmitter and receiver must be the same source; second, training is only performed during initialization, which cannot adapt to the dynamic changes in data delay; finally, it does not support parallel transmission of multiple pairs of LVDS lines.

[0007] Patent CN202010117247.7 discloses a method and system for implementing clock synchronization of LVDS high-speed serial communication. The disadvantages of this solution are that, first, the clocks of both ends of the transmitter and receiver must be the same source; second, training is only performed during initialization, which cannot adapt to the dynamic changes in data delay; finally, it does not support parallel transmission of multiple pairs of LVDS lines. Patent CN202110563176.8 discloses an asynchronous serial LVDS high-speed and stable transmission system and method. The disadvantages of this solution are that, first, the clocks of both ends of the transmitter and receiver must be the same source; second, 8b / 10b encoding is used, and the transmission efficiency is low; third, the control word in the 8b / 10b encoding is used for training, and training is only performed once when a control word error is detected. Retransmission is required to complete reliable transmission, which increases the complexity and resource overhead of the system; finally, it does not support parallel transmission of multiple pairs of LVDS lines. Patent CN201910068468.7 discloses a multi-channel high-speed serial LVDS data sequencing method and circuit based on FPGA. The disadvantages of this solution are: first, the receiving end oversamples the received data three times, which consumes a lot of general resources and scarce resources; second, it does not support parallel transmission of multiple pairs of LVDS lines.

[0008] In summary, the weaknesses of current research are: 1. Some solutions use 8b / 10b encoding, which has low transmission efficiency; 2. Some solutions use oversampling technology (i.e., multiple sampling of a data at different locations), which increases the overhead of general resources and scarce resources; 3. The synchronization technology in some solutions cannot achieve real-time dynamic adjustment; 4. Most solutions require strict source synchronization or system synchronization at both ends of the transmitter and receiver; 5. Most solutions only study the high-speed transmission of a single pair of LVDS, and do not propose a solution for parallel transmission of multiple LVDS lines. Even if some solutions involve parallel transmission of multiple LVDS lines, the reliability of the solution is poor; 6. Some solutions use retransmission technology, which increases the complexity of both ends of the transmitter and receiver, while reducing transmission efficiency. Summary of the invention

[0009] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a high-speed LVDS transmission system, which is a reliable and stable high-speed LVDS transmission system that is high-speed, efficient, supports parallel transmission, has low resource overhead, can be dynamically adjusted in real time, and does not require strict synchronization of transmission and reception, thereby overcoming the above-mentioned problems in the prior art.

[0010] In order to solve the above technical problems, the present invention adopts the following technical solutions to achieve the above problems:

[0011] A high-speed LVDS transmission system includes a protocol layer and an implementation layer, wherein the protocol layer includes a synchronization sequence and a transmission frame; the implementation layer includes a transmitting end and a receiving end, wherein the transmitting end includes a bit scrambling module, a framing module, a check value calculation module, and an output parallel / serial conversion module; the receiving end includes an input delay adjustment module, an input serial / parallel conversion module, a single-channel synchronization module, a check value verification module, a multi-channel synchronization module, an output control module, and a bit unwrapping module.

[0012] The present invention also includes the following technical features:

[0013] Specifically, the synchronization sequence is used for training and synchronization at the receiving end. The synchronization sequence cannot be sent continuously and a transmission frame must be used as an interval. The transmission frame is subdivided into an empty frame and a data frame. The empty frame is used to separate the two synchronization sequences before and after when there is no data frame, and is also used to monitor the transmission status when there is no data frame. The data frame is used to carry business data.

[0014] Specifically, the synchronization sequence is a known sequence; the transmission frame format includes a frame header, a frame length, data, and a check, wherein the frame length is optional; the frame header is used to locate the start of the transmission frame in the data stream, the frame length is used to locate the end of the transmission frame, the data portion is used to carry the actual transmitted data, the check protects the frame length and the data portion to ensure correct transmission, and is also used for multi-channel synchronization check at the receiving end.

[0015] Specifically, the bit scrambling module performs bit scrambling according to the data input externally by the scrambling polynomial, so that the 0-1 distribution of the output data is random, and the scrambling polynomial used by the commonly used PCIE protocol is selected; the framing module is used to group the scrambled data into a transmission frame format, and output it, and control the output at the same time, that is, when there is no business data, the synchronization sequence and the empty frame are sent alternately, and the empty frame is optional. When there is data, the framed data is sent, and the module does not calculate the check value, and the position of the output check value is left blank; the check value calculation module is used to calculate and fill the check value left blank for the framed data, and the framed data includes data frames and empty frames; the output parallel / serial conversion module converts the low-speed parallel data into high-speed serial data for transmission.

[0016] Specifically, the single-channel synchronization module is used to determine the position of the synchronization sequence in the transmitted data, and adaptively adjust the tap coefficient based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to restore the synchronization sequence; thereafter, the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

[0017] Specifically, the workflow of the single-channel synchronization module includes: the single-channel synchronization module is in an initialization state when it starts working, and then detects the input data sequence until the synchronization sequence is detected, and starts delay coefficient training; assuming that the delay coefficient range is 0 to X-1, the delay coefficient is set to 0 to X-1 in sequence, and the input data is sampled and stored after the previous stage works stably, and finally X sampling values ​​are obtained; the obtained X sampling values ​​are searched to obtain a continuous interval with the same sampling value of the largest range, the middle point of the interval is the optimal delay coefficient, and the delay coefficient is set to the value; the frame header of the transmission frame is searched, and the waiting timer is started at the same time; if the frame header has been detected, the frame is deframed according to the frame format until the current frame ends; after the frame ends, the data at the next moment is judged, and if it is a transmission frame header, the frame is deframed; if it is a synchronization sequence, the delay coefficient is recalculated; if the frame header is still not found after the waiting counter counts to a given value, it jumps to the initialization state and resynchronizes.

[0018] Specifically, the input delay adjustment module accepts the control of the single-channel synchronization module and adjusts the input data delay so that the sampling point is located within the optimal sampling interval; the input serial / parallel conversion module and the output parallel / serial conversion module are symmetrical in function and convert high-speed serial data into low-speed parallel data for use by subsequent modules; the check value verification module is used to perform check value verification on the serial received data to detect whether there are bit errors or abnormalities in the transmission process; the multi-channel synchronization module is used to perform multi-channel synchronization on the serial data; the output control module is used to receive the data after multi-channel synchronization and perform check value verification to detect whether there are bit errors or abnormalities in the transmission process and multi-channel synchronization. If the check value verification is wrong, no output is performed to ensure that the output data is reliable; the bit dewrapping module corresponds to the bit scrambling module and is used to restore the scrambled data to the original data.

[0019] Specifically, the working process of the multi-channel synchronization module includes: the multi-channel synchronization module stores each channel of input data respectively, and outputs the write address of the first channel of data to the read-out controller after delay, and the read-out controller synchronously reads the data in all memories and outputs it.

[0020] Specifically, when the system performs high-speed data transmission, the processing process of the transmitting end includes: splitting the data and sending it to the bit scrambling module for bit scrambling; sending the scrambled data to the framing module, and the framing module frames the scrambled data according to the transmission frame format determined by the protocol; sending the framed data to the check value calculation module, and the check value calculation module calculates the data, obtains its check value and fills it into the position specified by the protocol; the output parallel / serial conversion module converts the data into groups and outputs it through the chip output pin.

[0021] Specifically, the processing process of the receiving end includes: data is input to the chip LVDS pin and enters the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient; the input serial / parallel conversion module restores the delayed data; the single-channel synchronization module performs single-channel synchronization on each channel of data respectively; the check value calculation module performs check value verification on the synchronized data; the multi-channel synchronization module performs multi-channel synchronization on the data; the output control module verifies the input data, and if the verification is correct, the data is output, and if the verification is wrong, the current frame of data is skipped; the bit unwrapping module performs bit unwrapping on the output of the output control module according to the grouping to restore the original data.

[0022] Compared with the prior art, the present invention has the following technical effects:

[0023] The present invention has a high transmission rate and does not require 8b / 10b encoding; the present invention supports parallel and reliable transmission of any data path; the present invention has high efficiency, all LVDS lines are used to transmit data, and no state / control signals occupy additional LVDS lines; the present invention performs real-time dynamic adaptive training to adapt to rapid changes in signal delay; the present invention consumes less resources, and only one point needs to be sampled for each data path (each pair of LVDS lines), saving sampling and data delay resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the high-speed LVDS transmission principle.

[0025] Figure 2 This is a single-channel synchronous module workflow.

[0026] Figure 3 This is the block diagram of the multi-channel synchronization module.

[0027] Figure 4 This is a structural diagram of a single-channel transmitting end of the present invention.

[0028] Figure 5 The figure is a schematic diagram of the structure of the multi-channel transmitting end of the present invention.

[0029] Figure 6 This is a structural diagram of a single-channel receiving end of the present invention.

[0030] Figure 7 The figure is a schematic diagram of the structure of a multi-channel receiving end of the present invention. DETAILED DESCRIPTION

[0031] Specific embodiments of the present invention are given below. It should be noted that the present invention is not limited to the following specific embodiments, and all equivalent changes made on the basis of the technical solution of this application fall within the protection scope of the present invention.

[0032] Example:

[0033] like Figures 2 to 7 As shown, this embodiment provides a high-speed LVDS transmission system, including a protocol layer and an implementation layer, wherein the protocol layer includes the design of a transmission protocol between a transmitting and receiving end, including a synchronization sequence and a transmission frame; the implementation layer includes an implementation design for a transmitting end and an implementation design for a receiving end, including a transmitting end and a receiving end, wherein the transmitting end includes a bit scrambling module, a framing module, a check value calculation module, and an output parallel / serial conversion module; the receiving end includes an input delay adjustment module, an input serial / parallel conversion module, a single-channel synchronization module, a check value verification module, a multi-channel synchronization module, an output control module, and a bit unwrapping module.

[0034] The transmission protocol is designed as follows: The data sent from the sender to the receiver consists of two sequences:

[0035] The first is the synchronization sequence, which is used for training and synchronization at the receiving end. The synchronization sequence cannot be sent continuously and must be separated by a transmission frame. The second is the transmission frame, which can be further divided into an empty frame and a data frame. The empty frame is used to separate the two synchronization sequences before and after when there is no data frame, and is also used to monitor the transmission status when there is no data frame. The other is a data frame, which is used to carry service data. The synchronization sequence is a known sequence. The transmission frame format consists of a frame header, a frame length (optional), data, and a checksum. The frame header is used to locate the start of the transmission frame in the data stream, the frame length is used to locate the end of the transmission frame and the frame length is optional, and the data part is used to carry the actual transmitted data. The checksum protects the frame length (optional) and the data part to ensure that it is transmitted correctly. It is also used for multi-channel synchronization check at the receiving end.

[0036] The bit scrambling module performs bit scrambling according to the data input externally by the scrambling polynomial, so that the 0-1 distribution of the output data is relatively random, and the scrambling polynomial adopted by the commonly used PCIE and other protocols can be selected; the framing module is used to group the scrambled data into a transmission frame format and output it, and control the output at the same time, that is, when there is no business data, the synchronization sequence and the empty frame (optional) are sent alternately, and when there is data, the framed data is sent. This module does not calculate the check value, and the position where the check value should be output is left blank; the check value calculation module is used to calculate and fill the check value left blank for the framed data (including data frames and empty frames); the output parallel / serial conversion module converts the low-speed parallel data into high-speed serial data for transmission.

[0037] The single-channel synchronization module is used to determine the position of the synchronization sequence in the transmitted data and adaptively adjust the tap coefficient based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to restore the synchronization sequence; then the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

[0038] like Figure 2 ,The workflow of the single-channel synchronization module includes:

[0039] When the single-channel synchronization module starts working, it is in the initialization state, and then the input data sequence is detected until the synchronization sequence is detected, and the delay coefficient training begins; assuming that the optional range of the delay coefficient is 0 to X-1, the delay coefficient is set to 0 to X-1 in turn, and the input data is sampled and stored after waiting for a period of time until the previous stage works stably, and finally X sampling values ​​are obtained; the obtained X sampling values ​​are searched to obtain a continuous interval with the same sampling value of the largest range, and the middle point of the interval is considered to be the optimal delay coefficient, and the delay coefficient is set to this value; after waiting for a period of time, the frame header of the transmission frame is searched, and a waiting timer is started at the same time to prevent the frame header from being detected within the expected time due to training errors or other situations, thereby causing the module to be in an abnormal state for a long time, causing system abnormalities; if the frame header has been detected, the frame is deframed according to the frame format until the current frame ends; after the frame ends, the data at the next moment is judged, and if it is a transmission frame header, the frame is deframed; if it is a synchronization sequence, the delay coefficient is recalculated; if the frame header is still not found after the waiting counter count reaches a given value, it jumps to the initialization state and resynchronizes.

[0040] The input delay adjustment module accepts the control of the single-channel synchronization module and adjusts the input data delay so that the sampling point is within the optimal sampling interval; the input serial / parallel conversion module and the output parallel / serial conversion module are symmetrical in function and convert high-speed serial data into low-speed parallel data for use by the subsequent modules; the check value verification module is used to perform check value verification on the serial received data to detect whether there are bit errors or abnormalities in the transmission process; the multi-channel synchronization module is used to perform multi-channel synchronization on the serial data; the output control module is used to receive the data after multi-channel synchronization and perform check value verification to detect whether there are bit errors or abnormalities in the transmission process and multi-channel synchronization. If the check value verification is wrong, no output is performed to ensure the reliability of the output data; the bit dewrapping module corresponds to the bit scrambling module and is used to restore the scrambled data to the original data.

[0041] like Figure 3 The working process of the multi-channel synchronization module includes: the multi-channel synchronization module stores each input data separately, and outputs the write address of the first data to the read-out controller after a delay of several clocks. The read-out controller synchronously reads the data in all memories and outputs it.

[0042] In this embodiment, it is assumed that there is a need for high-speed data transmission between two chips via LVDS lines, the working clocks of the receiving and transmitting chips are both 200MHz, and the maximum data transmission rate is close to 3200Mbps, so the data needs to be transmitted in 16 parallel channels under the 200MHz working clock. Assuming that the high-speed LVDS transmission system uses a serial / parallel conversion coefficient of 4 (that is, the serial-to-parallel conversion module converts 1 channel of 800MHz data into 4 channels of 200MHz data, and the parallel-to-serial conversion module converts 4 channels of 200MHz data into 1 channel of 800MHz data) for data transmission, 4 lines are required to transmit data at a line rate of 800Mbps.

[0043] In this case, the sending end processes as follows:

[0044] Split the data and send it to the bit scrambling module for bit scrambling;

[0045] The scrambled data is sent to the framing module, which frames the scrambled data according to the transmission frame format determined by the protocol (the check value part is left blank);

[0046] The framed data is sent to the check value calculation module, which calculates the data, obtains its check value and fills it into the position specified by the protocol;

[0047] The output parallel / serial conversion module converts 4 groups of 4 channels of 200Mbps data into 4 channels of 800Mbps data and outputs them through the chip output pins.

[0048] The receiving end processing includes:

[0049] 4 channels of 800Mbps data are input to 4 pairs of LVDS pins on the chip and enter the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient;

[0050] The input serial / parallel conversion module restores the delayed 4-channel 800Mbps data into 4 groups of 4-channel 200Mbps data;

[0051] The single-channel synchronization module performs single-channel synchronization on each channel of data respectively;

[0052] The check value calculation module performs check value verification on the synchronized data;

[0053] The multi-channel synchronization module performs multi-channel synchronization on 4 groups of 4 channels of 200Mbps data;

[0054] The output control module verifies the input data. If the verification is correct, the data is output. If the verification is wrong, the current frame of data is skipped.

[0055] The bit decompression module performs bit decompression on the output of the output control module according to the grouping to restore the original data.

[0056] The undisclosed technologies in the present invention are common knowledge to those skilled in the art.

[0057] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0058] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0059] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A high-speed LVDS transmission system, characterized in that: It includes the protocol layer and the implementation layer, wherein the protocol layer includes the synchronization sequence and the transmission frame; The implementation level includes a transmitting end and a receiving end. The transmitting end includes a bit scrambling module, a framing module, a check value calculation module, and an output parallel / serial conversion module; the receiving end includes an input delay adjustment module, an input serial / parallel conversion module, a single-channel synchronization module, a check value verification module, a multi-channel synchronization module, an output control module, and a bit unwrapping module.

2. The high-speed LVDS transmission system according to claim 1, characterized in that: The synchronization sequence is used for training and synchronization at the receiving end. The synchronization sequence cannot be sent continuously and must use transmission frames as intervals. The transmission frames are subdivided into empty frames and data frames. The empty frame is used to separate the two synchronization sequences before and after when there is no data frame, and is also used to monitor the transmission status when there is no data frame. The data frame is used to carry business data.

3. The high-speed LVDS transmission system according to claim 2, characterized in that: The synchronization sequence is a known sequence; the transmission frame format includes a frame header, a frame length, data, and a checksum, wherein the frame length is optional; The frame header is used to locate the start of the transmission frame in the data stream, the frame length is used to locate the end of the transmission frame, the data part is used to carry the actual transmitted data, and the checksum protects the frame length and data part to ensure their correct transmission. It is also used for multi-channel synchronization check at the receiving end.

4. The high-speed LVDS transmission system according to claim 3, characterized in that: The bit scrambling module performs bit scrambling according to the data input externally by the scrambling polynomial, so that the 0-1 distribution of the output data is random, and the scrambling polynomial used by the commonly used PCIE protocol is selected; the framing module is used to group the scrambled data into a transmission frame format, and output it, and control the output at the same time, that is, when there is no business data, the synchronization sequence and the empty frame are sent alternately, and the empty frame is optional. When there is data, the framed data is sent. The module does not calculate the check value, and the position of the output check value is left blank; The check value calculation module is used to calculate and fill the check value left blank for the framed data, where the framed data includes a data frame and an empty frame; The output parallel / serial conversion module converts low-speed parallel data into high-speed serial data for transmission.

5. The high-speed LVDS transmission system according to claim 4, characterized in that: The single-channel synchronization module is used to determine the position of the synchronization sequence in the transmission data, and adaptively adjust the tap coefficient based on the synchronization sequence; after the adjustment is completed, word synchronization is performed to restore the synchronization sequence; thereafter, the frame header is searched and the frame is deframed according to the transmission frame format until the synchronization sequence is detected again.

6. The high-speed LVDS transmission system according to claim 5, characterized in that: The workflow of the single-channel synchronization module includes: the single-channel synchronization module is in an initialization state when it starts working, and then detects the input data sequence until the synchronization sequence is detected, and starts delay coefficient training; assuming that the delay coefficient range is 0 to X-1, the delay coefficient is set to 0 to X-1 in sequence, and after the previous stage works stably, the input data is sampled and stored, and finally X sampling values ​​are obtained; the obtained X sampling values ​​are searched to obtain a continuous interval with the same sampling value of the largest range, the middle point of the interval is the optimal delay coefficient, and the delay coefficient is set to the value; the frame header of the transmission frame is searched, and the waiting timer is started at the same time; if the frame header has been detected, the frame is deframed according to the frame format until the current frame ends; after the frame ends, the data at the next moment is judged, and if it is a transmission frame header, the frame is deframed; if it is a synchronization sequence, the delay coefficient is recalculated; if the frame header is still not found after the waiting counter counts to a given value, it jumps to the initialization state and resynchronizes.

7. The high-speed LVDS transmission system according to claim 5, characterized in that: The input delay adjustment module is controlled by the single-channel synchronization module to adjust the input data delay so that the sampling point is located within the optimal sampling interval; the input serial / parallel conversion module and the output parallel / serial conversion module have symmetrical functions and convert high-speed serial data into low-speed parallel data for use by the subsequent modules; the check value check module is used to check the check value of the serially received data to detect whether there is a bit error or abnormality in the transmission process; The multi-channel synchronization module is used to synchronize serial data in multiple channels; The output control module is used to receive the data after multi-channel synchronization is completed, and perform check value verification to detect whether there is bit error or abnormality during the transmission process and multi-channel synchronization. If the check value is wrong, no output is performed to ensure the reliability of the output data; The bit dewrapping module corresponds to the bit scrambling module and is used to restore the scrambled data to the original data.

8. The high-speed LVDS transmission system according to claim 7, characterized in that: The working process of the multi-channel synchronization module includes: the multi-channel synchronization module stores each channel of input data respectively, and outputs the write address of the first channel of data to the read-out controller after delay, and the read-out controller synchronously reads the data in all memories and outputs it.

9. The high-speed LVDS transmission system according to claim 1, characterized in that: When the system performs high-speed data transmission, the processing process of the transmitting end includes: splitting the data and sending it to the bit scrambling module for bit scrambling; sending the scrambled data to the framing module, and the framing module frames the scrambled data according to the transmission frame format determined by the protocol; sending the framed data to the check value calculation module, and the check value calculation module calculates the data to obtain its check value and fills it into the position specified by the protocol; the output parallel / serial conversion module converts the data into groups and outputs it through the chip output pins.

10. The high-speed LVDS transmission system according to claim 9, characterized in that: The processing process of the receiving end includes: data is input to the chip LVDS pin and enters the input delay adjustment module; the input delay adjustment module delays the input data according to the currently set delay coefficient; the input serial / parallel conversion module restores the delayed data; the single-channel synchronization module performs single-channel synchronization on each channel of data respectively; the check value calculation module performs check value verification on the synchronized data; the multi-channel synchronization module performs multi-channel synchronization on the data; the output control module verifies the input data, outputs the data if the verification is correct, and skips the current frame of data if the verification is wrong; the bit unwrapping module performs bit unwrapping on the output of the output control module according to the grouping to restore the original data.

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