Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device which comprises a memory stack pair, and the memory stack pair comprises a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure is provided with a first front surface and a first back surface opposite to the first front surface, the second memory semiconductor structure is provided with a second front surface and a second back surface opposite to the second front surface, and the first memory semiconductor structure is bonded to the second memory semiconductor structure; the first front surface of the first memory semiconductor structure is adjacent to the second front surface of the second memory semiconductor structure, and the first back surface is far away from the second back surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a memory stack structure. Background Art

[0002] As artificial intelligence (AI) becomes increasingly popular and widely used in many applications in our daily lives, the market demand for high-performance computing (HPC) is also growing rapidly. Since AI models usually require complex calculations on large amounts of data, the processing speed of AI is limited not only by the hardware computing power but also by the memory bandwidth (i.e., data access speed). In order to meet the HPC demand for high memory bandwidth, heterogeneous wafer-on-wafer (WoW) stacking technology is used to stack multiple memory wafers on a logic wafer. The WoW stacking structure allows the logic die to access more memory nearby, resulting in higher data bandwidth. However, since the stacking process affects the yield, the improvement of the heterogeneous structure process has become a key issue that needs to be urgently addressed in this field. Summary of the invention

[0003] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first memory stack pair. The first memory stack pair includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. The first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is adjacent to the second front side of the second memory semiconductor structure, and the first back side is away from the second back side.

[0004] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes N memory stack pairs. Each of the N memory stack pairs includes a first memory semiconductor structure and a second memory semiconductor structure. The first memory semiconductor structure has a first front side and a first back side opposite to the first front side. The second memory semiconductor structure has a second front side and a second back side opposite to the second front side. Wherein N≥1, the first memory semiconductor structure is bonded to the second memory semiconductor structure, and the first front side of the first memory semiconductor structure is adjacent to the second front side of the second memory semiconductor structure, and the first back side is away from the second back side.

[0005] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a first memory semiconductor structure having a first front side and a first back side, providing a second memory semiconductor structure having a second front side and a second back side, and bonding the first memory semiconductor structure to the second memory semiconductor structure to form a first memory stack pair, wherein the first front side of the first memory semiconductor structure is adjacent to the second front side of the second memory semiconductor structure.

[0006] Simple diagram description

[0007] Figure 1 Shows a semiconductor structure according to a comparative embodiment of the present disclosure;

[0008] Figures 2A to 2H Display for manufacturing Figure 1 A cross-sectional view or side view of one or more stages of a semiconductor structure;

[0009] Figure 3 A semiconductor device according to an embodiment of the present disclosure is shown;

[0010] Figure 4 shows a semiconductor device according to another embodiment of the present disclosure;

[0011] Figure 5 A semiconductor device according to another embodiment of the present disclosure is shown.

[0012] Figure 6 An embodiment of the present disclosure is shown for manufacturing Figure 5 A method flow chart of a semiconductor device in the present invention;

[0013] 7A to 7F An embodiment of the present disclosure is shown for manufacturing Figure 5 A cross-sectional view of one or more stages of a semiconductor device;

[0014] Figure 8 shows a semiconductor device according to another embodiment of the present disclosure;

[0015] 9A to 9C An embodiment of the present disclosure is shown for manufacturing Figure 8 A cross-sectional view of one or more stages of a semiconductor device;

[0016] Fig.10 shows a semiconductor device according to another embodiment of the present disclosure;

[0017] FIG. 11A to FIG. 11C An embodiment of the present disclosure is shown for manufacturing Fig.10 A cross-sectional view of one or more stages of a semiconductor device;

[0018] Fig.12 shows a semiconductor device according to another embodiment of the present disclosure;

[0019] FIG. 13A to FIG. 13C An embodiment of the present disclosure is shown for manufacturing Fig.12 A cross-sectional view of one or more stages of a semiconductor device. DETAILED DESCRIPTION

[0020] The following description of the present disclosure is accompanied by drawings, which are incorporated into and constitute a part of this specification and illustrate embodiments of the present disclosure, but the present disclosure is not limited to these embodiments. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0021] References to "one embodiment," "an exemplary embodiment," "an exemplary embodiment," "another embodiment," "another embodiment," etc. indicate that the embodiment includes a particular function, structure, or characteristic, but not every embodiment is required to include the particular function, structure, or characteristic. Further, repeated use of the phrase "in this embodiment" does not necessarily refer to the same embodiment, although it may be the same.

[0022] In order to make the disclosure fully understandable, detailed steps and structures are provided in the following description. Obviously, the implementation of the disclosure is not limited to the specific details known to those skilled in the art. In addition, known structures and steps are not described in detail to avoid unnecessary limitations of the disclosure. The preferred embodiments of the disclosure will be described in detail below. However, in addition to the detailed description, the disclosure can also be widely implemented in other embodiments. The field of the disclosure is not limited to such detailed description, but is defined by the scope of the patent application.

[0023] Figure 1 A semiconductor structure 900 with heterogeneous integration according to a comparative embodiment of the present disclosure is shown. The semiconductor structure 900 includes memory semiconductor structures 910A, 910B, 910C, and 910D and a logic semiconductor structure 920. Figure 1 As shown, memory semiconductor structures 910A, 910B, 910C, and 910D are sequentially stacked on a logic semiconductor structure 920 .

[0024] FIG. 2A to FIG. 2H A comparative example according to the present disclosure is shown for manufacturing Figure 1 FIG. 9 is a cross-sectional view or side view of one or more stages of the semiconductor structure 900 .

[0025] exist Figure 2A In the embodiment, a memory semiconductor structure 910A is provided. Figure 2A As shown, the memory semiconductor structure 910A includes a substrate 912A and a semiconductor dielectric 914A formed above the substrate 912A.

[0026] exist Figure 2B In the embodiment, the memory semiconductor structure 910A is bonded to the logic semiconductor structure 920 using the front side of the memory semiconductor structure 910A (ie, the side close to the semiconductor dielectric 914A, in other words, the side away from the substrate 912A).

[0027] exist Figure 2C In the present invention, the substrate 912A is thinned to form a through silicon via (TSV) 915A in the substrate 912A. In addition, a redistribution layer (RDL) 916A may be formed on the substrate 912A. The RDL 916A is connected to the interconnect structure 913A formed in the semiconductor dielectric 914A through the through silicon via 915A.

[0028] exist Figure 2D In the embodiment, the memory semiconductor structure 910B is bonded to the memory semiconductor structure 910A by using the front side of the memory semiconductor structure 910B (i.e., the side close to the semiconductor dielectric 914B, in other words, the side away from the substrate 912B) facing the back side of the memory semiconductor structure 910A (i.e., the side close to the substrate 912A). Figure 2E In the present invention, the substrate 912B of the second memory semiconductor structure 910B has been thinned, and a redistribution layer 916B is formed on the back side of the memory semiconductor structure 910B (i.e., the side close to the substrate 912B), and is connected to the interconnection structure 913B formed in the semiconductor dielectric 914B through a silicon via 915B formed in the substrate 912B.

[0029] Through similar processes, the memory semiconductor structures 910C and 910D may then be stacked on the memory semiconductor structure 910B, such as Figures 2F to 2H In this case, each memory semiconductor structure can be bonded to another memory semiconductor structure, and its front side faces the back side of the other memory semiconductor structure below.

[0030] In addition, FIG. 2A to FIG. 2HIn the process shown, the memory semiconductor structure 910A is bonded to the logic semiconductor structure 920 at an early stage. Therefore, the logic semiconductor structure 920 is disposed at the bottom during all bonding processes and thinning processes to serve as the base of the stacked structure. Therefore, the logic semiconductor structure 920 must withstand the physical stress applied during the bonding process and thinning process (such as chemical mechanical polishing (CMP) or grinding), which may damage the logic semiconductor structure 920 and reduce the yield. Specifically, each bonding stage of the memory semiconductor structure may cause a loss of yield. If a yield loss occurs in one of the bonding stages, it will further affect the yield of the entire device. In particular, since the design of the logic semiconductor structure 920 is complex and the cost is higher than that of the memory semiconductor structures 910A to 910D, damage to the logic semiconductor structure 920 may significantly increase the total manufacturing cost. For example, the logic semiconductor structure 920 may include one or more processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a controller, or an application-specific integrated circuit (ASIC). Therefore, the loss of the logic semiconductor structure 920 should be reduced as much as possible. In addition, the logic semiconductor structure can be replaced by an intermediate substrate (e.g., a glass substrate) to move the bonding process step of the logic semiconductor structure 920 to a later step. However, the use of the intermediate substrate will increase the overall process cost, and the debonding process of the intermediate substrate will also affect the yield. Therefore, the cost and yield loss of the entire process should also be considered.

[0031] Figure 3 A semiconductor device 100 according to an embodiment of the present disclosure is shown. The semiconductor device 100 includes a memory stack pair 11, and the memory stack pair 11 includes a memory semiconductor structure 110A and a memory semiconductor structure 110B. The memory semiconductor structure 110A is stacked on the memory semiconductor structure 110B. In some embodiments, the memory semiconductor structures 110A and 110B are volatile memories (e.g., dynamic random access memories, DRAMs) or non-volatile memories (e.g., NOR flash memories or NAND flash memories).

[0032] The memory semiconductor structure 110A includes a substrate 112A and a dielectric 114A. In some embodiments, the substrate 112A may include a semiconductor material, such as silicon, germanium, gallium, glass, or a combination thereof. In some embodiments, the substrate 112A may be a wafer substrate. In some embodiments, the substrate 112A is a silicon substrate. In some embodiments, the substrate 112A is a grain-level silicon substrate.

[0033] like Figure 3As shown, dielectric 114A is disposed above substrate 112A. In some embodiments, dielectric 114A includes a dielectric material, such as silicon oxide, silicon nitride, polymer, etc. In some embodiments, dielectric 114A includes a plurality of dielectric layers stacked on each other. In some embodiments, dielectric 114A includes the same material or different materials. In some embodiments, dielectric 114A includes an inter-layer dielectric (ILD) and an inter-metal dielectric (IMD).

[0034] In some embodiments, the memory semiconductor structure 110A further includes at least one interconnect structure 113A formed within the dielectric 114A. In some embodiments, the configuration of the interconnect structure 113A facilitates the formation of electrical wiring between devices, such as transistors and capacitors, formed in the active region (not shown) of the substrate 112A, so as to form a desired circuit (e.g., a memory cell). For example, the interconnect structure 113A may include metal lines extending laterally in different layers, and metal vias extending vertically to connect metal lines located in different layers. In some embodiments, the interconnect structure 113A and the dielectric 114A are formed in a process that can be a back end of line (BEOL).

[0035] The memory semiconductor structure 110B may be configured to be similar or identical to the memory semiconductor structure 110A. For example, the memory semiconductor structure 110B may further include a substrate 112B, a dielectric 114B, and at least one interconnect structure 113B formed in the dielectric 114B. In the present embodiment, the memory semiconductor structure 110A has a front side 110A1 (i.e., close to the dielectric 114A) and a back side 110A2 (i.e., close to the substrate 112A) opposite to the front side 110A1. In addition, the memory semiconductor structure 110B has a front side 110B1 (i.e., close to the dielectric 114B) and a back side 110B2 (i.e., close to the substrate 112B) opposite to the front side 110B1. In some embodiments, both the memory semiconductor structures 110A and 110B are DRAMs. In some embodiments, both the memory semiconductor structures 110A and 110B are DRAMs with the same capacity or density. In some embodiments, the memory semiconductor structures 110A and 110B have the same capacity and may be DRAMs manufactured using the same process and the same mask.

[0036] In the present embodiment, the memory semiconductor structure 110A is bonded to the memory semiconductor structure 110B through the bonding layer 130A1 formed on the front surface 110A1 of the memory semiconductor structure 110A and the bonding layer 130B1 formed on the front surface 110B1 of the memory semiconductor structure 110B. Figure 3 As shown, the bonding layer 130A1 includes a bonding dielectric 132A1 and at least one bonding pad 134A1. In some embodiments, the bonding pad 134A1 is surrounded by the bonding dielectric 132A1 and is at least partially exposed therefrom. In some embodiments, the bonding pad 134A1 extends through the bonding dielectric 132A1 to be electrically connected to the interconnect structure 113A formed in the dielectric 114A. Similarly, the bonding layer 130B1 includes the bonding dielectric 132B1 and at least one bonding pad 134B1 formed therein.

[0037] In some embodiments, the bonding layer 130A1 and the bonding layer 130B1 can be bonded through a hybrid bonding process. In some embodiments, the bonding pad 134A1 and the bonding pad 134B1 can be aligned to facilitate the execution of the hybrid bonding process. Specifically, the hybrid bonding process includes bonding the bonding dielectric 132A1 in the bonding layer 130A1 to the bonding dielectric 132B1 in the bonding layer 130B1 (dielectric to dielectric), and bonding the bonding pad 134A1 in the bonding layer 130A1 to the bonding pad 134B1 in the bonding layer 130B1 (metal to metal). For example, in the hybrid bonding process, the initial bonding can occur at the dielectric-to-dielectric interface at room temperature and atmospheric conditions. The metal-to-metal connection of copper can be formed through annealing and metal diffusion. However, the present disclosure is not limited thereto. Other feasible bonding processes may also be adopted to facilitate the hybrid bonding process.

[0038] In the present embodiment, the memory semiconductor structure 110A is bonded to the memory semiconductor structure 110B, wherein the front surface 110A1 of the memory semiconductor structure 110A is adjacent to the front surface 110B1 of the memory semiconductor structure 110B. In other words, the memory semiconductor structure 110A is bonded to the memory semiconductor structure 110B in a front-to-front (i.e., face-to-face) manner, and the back surface 110A2 of the memory semiconductor structure 110A is away from the back surface 110B2 of the memory semiconductor structure 110B.

[0039] In some embodiments, the memory semiconductor structures used to form the memory stack pair may have circuit layouts that are mirror images of each other. For example, the circuit layout of the memory semiconductor structure 110A may be a mirror image of the circuit layout of the memory semiconductor structure 110B. In this case, when the positions of the input / output ports of the memory semiconductor structure 110A and the positions of the input / output ports of the memory semiconductor structure 110B are stacked in a face-to-face manner, the two can be aligned, such as Figure 3 As shown in FIG. 1 . In this way, the configuration of the bonding pads 134A1 and 134B1 can be simplified. However, the present disclosure is not limited thereto. In some embodiments, the circuit layout of the memory semiconductor structure 110A can be mirror-symmetrical along the central symmetric surface that cuts through the dielectric 114A, and the circuit layout of the memory semiconductor structure 110B can be the same as the circuit layout of the memory semiconductor structure 110A, so that when the position of the input / output port of the memory semiconductor structure 110A and the position of the input / output port of the memory semiconductor structure 110B are stacked in a front-to-front manner, the two can still be aligned with each other. In addition, in this case, the memory semiconductor structure 110A and the memory semiconductor structure 110B can be manufactured using the same mask, thereby further reducing the manufacturing cost and the complexity of the bonding process.

[0040] In some embodiments, the memory stack pair 11 can be used as a stacking unit to be stacked with a logic semiconductor structure, so that the logic semiconductor structure can be joined at a later or final stage, thereby reducing the joining process steps when integrating with the logic semiconductor structure and protecting the expensive logic semiconductor structure from being damaged during the process.

[0041] Figure 4 A semiconductor device 100' according to another embodiment of the present disclosure is shown. The semiconductor device 100' can be manufactured by thinning the back substrate 112A of the semiconductor device 100 and forming its redistribution layer 116A and its bonding layer 130A2 to allow the logic semiconductor structure to be stacked on the memory stack pair 11. Specifically, the substrate 112A of the semiconductor device 100' located at the back side 110A2 of the memory semiconductor structure 110A can be thinned so as to form a through silicon via 115A within the substrate 112A. In addition, the redistribution layer 116A can be formed on the substrate 112A and can be connected to the interconnect structure 113A through the through silicon via 115A, and connected to the bonding layer 130A2 for bonding with the logic semiconductor structure. The redistribution layer 116A and the bonding layer 130A2 are formed adjacent to the back side 110A2 of the memory semiconductor structure 110A and away from the front side 110A1 of the memory semiconductor structure 110A.

[0042] Figure 5A semiconductor device 200 according to an embodiment of the present disclosure is shown. The semiconductor device 200 includes a memory stack pair 11 and a logic semiconductor structure 120 stacked on the memory stack pair 11. The logic semiconductor structure 120 includes a substrate 122, a dielectric 124 formed above the substrate 122, and at least one interconnect structure 123 formed within the dielectric 124.

[0043] In the present embodiment, the logic semiconductor structure 120 has a front side 1201 and a back side 1202 opposite to the front side 1201. The front side 1201 is close to the dielectric 124 and away from the substrate 122. The logic semiconductor structure 120 is bonded to the memory stack pair 11 using a bonding layer 140 formed on the front side 1201 of the logic semiconductor structure 120 and a bonding layer 130A2 formed on the back side 110A2 of the memory semiconductor structure 110A. In this way, the logic semiconductor structure 120 can be combined with the memory stack pair 11 to form a heterogeneous integration, wherein the front side 1201 of the logic semiconductor structure 120 is adjacent to the back side 110A2 of the memory semiconductor structure 110A. In this case, the logic semiconductor structure 120 can be stacked on the memory stack pair 11 after the memory stack pair 11 is formed, thereby protecting the logic semiconductor structure 120 from being damaged during the stacking process and thinning process of the memory stack pair 11. In some embodiments, the memory stack pair 11 can provide a reliable yield, and the logic semiconductor structure 120 can be integrated with the memory stack pair through a single bonding process, thereby reducing the impact of the bonding process on the yield.

[0044] Figure 6 The flowchart of a method M1 for manufacturing a semiconductor device 200 according to an embodiment of the present disclosure is shown. The method M1 includes steps S110 to S180. Figures 7A to 7F A cross-sectional view is shown of one or more stages of a method M1 for fabricating a semiconductor device 200 according to an embodiment of the present disclosure.

[0045] In steps S110 and S120, a memory semiconductor structure 110A and a memory semiconductor structure 110B are provided. Fig. 7A and Figure 7B As shown, bonding layers 130A1 and 130B1 may be formed on the front side 110A1 of the memory semiconductor structure 110A and the front side 110B1 of the memory semiconductor structure 110B, respectively, to facilitate the hybrid bonding process in step S130 .

[0046] In step S130, Figure 7CAs shown, the memory semiconductor structure 110A can be bonded to the memory semiconductor structure 110B by hybrid bonding the bonding layer 130A1 to the bonding layer 130B1. In this way, a memory stack pair 11 can be formed, wherein the front side 110A1 of the memory semiconductor structure 110A is adjacent to the front side 110B1 of the memory semiconductor structure 110B, and they are in a front-to-front (i.e., face-to-face) state. In some embodiments, the memory semiconductor structure 110A and the memory semiconductor structure 110B can be provided in the form of a wafer, and in this case, the memory stack pair 11 is a wafer-on-wafer (WoW) structure.

[0047] In step S140, the substrate 112A at the back side 110A2 of the memory semiconductor structure 110A may be thinned so as to form a through silicon via 115A in the substrate 112A in step S150. Fig.7D As shown, in step S160 , a redistribution layer 116A may be formed on the substrate 112A and connected to the interconnect structure 113A through the through silicon via 115A.

[0048] In step S170, a logic semiconductor structure 120 is provided. Fig. 7E As shown, the logic semiconductor structure 120 includes a substrate 122, a dielectric 124, and at least one interconnect structure 123 formed in the dielectric 124. Furthermore, a bonding layer 140 including a bonding dielectric 142 and at least one bonding pad 144 may be formed on the front side 1201 of the logic semiconductor structure 120. In some embodiments, the bonding pad 144 is surrounded by the bonding dielectric 142 and is at least partially exposed therefrom. In some embodiments, the bonding pad 144 extends through the bonding dielectric 142 to be electrically connected to the interconnect structure 123 formed in the dielectric 124.

[0049] In step S180, the bonding layer 140 is bonded to the bonding layer 130A2 by hybrid bonding, so that the logic semiconductor structure 120 can be bonded to the memory stack pair 11, so that the front side 1201 of the logic semiconductor structure 120 is adjacent to the back side 110A2 of the memory semiconductor structure 110A. Figure 7F shown.

[0050] Through method M1, the memory semiconductor structures 110A and 110B can be first bonded into a memory stack pair 11, and in a subsequent step, the logic semiconductor structure 120 can be bonded to the memory stack pair 11; therefore, the logic semiconductor structure 120 can be free from the physical stress generated during the bonding process of the memory stack pair 11. In addition, method M1 can be performed without any intermediate carrier, thus avoiding the defects and costs caused by the carrier. In this way, the semiconductor device 200 can be manufactured at a lower cost and a higher yield.

[0051] In some embodiments, the memory semiconductor structures 110A, 110B and the logic semiconductor structure 120 may be provided in a wafer form, and the semiconductor device 200 may refer to a wafer-on-wafer structure of the memory semiconductor structures 110A, 110B and the logic semiconductor structure 120. However, the present disclosure is not limited thereto. In some embodiments, Figure 7F The wafer-on-wafer structure shown may be further cut to form a plurality of stacked dies, and the semiconductor device 200 may also refer to a stacked die singulated from the WoW structure. In this case, the memory semiconductor structures 110A, 110B and the logic semiconductor structure 120 may be referred to as stacked memory dies and logic dies. In some embodiments, the logic semiconductor structure 120 may refer to a wafer, and the stack of the memory semiconductor structures 110A and 110B may refer to a stacked die, and the semiconductor structure may be referred to as a chip on wafer (CoW) structure.

[0052] In some embodiments, 7A to 7F The process shown is used to form a semiconductor device including more memory semiconductor structures, while ensuring that the logic semiconductor structure is bonded at a later stage, thereby reducing the impact on yield and the cost of the overall process.

[0053] Figure 8 The semiconductor device 300 according to an embodiment of the present disclosure is shown. The semiconductor device 300 is different from the semiconductor device 200 in that the semiconductor device 300 further includes another memory stack pair 12. The memory stack pair 12 includes a memory semiconductor structure 110C and a memory semiconductor structure 110D. In some embodiments, the memory semiconductor structure 110C can be 7A to 7C A similar process is shown stacked on the memory semiconductor structure 110D.

[0054] Furthermore, in some embodiments, the logic semiconductor structure 120 may be stacked on the memory stack pair 11 after the memory stack pair 11 is stacked on the memory stack pair 12. That is, the logic semiconductor structure 120 may be stacked at the back end of the manufacturing process of the semiconductor device 300.

[0055] 9A to 9C A cross-sectional view showing one or more stages of manufacturing a semiconductor device 300 according to an embodiment of the present disclosure. Fig.9A As shown, the memory stack pair 11 can be formed by stacking a memory semiconductor structure 110B on a memory semiconductor structure 110A. Fig.9AAs shown, the substrate 112B at the back side 110B2 of the memory semiconductor structure 110B may be thinned to form a through silicon via 115B in the substrate 112B and to form a redistribution layer 116B above the substrate 112B. The bonding layer 130B2 is formed on the redistribution layer 116B above the substrate 112B to facilitate the subsequent bonding process with the memory stack pair 12. In some embodiments, Fig.9A The memory stack pair 11 shown can be connected through a similar 7A to 7D The process shown is formed.

[0056] exist Fig. 9B In some embodiments, the memory stack pair 12 may be formed by stacking a memory semiconductor structure 110C on a memory semiconductor structure 110D. 7A to 7D The memory semiconductor structure 110C is formed by the process shown in the figure. For example, a memory semiconductor structure 110C including a substrate 112C and a dielectric 114C, and a memory semiconductor structure 110D including a substrate 112D and a dielectric 114D can be provided. A bonding layer 130C1 is formed on a front surface 110C1 of the memory semiconductor structure 110C (i.e., a side close to the dielectric 114C), and a bonding layer 130D1 is formed on a front surface 110D1 of the memory semiconductor structure 110D (i.e., a side close to the dielectric 114D). In this way, the memory semiconductor structure 110C can be bonded to the memory semiconductor structure 110D through the bonding layers 130C1 and 130D1, wherein the front surface 110C1 of the memory semiconductor structure 110C is adjacent to the front surface 110D1 of the memory semiconductor structure 110D.

[0057] In addition, if Fig. 9B As shown, the substrate 112C at the back side 110C2 of the memory semiconductor structure 110C is thinned to form a through silicon via 115C, and a redistribution layer 116C is formed over the substrate 112C. A bonding layer 130C2 is formed on the redistribution layer 116C over the substrate 112C.

[0058] exist Fig. 9C In the embodiment, the memory stack pair 11 is turned upside down so that the bonding layer 130B2 above the substrate 112B of the memory semiconductor structure 110B is hybrid-bonded to the bonding layer 130C2 above the substrate 112C of the memory semiconductor structure 110C, thereby bonding the memory stack pair 11 to the memory stack pair 12. In this way, the memory stack pair 11 can be stacked on the memory stack pair 12, wherein the back side 110B2 of the memory semiconductor structure 110B will be adjacent to the back side 110C2 of the memory semiconductor structure 110C. In subsequent steps, the logic semiconductor structure 120 can be connected to the memory stack pair 12 by mixing with the bonding layer 130B2 above the substrate 112B of the memory semiconductor structure 110C. FIG. 7D to FIG. 7FSimilar steps are used to bond to the memory stack pair 11. For the sake of brevity, the detailed steps are not repeated here.

[0059] like 9A to 9C As shown, the semiconductor device 300 can be manufactured by first forming and stacking the memory stack pairs 11 and 12, thereby allowing the logic semiconductor structure 120 to be subsequently stacked on the stacked memory stack pairs 11 and 12. In this way, the logic semiconductor structure 120 can be protected from physical stress caused during the bonding operation and / or thinning operation performed on the memory semiconductor structures 110A, 110B, 110C, and 110D, and thus the logic semiconductor structure 120 can be protected, thereby improving the yield.

[0060] exist Figure 5 and Figure 8 In the illustrated embodiment, the semiconductor devices 200 and 300 both include an even number of memory semiconductor structures (e.g., two memory semiconductor structures 110A and 110B in the semiconductor device 200, and four memory semiconductor structures 110A, 110B, 110C, and 110D in the semiconductor device 300), so any memory semiconductor structure can be stacked into a memory stacking pair first, and then the memory stacking pairs are stacked on each other, and the logic semiconductor structure 120 is stacked in a subsequent stage, so as to protect the logic semiconductor structure 120 from being damaged during the manufacturing process of the semiconductor devices 200 and 300 without using any carrier. The same principle can be applied to the manufacture of other semiconductor devices including an even number (e.g., 8, 10, or 12) of memory semiconductor structures, so as to stack the logic semiconductor structure in a subsequent stage. In other words, the semiconductor device includes N memory stacking pairs (N≥1), and each of the N memory stacking pairs includes two memory semiconductor structures stacked in a front-to-front (i.e., face-to-face) manner.

[0061] In some embodiments, when the semiconductor structure includes N memory stack pairs and N ≥ 3, the semiconductor structure can be formed by stacking the memory stack pairs in pairs and then stacking the stacked memory stack pairs. For example, if N = 5, the semiconductor structure can be formed by stacking two memory stack pairs, stacking another two memory stack pairs, stacking two stacked memory stack pairs, and then stacking the last memory stack pair on four stacked memory stack pairs. However, the present disclosure is not limited to this. In some other embodiments, two memory stack pairs can be stacked first, and then the remaining three memory stack pairs are stacked one by one on top of the stacked memory stack pairs to form a semiconductor structure including 5 memory stack pairs. Alternatively, the semiconductor structure can be formed by stacking two memory stack pairs, stacking another two memory stack pairs, stacking the remaining memory stack pair on one of the stacked memory stack pairs, and then stacking the two stacked memory stack pairs and the three stacked memory stack pairs. It should also be noted that in the above embodiments, each memory stack pair includes two memory semiconductor structures stacked face-to-face.

[0062] In some embodiments, a semiconductor device including an odd number of memory semiconductor structures may also allow logic semiconductor structures to be stacked in a back-end-of-line process without using any carrier. Fig.10 A semiconductor device 400 according to an embodiment of the present disclosure is shown. The semiconductor device 400 includes memory semiconductor structures 110A, 110B, 110E and a logic semiconductor structure 120 . FIG. 11A to FIG. 11C A cross-sectional view is shown illustrating one or more stages in fabricating a semiconductor device 400 according to an embodiment of the present disclosure.

[0063] exist Fig.11A In some embodiments, the memory semiconductor structure 110A is bonded to the memory semiconductor structure 110B, wherein the substrate 112A at the back side 110A2 of the memory semiconductor structure 110A is thinned, and a redistribution layer 116A and a bonding layer 130A2 are formed thereon. In some embodiments, the memory semiconductor structure 110A may be bonded to the memory semiconductor structure 110B according to 7A to 7D The process shown is stacked on the memory semiconductor structure 110B to form a memory stack pair 11 .

[0064] exist Fig. 11BIn the embodiment, the bonding layer 130A2 formed at the back surface 110A2 of the memory semiconductor structure 110A is bonded to the bonding layer 130E1 formed at the front surface 110E1 of the memory semiconductor structure 110E through hybrid bonding, thereby bonding the memory semiconductor structure 110E to the memory stack pair 11. That is, the front surface 110E1 of the memory semiconductor structure 110E is adjacent to the back surface 110A2 of the memory semiconductor structure 110A. In addition, as Fig. 11B As shown, the substrate 112E is thinned to form a through silicon via 115E therein, and a redistribution layer 116E and another bonding layer 130E2 may be sequentially formed over the substrate 112E. The redistribution layer 116E may be connected to the interconnect structure 113E formed in the dielectric 114E through the through silicon via 115E.

[0065] exist Fig. 11C , the logic semiconductor structure 120 is stacked on the memory semiconductor structure 110E that has been stacked on the memory stack pair 11. In the present embodiment, the bonding layer 130E2 formed on the back surface 110E2 of the memory semiconductor structure 110E and the bonding layer 140 formed on the front surface 1201 of the logic semiconductor structure 120 can be bonded to the memory semiconductor structure 110E through hybrid bonding, so that the front surface 1201 of the logic semiconductor structure 120 is adjacent to the back surface 110E2 of the memory semiconductor structure 110E.

[0066] As a result, the logic semiconductor structure 120 can be stacked on the memory semiconductor structures 110A, 110B, and 110E at a later stage of the manufacturing process, thereby protecting the logic semiconductor structure 120 from damage during the stacking and thinning processes of the memory semiconductors 110A, 110B, and 110E.

[0067] In some embodiments, a semiconductor device including an odd number of memory semiconductor structures, such as 5, 7, and 9, may also be implemented by a method similar to FIG. 11A to FIG. 11C For example, the memory semiconductor structures may be stacked in pairs to form a memory stack pair, and then the remaining single memory semiconductor structure may be stacked on the stacked memory stack pair, and finally the logic semiconductor structure may be stacked on the single memory semiconductor structure. Since the logic semiconductor structure may be stacked in a subsequent stage, the logic semiconductor structure 120 may be protected from damage during the stacking and thinning process of the memory semiconductor structure.

[0068] In some embodiments, a single memory semiconductor structure may be stacked anywhere between pairs of memory stacks. Fig.12A semiconductor device 500 according to another embodiment of the present disclosure is shown. The semiconductor device 500 includes five memory semiconductor structures 110A, 110B, 110C, 110D, and 110E, wherein the memory semiconductor structures 110A and 110B are stacked to form a memory stack pair 11, the memory semiconductor structures 110C and 110D are stacked to form a memory stack pair 12, and the memory semiconductor structure 110E is disposed between the memory stack pair 11 and the memory stack pair 12.

[0069] FIG. 13A to FIG. 13C A cross-sectional view is shown illustrating one or more stages in fabricating a semiconductor device 500 according to an embodiment of the present disclosure.

[0070] exist Fig.13A In some embodiments, the memory semiconductor structure 110A may be bonded to the memory semiconductor structure 110B to form the memory stack pair 11, and the memory semiconductor structure 110E may be bonded to the memory stack pair 11. In some embodiments, the memory semiconductor structures 110A, 110B, and 110E may be bonded to the memory stack pair 11. Fig.11A and Fig. 11B The memory semiconductor structure 110E is stacked according to the process shown, and the front side 110E1 of the memory semiconductor structure 110E will be adjacent to the back side 110A2 of the memory semiconductor structure 110A.

[0071] exist Fig. 13B In the embodiment, the memory semiconductor structure 110C is bonded to the memory semiconductor structure 110D to form a memory stack pair 12, wherein a front side 110C1 of the memory semiconductor structure 110C is adjacent to a front side 110D1 of the memory semiconductor structure 110D.

[0072] exist Fig. 13C In the embodiment, the memory stack pair 12 is turned upside down so that the bonding layer 130E2 is combined with the bonding layer 130C2 through hybrid bonding, thereby bonding the memory stack pair 12 to the memory semiconductor structure 110E. In this way, the back side 110E2 of the memory semiconductor structure 110E will be adjacent to the back side 110C2 of the memory semiconductor structure 110C. In subsequent steps, the logic semiconductor structure 120 can be bonded to the memory semiconductor structure 110E through hybrid bonding. FIG. 7D to FIG. 7F Similar steps are used to bond the memory stack pair 12 . For the sake of brevity, the detailed steps are not repeated here.

[0073] In this embodiment, the memory semiconductor structure 110E is stacked between the memory stack pair 11 and the memory stack pair 12, and the logic semiconductor structure 120 can be stacked on the memory stack pair 12 at a later stage, so that the logic semiconductor structure 120 can be protected from damage during the stacking and thinning process of the memory semiconductor structures 110A, 110B, 110C, 110D and 110E.

[0074] In some embodiments, the semiconductor device includes N memory stack pairs and M single memory semiconductor structures, where N≥1 and M≥1. The M single memory semiconductor structures may be stacked between two memory stack pairs (e.g., Fig.12 ), or between a memory stack pair and a logic semiconductor structure (e.g., Fig.10 ). In these embodiments, each memory stack pair includes two memory semiconductor devices stacked in a front-to-front manner. In addition, the front side of the single memory semiconductor structure is adjacent to the back side of one of the memory semiconductor structures in the memory stack pair. In some embodiments, the stacking method described in the aforementioned embodiments can be applied to form a semiconductor device comprising N memory stack pairs and M single memory semiconductor structures. That is, regardless of the number of memory stack pairs and the number of single memory semiconductor structures to be stacked in the semiconductor device, the method provided by the present invention enables the memory semiconductor structures to be properly stacked and allows the logic semiconductor structure to be stacked at a later or final stage, thereby protecting the logic semiconductor structure from damage and reducing the impact that the bonding process may have on the yield.

[0075] In summary, the semiconductor device and the method for forming the same provided by the embodiments of the present invention can enable every two memory semiconductor structures to be stacked in a front-to-front manner to form a memory stack pair, and enable the logic semiconductor structure to be stacked on the memory stack pair in a subsequent stage, thereby protecting the logic semiconductor structure from damage caused by the physical stress generated during the stacking and thinning process of the memory semiconductor structure. In this way, the yield of the semiconductor device can be significantly improved.

[0076] In addition, the scope of the present disclosure is not limited to the specific embodiments of the procedures, machines, manufactures, material compositions, components, methods, and steps described in the specification. From the disclosure of the present disclosure, it will be readily apparent to those skilled in the art that procedures, machines, manufactures, material compositions, components, methods, or steps that currently exist or will be developed in the future can be used according to the present disclosure to perform the same functions as the corresponding embodiments described herein or obtain substantially the same results. Therefore, it is intended that the scope of the attached claims include such procedures, machines, manufactures, material compositions, components, methods, and steps within their scope.

[0077] Explanation of symbols

[0078] 11, 12: Memory stacking pair

[0079] 100, 100', 200, 300, 400, 500: Semiconductor devices

[0080] 110A1, 110B1, 110C1, 110D1, 110E1, 1201: Front

[0081] 110A2, 110B2, 110C2, 110D2, 110E2, 1202: Back

[0082] 114A, 114B, 114C, 114D, 114E, 124: Dielectric

[0083] 130A1, 130B1, 130C1, 130D1, 130E1: Bonding layer

[0084] 130A2, 130B2, 130C2, 130E2, 140: Bonding layer

[0085] 132A1, 132B1, 142: Bonding dielectric

[0086] 134A1, 134B1, 144: Bonding pads

[0087] 900: Semiconductor structures

[0088] 910A, 910B, 910C, 910D: Memory semiconductor structure

[0089] 110A, 110B, 110C, 110D, 110E: Memory semiconductor structure

[0090] 912A, 912B, 112A, 112B, 112C, 112D, 112E, 122: Base plate

[0091] 913A, 913B, 113A, 113B, 113E, 123: Interconnection structure

[0092] 914A, 914B: Semiconductor Dielectrics

[0093] 915A, 915B, 115A, 115B, 115C, 115E: Through Silicon Via

[0094] 916A, 916B, 116A, 116B, 116C, 116E: Redistribution layer

[0095] 920, 120: Logic semiconductor structure

[0096] M1: Methods

[0097] S110, S120, S130, S140, S150, S160, S170, S180: Method

Claims

1. A semiconductor device comprising: A first memory stack pair comprising A first memory semiconductor structure having a first front side and a first back side opposite to the first front side; as well as a second memory semiconductor structure having a second front side and a second back side opposite to the second front side, The first memory semiconductor structure is bonded to the second memory semiconductor structure, the first front surface of the first memory semiconductor structure is adjacent to the second front surface of the second memory semiconductor structure, and the first back surface is far away from the second back surface.

2. The semiconductor device according to claim 1, further comprising: A logic semiconductor structure has a front side and a back side, wherein the logic semiconductor structure is bonded to the first memory stack pair, and the front side of the logic semiconductor structure is adjacent to the first back side of the first memory semiconductor structure.

3. The semiconductor device according to claim 1, further comprising: a second memory stack pair, comprising a third memory semiconductor structure having a third front side and a third back side; as well as a fourth memory semiconductor structure having a fourth front side and a fourth back side; The third memory semiconductor structure is bonded to the fourth memory semiconductor structure, and the third front surface of the third memory semiconductor structure is adjacent to the fourth front surface of the fourth memory semiconductor structure. 4 . The semiconductor device of claim 3 , wherein the first memory stack pair is bonded to the second memory stack pair, and the second backside of the second memory semiconductor structure is adjacent to the third backside of the third memory semiconductor structure.

5. The semiconductor device according to claim 4, further comprising: A logic semiconductor structure has a front side and a back side, wherein the logic semiconductor structure is bonded to the first memory stack pair, and the front side of the logic semiconductor structure is adjacent to the first back side of the first memory semiconductor structure.

6. The semiconductor device according to claim 1, further comprising: a fifth memory semiconductor structure having a fifth front side and a fifth back side; The fifth memory semiconductor structure is bonded to the first memory stack pair, and the fifth front surface of the fifth memory semiconductor structure is adjacent to the first back surface of the first memory semiconductor structure.

7. The semiconductor device of claim 6, further comprising a logic semiconductor structure having a front side and a back side, wherein the logic semiconductor structure is bonded to the fifth memory semiconductor structure, and the front side of the logic semiconductor structure is adjacent to the fifth back side of the fifth memory semiconductor structure. 8 . The semiconductor device of claim 6 , further comprising a second memory stack pair bonded to the fifth back side of the fifth memory semiconductor structure.

9. The semiconductor device of claim 1, wherein: The circuit layout of the first memory semiconductor structure is the same as the circuit layout of the second memory semiconductor structure, and the layout of the first memory semiconductor structure is mirror-symmetrical.

10. The semiconductor device of claim 1, wherein: The circuit layout of the first memory semiconductor structure is a mirror image of the circuit layout of the second memory semiconductor structure.

11. The semiconductor device of claim 1, wherein: The first memory stack pair includes a redistribution layer formed on the first backside of the first memory semiconductor structure.

12. The semiconductor device of claim 1, wherein: The first memory semiconductor structure and the second memory semiconductor structure are dynamic random access memories.

13. A semiconductor device comprising: N memory stack pairs, each of the N memory stack pairs includes A first memory semiconductor structure having a first front side and a first back side opposite to the first front side; as well as a second memory semiconductor structure having a second front side and a second back side opposite to the second front side, Wherein N≥1, the first memory semiconductor structure is bonded to the second memory semiconductor structure, the first front surface of the first memory semiconductor structure is adjacent to the second front surface of the second memory semiconductor structure, and the first back surface is far away from the second back surface.

14. The semiconductor device of claim 13, wherein: A first memory stack pair among the N memory stack pairs is bonded to a second memory stack pair among the N memory stack pairs, and a back surface of a memory semiconductor structure in the first memory stack pair is adjacent to a back surface of a memory semiconductor structure in the second memory stack pair.

15. The semiconductor device according to claim 13, further comprising: M single memory semiconductor structures are stacked with the N memory stack pairs, and M≥1, wherein a single memory semiconductor structure of the M single memory semiconductor structures is joined to a memory stack pair of the N memory stack pairs, and the single memory semiconductor structure includes a substrate and a front side away from the substrate, wherein the front side of the single memory semiconductor structure is adjacent to a back side of a memory semiconductor structure of the memory stack pair.

16. A method for manufacturing a semiconductor device, comprising: Providing a first memory semiconductor structure having a first front side and a first back side; Providing a second memory semiconductor structure having a second front side and a second back side; as well as The first memory semiconductor structure is bonded to the second memory semiconductor structure to form a first memory stack pair, wherein the first front side of the first memory semiconductor structure is adjacent to the second front side of the second memory semiconductor structure.

17. The method of claim 16, further comprising: A logic semiconductor structure is provided, wherein the logic semiconductor structure has a front side and a back side; as well as The logic semiconductor structure is bonded to the first memory stack pair, wherein the front side of the logic semiconductor structure is adjacent to the first back side of the first memory semiconductor structure.

18. The method of claim 16, further comprising: Providing a third memory semiconductor structure having a third front side and a third back side; Providing a fourth memory semiconductor structure having a fourth front side and a fourth back side; as well as bonding the third memory semiconductor structure to the fourth memory semiconductor structure to form a second memory stack pair, wherein the third front side of the third memory semiconductor structure is adjacent to the fourth front side of the fourth memory semiconductor structure; as well as The first memory stack pair is bonded to the second memory stack pair, wherein the second backside of the second memory semiconductor structure is adjacent to the third backside of the third memory semiconductor structure.

19. The method of claim 18, wherein the step of bonding the first memory stack pair to the second memory stack pair comprises: thinning the substrate at the second back side of the second memory semiconductor structure; thinning the substrate at the third back side of the third memory semiconductor structure; forming a bonding layer over the substrate of the second memory semiconductor structure; forming a bonding layer over the substrate of the third memory semiconductor structure; as well as The bonding layer above the substrate of the second memory semiconductor structure is bonded to the bonding layer above the substrate of the third memory semiconductor structure.

20. The method of claim 18, further comprising: Providing a logic semiconductor structure having a front side and a back side; as well as After bonding the first memory stack pair to the second memory stack pair, bonding the logic semiconductor structure to the first memory stack pair.

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