Capacitor, manufacturing method thereof, and semiconductor device including interconnection structure thereof

Abstract

The invention provides a capacitor, a manufacturing method thereof and a semiconductor device having an interconnection structure including the capacitor. The interconnection structure may include a capacitor of a specified structure and / or a guard ring surrounding the capacitor. The capacitor may include an arcuate region having an extended width, the arcuate region permitting the inclusion of an aperture containing air or another gas. Alternatively, the capacitor may be a metal-insulator-metal capacitor or a metal-insulator-metal-insulator-metal capacitor having a vertical trench and a horizontal plate and formed of a conformal layer. The guard ring reduces noise that may damage the capacitor. Any combination of these three features can be used to improve capacitance and reliability.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a method of manufacturing a capacitor, a capacitor, and a semiconductor device including an interconnect structure of the capacitor. Background Art

[0002] Semiconductor packages containing integrated circuits are becoming increasingly complex. For example, a System on Integrated Chip (SoIC) has been developed that includes multiple device dies, such as processors and memory cubes that are vertically stacked and interconnected. The device dies can be formed using different technologies and have different functions, and can be combined unevenly to obtain the desired functionality, thereby forming a system combined in one chip carrier package. This reduces manufacturing costs and optimizes device performance. Similar three-dimensional packages include System in Package (SiP), Wafer Level Package (WLP), and Package on Package (PoP).

[0003] Integrated circuits are formed on semiconductor wafers. The photolithography patterning process uses ultraviolet light to transfer the desired mask pattern to the photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to the layers below the photoresist. The process is repeated many times with different patterns to build up different layers on the wafer substrate and make useful devices. Summary of the invention

[0004] According to some embodiments, a method of manufacturing a capacitor includes forming a trench in a dielectric material. Depositing a first metal on multiple sidewalls and bottom surfaces of the trench and on the surface of the dielectric material to form a first metal layer. Depositing a first insulator on the first metal layer on the sidewalls and bottom surfaces of the trench and on the surface of the dielectric material to form a first insulator layer. Depositing a second metal on the first insulator layer on the sidewalls and bottom surfaces of the trench, above the second insulator in the trench, and on the surface of the dielectric material to form a second metal layer. Planarizing to remove multiple portions of the second metal layer and the first insulator layer on the surface of the dielectric material. Applying a main insulator on the surface of the dielectric material to isolate the second metal in the trench. Forming a third metal layer on the first insulator layer on the surface of the dielectric material. Patterning to form a first horizontal plate with the first metal layer, a second horizontal plate with the first insulator layer, and a third horizontal plate with the third metal layer to obtain a capacitor.

[0005] According to some embodiments, a capacitor includes a vertical groove, a first horizontal plate, a second horizontal plate, and a third horizontal plate. A first metal, a first insulator, and a second metal are arranged in the vertical groove. The first horizontal plate is located above the vertical groove, and the first horizontal plate is connected to the first metal in the vertical groove. The second horizontal plate is located above the first horizontal plate, and the second horizontal plate is connected to the first insulator in the vertical groove. The third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal.

[0006] According to some embodiments, a semiconductor device having an interconnect structure including a capacitor, wherein the capacitor includes a vertical trench, a first horizontal plate, a second horizontal plate, and a third horizontal plate. A first metal, a first insulator, a second metal, and a second insulator are disposed in the vertical trench. The first horizontal plate is located above the vertical trench, and the first horizontal plate is connected to the first metal in the vertical trench. The second horizontal plate is located above the first horizontal plate, and the second horizontal plate is connected to the first insulator in the vertical trench. The third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of some embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A is a Y-axis cross-sectional view of a semiconductor package having an interconnect structure according to some embodiments; the interconnect structure includes a capacitor having a bow region and also includes a guard ring surrounding the capacitor;

[0009] Figure 1B is a plan view of the capacitor and guard ring;

[0010] Figure 1C is an enlarged Y-axis cross-sectional view of the capacitor;

[0011] Figure 2 is a first method for manufacturing an interconnect structure together with a capacitor and a guard ring according to some embodiments;

[0012] Figure 3A It's at the beginning Figure 2 A Y-axis cross-sectional view of the interconnect structure before the method;

[0013] Figure 3B is a Y-axis cross-sectional view of the interconnect structure after applying an etch stop layer;

[0014] Figure 3C is a Y-axis cross-sectional view of the interconnect structure after a dielectric layer is applied over the etch stop layer;

[0015] Figure 3D is a Y-axis cross-sectional view of the interconnect structure after doping the dielectric material to form a doped dielectric region;

[0016] Figure 3E is a Y-axis cross-sectional view of the interconnect structure after a photoresist layer has been applied;

[0017] Figure 3F is a Y-axis cross-sectional view of the interconnect structure after a trench for a capacitor has been etched into the dielectric material and through the doped dielectric region; the resulting trench has a bowed region;

[0018] Figure 3G is a Y-axis cross-sectional view of the interconnect structure after a first metal has been deposited;

[0019] Figure 3H is a Y-axis cross-sectional view of the interconnect structure after a first insulator has been deposited;

[0020] Fig. 3I is a Y-axis cross-sectional view of the interconnect structure after a second metal has been deposited; as illustrated here, the second metal fills the gap at the top of the trench, thereby creating a void within the trench; the void can be considered a second insulator;

[0021] Figure 3J is a Y-axis cross-sectional view of the interconnect structure after planarizing the surface of the dielectric material;

[0022] Figure 3K is a Y-axis cross-sectional view of the interconnect structure after the first insulator has been reapplied; this isolates the second metal in the trench;

[0023] Figure 3L is a Y-axis cross-sectional view of the interconnect structure after a third metal layer has been deposited;

[0024] Figure 3M is a Y-axis cross-sectional view of the interconnect structure after patterning to form horizontal plates of a capacitor and after application of a capping layer;

[0025] Figure 3N is a Y-axis cross-sectional view of the interconnect structure after depositing additional material to cover the capacitor;

[0026] Fig.3O is a Y-axis cross-sectional view of the interconnect structure after adding other etch stop layers and interconnect layers;

[0027] Figure 3P is a Y-axis cross-sectional view of the interconnect structure after etching to form a top via opening;

[0028] Figure 4A It is a plan view of one configuration of the grooves and horizontal plates of the capacitor; Figure 4B yes Figure 4A A perspective view of a capacitor;

[0029] FIG. 4C to FIG. 4J are various plan views of capacitors according to some embodiments, showing different shapes and configurations of grooves and horizontal plates of the capacitors;

[0030] Figure 5 is a Y-axis cross-sectional view illustrating a variation of a capacitor in which the aspect ratio (ratio of trench depth to plate width) of the capacitor is higher than Figure 1A capacitors;

[0031] Fig. 6A and Figure 6B is a cross-sectional view illustrating additional variations of capacitors in which arcuate regions of the capacitor are located at different depths in a trench of the capacitor;

[0032] Fig. 7A and Figure 7B A second method for manufacturing an interconnect structure according to some embodiments is collectively described; here, a second insulator is included in the trench;

[0033] Fig. 8A is a Y-axis cross-sectional view of the interconnect structure after a second metal has been deposited; as illustrated here, the second metal does not fill the gap at the top of the trench;

[0034] Figure 8B is a Y-axis cross-sectional view of the interconnect structure after a second insulator has been deposited in the trench;

[0035] Figure 8C is a Y-axis cross-sectional view of the interconnect structure after planarization;

[0036] Fig.8D is a Y-axis cross-sectional view of the interconnect structure after etching the second insulator to form a recess;

[0037] Fig. 8E is a Y-axis cross-sectional view of the interconnect structure after the recess has been filled with a second metal;

[0038] Fig. 9 is a third method for manufacturing an interconnect structure according to some embodiments; the capacitor has a different structure;

[0039] Fig. 10A is a Y-axis cross-sectional view of the interconnect structure after a second metal has been deposited and patterned to form a horizontal plate of a capacitor;

[0040] Fig. 10B is a Y-axis cross-sectional view of the interconnect structure after a capping layer is applied to the capacitor;

[0041] Fig. 10Cis a Y-axis cross-sectional view of the final interconnect structure after other interconnect layers are added and top vias are formed;

[0042] Fig. 10D is a Y-axis cross-sectional view of a variation of a capacitor in which a bow region is not present in the capacitor;

[0043] Fig.11 is a fourth method for manufacturing an interconnect structure according to some embodiments; the capacitor has a MIMIM structure formed of five conformal layers;

[0044] Fig. 12A is a Y-axis cross-sectional view of the interconnect structure after a trench for a capacitor has been formed in the dielectric material;

[0045] Fig. 12B is a Y-axis cross-sectional view of the interconnect structure after five conformal layers (MIMIM) have been deposited in the trenches and over the dielectric material;

[0046] Fig. 12C is a Y-axis cross-sectional view of the interconnect structure after patterning to obtain a stepped profile exposing all three metal layers of the capacitor;

[0047] Fig.12D is a Y-axis cross-sectional view of the interconnect structure after a capping layer is applied to the capacitor;

[0048] Fig.12E is a Y-axis cross-sectional view of the final interconnect structure after other interconnect layers are added and top vias are formed;

[0049] Fig.12F is a Y-axis cross-sectional view of a variation of a MIMIM capacitor, wherein a bow region is present in the capacitor;

[0050] Fig.13A It is a plan view of one configuration of the grooves and horizontal plates of the capacitor; Fig. 13B yes Fig.13A A perspective view of a capacitor;

[0051] FIG. 13C to FIG. 13J are various plan views of capacitors according to some embodiments, showing different shapes and configurations of grooves and horizontal plates of the capacitors;

[0052] Fig.14 is a fifth method for manufacturing an interconnect structure according to some embodiments; the capacitor has a MIMIM structure with five horizontal plates;

[0053] Fig.15A is a Y-axis cross-sectional view of the interconnect structure after a second metal has been applied and patterned to obtain three horizontal sheets;

[0054] Fig. 15Bis a Y-axis cross-sectional view of the interconnect structure after a fourth horizontal plate (insulator) and a fifth horizontal plate (metal) are applied and patterned to obtain a stepped profile exposing all three metal layers of the capacitor;

[0055] Fig. 15C is a Y-axis cross-sectional view of the interconnect structure after a capping layer is applied to the capacitor;

[0056] Fig.15D is a Y-axis cross-sectional view of the final interconnect structure after other interconnect layers are added and top vias are formed;

[0057] Fig.15E is a Y-axis cross-sectional view of a variation of a capacitor in which a bow region is not present in the capacitor;

[0058] Fig.16 is an alternative method for fabricating an interconnect structure in which a guard ring is formed around a capacitor according to some embodiments;

[0059] Fig.17A It's at the beginning Fig.16 A Y-axis cross-sectional view of the interconnect structure before the method;

[0060] Fig. 17B is a Y-axis cross-sectional view of the interconnect structure after forming a through hole opening and a guard ring opening;

[0061] Fig. 17C is a Y-axis cross-sectional view of the interconnect structure after filling the via opening and the guard ring opening to form a top via and a guard ring around the capacitor;

[0062] FIG. 17D to FIG. 17F are various plan views of interconnect structures showing different shapes and configurations of capacitors and guard rings;

[0063] Fig.18A is a schematic plan view of a capacitor array having a CMOS image sensor according to some embodiments;

[0064] Fig.18B The Y-axis cross-sectional view of an image signal processor (ISP) semiconductor package connected to a CMOS image sensor (CIS) package.

[0065]

Explanation of symbols

[0066] 100:Semiconductor packaging

[0067] 102: Semiconductor grains

[0068] 104:Substrate

[0069] 106: Layer

[0070] 108, 374, 384: Interconnection structure

[0071] 109:Logical area

[0072] 110: first dielectric layer

[0073] 111, 113, 115, 117, 119, 121, 123, 125, 127, 155, 175, 185, 195, 225, 265, 267: thickness

[0074] 112: Second dielectric layer

[0075] 114: third dielectric layer

[0076] 116: fourth dielectric layer

[0077] 118: fifth dielectric layer

[0078] 120, 122, 124, 126: Etching stop layer

[0079] 128: Contact

[0080] 130: Perforation

[0081] 132: Perforated opening

[0082] 140: Protection ring

[0083] 142: Protection ring opening

[0084] 145, 167, 177, 187, 197, 255: Width

[0085] 150:Capacitor

[0086] 151: Top level

[0087] 153: Bottom level

[0088] 160: Groove

[0089] 162: Side wall

[0090] 164: Bottom surface

[0091] 165, 257: Depth

[0092] 169: Length

[0093] 170: First level plate

[0094] 171: First metal layer

[0095] 180: Second level plate

[0096] 181: first insulator layer

[0097] 190: Third level plate

[0098] 191: Second metal layer

[0099] 200: Insulator horizontal plate

[0100] 201: second insulator layer

[0101] 203: Groove

[0102] 210: Fifth level plate

[0103] 211: The third metal layer

[0104] 220: Covering layer

[0105] 230: Top through hole

[0106] 232: Top through hole opening

[0107] 240:Arch area

[0108] 242: doped dielectric region

[0109] 244: Photoresist layer

[0110] 250: Porosity

[0111] 260, 290: dielectric layer

[0112] 270: Dielectric Materials

[0113] 272: Top surface

[0114] 282:Capacitor bottom metal

[0115] 284:Capacitor top metal

[0116] 300: First Method

[0117] 302: Second Method

[0118] 304: The Third Method

[0119] 306: The Fourth Method

[0120] 308: Fifth Method

[0121] 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, 332, 334, 336, 338, 340, 342, 344, 346, 348, 350, 352, 354, 356, 358, 362, 364, 366, 368: Step 360: Method

[0122] 370:CIS semiconductor packaging

[0123] 372, 382: Transistor

[0124] 376: Photoelectric sensor

[0125] 378, 388: Metal bonding pad

[0126] 380:ISP semiconductor packaging

[0127] 390: Mixed joint

[0128] AA:Line DETAILED DESCRIPTION

[0129] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of the components and configurations described below are to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, some embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0130] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used in some embodiments of the present disclosure to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure may likewise be interpreted accordingly.

[0131] The terms "horizontal" and "vertical" as used in some embodiments of the present disclosure are also spatially relative terms. The term "horizontal" refers to a plane parallel to the plane of the wafer substrate, while the term "vertical" refers to a plane that intersects the wafer substrate and forms a substantially perpendicular angle with the wafer substrate. "Length" and "width" are measured in the horizontal direction, while "height" or "thickness" or "depth" is measured in the vertical direction.

[0132] The numerical values ​​in the description and claim range of some embodiments of the present disclosure should be understood to include the same numerical values ​​when reduced to the same number of significant figures and the numerical values ​​that differ from the specified values ​​by less than the experimental error of the conventional measurement technology for determining the value of the type described in some embodiments of the present disclosure. All ranges disclosed in some embodiments of the present disclosure include the listed endpoints.

[0133] The term "about" can be used to include any numerical value, and the numerical value can be varied without changing the basic function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0134] Some embodiments of the present disclosure are about systems and devices composed of multiple components and / or different layers. When the terms "on" or "above" are used with reference to two different components or layers, these terms only indicate that one component / layer is on or above another component layer. These terms do not require that the two components / layers are in direct contact with each other, and allow other components / layers to be between them. The term "directly" can be used to indicate that two components / layers are in direct contact with each other without any other components / layers being between them. In addition, depending on the context, when it is mentioned that a process step is performed on a component / substrate, this should be interpreted as also performing such steps on any layer that may be present on the component / substrate.

[0135] The term "semiconductor package" as used in some embodiments of the present disclosure refers to a combination of one or more integrated circuits (also referred to as dies, chips, or microchips) and an interconnect structure that allows the integrated circuits to communicate with one or more other packages. The interconnect structure may be made of one or more interconnect layers. Examples of interconnect layers may include a redistribution layer (RDL) or an interposer with bonding pads or C4 bumps or pillars. A semiconductor package may have an interconnect structure on only one side or both sides, as will be further seen in some embodiments of the present disclosure. It should be noted that in the art, the term "package" is used to refer to many different structures and does not have a single fixed definition.

[0136] Some embodiments of the present disclosure are directed to various capacitors that may be present in an interconnect structure and methods for making such capacitors. An interconnect structure is constructed on a substrate and is formed by a combination of dielectric layers. The dielectric layers include conductive features for communication between various components on the substrate. The interconnect structure may have several dielectric layers, where the conductive features are vertically interconnected by vias.

[0137] The capacitors of some embodiments of the present disclosure include several features. In some embodiments, the capacitor may include an arcuate region that can be used for stress relief. In other embodiments, the capacitor may be a metal-insulator-metal (MIM) capacitor or a metal-insulator-metal-insulator-metal (MIMIM) capacitor formed by a combination of vertical grooves and horizontal plates. In still other embodiments, the capacitor may be surrounded by a guard ring that reduces noise and improves the reliability of the capacitor.

[0138] Figure 1A FIG. 4 is a cross-sectional view of an example of a semiconductor package having an interconnect structure according to some embodiments of the present disclosure. The interconnect structure includes a capacitor having a bow region and also includes a guard ring surrounding the capacitor. Figure 1B is a plan view, where Figure 1A It is taken through line AA. Figure 1C is an enlarged cross-sectional view of a capacitor.

[0139] Initially, semiconductor package 100 includes a semiconductor die 102 on which a resistor structure will be built. The die includes a substrate 104 and a plurality of layers, here shown as one layer 106, on substrate 104 on which integrated circuits are formed.

[0140] In certain embodiments, the substrate is a wafer made of a semiconductor material. Such semiconductor material may include silicon, for example in the form of crystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In a specific embodiment, the wafer substrate is silicon.

[0141] Integrated circuits are constructed from different patterns of conductive and electrically insulating materials to fabricate useful components. Suitable examples of integrated circuit components can include, for example but not limited to, active components (such as transistors), passive components (such as capacitors, inductors, resistors, and the like), or combinations thereof. These components can be made of conductive materials such as metals (such as copper, aluminum, gold, tungsten, iron, ruthenium, iridium, and their alloys). Suitable examples of electrically insulating materials (i.e., dielectric materials) can include oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), or hafnium dioxide (HfO2); nitrides such as silicon carbonitride (SiCN), silicon nitride (SiN), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), or silicon oxynitride (SiO x N y ), where 0 < x, y ≤ 1; silicates such as hafnium silicate (HfSi x O y ), or zirconium silicate (ZrSi x O y ), where 0 < x, y ≤ 1; polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), borosilicate glass (BSG), high-k dielectric materials, or low-k dielectric materials.

[0142] Next, the interconnect structure 108 includes a plurality of interconnect or dielectric layers and etch stop layers. The interconnect layers can be independently considered intermetal dielectric (IMD) layers or interlayer dielectric (ILD) layers. These dielectric layers can be at any level within the interconnect structure on the semiconductor die 102. Five interconnect or dielectric layers 110, 112, 114, 116, 118 are illustrated here, which are separated by four etch stop layers 120, 122, 124, 126. However, any number of interconnect layers and etch stop layers can be present in the interconnect structure. Metal contacts 128 are illustrated as being present within the first dielectric layer 110, which is adjacent to the semiconductor die.

[0143] The dielectric layer(s) may have the same or different compositions and may be made of the dielectric materials listed previously above. In certain embodiments, the dielectric layer is formed of silicon oxide (SiO x ). Adjacent etch stop layers are typically made of different materials, which may also be dielectric materials. In certain embodiments, the etch stop layer is made of SiN, SiC, TiN, and AlO x (0 < x ≤ 1).

[0144] Refer to Figure 1A , in some embodiments, the thickness 111 of the first dielectric layer 110 is from about 700 angstroms to about 1000 angstroms (or from about 70 nanometers to about 100 nm). In some embodiments, the thickness 121 of the first etch stop layer 120 is from about 150 angstroms to about 300 angstroms. In some embodiments, the thickness 113 of the second dielectric layer 112 is from about 500 angstroms to about 7500 angstroms. In some embodiments, the thickness 123 of the second etch stop layer 120 is from about 400 angstroms to about 600 angstroms. In some embodiments, the thickness 115 of the third dielectric layer 114 is from about 1500 angstroms to about 20,000 angstroms. In some embodiments, the thickness 125 of the third etch stop layer 124 is from about 150 angstroms to about 350 angstroms. In some embodiments, the thickness 117 of the fourth dielectric layer 116 is from about 5500 angstroms to about 7500 angstroms. In some embodiments, the thickness 127 of the fourth etch stop layer 126 is from about 400 angstroms to about 600 angstroms. In some embodiments, the thickness 119 of the fifth dielectric layer 118 is from about 1500 angstroms to about 20,000 angstroms. However, other values and ranges for each of these layers are also within the scope of some embodiments of the present disclosure.

[0145] Next, the vias 130 are illustrated on the right hand side of Figure 1A . The guard ring 140 surrounding the capacitor 150 is also illustrated. The top of the capacitor defines a top level 151, and the bottom of the capacitor defines a bottom level 153. The guard ring 140 forms a solid wall around the capacitor between the top level 151 and the bottom level 153.

[0146] Figure 1B is a slice through the fourth dielectric layer 116. As can be seen more clearly here, the guard ring 140 surrounds the capacitor 150. The capacitor bottom metal (or CBM) 282 and the capacitor top metal (or CTM) 284 are shown along with two top vias 230. Two vias 130 are also illustrated.

[0147] The trench 160 is represented by the dashed box. In some embodiments, the trench 160 has a length 169 of about 5000 angstroms to about 10,000 angstroms. In some embodiments, the trench 160 has a width 167 of about 1000 angstroms to about 3000 angstroms. However, other values ​​and ranges for each of these measurements are also within the scope of some embodiments of the present disclosure.

[0148] Reference Figure 1C As described herein, capacitor 150 is formed from a conductive metal and an electrically insulating dielectric material (ie, an insulator) disposed within a vertical trench 160 and as a set of horizontal plates 170 , 180 , 190 .

[0149] The first metal layer 171 conforms to the sidewalls 162 and bottom surface 164 of the trench. The first metal layer also forms a first horizontal plate 170. In certain embodiments, both the first metal layer and the first horizontal plate are formed of a first metal.

[0150] There is a first insulator layer 181 on the first metal layer 171. The first insulator layer also conforms to the sidewalls and bottom surface of the trench. The first insulator layer also forms a second horizontal plate 180 on the first horizontal plate. In a specific embodiment, the first insulator layer and the second horizontal plate are both formed of the first insulator.

[0151] A second metal layer 191 is present on the first insulator layer 181. The second metal also conforms to the sidewalls and bottom surface of the trench. The second metal also surrounds the second insulator. A second metal layer is also deposited over the second insulator, and the second metal layer can also be described as encapsulating the second insulator. As described here, the second insulator can also be viewed as a pore 250 filled with air or another gas. Also as described here, a second horizontal plate 180 covers the second metal layer 191 and isolates the second metal layer. The second metal layer is formed of the second metal.

[0152] There is a third horizontal plate 190 on the second horizontal plate 180. The third horizontal plate is formed of a third metal. It should be noted that the horizontal plates have a stepped profile in cross section, where the width 177 of the first horizontal plate 170 is greater than the width 187 of the second horizontal plate. The width 177 of the first horizontal plate is also greater than the width 197 of the third horizontal plate. The width 187 of the second horizontal plate is greater than or equal to the width 197 of the third horizontal plate, thereby electrically isolating the first horizontal plate 170 from the third horizontal plate 190. This permits the formation of a top through hole for each of the metal horizontal plates. However, this relationship is not necessarily required, for example, when the first horizontal plate can be accessed by the metal contact 128.

[0153] In a particular embodiment, the first metal, the second metal, and the third metal may be elemental metals or metal alloys. Examples of suitable materials may include, for example, TiN, TaN, Ti, or Ta. In a particular embodiment, the first insulator is a high-k dielectric material such as HfO x 、AlO x or ZrO x (0 <x≤1)。

[0154] Finally, there is a capping layer 220 over the first horizontal plate 170, the second horizontal plate 180, and the third horizontal plate 190. The capping layer conforms to the shape of the horizontal plates and acts as an etch stop layer. The capping layer can be made of any suitable dielectric material. In a specific embodiment, the capping layer is formed of SiN or SiC.

[0155] refer to Figure 1C In some embodiments, the thickness 175 of the first horizontal sheet 170 is about 1000 angstroms to about 3000 angstroms. In some embodiments, the thickness 185 of the second horizontal sheet 180 is about 20 angstroms to about 100 angstroms. In some embodiments, the thickness 195 of the third horizontal sheet 190 is about 1000 angstroms to about 3000 angstroms. In some embodiments, the thickness 225 of the capping layer 220 is about 700 angstroms to about 1200 angstroms. In some embodiments, the trench 160 has a depth 165 of about 200 angstroms to about 30,000 angstroms. The trench depth is measured from the bottom surface of the first horizontal sheet to the bottom surface 164 of the trench. However, other values ​​and ranges for each of these measurements are also within the scope of some embodiments of the present disclosure.

[0156] exist Figure 1A and Figure 1C In FIG. 1 , the top via 230 extends through the interconnect structure and contacts the third horizontal plate 190 (CTM) of the capacitor. Figure 1B As seen in the plan view of FIG. 1 , another top via 230 also extends through the interconnect structure to contact the first horizontal plate 170 (CBM) of the capacitor.

[0157] Reference Figure 1C , the trench 160 of the capacitor 150 includes an arcuate region 240 (indicated by the dashed box). Typically, the length and width of the trench decreases in a relatively linear manner from the top of the trench to the bottom surface of the trench due to the etching process. However, in the arcuate region, the length and / or width of the trench increases in a non-linear manner and then decreases. In a specific embodiment, the arcuate region is located between 2% and 98% of the depth of the trench (with 0% at the top of the trench and 100% at the bottom of the trench). As illustrated here, the arcuate region is near the top of the trench.

[0158] Figure 1CAlso illustrated is a pore 250, which contains air or another gas and thus acts as a second insulator. The top of the trench has a width 167, and the pore has a width 255. In a particular embodiment, the width 255 of the pore (measured at its widest point) is about 1% to about 20% of the width 167 of the top of the trench. The pore also has a depth 257. In a particular embodiment, the depth 257 of the pore is about 10% to about 50% of the depth 165 of the trench.

[0159] The aspect ratio of the trench can be measured as the ratio of the trench depth 165 to the trench width 167. In a particular embodiment, the aspect ratio of the trench is from about 3 to about 15, and in a more specific embodiment, from about 11 to about 15. Other values ​​and ranges for each of these measurements are also within the scope of some embodiments of the present disclosure.

[0160] Still refer to Figure 1C , the three horizontal plates 170, 180, 190 of the capacitor are generally located in the dielectric layer 260 between the two etch stop layers 124, 126. The three horizontal plates collectively have a thickness 155. In a particular embodiment, the combined thickness 155 of the three horizontal plates is at most about 50% of the thickness 265 of the dielectric layer. Other values ​​and ranges are also within the scope of some embodiments of the present disclosure.

[0161] It should be noted that Figure 1C 1, the first horizontal plate 170 is embedded within the dielectric layer 260, rather than being embedded on the etch stop layer 124. The thickness of the dielectric layer between the etch stop layer 124 and the first horizontal plate 170 is indicated by the reference numeral thickness 267. In a specific embodiment, the thickness 267 is about 500 angstroms to about 3000 angstroms. Other values ​​and ranges are also within the scope of some embodiments of the present disclosure. It should also be noted that the trench 160 is illustrated as extending through the first etch stop layer 120. Therefore, if desired, the capacitor 150 can contact the metal contact 128 in the first dielectric layer 110. However, this is not required.

[0162] Figure 2 is a flow chart illustrating a first method 300 for fabricating an interconnect structure according to some embodiments. Some steps of the method are also described in Figures 3A to 3P , which are Y-axis cross-sectional views. These figures provide different views for better understanding. Although the method steps are discussed below in terms of forming a single capacitor, guard ring, and through-hole, this discussion should also be broadly interpreted as being applicable to forming multiple structures simultaneously.

[0163] It should be noted that certain conventional steps are not explicitly described in the following discussion.For example, a pattern / structure may be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching.

[0164] In general, the photoresist layer can be applied, for example, by spin coating or by spraying, roller coating, dip coating or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include a vacuum chuck that holds the substrate in a plate. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to evenly spread the photoresist from the center of the substrate to the periphery of the substrate. The rotation speed of the platform is then fixed, which controls the thickness of the final photoresist layer.

[0165] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking occurs at a temperature of about 90° C. to about 110° C. A hot plate or oven or similar equipment may be used for baking. Thus, a photoresist layer is formed on the substrate.

[0166] The photoresist layer is then patterned via exposure to radiation. The radiation can be any wavelength of light that carries the desired mask pattern. In a particular embodiment, EUV light with a wavelength of about 13.5 nm is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation while some portions of the photoresist are not exposed to radiation. This exposure results in some portions of the photoresist becoming soluble in a developer while other portions of the photoresist remain insoluble in the developer.

[0167] An additional resist bake step (post-exposure bake or PEB) may occur after exposure to radiation. This may, for example, help release acid leaving groups (ALGs) or other molecules that are important in chemically amplified resists.

[0168] The photoresist layer is then developed using a developer. The developer can be an aqueous or organic solution. During the development step, the soluble portion of the photoresist layer is dissolved and washed away, leaving behind the photoresist pattern. An example of a common developer is aqueous tetramethylammonium hydroxide (TMAH). In general, any suitable developer may be used. Sometimes, a post-development bake or "hard bake" may be performed to stabilize the photoresist pattern after development for optimal performance in subsequent steps.

[0169] Continuing, portions of the layers below the patterned photoresist layer are now exposed. Etching transfers the photoresist pattern to the layers below the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, at high temperature using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other strippers or by dry etching using oxygen plasma.

[0170] Generally speaking, any etching step used in some embodiments of the present disclosure may be performed using wet etching, dry etching, or plasma etching processes (such as reactive ion etching (RIE) or inductively coupled plasma (ICP) or a combination thereof) as appropriate. The etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), carbon fluoride, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), or the like, or combinations thereof in different ratios. For example, hydrofluoric acid and ammonium fluoride may be used to wet etch silicon dioxide. Alternatively, various mixtures of CHF3, O2, CF4, and / or H2 may be used to dry etch silicon dioxide.

[0171] For example, a chemical mechanical polishing (CMP) process can be used to planarize the surface. Generally speaking, CMP is performed using a rotating platform with a polishing pad attached. The substrate is attached to a rotating carrier. A slurry or solution containing various chemicals and abrasives is distributed on the polishing pad or wafer substrate. During polishing, the polishing pad and the carrier are both rotated, and this causes mechanical and chemical effects on the surface of the wafer substrate and / or the top layer thereon, thereby removing undesirable materials and producing a highly flat surface. A post-CMP cleaning step is then performed using a rotating scrubber brush together with a cleaning solution to clean one or both sides of the wafer substrate.

[0172] Figure 3Ais a cross-sectional view of the interconnect structure before starting the method. As illustrated here, the logic area 109 is presented on the right hand side, as indicated by the dashed line. A partial through-hole 130 exists in the logic area. Continuing, a metal contact 128 has been formed on the substrate 104 or on the semiconductor die 102. A first dielectric layer 110 is formed on the substrate, and the first dielectric layer 110 also covers the metal contact. A first etch stop layer 120 has been formed on the first dielectric layer 110. A second dielectric layer 112, a second etch stop layer 122, and a third dielectric layer 114 are also illustrated. They are collectively further referred to as dielectric material 270. Only one side of the guard ring 140 is illustrated here. The guard ring 140 and the through-hole 130 have been partially formed. For convenience, the semiconductor die 102 is omitted in other figures.

[0173] Then from Figure 2 Step 310 starts and Figure 3B As illustrated in FIG. 2 , an etch stop layer 124 is formed on the dielectric material 270 .

[0174] Then, in Figure 2 In step 312, Figure 3C As described in , a dielectric layer 260 is formed on the etch stop layer 124. The dielectric layer may be planarized. Return to Figure 1C , dielectric layer 260 corresponds to the portion having thickness 265 between etch stop layer 124 and first horizontal plate 170. Dielectric layer 260 forms a top surface 272 of the dielectric material / structure. This will permit better etch profile control during the etch for forming trench 160.

[0175] Next, in Figure 2 In the optional step 314 of Figure 3D As described in , a dielectric material is doped to form a doped dielectric region 242. This can be accomplished, for example, using ion implantation or other suitable processes. In short, an ion implanter is used to implant atoms, thereby modifying the etching selectivity of the dielectric material in the implantation location. An ion implanter typically includes an ion source, a beam line, and a process chamber. The ion source produces the desired ions (here, for example, boron (B) or arsenic (As)). The beam line organizes the ions into a beam with high purity in terms of ion mass spectrum, energy, and species. A mask such as a patterned photoresist layer or a hard mask layer is used to expose the desired area of ​​the dielectric material. Next, the ion beam is used to irradiate the semiconductor wafer substrate in the processing chamber. The ion beam strikes the exposed area, and the ions can be implanted in the dielectric material at a desired depth as dopants. The steps result in a capacitor having a bow region.

[0176] Then, in Figure 2 In step 316 of Figure 3E As described in , a photoresist layer 244 is applied and patterned to expose the desired locations of the trenches for the capacitors. Figure 2 In step 318 of Figure 3F As illustrated in FIG. 1 , a trench 160 is formed in the dielectric material. This is typically accomplished by etching. In this regard, the etchant has a higher etch selectivity for the material in the doped dielectric region than for the dielectric material, and thus etching sideways into the doped dielectric region is faster than etching down into the dielectric material. As illustrated here, after removing the photoresist layer, the resulting trench is at a depth corresponding to Figure 3D The doped dielectric region has an arcuate region 240. The trench sidewalls 162 and bottom surface 164 are also most evident here.

[0177] Next, in Figure 2 In step 320, Figure 3G As described in the foregoing, a first metal is deposited on the sidewalls 162 and bottom surface 164 of the trench and on the surface of the dielectric material in a conformal manner. The deposited layer is referred to as a first metal layer 171 in some embodiments of the present disclosure. Conformal deposition can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition techniques.

[0178] Next, in Figure 2 In step 322 of Figure 3H As described in the foregoing, a first insulator is deposited on the first metal layer 171 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material in a conformal manner. The deposited layer is referred to as a first insulator layer 181 in some embodiments of the present disclosure. This can be accomplished by CVD, PVD, ALD or other deposition processes.

[0179] Then, in Figure 2 In step 324 of Fig. 3I As described in the foregoing, a second metal is deposited on the first insulator layer 181 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material in a conformal manner. The deposited layer is referred to as a second metal layer 191 in some embodiments of the present disclosure. This can be accomplished by CVD, PVD, ALD or other deposition processes.

[0180] As illustrated here, the second metal fills the gap at the top of the trench, thereby creating a void 250 in the trench. The void can be considered a second insulator. Therefore, the second metal layer also covers the second insulator. Generally speaking, most of the void is located in the arcuate region. For example, at least 50% of the void depth 257 can exist in the arcuate region 240.

[0181] Continue, in Figure 2 In step 328 of Figure 3J As described in , the second metal layer and the portion of the first insulator layer on the surface are removed from the surface of the dielectric material. This can be done by a planarization process such as CMP. The horizontal portion of the first metal layer 171 is thus exposed and separated from the second metal layer 191 in the trench by the first insulator layer 181.

[0182] Then, in Figure 2 In step 334 of Figure 3K , a primary insulator is applied to the surface of the dielectric material. In some specific embodiments, the primary insulator is the same as the first insulator, and therefore in the description, the layer is still referred to as the first insulator layer 181. Thus, the second metal layer 191 is isolated in the trench.

[0183] Next, in Figure 2 In step 336 of Figure 3L As described in the above, a third metal layer 211 is formed on the first insulator layer 181. Next, Figure 2 In step 338, patterning is performed to form a first horizontal plate 170 with a first metal layer, a second horizontal plate 180 with a first insulator layer, and a third horizontal plate 190 with a third metal layer. Thus, capacitor 150 is formed. Next, in Figure 2 In step 348, a cover layer 220 is applied over the three horizontal panels. The resulting structure is illustrated in Figure 3M As can be seen here, the first horizontal plate 170 and the third horizontal plate 190 are both exposed from the top.

[0184] Next, in Figure 2 In step 350, Figure 3N As illustrated in , additional dielectric material is deposited to cover the capacitors. Thus, the horizontal plates 170, 180, 190 of the capacitors are embedded within the dielectric layer 260.

[0185] Then, in Figure 2 In step 352, an etch stop layer 126 is formed on the dielectric layer 260. Figure 2 In step 354, a dielectric layer is formed on the etch stop layer 126. The two steps 352 and 354 can be repeated as needed. After adding the etch stop layer 126 and the interconnect layer (or fifth dielectric layer) 118, the resulting structure is shown in FIG. Fig.3O middle.

[0186] exist Figure 2 In step 356 of Figure 3P As described in FIG. 1 , etching is performed to form a top via opening 232 leading to the capacitor. A guard ring opening 142 and a through-hole opening 132 may also be formed. Next, in FIG. Figure 2In step 358, the top through hole opening 232, the guard ring opening 142 and the through hole opening 132 are filled with appropriate materials to obtain the top through hole 230, the guard ring 140 and the through hole 130. Figures 3A to 3P As described in FIG. 1 , the guard ring 140 and the through hole 130 are formed through multiple opening and filling steps. The resulting structure is shown in FIG. Figure 1A middle.

[0187] Figure 4A is a plan view of one configuration of the grooves and horizontal plates of capacitor 150. Dashed line AA indicates the plan view, Figure 1A is intercepted through it. Figure 4A , the cover layers are not shown. The capacitor bottom metal or CBM (here the first horizontal plate 170) and the capacitor top metal or CTM (here the third horizontal plate 190) are shown. The trench 160 is shown as rectangular and extends down into the page, and only one top via 230 is illustrated in the center of the third horizontal plate. Figure 4B yes Figure 4A Here, the second horizontal plate 180 is visible.

[0188] FIG. 4C to FIG. 4J 2 are various plan views of capacitors according to some embodiments, showing different shapes and configurations of the trench 160, top via 230, capacitor bottom metal (or CBM) 282, and capacitor top metal (or CTM) 284 of the capacitor, which can be used to optimize density and capacitance for various applications. Approximately the same surface area is used in each figure, and these are merely illustrative, non-limiting examples.

[0189] exist Figure 4C In the example, two capacitors are arranged vertically. Figure 4D In the example, two capacitors are arranged horizontally. Figure 4E In the capacitor, there are two trenches that intersect at their centers to form a cross. Figure 4F In FIG. 1 , the capacitor includes four grooves. Two grooves are arranged on the X-axis, and two grooves are arranged on the Y-axis. The four grooves intersect at their ends to form a square annular groove. Figure 4G In the embodiment, two capacitors are arranged vertically. Each capacitor has two parallel trenches. Figure 4H In the embodiment, two capacitors are arranged horizontally. Each capacitor has two parallel trenches. Fig. 4I In the , the capacitor has four trenches that are configured to form the shape of a number symbol, a pound sign, or a hash mark. Figure 4JIn the example, the capacitor has six trenches that are configured to form a large square shape that is divided into four smaller squares. In these examples, the top via 230 is shown in the center of the CTM, but can be located anywhere in the surface area of ​​the CTM.

[0190] The capacitors can be of various sizes as desired. Figure 5 is a Y-axis cross-sectional view illustrating this variation of the capacitor. Here, the trench depth 165 is greater than Figure 1A The capacitors are much deeper. Therefore, the aspect ratio (ratio of trench depth to plate width) of the capacitors is also higher. Figure 1A In , the capacitors exist in three different dielectric layers 112, 114, 116. In contrast, in Figure 5 , the capacitors are present in five different dielectric layers 112, 114, 116, 118, 290. In general, the capacitors may be present in any desired number of dielectric layers, including only one dielectric layer.

[0191] Fig. 6A and Figure 6B is a cross-sectional view illustrating an additional variation of capacitor 150. Figure 1A In the case of the arcuate region, the arcuate region is near the top of the groove. Fig. 6A In the embodiment, the arcuate region 240 is located in the middle of the groove. Figure 6B In the embodiment of FIG. 1 , the arcuate region 240 is near the bottom of the trench. The pore 250 also changes position. The position of the arcuate region is based on the position of the doped dielectric region, and thus Figure 2 The location of the doping step 314 in the method can be changed according to the location of the desired arcuate region. For example, if the arcuate region is required to be near the bottom of the trench, such as Figure 6B In the embodiment of the present invention, it may be necessary to dope the second dielectric layer 112 before forming the other dielectric layers 114, 116, 118.

[0192] exist Figure 2 In the method Figures 3A to 3P In the description, the second insulator is an air void. However, it is also contemplated that the second insulator material may be deposited in the trenches. Fig. 7A and Figure 7B A second method 302 for manufacturing the interconnect structure according to some embodiments is described together. Here, the second insulator is included in the trench of the insulator. Some steps of the method are also described in FIG. 8A to FIG. 8E middle.

[0193] Fig. 7A Steps 310 to 324 are Figure 2 However, Fig. 7A After step 324, it is different. As described above with respect to step 324 and Fig. 3I As discussed, Figure 2 In the first method, the second metal fills the gap at the top of the trench, thereby creating a void 250 in the trench. Fig. 8A As shown in FIG. 1 , the second metal does not fill the gap at the top of the trench. Therefore, additional material can still be deposited in the trench 160.

[0194] Continue, then, in Fig. 7A In step 326 of Figure 8B As described in the foregoing, a second insulator is deposited on the second metal layer 191 on the sidewalls and bottom surface of the trench in a conformal manner, and a second insulator may also be deposited on the surface of the dielectric material. The deposited layer is referred to as a second insulator layer 201 in some embodiments of the present disclosure. This may be accomplished by CVD, PVD, ALD, or other deposition processes.

[0195] In a particular embodiment, the second insulator is silicon nitride (SiN), which can provide tensile or compressive stress to balance any stress in the interconnect structure. In this regard, silicon nitride can be deposited using ALD (for high aspect ratio trench fill) or CVD. Common growth temperatures for silicon nitride range from 200°C to 800°C. Silicon precursors used for deposition may include silanes and halogenated silanes. Examples may include, but are not limited to, tetraethyl orthosilicate (TEOS), trimethylsilane, tetramethylsilane, hexachlorodisilane (HCDS), iodosilane and other chlorosilanes. Nitrogen precursors used for deposition may include, but are not limited to, ammonia (NH3), N2, and N2O. To promote the dissociation of the precursors, a plasma source such as an inductively coupled plasma (ICP) or a capacitively coupled plasma (CCP) may be used. In order to better control the dissociation rate of the precursor and the viscosity of the precursor flowing to the wafer substrate, other gases such as argon, hydrogen or nitrogen may also be included to promote dissociation or reduce viscosity.

[0196] The stress applied by SiN can be adjusted / controlled / changed by: (1) changing the deposition or growth temperature to control the degree of thermal expansion of the resulting SiN; (2) using different precursors to change the crystalline quality of the resulting SiN; and / or (3) changing the way the precursor dissociates to control the material that starts the SiN growth. For example, generally, higher growth temperatures will result in the formation of a layer with greater tensile stress. For example, by increasing the growth temperature to a range of 400°C to 600°C, the stress of the SiN can be increased by 3.2 MPa / °C for a SiN layer having a thickness of about 200nm to about 300nm. The SiN can also be made to apply greater tensile stress by reducing the amount of impurities in the SiN. This can be done, for example, by increasing the dissociation rate of the precursor using a plasma source or a gas containing gases such as argon or hydrogen.

[0197] Next, in Fig. 7A In step 328 of Figure 8C As described in , the surface of the dielectric material is planarized to remove the second insulator layer, the second metal layer, and the portion of the first insulator layer on the surface. This can be done, for example, by CMP. The horizontal portion of the first metal layer 171 is thus exposed. The second insulator layer 201 surrounded by the second metal layer 191 is also exposed.

[0198] Next, in Fig. 7A In step 330, Fig.8D As described in FIG. 2 , a groove 203 is formed on the second insulator layer 201. This can be done, for example, by etching. Fig. 7A In step 332 of Fig. 8E As described in the embodiment of the present invention, the groove is filled with the second metal layer 191. Additional planarization may be performed as needed to remove excess second metal. Therefore, the resulting structure is functionally the same as Figure 3J The same. Therefore, Fig. 7A and Figure 7B The following steps 334 to 358 are related to Figure 2 Same, and like Figure 3K to Figure 3P As described in .

[0199] Fig. 9 is a third method 304 for manufacturing another interconnect structure according to some embodiments. The capacitor has a different structure. Some steps of the method are also described in FIG. 10A to FIG. 10C middle.

[0200] Fig. 9 Steps 310 to 326 are Fig. 7A and Figure 7B However, Fig. 9 The difference after step 326 is that steps 328 to 336 are not performed. Fig. 9 In step 338 of Fig. 10A As described in FIG. 1 , patterning is performed to form a first horizontal plate 170 with a first metal layer, a second horizontal plate 180 with a first insulator layer, and a third horizontal plate 190 with a second metal layer. Thus, capacitor 150 is formed. Next, in Fig. 9 In step 348, a cover layer 220 is applied over the three horizontal panels. The resulting structure is illustrated in Fig. 10B As seen here, the first horizontal plate 170 and the third horizontal plate 190 are both exposed from the top, but this is not necessarily required.

[0201] Therefore, the resulting structure is functionally similar to Figure 3M Same. Therefore, Fig. 9 The following steps 350 to 358 are related to Fig. 7A and Figure 7B The steps are the same. Fig. 10C is a cross-sectional view of the final interconnect structure including the capacitor 150 and the guard ring 140 .

[0202] Fig. 10D is a Y-axis cross-sectional view of a variation of the capacitor when the optional doping step 314 is not performed, so there are no bow regions in the capacitor 150. Therefore, there are no voids. A guard ring 140 surrounds the capacitor, but is only illustrated on one side of the capacitor.

[0203] Fig.11 306 is a fourth method for manufacturing an interconnect structure according to some embodiments. Here, the capacitor has a MIMIM structure formed by five conformal layers. Some steps of the method are also described in FIG. 12A to FIG. 12E middle.

[0204] Fig.11 Steps 310 to 318 and Figure 2 About the same. Fig. 12A The resulting structure is shown after step 318, when the trench 160 of the capacitor has been formed in the dielectric material 270. The sidewalls 162 and bottom surface 164 of the trench are labeled here along with the top surface 272 of the dielectric material.

[0205] exist Fig.11 In step 320, a first metal is deposited in a conformal manner on the sidewalls 162 and bottom surface 164 of the trench and on the surface of the dielectric material. This forms a first metal layer 171. Next, in Fig.11 In step 322, a first insulator is deposited on the first metal layer 171 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material in a conformal manner. This forms a first insulator layer 181. Continuing, in Fig.11In step 324, a second metal is deposited on the first insulator layer 181 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material in a conformal manner. This forms a second metal layer 191. Next, Fig.11 In step 326, a second insulator is deposited in a conformal manner on the second metal layer 191 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material. This forms a second insulator layer 201. Finally, in Fig.11 In step 336, a third metal is deposited in a conformal manner on the second insulator layer 201 on the sidewalls and bottom surface of the trench and on the surface of the dielectric material. This forms a third metal layer 211. The resulting structure is shown in FIG. Fig. 12B Portions of all five layers are present on the top surface 272 of the dielectric structure. The conformal layers may be deposited using PVD, CVD, ALD or other suitable processes.

[0206] Continue, in Fig.11 In step 346 of Fig. 12C As illustrated in , patterning is performed to form a first horizontal plate 170 with a first metal layer, a second horizontal plate 180 with a first insulator layer, a third horizontal plate 190 with a second insulator layer, a fourth horizontal plate with a second insulator layer, and a fifth horizontal plate with a third metal layer. Thus, a capacitor 150 is formed. As seen here, the first horizontal plate 170, the third horizontal plate 190, and the fifth horizontal plate 210 (all three metal layers) are exposed from the top. The second horizontal plate (insulator layer) is sized to isolate the first horizontal plate from the third horizontal plate. The fourth horizontal plate (insulator layer) is sized to isolate the third horizontal plate from the fifth horizontal plate. Generally speaking, the fifth horizontal plate has the smallest width / length, while the first horizontal plate has the largest width / length.

[0207] Then, in Fig.11 In step 348, a cover layer 220 is applied over the five horizontal panels. The resulting structure is illustrated in Fig.12D As can be seen here, the first horizontal plate 170 and the third horizontal plate 190 are both exposed from the top. Fig.11 Steps 350 to 358 are Figure 2 The capacitor (or resulting structure) 150 is described in Fig.12E , where the top through hole 230 is visible.

[0208] Fig.12F 2 is a Y-axis cross-sectional view of a variation of a MIMIM capacitor, where an arcuate region 240 is present in the capacitor, and a void 250 is also present. This can be achieved by using a doped dielectric region 242 to shape the trench, which is Fig.11It should be noted that in the description, the pores 250 exist in the third metal layer, rather than in the third metal layer. Figure 1A In addition, the aperture extends above the first horizontal plate 170 and is not completely within the trench. Two top vias 230 are illustrated here that contact the third horizontal plate 190 and the fifth horizontal plate 210. The first horizontal plate 170 contacts the intermetallic contacts 128.

[0209] Fig.13A It is a plan view of a configuration of the groove and horizontal plate of the capacitor. The dotted line AA indicates the plan view. Fig.12E Can be cut through it. Fig.13A In FIG. 1 , the cover layer is not shown. All three metal horizontal plates 170, 190, 210 are visible and exposed from the top. Likewise, the groove 160 is shown as rectangular and extends downward into the page. Three top through holes 230 are illustrated, one top through hole contacting each metal horizontal plate. Fig. 13B yes Fig.13A Here, the two insulator horizontal plates 180, 200 are visible.

[0210] FIG. 13C to FIG. 13J 1 are various plan views of capacitors according to some embodiments, showing different shapes and configurations of the grooves and horizontal plates of the capacitors, which can be used to optimize density and capacitance for various applications. Approximately the same surface area is used in each figure, and these are merely illustrative, non-limiting examples. Each figure is similar to that in FIG. 1 except that the capacitor has three metal horizontal plates and three top vias are illustrated in various locations. FIG. 4C to FIG. 4J The corresponding figure in .

[0211] Fig.14 308 is a fifth method for manufacturing an interconnect structure according to some embodiments. The capacitor has a MIMIM structure with five horizontal plates. Some steps of the method are also described in FIG. 15A to FIG. 15D middle.

[0212] Fig.14 Steps 310 to 324 are Fig. 9 After step 324, proceed to step 338. Fig.15A Shown in Fig.14 The resulting structure after step 338. Patterning has been performed to form a first horizontal plate 170 with a first metal layer, a second horizontal plate 180 with a first insulator layer, and a third horizontal plate 190 with a second metal layer.

[0213] Continue, in Fig.14 In step 340, a second insulator layer is conformally deposited on the dielectric material. Fig.14In step 342, a third metal layer is conformally deposited on the dielectric material. Next, Fig.14 In step 344, patterning is performed to form the fourth horizontal plate 200 with the second insulator layer and the fifth horizontal plate 210 with the third metal layer.

[0214] The resulting structure is shown in Fig. 15B Similarly, the first horizontal plate 170, the third horizontal plate 190, and the fifth horizontal plate 210 (all three metal layers) are exposed from the top. The second horizontal plate (insulator layer) is sized to isolate the first horizontal plate from the third horizontal plate. The fourth horizontal plate (insulator layer) is sized to isolate the third horizontal plate from the fifth horizontal plate. Generally speaking, the fifth horizontal plate has the smallest width / length, while the first horizontal plate has the largest width / length.

[0215] Then, in Fig.14 In step 348, a covering layer is applied over the five horizontal panels. The resulting structure is illustrated in Fig. 15C middle. Fig.14 Steps 350 to 358 are Fig. 9 The capacitor (or resulting structure) 150 is described in Fig.15D , where top via 230 is visible. The capacitor includes an aperture 250.

[0216] Fig.15E is a Y-axis cross-sectional view of a variation of the capacitor where no bowing region or void is present in capacitor 150. Guard ring 140 surrounds the capacitor but is only illustrated on one side of the capacitor.

[0217] Fig.16 360 is a method for fabricating an interconnect structure in which a guard ring is formed around a capacitor according to some embodiments. Some steps of the method are also described in 17A to 17C middle.

[0218] exist Fig.16 In step 362, a capacitor is formed in the dielectric material. Fig.16 In step 364, the capacitor is covered with additional dielectric material. Additional steps for making the capacitor can be found, for example, in Figure 2 , Fig. 7A , Figure 7B , Fig. 9 , Fig.11 and Fig.14 middle. Fig.17A is a cross-sectional view of the resulting interconnect structure. The structure in this state is similar to that of Fig.3O The structure shown in FIG. 1 includes a capacitor 150 and a portion of a through-hole 130 .

[0219] Next, in Fig.16 In step 366 of Fig. 17B , a guard ring opening 142 is formed around the capacitor 150 in the dielectric material 270. The guard ring opening passes through the dielectric material 270 and extends at least from the top level 151 of the capacitor to the bottom level 153 of the capacitor. The top via opening 232 and the through-hole opening 132 are also illustrated as being formed in the same step.

[0220] Then, in Fig.16 In step 368 of Fig. 17C As described in , the guard ring opening is filled with metal to form a guard ring 140 around the capacitor. The top via opening and the through-hole opening are also filled to form the top via 230 and the through-hole 130. Fig. 17C In, with Figure 1A The guard ring 140 is illustrated as having a constant width 145 from the top level 151 to the bottom level 153, compared to the guard ring 140 having different widths along its depth. In a specific embodiment, the guard ring 140 has a minimum width 145 of about 0.5 microns to effectively reduce noise. Although the width of the guard ring may vary along its height, it will never decrease below about 0.5 microns.

[0221] In addition, the guard ring is formed completely in one filling step rather than in Figure 2 It should be noted that no current or signal passes through the guard ring and therefore no electrical contact is made with the guard ring.

[0222] FIG. 17D to FIG. 17F 2 are various plan views of the interconnect structure, showing different shapes and configurations of capacitors and guard rings that may be used as desired depending on the application. The dielectric layer 260 has the same surface area in each of the figures, and these are merely illustrative, non-limiting examples. Each figure includes a guard ring 140, a capacitor bottom metal (or CBM) 282, a capacitor top metal (or CTM) 284, and two top vias 230 contacting the CBM and CTM. Fig.17D In FIG. 1 , the guard ring 140 has a rectangular shape, and the capacitor 150 also has a rectangular shape. Fig.17E In FIG. 1 , the guard ring 140 has a hexagonal shape, and the capacitor 150 has a rectangular shape. Fig.17D In FIG. 1 , the guard ring 140 and the capacitor 150 each have a circular shape.

[0223] Semiconductor packages having interconnect structures containing capacitors and / or guard rings surrounding capacitors as described in some embodiments of the present disclosure may be used in various applications. Those semiconductor packages may be used in various applications, such as image signal processors (ISPs) that may be combined with CMOS image sensors; or global shutters for high-speed capture in cameras or monitors. Other potential applications may include bipolar-CMOS-DMOS (BCD) circuits for driving discrete high-voltage components; drivers for LCD, OLED, AMOLED, or QLED display panels; image sensors that may be used in systems such as cell phones, facial recognition systems, or as motion sensors for automotive applications, security applications, energy efficiency, etc.; power management devices that control the flow and direction of power; and / or artificial intelligence applications.

[0224] Fig.18A 3 is a schematic plan view of a capacitor array for a CMOS image sensor according to some embodiments. As shown here, the CMOS image sensor includes an array of photo sensors 376 that convert light into electrical signals. A color filter array is used to filter light by a range of wavelengths to obtain information about light intensity. As illustrated here, a Bayer color filter is used with two green elements, one red element, and one blue element (denoted as R, G, or B). Capacitor 150 is electrically connected to each photo sensor at a 1:1 ratio.

[0225] Fig.18B 2 is a cross-sectional view of a CMOS image sensor (CIS) semiconductor package 370 connected to an image signal processor (ISP) semiconductor package 380. The front side of the CIS semiconductor package includes a photo sensor 376 on the right hand side. The transistor 372 on the left hand side is used for control. There is an interconnect structure 374 on the back side of the CIS semiconductor package. The ISP semiconductor package includes a transistor 382 and an interconnect structure 384. There is a capacitor 150 of some embodiments of the present disclosure in the interconnect structure. The CIS semiconductor package 370 and the ISP semiconductor package 380 are connected to each other via a hybrid bond 390 using a dielectric bond and a metal bond. There are metal bonding pads 378, 388 in each package.

[0226] Whether used alone or together, the capacitors and guard rings described in some embodiments of the present disclosure have several advantages. Various capacitors can be implemented using many different geometries and mixed as needed, providing flexibility in trench design. The design is compatible with logic processes and has robust reliability. The morphology of the capacitor can also be better controlled. The use of deep trenches can increase the capacitance per unit area by up to 4 times compared to traditional structures. This allows large amounts of image data to be processed simultaneously. Deep trenches can also relieve stress, which can be caused by, for example, differences in expansion coefficients between different layers or due to uneven distribution of materials within a layer. The presence of the arched region can also provide stress relief, and the second insulator (such as air pores) allows the capacitor to flex in response to stress while still acting as a capacitor. The use of guard rings improves the reliability of the capacitor and reduces noise that can damage the capacitor. This noise can be caused by surrounding interconnect structures or layers above and below the capacitor, and it can produce electrical effects that damage the capacitor.

[0227] Thus, in some embodiments, some embodiments of the present disclosure are directed to various methods of manufacturing a capacitor. A trench is formed in a dielectric material. A first metal is deposited on multiple sidewalls and bottom surfaces of the trench and on the surface of the dielectric material to form a first metal layer. A first insulator is deposited on the first metal layer on the sidewalls and bottom surfaces of the trench and on the surface of the dielectric material to form a first insulator layer. A second metal is deposited on the first insulator layer on the sidewalls and bottom surfaces of the trench, over the second insulator in the trench, and on the surface of the dielectric material to form a second metal layer. For example, by planarization to remove multiple portions of the second metal layer and the first insulator layer on the surface of the dielectric material. A main insulator is applied to the surface of the dielectric material to isolate the second metal in the trench. A third metal layer is formed on the first insulator layer on the surface of the dielectric material. Patterning is performed to form a first horizontal plate with the first metal layer, a second horizontal plate with the first insulator layer, and a third horizontal plate with the third metal layer to obtain a capacitor.

[0228] The method may further include applying a capping layer over the first horizontal plate, the second horizontal plate, and the third horizontal plate. In some other embodiments, the method may further include doping the dielectric material to form a doped dielectric region before forming the trench in the dielectric material, so that the trench is formed with an arcuate region. The second insulator may be located within the arcuate region. The depth of the arcuate region may be 10% to 50% of the depth of the trench.

[0229] In other embodiments, the method may further include: forming a plurality of top via openings leading to the first horizontal plate and the third horizontal plate and a guard ring opening surrounding the capacitor; and filling the top via openings and the guard ring openings to form a plurality of top vias and a guard ring.

[0230] In some embodiments, the second insulator in the trench is air or silicon nitride.The dielectric material may be part of the interconnect structure.

[0231] In some embodiments, the method may further include: depositing a second insulator in the trench after conformally depositing the second metal layer. Then, after planarizing to remove the second metal layer and portions of the first insulator layer, etching the second insulator to form a recess. Then, refilling the recess with the second metal so that the second metal layer is located above the second insulator.

[0232] In certain embodiments, the second horizontal plate exposes a perimeter of the first horizontal plate. In other embodiments, the trench has an aspect ratio of 3 to 15. In yet other additional embodiments, the trench may be through an etch stop layer.

[0233] In some embodiments of the present disclosure, a capacitor is disclosed, including a vertical groove, a first horizontal plate, a second horizontal plate, and a third horizontal plate. A first metal, a first insulator, and a second metal are arranged in the vertical groove. The first horizontal plate is located above the vertical groove, and the first horizontal plate is connected to the first metal in the vertical groove. The second horizontal plate is located above the first horizontal plate, and the second horizontal plate is connected to the first insulator in the vertical groove. The third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal.

[0234] In some embodiments, the capacitor further comprises a covering layer covering the first horizontal plate, the second horizontal plate, and the third horizontal plate. In some embodiments, the second horizontal plate isolates the second metal from the third horizontal plate. In other embodiments, the third metal and the second metal are the same material, and the third horizontal plate is connected to the second metal in the vertical groove. In still other embodiments, there is also a second insulator in the groove. That is, the capacitor comprises a second insulator in the vertical groove.

[0235] In additional embodiments, the capacitor may further include a fourth horizontal plate located above the third horizontal plate, the fourth horizontal plate being made of the second insulator, and a fifth horizontal plate located above the fourth horizontal plate, the fifth horizontal plate being made of the fourth metal.

[0236] Some embodiments of the present disclosure also disclose a semiconductor device having an interconnect structure including a capacitor, wherein the capacitor has one of the above structures. For example, the capacitor includes a vertical groove, a first horizontal plate, a second horizontal plate, and a third horizontal plate. The first metal, the first insulator, the second metal, and the second insulator are arranged in the vertical groove. The first horizontal plate is located above the vertical groove, and the first horizontal plate is connected to the first metal in the vertical groove. The second horizontal plate is located above the first horizontal plate, and the second horizontal plate is connected to the first insulator in the vertical groove. The third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal. In a specific embodiment, the semiconductor device is an image signal processor, and the capacitor is electrically connected to a photodiode.

[0237] Some embodiments of the present disclosure also disclose a capacitor with an arched region, including: a vertical trench with an arched region, a first metal, a first insulator, a second metal and a second insulator configured in the vertical trench, wherein the second insulator is encapsulated or surrounded by the second metal.

[0238] In some other embodiments, the capacitor further comprises: a first horizontal plate located above the vertical trench, the first horizontal plate connected to the first metal in the vertical trench; a second horizontal plate located above the first horizontal plate, the second horizontal plate connected to the first insulator in the vertical trench; and a third horizontal plate located above the second horizontal plate, the third horizontal plate made of a third metal. In some embodiments, the second horizontal plate isolates the second metal from the third horizontal plate. In other embodiments, the third metal and the second metal are the same, and the third horizontal plate is connected to the second metal in the vertical trench.

[0239] Some embodiments of the present disclosure also disclose a method for manufacturing a capacitor having an arcuate region. A dielectric material is doped to form a doped dielectric region. A photoresist layer is patterned over the dielectric material exposing the doped dielectric region. The dielectric material and the doped dielectric region are then etched to form a trench having an arcuate region. A first metal is conformally deposited on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a first metal layer. A first insulator is conformally deposited on the first metal layer on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a first insulator layer. A second metal is conformally deposited on the first insulator layer on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a second metal layer. Thus, a capacitor is obtained.

[0240] In some other embodiments, after conformally depositing the second metal layer, a second insulator is deposited in the trench. The second insulator is then covered with the second metal.

[0241] Some embodiments of the present disclosure also disclose a semiconductor device including a capacitor having a bow-shaped region.

[0242] In various embodiments, a capacitor is also disclosed, the capacitor includes a vertical groove, a first metal, a first insulator, a second metal, and a second insulator are arranged in a ring shape in the vertical groove. There is a first horizontal plate above the vertical groove, and the first horizontal plate is connected to the first metal in the vertical groove. There is a second horizontal plate above the first metal horizontal plate, and the second horizontal plate is connected to the first insulator in the vertical groove. There is a third horizontal plate above the second horizontal plate, and the third horizontal plate is connected to the second metal in the vertical groove. If necessary, there may be a covering layer to cover the first horizontal plate, the second horizontal plate, and the third horizontal plate.

[0243] An alternative method for making a capacitor is also disclosed. A trench is formed in a dielectric material. A first metal is conformally deposited on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a first metal layer. A first insulator is conformally deposited on the first metal layer on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a first insulator layer. A second metal is conformally deposited on the first insulator layer on the sidewalls and bottom surface of the trench and on the surface of the dielectric material to form a second metal layer, wherein the second metal layer surrounds the air void. Patterning is then performed to form a first horizontal plate with the first metal layer, a second horizontal plate with the first insulator layer, and a third horizontal plate with the second metal layer. A semiconductor device including a capacitor of the structure is also disclosed in some embodiments of the present disclosure.

[0244] Some embodiments of the present disclosure also relate to an interconnect structure for an integrated circuit, including a capacitor in a dielectric material and a guard ring surrounding the capacitor.

[0245] Some embodiments of the present disclosure also disclose methods for manufacturing interconnect structures for integrated circuits, including: forming trenches and guard ring openings around the trenches in a dielectric material; forming capacitors in the trenches and on a surface of the dielectric material; and filling the guard ring openings with metal to form a guard ring around the capacitors.

[0246] Some embodiments of the present disclosure also disclose a semiconductor device, the semiconductor device comprising: a capacitor in a dielectric material; and a guard ring surrounding the capacitor.

[0247] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and various changes, substitutions and modifications can be made in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A method for manufacturing a capacitor, characterized in that: Include: forming a trench in a dielectric material; Depositing a first metal on a plurality of sidewalls and a bottom surface of the trench and on a surface of the dielectric material to form a first metal layer; Depositing a first insulator on the first metal layer on the sidewalls and the bottom surface of the trench and on the surface of the dielectric material to form a first insulator layer; Depositing a second metal on the first insulator layer on the sidewalls and the bottom surface of the trench, over a second insulator in the trench, and on the surface of the dielectric material to form a second metal layer; planarizing to remove portions of the second metal layer and the first insulator layer on the surface of the dielectric material; applying a primary insulator on the surface of the dielectric material to isolate the second metal in the trench; forming a third metal layer on the first insulator layer on the surface of the dielectric material; and Patterning is performed to form a first horizontal plate with the first metal layer, a second horizontal plate with the first insulator layer and a third horizontal plate with the third metal layer to obtain the capacitor.

2. The method according to claim 1, characterized in that Also includes: Before forming the trench in the dielectric material, the dielectric material is doped to form a doped dielectric region so that the trench is formed with a bow-shaped region.

3. The method according to claim 2, characterized in that The second insulator is located in the arcuate region.

4. The method according to claim 1, characterized in that Also includes: forming a plurality of top through-hole openings leading to the first horizontal plate and the third horizontal plate and a guard ring opening surrounding the capacitor; and The top via openings and the guard ring opening are filled to form a plurality of top vias and a guard ring.

5. The method according to claim 1, characterized in that Also includes: After conformally depositing the second metal layer, depositing the second insulator in the trench; and After planarizing to remove the portions of the second metal layer and the first insulator layer, etching the second insulator to form a recess; and The recess is refilled with the second metal such that the second metal layer is over the second insulator.

6. A capacitor, characterized in that: Include: a vertical trench, wherein a first metal, a first insulator and a second metal are disposed in the vertical trench; a first horizontal plate, located above the vertical groove, the first horizontal plate connected to the first metal in the vertical groove; a second horizontal plate located above the first horizontal plate, the second horizontal plate being connected to the first insulator in the vertical groove; and A third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal.

7. The capacitor according to claim 6, wherein: Also includes: A covering layer covers the first horizontal plate, the second horizontal plate and the third horizontal plate.

8. The capacitor according to claim 6, wherein: The second horizontal plate separates the second metal from the third horizontal plate.

9. The capacitor according to claim 6, wherein: Also includes: a fourth horizontal plate located above the third horizontal plate, the fourth horizontal plate being made of a second insulator; and A fifth horizontal plate is located above the fourth horizontal plate, and the fifth horizontal plate is made of a fourth metal.

10. A semiconductor device having an interconnect structure including a capacitor, characterized in that: The capacitor contains: a vertical trench, wherein a first metal, a first insulator, a second metal and a second insulator are disposed in the vertical trench; a first horizontal plate, located above the vertical groove, the first horizontal plate connected to the first metal in the vertical groove; a second horizontal plate located above the first horizontal plate, the second horizontal plate being connected to the first insulator in the vertical groove; and A third horizontal plate is located above the second horizontal plate, and the third horizontal plate is made of a third metal.

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