A pGaN gate enhancement device and its self-terminating etching method

Abstract

This invention discloses a pGaN gate enhancement-mode device and its self-terminating etching method. The self-terminating etching method includes: sequentially growing a core layer, a buffer layer, a channel layer, a barrier layer, a high-Al composition layer, and a p-GaN layer on a substrate; etching away the p-GaN layer except for the gate electrode region to expose the high-Al composition layer; performing F-plasma surface treatment on the high-Al composition layer to form an AlF3 layer on its upper surface; etching the AlF3 layer in the source and drain electrode regions at both ends of the device down to the upper surface of the barrier layer, and forming source and drain electrodes on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; the remaining AlF3 layer serves as a passivation layer to protect the barrier layer; and forming the gate electrode on the upper surface of the p-GaN layer. This invention effectively improves the surface roughness of the barrier layer after etching and effectively suppresses the gate leakage current of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a pGaN gate enhancement device and its self-terminating etching method. Background Technology

[0002] GaN's unique material advantages give it enormous potential and application prospects in the field of power devices, while GaNHEMT devices are naturally depletion-mode. To reduce costs, improve device safety and reliability, and promote the upgrading of related industries, the development of enhancement-mode devices is necessary.

[0003] Among the current mainstream methods for fabricating enhancement-mode GaN HEMT devices, those using p-GaN gates offer low on-resistance and high positive threshold voltage. The current mainstream approach involves forming a PN junction structure below the gate electrode, utilizing p-GaN to deplete the 2DEG beneath the channel, thus achieving channel pinch-off. This device structure is known as a p-GaN gate enhancement-mode device. A crucial process step in fabricating p-GaN gate enhancement-mode devices is etching away the entire p-GaN layer outside the gate electrode region. Currently, inductively coupled plasma (ICP) etching is commonly used. Common GaN-ICP etching gases include BCl3 / Cl2; however, these gases have low selectivity for GaN / AlGaN etching, making it difficult to precisely control the etching time to ensure complete etching of the p-GaN layer without damaging the AlGaN barrier layer. Residual p-GaN or thinning of the AlGaN barrier layer due to etching can lead to a decrease in the 2DEG concentration below, thereby affecting the device's output characteristics. The mainstream process for removing non-gate electrode regions of p-GaN through etching presents challenges in terms of roughness, uniformity, and selectivity due to the characteristics of the etching process. Therefore, achieving minimal surface etching damage and realizing self-terminating p-GaN etching to ensure complete etching of p-GaN without damaging the AlGaN barrier layer are key challenges in the fabrication of p-GaN gate enhancement-mode devices. Existing p-GaN etching processes mainly improve the GaN / AlGaN etching selectivity by adding auxiliary gases such as SF6 or O2 to the etching gas, forming a barrier layer with the Al element in the AlGaN barrier layer.

[0004] However, in order to achieve a higher etching selectivity, it is often necessary to increase the proportion of auxiliary gas, which can lead to adverse effects such as damage to the GaF3 or Ga-O bond surfaces. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a pGaN gate enhancement device and its self-terminating etching method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a self-terminating etching method based on a pGaN gate enhancement-mode device, the self-terminating etching method comprising:

[0007] A core layer, a buffer layer, a channel layer, a barrier layer, a high Al composition layer, and a p-GaN layer are sequentially grown on the substrate.

[0008] The p-GaN layer, except for the gate electrode region, is etched away to expose the high Al composition layer;

[0009] The high-Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high-Al composition layer;

[0010] The AlF3 layer at both ends of the device is etched up to the upper surface of the barrier layer, and a source electrode and a drain electrode are formed on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; the remaining AlF3 layer serves as a passivation layer to protect the barrier layer;

[0011] A gate electrode is formed on the upper surface of the p-GaN layer.

[0012] In one embodiment of the present invention, a high-Al composition layer is grown on the barrier layer, comprising:

[0013] A high-Al content layer is obtained by growing AlGaN material with an Al content greater than 0.5 and a thickness of 1 nm to 2 nm on the barrier layer.

[0014] In one embodiment of the present invention, etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer includes:

[0015] Using fluorine-based gas, the p-GaN layer, except for the gate electrode region, is etched away to expose the high-Al composition layer.

[0016] In one embodiment of the present invention, the high-Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high-Al composition layer, including:

[0017] The high-Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high-Al composition layer.

[0018] In one embodiment of the present invention, the high-Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high-Al composition layer, including:

[0019] The high-Al composition layer was subjected to RF plasma surface treatment using an ICP device to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high-Al composition layer. The ICP process parameters used included: ICP power of 150 W, RF power of 20 W, CF4 gas flow rate of 30 sccm, and processing time of 120 s.

[0020] In one embodiment of the present invention, before forming the source electrode and the drain electrode, the method further includes:

[0021] The AlF3 layers at both ends of the device are etched up to the upper surface of the buffer layer to form a mesa isolation.

[0022] In one embodiment of the present invention, etching the AlF3 layer at both ends of the device up to the upper surface of the buffer layer includes:

[0023] The AlF3 layers at both ends of the device are etched up to the upper surface of the buffer layer using at least one gas selected from chlorine, fluorine, Ar, N2, or O2.

[0024] Secondly, embodiments of the present invention provide a pGaN gate enhancement device, wherein the pGaN gate enhancement device is fabricated using the self-terminating etching method for pGaN gate enhancement devices described in any one of the first aspects; the pGaN gate enhancement device comprises:

[0025] The substrate layer, and the nucleation layer, buffer layer, channel layer, barrier layer and high Al composition layer sequentially located on the substrate layer;

[0026] The p-GaN layer is located on the high Al composition layer near one end of the device;

[0027] An AlF3 layer is located on the remaining high-Al composition layer;

[0028] The source electrode and drain electrode are located in the source and drain electrode regions at both ends of the device and extend through the AlF3 layer to the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer;

[0029] The gate electrode is located on the p-GaN layer.

[0030] In one embodiment of the present invention, the high Al content layer is an AlGaN material with an Al content greater than 0.5 and a thickness of 1 nm to 2 nm.

[0031] In one embodiment of the present invention, the thickness of the AlF3 layer is 0.5 nm to 1 nm.

[0032] The beneficial effects of this invention are:

[0033] The self-terminating etching method for pGaN gate enhancement devices proposed in this invention further improves the fabrication method based on device structure improvements, thereby producing GaN-based enhancement devices with high electron mobility. It combines the high threshold voltage, high breakdown voltage, high current density, and excellent pinch-off characteristics inherent in GaN-based HEMT devices, while reducing the required proportion of auxiliary gas during etching, thus minimizing the adverse effects of auxiliary gas and effectively improving the surface roughness of the barrier layer after etching, avoiding over-etching of the barrier layer. Simultaneously, it effectively suppresses the gate leakage current of the device. Specifically, by adding a high-Al composition layer between the barrier layer and the p-GaN layer, the increased Al composition makes it easier for F ions in the etching gas to form an AlF3 layer with the Al in the high-Al composition layer during the etching of the non-gate region of the p-GaN layer, thus improving the gate efficiency. High etching selectivity reduces etching damage to the barrier layer surface. After etching the p-GaN layer in the non-gate region, the sample is placed in F plasma for surface treatment. This further promotes the formation of the AlF3 layer, which acts as a passivation layer to protect the barrier layer and suppress gate leakage current. On the other hand, the F plasma treatment forms a thin insulating layer on the surface of the p-GaN layer, which significantly reduces the leakage current of the Schottky gate and reduces surface states and defects caused by etching the non-P-GaN gate region, thus improving the performance of GaN-based HEMT devices. The growth of the high Al composition layer and the F plasma treatment after etching are compatible with existing material growth processes and p-GaN etching processes, eliminating the need for additional photolithography operations and saving costs. This effectively reduces production costs while improving device performance.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] Figure 1 This is a schematic flowchart of a self-terminating etching method for a pGaN gate enhancement device provided in an embodiment of the present invention;

[0036] Figures 2a to 2g This is a schematic diagram of the structure corresponding to the self-terminating etching process of the pGaN gate enhancement device provided in the embodiments of the present invention;

[0037] Figure 3 This is based on the embodiments of the present invention. Figure 1 The transfer curve and gate electrode leakage current of the pGaN gate enhancement device obtained by the self-terminating etching method.

[0038] Figure 4 It is original and unprocessed Figure 1 A schematic diagram of the roughness of the barrier layer processed by the self-terminating etching method;

[0039] Figure 5 It was through Figure 1 A schematic diagram of the roughness of the barrier layer processed by the self-terminating etching method;

[0040] Figure 6 This is a schematic diagram of the structure of a pGaN gate enhancement device provided in an embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 01-Substrate layer; 02-Nucleation layer; 03-Buffer layer; 04-Channel layer; 05-Barrier layer; 06-High Al composition layer; 07-p-GaN layer; 08-AlF3 layer; 09-Source electrode; 10-Drain electrode; 11-Gate electrode. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0044] Please see Figure 1 This invention provides a self-terminating etching method based on a pGaN gate enhancement-mode device. The self-terminating etching method includes:

[0045] S10. On the substrate layer 01, the core layer 02, buffer layer 03, channel layer 04, barrier layer 05, high Al composition layer 06 and p-GaN layer 07 are grown sequentially.

[0046] In this embodiment of the invention, the substrate layer 01 is made of any one of silicon, sapphire, silicon carbide, gallium nitride, or diamond self-supporting substrate.

[0047] In this embodiment of the invention, a metal-organic chemical vapor deposition process is used to sequentially grow a core layer 02, a buffer layer 03, a channel layer 04, a barrier layer 05, a high Al composition layer 06, and a p-GaN layer 07 on a substrate layer 01, as follows: Figure 2a As shown in the diagram, the nucleation layer 02 is made of AlN superlattice; the buffer layer 03 is made of GaN or AlGaN, where the Al composition in the AlGaN gradually decreases from 0.7 to 0.1 from bottom to top; the channel layer 04 is made of GaN; the barrier layer 05 is made of AlGaN, where the Al composition is 0.25; and the high Al composition layer 06 is made of AlGaN, where the Al composition is greater than 0.5. The high Al composition layer 06, with an Al composition greater than 0.5, facilitates self-terminating etching. Higher Al composition allows for a larger selective etching ratio between the p-GaN layer 07 and the barrier layer 05, resulting in less interface damage.

[0048] In this embodiment of the invention, a metal-organic chemical vapor deposition process is used to sequentially grow a nucleation layer 02 with a thickness of 0.5 nm to 2 nm, a buffer layer 03 with a thickness of 0.2 μm to 1 μm, a channel layer 04 with a thickness of 100 nm to 300 nm, a barrier layer 05 with a thickness of 10 nm to 30 nm, a high Al composition layer 06 with a thickness of 1 nm to 2 nm, and a p-GaN layer 07 with a thickness of 70 nm to 120 nm on a substrate layer 01.

[0049] In conventional pGaN gate enhancement devices, the p-GaN gate typically incorporates a certain proportion of SF6 into the etching gas to improve etching selectivity, but the proportion of the auxiliary gas is usually 40% or higher. A higher proportion of auxiliary gas leads to the formation of more non-volatile compounds such as GaF3 during etching, which is detrimental to the formation of a high-quality etch interface. By adding a high-Al composition layer 06 between the barrier layer 05 and the p-GaN layer 07, the proportion of auxiliary gas in the etching gas can be reduced, thereby reducing the formation of non-volatile compounds such as GaF3 during etching. The thickness of the high-Al composition layer 06 is crucial; a suitable thickness allows for self-terminating etching without significantly impacting device performance. In this embodiment, a high-Al composition layer 06 of 1 nm to 2 nm is preferred. A high-Al composition layer 06 smaller than 1 nm results in poor self-terminating etching, while a high-Al composition layer 06 larger than 2 nm alters the 2DEG concentration and mobility in the channel, thus affecting device performance.

[0050] S20. Etch away the p-GaN layer 07 except for the gate electrode region to expose the high Al composition layer 06.

[0051] In this embodiment of the invention, a patterned gate electrode region is obtained through photolithography; such as... Figure 2b As shown, based on fluorine-based gas, the p-GaN layer 07, except for the gate electrode region, is etched away using an ICP process, leaving only the p-GaN layer 07 below the gate electrode region to expose the high Al composition layer 06. Figure 2c As shown. Here, fluorine-based gas was chosen to better achieve the desired effect of F plasma surface treatment on the high-Al composition layer O6.

[0052] S30. Perform F plasma surface treatment on the high Al composition layer 06 to form an AlF3 layer 08 on the upper surface of the high Al composition layer 06.

[0053] This invention embodiment performs F plasma surface treatment on a high Al composition layer 06 to form an AlF3 layer 08 on the upper surface of the high Al composition layer 06. The method includes: using an ICP device, placing the sample obtained in S20 into F plasma to perform F plasma surface treatment on the high Al composition layer 06 to form an AlF3 layer 08 on the upper surface of the high Al composition layer 06. Figure 2d As shown, the AlF3 layer 08 is a thin-layer structure with a thickness of 0.5nm to 1nm. The ICP process parameters used include: ICP power of 150W, RF power of 20W, CF4 gas flow rate of 30sccm, and processing time of 120s, to ensure that the device performance is not significantly damaged under these parameters and that the gate leakage current is effectively suppressed.

[0054] S40. Etch the AlF3 layer 08 at both ends of the device source and drain electrode regions up to the upper surface of the barrier layer 05, and form the source electrode 09 and drain electrode 10 on the upper surface of the barrier layer 05; wherein, the source electrode 09 is close to the p-GaN layer 07; the remaining AlF3 layer 08 serves as a passivation layer to protect the barrier layer 05.

[0055] Before forming the source electrode 09 and drain electrode 10, this embodiment of the invention further includes: etching the AlF3 layer 08 at both ends of the device up to the upper surface of the buffer layer 03 to form a mesa isolation, such as... Figure 2e As shown. More specifically, in this embodiment of the invention, etching the AlF3 layer 08 at both ends of the device up to the upper surface of the buffer layer 03 includes: etching the AlF3 layer 08 at both ends of the device up to the upper surface of the buffer layer 03 using an ICP or RIE (Reactive Ion Etching) process based on at least one gas selected from chlorine-based, fluorine-based, Ar, N2, or O2, i.e., the etching depth is the sum of the thicknesses of the AlF3 layer 08, the high Al composition layer 06, the barrier layer 05, and the channel layer 04.

[0056] Furthermore, in this embodiment of the invention, patterned source and drain electrode regions are obtained through photolithography. Based on at least one gas selected from chlorine-based, fluorine-based, Ar, N2, or O2, the AlF3 layer 08 at both ends of the device is etched up to the upper surface of the barrier layer 05 using ICP or RIE processes. The etching depth is the sum of the thicknesses of the AlF3 layer 08 and the high-Al composition layer 06. Then, an ohmic metal, such as a Ti / Al / Ni / Au or Ti / Al / Ti / Au stack, is deposited on the upper surface of the barrier layer 05 in the source and drain electrode regions using electron beam evaporation to form the source electrode 09 and drain electrode 10. Figure 2f As shown, it is thermally annealed at a high temperature above 800°C for 15s to 60s in a nitrogen atmosphere to form an ohmic contact.

[0057] S50, A gate electrode 11 is formed on the upper surface of the p-GaN layer 07.

[0058] In this embodiment of the invention, a patterned gate electrode region is obtained through photolithography. A gate metal, such as a Ni / Au or Ni / TiN stack, is deposited on the upper surface of the p-GaN layer 07 in the gate electrode region using electron beam evaporation to form the gate electrode 11. Figure 2gAs shown.

[0059] Currently, the gate leakage current of conventional p-GaN gate enhancement devices is around 10⁻⁴ mA / mm, while the pGaN gate enhancement device prepared by the self-terminating etching method proposed in this invention, such as... Figure 3 As shown, the gate leakage current is below 10⁻⁶ mA / mm, which reduces the gate current by at least two orders of magnitude. This invention effectively suppresses the gate leakage current of the device without reducing the device output current. Figure 3 The horizontal axis represents the gate voltage Vg, in V; the vertical axis on the left represents the device output current Id, in mA / mm; and the vertical axis on the right represents the gate leakage current Ig, in mA / mm.

[0060] Depend on Figure 4 It can be seen that the roughness Ra of the barrier layer without the self-terminating etching method proposed in this invention is 1.694 nm; Figure 5 It can be seen that the surface roughness Ra of the barrier layer treated by the self-terminating etching method proposed in this invention is 0.231. The comparison shows that the self-terminating etching method proposed in this invention effectively improves the surface roughness of the barrier layer after etching. Specifically, this can be achieved through... Figure 4 and Figure 5 The horizontal and vertical coordinate information determines the size of the measurement area.

[0061] In summary, the self-terminating etching method for pGaN gate enhancement devices proposed in this invention further improves the fabrication method based on the improved device structure, thereby producing GaN-based enhancement devices with high electron mobility. It combines the high threshold voltage, high breakdown voltage, high current density, and excellent pinch-off characteristics inherent in GaN-based HEMT devices, while reducing the required proportion of auxiliary gas during etching, thus minimizing the adverse effects of the auxiliary gas. This effectively improves the surface roughness of the barrier layer 05 after etching, avoiding over-etching of the barrier layer 05, and effectively suppressing the gate leakage current. Specifically, by adding a high-Al composition layer 06 between the barrier layer 05 and the p-GaN layer 07, the increased Al composition makes it easier for F ions in the etching gas to form an AlF3 layer with the Al in the high-Al composition layer 06 during the etching of the non-gate region p-GaN layer 07. To improve the etching selectivity and reduce etching damage to the surface of the barrier layer 05, the sample is placed in F plasma for surface treatment after etching of the non-gate region p-GaN layer 07. This further promotes the formation of the AlF3 layer 08, which acts as a passivation layer to protect the barrier layer 05 and suppress gate leakage current. Furthermore, the F plasma treatment forms a thin insulating layer on the surface of the p-GaN layer 07, significantly reducing the leakage current of the Schottky gate and decreasing surface states and defects caused by etching of the non-P-GaN gate region, thus improving the performance of the GaN-based HEMT device. The growth of the high-Al composition layer 06 and the subsequent F plasma treatment are compatible with existing material growth processes and p-GaN etching processes, eliminating the need for additional photolithography operations and saving costs. This effectively reduces production costs while improving device performance.

[0062] Secondly, please see Figure 6 This invention provides a pGaN gate enhancement device, which is fabricated using any one of the self-terminating etching methods for pGaN gate enhancement devices according to the first aspect; the pGaN gate enhancement device includes:

[0063] Substrate layer 01, and nucleation layer 02, buffer layer 03, channel layer 04, barrier layer 05, and high Al composition layer 06 sequentially located on substrate layer 01;

[0064] p-GaN layer 07 is located on high Al composition layer 06 near one end of the device;

[0065] AlF3 layer 08 is located on the remaining high-Al composition layer 06;

[0066] The source electrode 09 and the drain electrode are located in the source and drain electrode 10 regions at both ends of the device and extend through the AlF3 layer 08 to the upper surface of the barrier layer 05; wherein, the source electrode 09 is close to the p-GaN layer 07.

[0067] Gate electrode 11 is located on p-GaN layer 07.

[0068] In this embodiment of the invention, the high Al content layer 06 is an AlGaN material with an Al content greater than 0.5 and a thickness of 1 nm to 2 nm.

[0069] In this embodiment of the invention, the thickness of the AlF3 layer 08 is 0.5 nm to 1 nm.

[0070] As for the device embodiment of the second aspect, since it is basically similar to the self-terminating etching method embodiment of the first aspect, the description is relatively simple. For relevant details, please refer to the description of the self-terminating etching method embodiment of the first aspect.

[0071] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0072] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0073] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A self-terminating etching method for a pGaN gate enhancement-mode device, characterized in that, The self-terminating etching method includes: A core layer, a buffer layer, a channel layer, a barrier layer, a high Al composition layer, and a p-GaN layer are sequentially grown on the substrate. The p-GaN layer, except for the gate electrode region, is etched away to expose the high Al composition layer; The high-Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high-Al composition layer; The AlF3 layer at both ends of the device is etched up to the upper surface of the barrier layer, and a source electrode and a drain electrode are formed on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; the remaining AlF3 layer serves as a passivation layer to protect the barrier layer; A gate electrode is formed on the upper surface of the p-GaN layer.

2. The self-terminating etching method for pGaN gate enhancement devices according to claim 1, characterized in that, A high-Al composition layer is grown on the barrier layer, comprising: A high-Al content layer is obtained by growing AlGaN material with an Al content greater than 0.5 and a thickness of 1 nm to 2 nm on the barrier layer.

3. The self-terminating etching method for pGaN gate enhancement devices according to claim 1, characterized in that, Etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer includes: Using fluorine-based gas, the p-GaN layer, except for the gate electrode region, is etched away to expose the high-Al composition layer.

4. The self-terminating etching method for pGaN gate enhancement devices according to claim 1, characterized in that, The high-Al composition layer is subjected to F-plasma surface treatment to form an AlF3 layer on the upper surface of the high-Al composition layer, including: The high-Al composition layer was subjected to RF plasma surface treatment using an ICP device to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high-Al composition layer. The ICP process parameters used included: ICP power of 150 W, RF power of 20 W, CF4 gas flow rate of 30 sccm, and processing time of 120 s.

5. The self-terminating etching method for pGaN gate enhancement devices according to claim 1, characterized in that, Before forming the source and drain electrodes, the process also includes: The AlF3 layers at both ends of the device are etched up to the upper surface of the buffer layer to form a mesa isolation.

6. The self-terminating etching method for pGaN gate enhancement devices according to claim 5, characterized in that, The etching process extends from the AlF3 layer at both ends of the device up to the upper surface of the buffer layer, including: The AlF3 layers at both ends of the device are etched up to the upper surface of the buffer layer using at least one gas selected from chlorine, fluorine, Ar, N2, or O2.

7. A pGaN gate enhancement-mode device, characterized in that, The pGaN gate enhancement device is prepared by the self-terminating etching method of any one of claims 1 to 6; The pGaN gate enhancement device includes: The substrate layer, and the nucleation layer, buffer layer, channel layer, barrier layer and high Al composition layer sequentially located on the substrate layer; The p-GaN layer is located on the high Al composition layer near one end of the device; An AlF3 layer is located on the remaining high-Al composition layer; the thickness of the AlF3 layer is 0.5 nm to 1 nm. The source electrode and drain electrode are located in the source and drain electrode regions at both ends of the device and extend through the AlF3 layer to the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; The gate electrode is located on the p-GaN layer.

8. The pGaN gate enhancement-mode device according to claim 7, characterized in that, The high Al content layer is an AlGaN material with an Al content greater than 0.5 and a thickness of 1 nm to 2 nm.

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