A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor layer; forming a gate cap layer on a barrier layer of the semiconductor layer; forming a gate dielectric layer; forming a first field plate on the gate dielectric layer, the first field plate corresponding to covering the gate cap layer and extending along the edge of one side of the gate cap layer, and the first field plate being provided with a field plate hole in the area corresponding to the gate cap layer; forming a source metal and a drain metal, the first field plate being located between the source metal and the drain metal in the horizontal direction, the first field plate extending towards the drain metal and covering the edge of the gate cap layer close to the drain metal; and forming a gate contact hole, the opening size of the gate contact hole being smaller than that of the field plate hole to form a nested hole structure. Thus, the application can avoid the breakdown phenomenon caused by the large electric field intensity between the gate and the drain, and can simplify the preparation process, shorten the preparation procedure, and improve the reliability and yield of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] High electron mobility transistor (HEMT) is a field effect transistor based on the high mobility characteristics of two-dimensional electron gas in heterojunction, which has high electron mobility at low temperature and low electric field, and can realize high speed and low noise operation. At present, gallium nitride high electron mobility transistor (GaN HEMT) has been widely used in power conversion circuits of consumer electronics due to its fast switching rate, small on-resistance and small loss. With the development of science and technology, the application end puts forward higher requirements for power devices, such as higher efficiency, higher frequency, miniaturization and lightness. In order to improve the performance of HEMT devices, various methods are adopted, and there are great differences in the structure and preparation method of HEMT devices. In general, in order to improve the performance of devices, the reliability of HEMT devices is affected, the manufacturing difficulty is increased, or the production efficiency is reduced, so that the application prospect of HEMT devices is limited. Therefore, how to improve the performance of devices while maintaining their reliability and improving production efficiency has become a technical problem to be solved for gallium nitride HEMT. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device and a preparation method thereof, so as to improve the device performance and reliability of HEMT, and improve the production efficiency.

[0004] In order to achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a semiconductor device, comprising:

[0005] providing a semiconductor layer, the semiconductor layer comprising a channel layer and a barrier layer;

[0006] forming a gate cap layer on the barrier layer, the gate cap layer covering part of the area of the barrier layer;

[0007] forming a gate dielectric layer on the gate cap layer and the barrier layer;

[0008] forming a first field plate on the gate dielectric layer, the first field plate corresponding to covering the gate cap layer and extending along the edge of one side of the gate cap layer; a field plate hole is formed on the area of the first field plate corresponding to the gate cap layer;

[0009] forming a source metal and a drain metal, the source metal and the drain metal penetrating the gate dielectric layer and connecting with the barrier layer; in the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends to the drain metal and covers the edge of the gate cap layer close to the drain metal;

[0010] forming a gate contact hole extending downward from above the first field plate to expose the gate cap layer, the gate contact hole having an opening size smaller than that of the field plate hole, and the gate contact hole and the field plate hole not overlapping in boundary to form a nested hole structure;

[0011] forming a gate metal in the gate contact hole, the gate metal being connected to the gate cap layer through the gate contact hole.

[0012] Optionally, in the step of forming the first field plate on the gate dielectric layer, the step comprises:

[0013] forming a field plate metal layer on the gate dielectric layer;

[0014] patterning the field plate metal layer based on one etching process to form the first field plate having the field plate hole.

[0015] Optionally, in the step of forming the first field plate on the gate dielectric layer, the step comprises:

[0016] forming a field plate metal layer on the gate dielectric layer;

[0017] patterning the field plate metal layer to reserve a portion of the field plate metal layer covering the gate cap layer and a side edge of the gate cap layer close to the drain metal;

[0018] forming the field plate hole by opening a portion of the field plate metal layer corresponding to the area covering the gate cap layer.

[0019] Optionally, in the step of forming the source metal and the drain metal, the step further comprises:

[0020] forming a first dielectric layer on the first field plate and the gate dielectric layer, the first dielectric layer filling the field plate hole;

[0021] forming a source contact hole and a drain contact hole in the first dielectric layer and the gate dielectric layer, the source contact hole and the drain contact hole exposing the barrier layer;

[0022] forming a first electrode metal layer on the first dielectric layer, in the source contact hole and in the gate contact hole;

[0023] patterning the first electrode metal layer to reserve the first electrode metal layer in the source contact hole and the drain contact hole to obtain the source metal and the drain metal, and to reserve a portion of the first electrode metal layer on the first dielectric layer to form a second field plate, the second field plate being horizontally between the first field plate and the drain metal, and the second field plate and a projection of the first field plate in the vertical direction partially overlapping.

[0024] Optionally, in the step of forming the gate contact hole, the step comprises:

[0025] forming the gate contact hole by using a photolithography self-alignment process and an etching process.

[0026] Optionally, the step of forming the gate contact hole includes:

[0027] A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer covers the patterned first electrode metal layer;

[0028] A gate contact hole is formed in the second dielectric layer. The gate contact hole extends downward from the second dielectric layer through the first dielectric layer and the gate dielectric layer to expose the gate cap layer.

[0029] Optionally, the step of forming gate metal within the gate contact hole includes:

[0030] A second electrode metal layer is formed above the second dielectric layer and inside the gate contact hole;

[0031] A patterned second electrode metal layer is formed, at least the second electrode metal layer inside the gate contact hole is retained to form the gate metal, and a portion of the second electrode metal layer on the second dielectric layer is retained to form the third field plate; in the horizontal direction, the third field plate is located between the second field plate and the drain metal, and the third field plate overlaps with the projection portion of the second field plate in the vertical direction.

[0032] Optionally, multiple field plate holes are provided, and the multiple field plate holes are spaced apart in the area of ​​the gate cap layer corresponding to the first field plate, and the gate contact holes are provided in one-to-one correspondence with the field plate holes.

[0033] According to one aspect of the present invention, a semiconductor device is also provided, comprising:

[0034] The semiconductor layer includes a channel layer and a barrier layer;

[0035] Gate cap layer, partially covering the barrier layer;

[0036] A gate dielectric layer covers the gate cap layer and the barrier layer;

[0037] A first field plate is formed on the gate dielectric layer and correspondingly covers the gate cap layer. The first field plate covers at least one edge of the gate cap layer. A field plate hole is provided in the area of ​​the first field plate corresponding to the gate cap layer.

[0038] The source metal and drain metal are located above the semiconductor layer. Both the source metal and drain metal penetrate the gate dielectric layer and are connected to the barrier layer. In the horizontal direction, the first field plate is located between the source metal and the drain metal. The first field plate extends towards the drain metal and covers the edge of the gate cap layer near the drain metal.

[0039] The gate contact hole extends downward from above the field plate hole corresponding to the field plate hole to the exposed gate cap layer. The opening size of the gate contact hole is smaller than the opening size of the field plate hole. The boundary of the gate contact hole does not coincide with the boundary of the field plate hole, so as to form a nested hole structure with the field plate hole.

[0040] The gate metal is located at least within the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

[0041] Optionally, multiple field plate holes are provided, and the multiple field plate holes are spaced apart in the area of ​​the gate cap layer corresponding to the first field plate, and the gate contact holes are provided in one-to-one correspondence with the field plate holes.

[0042] Compared with the prior art, the semiconductor device and its fabrication method of the present invention have at least the following beneficial effects:

[0043] The semiconductor device fabrication method of the present invention includes forming a first field plate on a gate dielectric layer. The first field plate covers a gate cap layer and extends along the edge of the gate cap layer near the drain metal. A field plate via is formed in the region of the first field plate corresponding to the gate cap layer. Thus, the first field plate can completely cover the edge of the gate cap layer near the drain metal. In the device off-state, the field plate structure ensures the continuity of the low-potential region, making the channel electric field more uniform, thereby preventing the gate edge from being broken down and improving device reliability. Furthermore, the field plate via formed on the first field plate allows for subsequent formation of gate contact holes using photolithography alignment, reducing one mask and photolithography step, simplifying the fabrication process, and shortening the fabrication time. During the formation of the gate contact hole, the opening size of the gate contact hole is controlled to be smaller than the opening size of the field plate via, and the boundary of the gate contact hole does not coincide with the boundary of the field plate via to form a nested via structure. This avoids etching the first field plate during the formation of the gate contact hole, which would cause etching difficulties, and also avoids electrical contact between the gate metal subsequently formed in the gate contact hole and the first field plate, improving device reliability and yield. Furthermore, the present invention does not increase the gate length or the gate-source / gate-drain spacing, thus improving the device withstand voltage without increasing the device size.

[0044] The first field plate in the semiconductor device of the present invention includes a portion covering the edge of the gate cap layer near the drain metal side, which can protect the location with high electric field strength near the drain side of the gate and avoid breakdown. Furthermore, the semiconductor device of the present invention is formed using the above-described semiconductor device fabrication method, which similarly simplifies the fabrication process, shortens the fabrication flow, and improves device reliability and yield. Attached Figure Description

[0045] Figure 1a This is a schematic diagram of the structure of the semiconductor device in the embodiments of the present invention;

[0046] Figure 1b This is a flowchart of the steps involved in fabricating a semiconductor device according to an embodiment of the present invention;

[0047] Figure 2To provide a schematic diagram of the structure of a semiconductor layer;

[0048] Figure 3 For Figure 2 A schematic diagram of the structure after a gate cap layer is formed on the semiconductor layer;

[0049] Figure 4 For Figure 3 A schematic diagram of the structure after the gate dielectric layer is formed on the semiconductor layer and the gate cap layer;

[0050] Figure 5 For Figure 4 A schematic diagram of the structure after the first field plate is formed on the gate dielectric layer;

[0051] Figure 6 For Figure 5 A schematic diagram of the structure after the first dielectric layer is formed on the first field plate and the gate dielectric layer;

[0052] Figure 7 For Figure 6 A schematic diagram of the structure after the source metal, gate metal and second field plate are formed on the structure;

[0053] Figure 8 For Figure 7 A schematic diagram of the structure after the second dielectric layer is formed on the structure;

[0054] Figure 9 For Figure 8 A schematic diagram of the structure after the gate contact hole is formed on the structure;

[0055] Figure 10 For Figure 9 A schematic diagram of the structure after the gate metal and the third field plate are formed on the structure;

[0056] Figure 11 For Figure 10 A schematic diagram of the structure after an interlayer dielectric layer is formed on the structure;

[0057] Figure 12 for Figure 11 The structure as a projected view in the top (vertical) direction;

[0058] Figure 13 This is a schematic diagram of the three-dimensional structure of the first plate.

[0059] Figure 14 For Figure 13 A schematic diagram of the three-dimensional structure after the gate metal is formed on the first field plate.

[0060] List of reference numerals in the attached diagram:

[0061] 100 Semiconductor Layer

[0062] 101 Substrate

[0063] 102 Channel Layer

[0064] 103 Barrier Layer

[0065] 110 Gate cap layer

[0066] 120 gate dielectric layer

[0067] 130 First game board

[0068] 131 Field plate hole

[0069] 140 Isolation Structure

[0070] 150 First dielectric layer

[0071] 161 Source Metal

[0072] 162 Drain Metal

[0073] 163 Second Board

[0074] 170 Second dielectric layer

[0075] 180 gate contact hole

[0076] 191 Gate metal

[0077] 192 Third Session

[0078] 200 interlayer dielectric layer Detailed Implementation

[0079] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0080] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0081] During the operation of HEMT devices, the drain terminal experiences a high voltage, while the source / gate terminal experiences a low voltage. The electric field is depleted along the channel direction, and the electric field strength is strongest near the gate edge, which is also the most vulnerable to breakdown. Typically, several layers of metal field plates are arranged near the gate towards the drain to homogenize the electric field distribution in the channel, thereby preventing premature breakdown at the gate edge and improving the device's breakdown voltage. Figure 1a As shown, when fabricating HEMT devices, in order to avoid the dielectric aperture process of the gate contact hole 180 being etched onto the first field plate 130, the inventors leave a certain distance D between the first field plate 130 and the gate cap layer 110. This results in the fact that although the field plate plays a certain role, the edge of the gate cap layer 110 is not completely protected and still has a high risk of breakdown.

[0082] To address the background technology and the aforementioned technical problems, this embodiment provides a semiconductor device and its fabrication method, aiming to protect the edge of the gate cap layer near the drain metal direction, prevent the gate edge from being broken down, and at the same time prevent the gate contact hole from being etched onto the field plate, thereby reducing manufacturing difficulty and simplifying manufacturing costs.

[0083] The present invention will now be described in detail with reference to specific embodiments.

[0084] Example 1

[0085] This embodiment provides a method for fabricating a semiconductor device, referring to... Figure 1b The method for fabricating this semiconductor device includes:

[0086] S1: Provide a semiconductor layer, the semiconductor layer including a channel layer and a barrier layer;

[0087] S2: A gate cap layer is formed on the barrier layer, and the gate cap layer covers a portion of the barrier layer.

[0088] S3: A gate dielectric layer is formed on the gate cap layer and the barrier layer;

[0089] S4: A first field plate is formed on the gate dielectric layer, the first field plate correspondingly covers the gate cap layer and extends along one edge of the gate cap layer; a field plate hole is formed on the area of ​​the first field plate corresponding to the gate cap layer;

[0090] S5: Form source metal and drain metal, both of which penetrate the gate dielectric layer and are connected to the barrier layer; in the horizontal direction, the first field plate is located between the source metal and the drain metal, and the first field plate extends toward the drain metal and covers the top of the gate cap layer near the edge of the drain metal.

[0091] S6: Form a gate contact hole, extending downward from the top of the first field plate corresponding to the field plate hole to the exposed gate cap layer. The opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not coincide with the boundary of the field plate hole to form a nested hole structure.

[0092] S7: Gate metal is formed in the gate contact hole, and the gate metal is connected to the gate cap layer through the gate contact hole.

[0093] Specifically, please refer to... Figure 2 Step S1 is executed, providing a semiconductor layer 100, which includes a channel layer 102 and a barrier layer 103.

[0094] As an example, the semiconductor layer 100 consists of a substrate layer 101, a channel layer 102, and a barrier layer 103 stacked sequentially from bottom to top. The substrate layer 101 is made of conventional semiconductor substrate materials such as silicon or aluminum oxide. The band gap of the barrier layer 103 is larger than that of the channel layer 102 to form a potential well at the heterojunction between the channel layer 102 and the barrier layer 103, capable of accommodating a two-dimensional electron gas (2DEG). In this embodiment, the channel layer 102 is made of gallium nitride, and the barrier layer 103 is made of gallium aluminum nitride. Therefore, the semiconductor device fabricated in this embodiment is a gallium nitride HEMT device.

[0095] Please refer to the following: Figure 3 Step S2 is executed to form a gate cap layer 110 on the barrier layer 103, the gate cap layer 110 covering a portion of the barrier layer 103.

[0096] As an example, the gate cap layer 110 can be a P-type doped material layer or a metal material layer. When the gate cap layer 110 is a P-type doped material layer, it can be a P-type gallium nitride layer doped with magnesium. When the gate cap layer 110 is a metal material layer, it can be gold, titanium, aluminum, tungsten, etc.

[0097] Furthermore, when the gate cap layer 110 is a P-type doped material layer, a P-type gallium nitride layer can be deposited on the barrier layer 103 by chemical vapor deposition, and then a portion of the area can be etched away to form the gate cap layer 110 at the gate region.

[0098] Please refer to the following: Figure 4 Step S3 is executed to form a gate dielectric layer 120 on the gate cap layer 110 and the barrier layer 103. Specifically, the gate dielectric layer 120 can be formed using a chemical vapor deposition method, such as low-pressure chemical vapor deposition (LPCVD). Optionally, the material of the gate dielectric layer 120 includes silicon nitride. Alternatively, as... Figure 4 As shown, before forming the gate dielectric layer 120, the step of forming an isolation structure 140 is also included. The isolation structure 140 penetrates the barrier layer 103 vertically and contacts the channel layer 102 to achieve electrical isolation between the device and other regions in the semiconductor layer 100.

[0099] Reference Figure 5 Combination Figure 12 , Figure 13 In step S4, a first field plate 130 is formed on the gate dielectric layer 120. The first field plate 130 covers the gate cap layer 110 and extends along one edge of the gate cap layer 110. A field plate hole 131 is formed on the area of ​​the first field plate 130 corresponding to the gate cap layer 110. In this embodiment, the vertical projection of the first field plate 130 completely covers the lower gate cap layer 110, and the first field plate 130 also extends towards the drain metal 162 to be formed later, covering the edge of the gate cap layer 110 near the drain metal 162. Thus, the vertical projections of the first field plate 130 and the gate cap layer 110 can overlap ("vertical projection" or "projection in the vertical direction" refers to the projection falling on the horizontal plane or the surface of the substrate layer 101), so as to protect the edge of the gate terminal near the drain side and prevent breakdown at the location with a large electric field strength. Furthermore, in this embodiment, a field plate hole 131 is formed on the area of ​​the first field plate 130 corresponding to the gate cap layer 110. The field plate hole 131 is used for photolithographic alignment of the subsequent gate contact hole 180 opening, so as to avoid etching the first field plate 130 by the dielectric opening process, which would cause etching difficulties.

[0100] As an example, the step of forming the first field plate 130 on the gate dielectric layer 120 includes: forming a field plate metal layer on the gate dielectric layer 120; and patterning the field plate metal layer using a single etching process to form the first field plate 130 having field plate holes 131. In the process of forming the first field plate 130 with field plate holes 131 using a single etching process, a mask with a field plate hole pattern can be used to etch and form the first field plate 130. This allows the first field plate 130 with field plate holes 131 to be formed using only a single etching process, simplifying the manufacturing process and improving production efficiency.

[0101] As an example, the step of forming the first field plate 130 on the gate dielectric layer 120 includes: forming a field plate metal layer on the gate dielectric layer 120, patterning the field plate metal layer to retain a portion of the field plate metal layer covering the gate cap layer 110 and the edge of the gate cap layer 110 near the drain metal 162, and making an opening in the portion of the field plate metal layer corresponding to the area covering the gate cap layer 110 to form a field plate hole 131.

[0102] Optionally, the number of apertures 131 in the field plate is at least one, but can also be two or more. (Refer to...) Figure 12 Alternatively, when there are multiple field plate holes 131, the multiple field plate holes 131 are spaced apart in the area of ​​the gate cap layer 110 corresponding to the first field plate 130.

[0103] Please continue to refer to Figure 7 Step S5 is executed to form source metal 161 and drain metal 162. Both source metal 161 and drain metal 162 penetrate the gate dielectric layer 120 and are connected to the barrier layer 103. In the horizontal direction, the first field plate 130 is located between the source metal 161 and drain metal 162. The first field plate 130 extends towards the drain metal 162 and covers the gate cap layer 110 above the edge near the drain metal 162.

[0104] As an example, before forming the source metal 161 and drain metal 162, refer to Figure 6 First, a first dielectric layer 150 is formed on the first field plate 130 and the gate dielectric layer 120, and the first dielectric layer 150 fills the field plate vias 131. Source contact holes and drain contact holes are formed in the first dielectric layer 150 and the gate dielectric layer 120, exposing the barrier layer 103. A first electrode metal layer is formed on the first dielectric layer 150, inside the source contact holes, and inside the gate contact holes 180. (Refer to...) Figure 7The first electrode metal layer is patterned, and the first electrode metal layer within the source and drain contact holes is retained to obtain source metal 161 and drain metal 162. A portion of the first electrode metal layer on the first dielectric layer 150 is retained to form a second field plate 163. In the horizontal direction, the second field plate 163 is located between the first field plate 130 and the drain metal 162, and the projection portions of the second field plate 163 and the first field plate 130 in the vertical direction overlap. The overlapping of the formed second field plate 163 and the first field plate 130 allows for the modulation of the electric field in the region between the gate and drain to achieve a uniform electric field distribution. Of course, the second field plate 163 can be fabricated separately or simultaneously with the source metal 161 and drain metal 162. In this embodiment, the second field plate 163 is fabricated simultaneously with the source metal 161 and drain metal 162, which can reduce the number of mask uses and photolithography steps, and shorten the manufacturing cycle.

[0105] Please continue to refer to Figure 9 Step S5 is executed to form the gate contact hole 180. The gate contact hole 180 extends downward from above the first field plate 130 corresponding to the field plate hole 131 to expose the gate cap layer 110, as shown in the figure. Figure 12 or Figure 14 The opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131, and the boundary of the gate contact hole 180 does not coincide with the boundary of the field plate hole 131 to form a nested hole structure. To avoid electrical contact between the gate metal 191 subsequently formed within the gate contact hole 180 and the first field plate 130, or to prevent the gate contact hole 180 from etching into the first field plate 130, the opening size of the gate contact hole 180 must be smaller than the opening size of the field plate hole 131, resulting in a dielectric layer of a certain thickness between them. Since the field plate hole 131 is formed first in this embodiment, the gate contact hole 180 can be formed using a photolithography self-alignment process and an etching process based on the field plate hole 131 window, thereby reducing the number of mask uses and photolithography cycles, and shortening the manufacturing cycle.

[0106] As an example, before forming the gate contact hole 180, refer to Figure 8 A second dielectric layer 170 is formed on the first dielectric layer 150, and the second dielectric layer 170 covers the patterned first electrode metal layer. (Refer to...) Figure 9 A gate contact hole 180 is formed in the second dielectric layer 170. The gate contact hole 180 extends downward from the second dielectric layer 170 through the first dielectric layer 150 and the gate dielectric layer 120 to expose the gate cap layer 110.

[0107] Please continue to refer to Figure 10 In step S5, a gate metal 191 is formed in the gate contact hole 180, and the gate metal 191 is connected to the gate cap layer 110 through the gate contact hole 180.

[0108] As an example, before forming the gate metal 191, a second electrode metal layer is first formed above the second dielectric layer 170 and within the gate contact hole 180. (Refer to...) Figure 10 The second electrode metal layer is patterned, and at least the second electrode metal layer within the gate contact hole 180 is retained to form the gate metal 191. A portion of the second electrode metal layer on the second dielectric layer 170 is retained to form the third field plate 192. In the horizontal direction, the third field plate 192 is located between the second field plate 163 and the drain metal 162, and the vertical projection portions of the third field plate 192 and the second field plate 163 overlap. Similarly, the overlapping of the formed third field plate 192 and the second field plate 163 allows for the modulation of the regional electric field between the gate and drain to achieve a uniform electric field distribution. Of course, the third field plate 192 can be fabricated separately or simultaneously with the gate metal 191. In this embodiment, the third field plate 192 and the gate metal 191 are fabricated simultaneously, which can reduce the number of mask uses and photolithography steps, and shorten the manufacturing cycle.

[0109] After forming the gate metal 191, refer to Figure 11 The device also includes an interlayer dielectric layer 200 formed above the gate metal 191, the third field plate 192, and the second dielectric layer 170, and a metal interconnect layer formed within the interlayer dielectric layer 200. The metal interconnect layer is used to realize the electrical connection and electrical lead-out of the internal structure in the device, and the interlayer dielectric layer 200 is used for electrical isolation between some structures within the metal interconnect layer. A passivation layer is also formed above the interlayer dielectric layer 200 and the metal interconnect layer, which is used to achieve insulation protection. The aforementioned interlayer dielectric layer 200, metal interconnect layer, and passivation layer are all conventional configurations in the art, and their structures, materials, and formation methods will not be described in detail here.

[0110] The semiconductor device fabrication method of this embodiment includes forming a first field plate on a gate dielectric layer. The first field plate covers the gate cap layer and extends along the edge of the gate cap layer near the drain metal. Field plate vias are formed in the region of the first field plate corresponding to the gate cap layer. Thus, the first field plate can completely cover the edge of the gate cap layer near the drain metal. In the device off-state, the field plate structure ensures the continuity of the low-potential region, making the channel electric field more uniform, thereby preventing the gate edge from being broken down and improving device reliability. Furthermore, the field plate vias formed on the first field plate allow for subsequent formation of gate contact vias using photolithography alignment, reducing the need for a mask and photolithography process, simplifying the fabrication process and shortening the fabrication time. During the formation of the gate contact vias, the opening size of the gate contact vias is controlled to be smaller than the opening size of the field plate vias, and the boundaries of the gate contact vias and the field plate vias do not coincide to form a nested via structure. This avoids etching the first field plate during the formation of the gate contact vias, preventing etching difficulties, and also avoids electrical contact between the gate metal subsequently formed within the gate contact vias and the first field plate, improving device reliability and yield. Furthermore, this embodiment does not increase the gate length or the gate-source / gate-drain spacing, thus improving the device withstand voltage without increasing the device size.

[0111] Example 2

[0112] This embodiment provides a semiconductor device, which is fabricated using any of the methods described in Embodiment 1 above, or other suitable methods. (Refer to...) Figure 11 The semiconductor device includes a semiconductor layer 100, a gate cap layer 110, a gate dielectric layer 120, a first field plate 130, a source metal 161, a drain metal 162, a gate contact hole 180, and a gate metal 191.

[0113] The semiconductor layer 100 includes a channel layer 102 and a barrier layer 103, with a gate cap layer 110 partially covering the barrier layer 103. A gate dielectric layer 120 covers the gate cap layer 110 and the barrier layer 103. A first field plate 130 is formed on the gate dielectric layer 120 and correspondingly covers the gate cap layer 110. The first field plate 130 covers at least one edge of the gate cap layer 110, and a field plate via 131 is provided in the area of ​​the first field plate 130 corresponding to the gate cap layer 110. A source metal 161 and a drain metal 162 are located above the semiconductor layer 100, both penetrating the gate dielectric layer 120 and connected to the barrier layer 103. In the horizontal direction, the first field plate 130 is located between the source metal 161 and the drain metal 162, extending towards the drain metal 162 and covering the edge of the gate cap layer 110 near the drain metal 162. The gate contact hole 180 extends downward from above the first field plate 130 corresponding to the field plate hole 131 to the exposed gate cap layer 110. The opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131, and the boundary of the gate contact hole 180 does not coincide with the boundary of the field plate hole 131, so as to form a nested hole structure with the field plate hole 131. The gate metal 191 is located at least within the gate contact hole 180, and the gate metal 191 is connected to the gate cap layer 110 through the gate contact hole 180.

[0114] Optionally, refer to Figure 11 Combination Figure 12 or Figure 13 The number of field plate holes 131 is at least one, and can be two or more. When there are multiple field plate holes 131, the multiple field plate holes 131 are spaced apart in the region of the first field plate 130 corresponding to the gate cap layer 110. The gate contact hole 180 extends downward from above the first field plate 130 corresponding to the field plate hole 131 to expose the gate cap layer 110, as shown in the figure. Figure 14 The opening size of the gate contact hole 180 is smaller than the opening size of the field plate hole 131, and the boundary of the gate contact hole 180 does not coincide with the boundary of the field plate hole 131 to form a nested hole structure. In order to avoid electrical contact between the gate metal 191 subsequently formed in the gate contact hole 180 and the first field plate 130, or to avoid the gate contact hole 180 etching the first field plate 130 during etching, the opening size of the gate contact hole 180 needs to be smaller than the opening size of the field plate hole 131, so that there is a dielectric layer of a certain thickness between the two.

[0115] The first field plate in the semiconductor device of the present invention includes a portion covering the edge of the gate cap layer near the drain metal side, which can protect the area with high electric field strength near the drain of the gate and prevent breakdown. The opening size of the gate contact hole is smaller than the opening size of the field plate hole, and the boundary of the gate contact hole does not coincide with the boundary of the field plate hole to form a nested hole structure. This avoids electrical contact between the gate metal subsequently formed in the gate contact hole and the first field plate, and also avoids the etching difficulty caused by etching the first field plate during the etching of the gate contact hole, reducing manufacturing difficulty and improving device reliability. Furthermore, the semiconductor device of the present invention is formed using the above-described semiconductor device fabrication method, which also has the effects of simplifying the fabrication process, shortening the fabrication process, and improving device reliability and yield.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a semiconductor layer, the semiconductor layer comprising a channel layer and a barrier layer; forming a gate cap layer on the barrier layer, the gate cap layer covering part of the barrier layer; forming a gate dielectric layer on the gate cap layer and the barrier layer; forming a first field plate on the gate dielectric layer, the first field plate corresponding to covering the gate cap layer and extending along the edge of one side of the gate cap layer, the first field plate corresponding to the area of the gate cap layer being formed with a field plate hole; forming a source metal and a drain metal, both the source metal and the drain metal penetrating the gate dielectric layer and connecting with the barrier layer; in the horizontal direction, the first field plate is between the source metal and the drain metal, the first field plate extending towards the drain metal and covering the edge of the gate cap layer close to the drain metal; forming a gate contact hole, the gate contact hole extending downwards from above the first field plate corresponding to the field plate hole to expose the gate cap layer, the opening size of the gate contact hole being smaller than the opening size of the field plate hole, the boundary of the gate contact hole not coinciding with the boundary of the field plate hole to form a nested hole structure; forming a gate metal in the gate contact hole, the gate metal connecting with the gate cap layer through the gate contact hole.

2. The method of producing a semiconductor device according to claim 1, wherein In the step of forming a first field plate on the gate dielectric layer, the method comprises: forming a field plate metal layer on the gate dielectric layer; based on one etching process, patterning the field plate metal layer to form the first field plate with the field plate hole.

3. The method of manufacturing a semiconductor device according to claim 1, wherein In the step of forming a first field plate on the gate dielectric layer, the method comprises: forming a field plate metal layer on the gate dielectric layer; patterning the field plate metal layer to retain part of the field plate metal layer covering the gate cap layer and the edge of the gate cap layer close to one side of the drain metal; forming the field plate hole by opening the part of the field plate metal layer corresponding to the area covering the gate cap layer.

4. The method of producing a semiconductor device according to Claim 1, wherein In the step of forming a source metal and a drain metal, the method further comprises: forming a first dielectric layer on the first field plate and the gate dielectric layer, the first dielectric layer filling the field plate hole; forming a source contact hole and a drain contact hole in the first dielectric layer and the gate dielectric layer, the source contact hole and the drain contact hole exposing the barrier layer; forming a first electrode metal layer on the first dielectric layer, in the source contact hole and in the gate contact hole; patterning the first electrode metal layer, retaining the first electrode metal layer in the source contact hole and the drain contact hole to obtain the source metal and the drain metal, retaining part of the first electrode metal layer on the first dielectric layer to form a second field plate, in the horizontal direction, the second field plate being between the first field plate and the drain metal, the second field plate partially overlapping the projection of the first field plate in the vertical direction.

5. The method of producing a semiconductor device according to Claim 1, wherein In the step of forming a gate contact hole, the method comprises: forming the gate contact hole by using a photolithography self-alignment process and an etching process.

6. The method of producing a semiconductor device according to claim 4, wherein In the step of forming a gate contact hole, the method comprises: forming a second dielectric layer on the first dielectric layer, the second dielectric layer covering the patterned first electrode metal layer; forming a gate contact hole in the second dielectric layer, the gate contact hole extending downward from the second dielectric layer through the first dielectric layer and the gate dielectric layer to expose the gate cap layer.

7. The method of producing a semiconductor device according to claim 6, wherein In the step of forming a gate metal in the gate contact hole, the step includes: forming a second electrode metal layer on the second dielectric layer and in the gate contact hole; patterning the second electrode metal layer to at least retain the second electrode metal layer in the gate contact hole to form the gate metal and to retain a portion of the second electrode metal layer on the second dielectric layer to form a third field plate, the third field plate being located between the second field plate and the drain metal in a horizontal direction, and the third field plate partially overlapping a projection of the second field plate in a vertical direction.

8. The method of producing a semiconductor device according to Claim 1, wherein The field plate holes are arranged in a plurality, and the plurality of field plate holes are arranged in intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact hole and the field plate hole are arranged one-to-one.

9. A semiconductor device, characterized by comprising: The semiconductor structure includes: a semiconductor layer including a channel layer and a barrier layer; a gate cap layer partially covering the barrier layer; a gate dielectric layer covering the gate cap layer and the barrier layer; a first field plate formed on the gate dielectric layer and corresponding to cover the gate cap layer, the first field plate covering at least an edge of a side of the gate cap layer, and a field plate hole being arranged in a region of the first field plate corresponding to the gate cap layer; a source metal and a drain metal located above the semiconductor layer, the source metal and the drain metal both extending through the gate dielectric layer and connected to the barrier layer, the first field plate being located between the source metal and the drain metal in a horizontal direction, the first field plate extending toward the drain metal and covering an edge of the gate cap layer close to the drain metal; a gate contact hole extending downward from above the first field plate corresponding to the field plate hole to expose the gate cap layer, an opening size of the gate contact hole being smaller than an opening size of the field plate hole, and a boundary of the gate contact hole not coinciding with a boundary of the field plate hole to form a nested hole structure with the field plate hole; a gate metal located at least in the gate contact hole, the gate metal being connected to the gate cap layer through the gate contact hole.

10. The semiconductor device of claim 9, wherein, The field plate holes are arranged in a plurality, and the plurality of field plate holes are arranged in intervals in a region of the first field plate corresponding to the gate cap layer, and the gate contact hole and the field plate hole are arranged one-to-one.

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