Semiconductor device, manufacturing method, chip and electronic equipment

Abstract

The invention relates to the field of semiconductors, and provides a semiconductor device, a manufacturing method, a chip and electronic equipment. The semiconductor device comprises a substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer and a grid electrode, the well region, the buffer region, the source region and the drain region are located on the substrate, the source region is formed on the surface of the well region, and the drain region is formed on the surface of the buffer region. The dielectric layer comprises a first dielectric layer made of a high dielectric constant material and a second dielectric layer made of a low dielectric constant material, and the first dielectric layer is located on the surface of the substrate between the well region and the buffer region and extends to the surface of the well region; the gate is located on the surface of the first dielectric layer, and the second dielectric layer is located on the surfaces of the buffer region and the drain region. An inversion channel is formed in the substrate between the well region and the buffer region by using the first dielectric layer made of a high-dielectric-constant material, so that the on-resistance is reduced; the breakdown voltage of the drain end is improved through the buffer region, the gate-drain capacitance is reduced through the second dielectric layer made of the low-dielectric-constant material, and meanwhile the voltage withstanding characteristic of the gate and the drain end is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a manufacturing method, a chip, and an electronic device. Background Art

[0002] Power semiconductor devices have the advantages of high power, high gain, good linearity, and high breakdown voltage, and are one of the core devices of power integrated circuits. Power semiconductor devices include: Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS), Vertical Double-diffused Metal-Oxide Semiconductor (VDMOS), Super Junction MOSFET (SJ-MOS), etc. Among them, LDMOS devices are widely used in power, rail transportation, electric vehicles, smart home appliances, medical and radar fields. The performance and reliability of LDMOS devices determine the use effect in power and related industrial applications, and the efficiency and linearity of LDMOS devices directly determine the performance of wireless communication systems. The advantage of high breakdown voltage of LDMOS devices enables LDMOS devices to withstand higher standing wave ratios in the case of mismatch. LDMOS devices are widely used in power management, isolated signal chain, switch control, drive and wireless communication chips. LDMOS devices are usually used to make switch tubes and driver tubes in power management, isolated signal chain, switch control, and driver chips, and RF power amplifiers in communication base stations. In power supply, isolation, switch control, drive, communication and related chips, LDMOS devices are required to meet the complex environment application requirements of high output power, high breakdown voltage, large drive current, low on-resistance, low parasitic capacitance and long reliability life.

[0003] The breakdown voltage (BV) and on-resistance (Ron) of LDMOSFET devices are important indicators. In practical applications, LDMOSFET devices with high breakdown voltage and low on-resistance are required. In the prior art, the source region of the LDMOSFET device is on the surface of the body region, the drain region is on the surface of the drift region, and the field oxygen is below the gate. The field plate modulation above the field oxygen is used to reduce the surface electric field of the device, thereby increasing the breakdown voltage. The field oxygen isolation structure is usually made using silicon local oxidation isolation (LOCOS) technology and shallow trench isolation (STI) technology. In order to increase the breakdown voltage, the thickness of STI or LOCOS needs to be increased. When the device is working, the current flows from the source end along the lower surface of the field oxygen to the drain. The thicker the field oxygen, the longer the outflow path of the current from the source to the drain, and the larger the on-resistance, making it difficult to obtain a lower on-resistance at a higher breakdown voltage. Moreover, there is field oxygen between the gate and the drain region. The thicker the field oxygen, the larger the gate-drain parasitic capacitance and related reliability issues, which are not conducive to the application of LDMOS in the fields of electricity, electric vehicles, rail transportation, smart home appliances, communications, medical care, radar, etc. Summary of the invention

[0004] In order to solve the above technical defects, the present invention provides a semiconductor device and a manufacturing method.

[0005] In one aspect, the present invention provides a semiconductor device, comprising: a substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer and a gate, wherein the well region, the buffer region, the source region and the drain region are located on the substrate, the source region is formed on the surface of the well region, the drain region is formed on the surface of the buffer region, and the well region and the buffer region are separated by a substrate material; The dielectric layer comprises a first dielectric layer made of a high dielectric constant material and a second dielectric layer made of a low dielectric constant material, wherein the dielectric constant k of the material of the first dielectric layer is greater than 3.9, and the dielectric constant k of the material of the second dielectric layer is less than or equal to 2.8; The first dielectric layer is located on the surface of the substrate between the well region and the buffer region, and extends to the surface of the well region; The gate is located on the surface of the first dielectric layer; The second dielectric layer is located on the surfaces of the buffer region and the drain region, one end of the second dielectric layer is connected to the gate and one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region.

[0006] In an embodiment of the present invention, the dielectric layer also includes a third dielectric layer of a low dielectric constant material, and the dielectric constant of the material of the third dielectric layer is k≤2.8; the third dielectric layer is located on the surface of the well region and the source region, one end of the third dielectric layer is connected to the gate and the other end of the first dielectric layer, and the other end of the third dielectric layer is connected to the source region.

[0007] In an embodiment of the present invention, the buffer zone includes a plurality of grooves filled with strained silicon material, and the plurality of grooves filled with strained silicon material are arranged at intervals in the buffer zone.

[0008] In an embodiment of the present invention, the strained silicon materials filled in the plurality of trenches are all SiGe; or, the strained silicon materials filled in the plurality of trenches are all SiC.

[0009] In an embodiment of the present invention, the strained silicon material filled in a portion of the plurality of trenches is SiGe, and the strained silicon material filled in another portion of the plurality of trenches is SiC.

[0010] In the embodiment of the present invention, a plurality of trenches filled with SiGe and a plurality of trenches filled with SiC are arranged in an alternating manner.

[0011] In the embodiment of the present invention, the shape of the groove is rectangular, hexagonal, stripe or triangle.

[0012] In the embodiment of the present invention, the high dielectric constant material of the first dielectric layer is aluminum oxide or hafnium oxide, and the low dielectric constant material of the second dielectric layer is carbon-doped silicon oxide.

[0013] In an embodiment of the present invention, the semiconductor device further includes: a transition region, wherein the transition region is located in the substrate between the well region and the buffer region.

[0014] The transition region includes a plurality of N-type doping regions and a plurality of P-type doping regions, and the plurality of N-type doping regions and the plurality of P-type doping regions are arranged alternately.

[0015] In an embodiment of the present invention, the plurality of N-type doping regions and the plurality of P-type doping regions in the transition region are arranged in an array.

[0016] In the embodiment of the present invention, the multiple N-type doping regions and the multiple P-type doping regions in the transition zone have different doping concentrations, and the doping concentrations of the N-type doping regions and the P-type doping regions decrease from near to far relative to the first dielectric layer.

[0017] In an embodiment of the present invention, the substrate is an SOI substrate, which includes, from bottom to top, a substrate silicon layer, an insulating layer and an active silicon layer; the well region, the buffer region, the source region and the drain region are formed in the active silicon layer.

[0018] In the embodiment of the present invention, the substrate silicon layer is grounded through conductive through holes arranged at both ends. The inner wall of the conductive through hole is filled with insulating material. The conductive through hole is filled with metal material or conductive doped silicon material.

[0019] In the embodiment of the present invention, the conductive via at one end of the substrate silicon layer penetrates the well region, the active silicon layer and the insulating layer; the conductive via at the other end of the substrate silicon layer penetrates the buffer region, the active silicon layer and the insulating layer.

[0020] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a well region and a buffer region separated from the well region in the substrate; forming a source region on the surface of the well region and forming a drain region on the surface of the buffer region; Depositing a high dielectric constant material on the surface of the substrate between the well region and the buffer region to form a first dielectric layer extending to the surface of the well region, wherein the dielectric constant k of the high dielectric constant material is greater than 3.9; Depositing a low dielectric constant material on the surface of the buffer region and the drain region to form a second dielectric layer, so that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region, and the dielectric constant k of the low dielectric constant material is less than or equal to 2.8; A gate is formed on the surface of the first dielectric layer so that the gate is connected to one end of the second dielectric layer.

[0021] In an embodiment of the present invention, a well region and a buffer region separated from the well region are formed in a substrate, including: selecting a P-type substrate, forming graphic windows of the well region and the buffer region on the surface of the P-type substrate, and injecting P-type ions and N-type ions into the two graphic windows respectively to form a P-type well region and an N-type buffer region.

[0022] In an embodiment of the present invention, a source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer region, including: forming a source region graphic window and a drain region graphic window on the surface of the P-type well region and the surface of the N-type buffer region, respectively, and injecting N-type ions into the source region graphic window and the drain region graphic window to form the source region and the drain region.

[0023] In an embodiment of the present invention, a high dielectric constant material is deposited on the substrate surface between the well region and the buffer region, including: using an atomic layer deposition process to deposit a high dielectric constant material on a portion of the surface of the well region and on the substrate surface between the well region and the buffer region to form a first dielectric layer with a high dielectric constant.

[0024] In an embodiment of the present invention, a low dielectric constant material is deposited on the surface of the buffer region and the drain region, including: using a plasma enhanced chemical vapor deposition process to deposit the low dielectric constant material on the surface of the buffer region, the surface of the drain region, the surface of the source region, and another part of the surface of the well region to form a second dielectric layer and a third dielectric layer with a low dielectric constant.

[0025] In the embodiment of the present invention, forming a gate on the surface of the first dielectric layer includes: depositing heavily doped polysilicon on the surface of the first dielectric layer, and etching to form a polysilicon gate, wherein the doping concentration of the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 .

[0026] In an embodiment of the present invention, the method further comprises: forming a plurality of grooves in the buffer zone; The plurality of trenches are filled with strained silicon material, wherein the strained silicon material is SiGe or SiC.

[0027] In an embodiment of the present invention, the method further includes: forming a transition region in the substrate between the well region and the buffer region, the transition region including a plurality of N-type doping regions and a plurality of P-type doping regions, the plurality of N-type doping regions and the plurality of P-type doping regions being arranged alternately with each other.

[0028] In an embodiment of the present invention, a transition region is formed in the substrate between the well region and the buffer region, including: Using high energy and low dose ion implantation, N-type ions are implanted into the corresponding N-type doped area in the substrate to form the N-type doped area below; Using high-energy, low-dose ion implantation, P-type ions are implanted into the corresponding P-type doped area in the substrate to form a P-type doped area below; Using low-energy, high-dose ion implantation, P-type ions are implanted into the corresponding P-type doped area on the substrate to form an upper P-type doped area; By adopting a low-energy, high-dose ion implantation method, N-type ions are implanted into the corresponding N-type doped area on the substrate to form an upper N-type doped area, thereby obtaining a transition area where the N-type doped area and the P-type doped area are spaced apart.

[0029] In an embodiment of the present invention, the method further includes: forming a well region, a buffer region, a source region and a drain region in the active silicon layer; etching the active silicon layer and the insulating layer to form a conductive through hole connected to the substrate silicon layer.

[0030] In an embodiment of the present invention, etching the active silicon layer and the insulating layer to form a conductive through hole connected to the substrate silicon layer includes: Etching the active silicon layer and the insulating layer, stopping the etching when the lower surface of the insulating layer is reached, and forming a deep through hole connected to the substrate silicon layer; The sidewalls of the deep through holes are filled with silicon dioxide or silicon nitride, and the inside of the deep through holes is filled with metal or doped silicon material to form conductive through holes.

[0031] The present invention also provides a chip, which includes the above-mentioned semiconductor device.

[0032] The present invention also provides an electronic device, which comprises the semiconductor device mentioned above.

[0033] The present invention sets a first dielectric layer of a high dielectric constant material on the surface of the substrate between the well region and the buffer region, and sets a second dielectric layer of a low dielectric constant material between the gate and the drain region. In the first aspect, since the material of the first dielectric layer is a high dielectric constant material, compared with the field oxygen dielectric layer of the conventional LDMOS structure, the first dielectric layer can be made very thin while maintaining the same capacitance. Since the first dielectric layer is very thin, when the same current is applied to the gate, it is easier to generate inversion electrons (inversion layer) in the substrate between the well region and the buffer region below the first dielectric layer, thereby forming an inversion channel. The inversion electron concentration of the inversion layer is much higher than the electron concentration of the drift region in the conventional structure, which can reduce the on-resistance. In the second aspect, a buffer region is set at the drain end, and the drain end current is buffered by the buffer region, so that the breakdown voltage of the drain end can be increased. In the third aspect, a second dielectric layer of a low dielectric constant material is added between the gate and the drain region. Compared with the field oxygen dielectric layer of the conventional LDMOS structure, the second dielectric layer of the low dielectric constant reduces the parasitic capacitance between the gate and the drain end (i.e., the gate-drain capacitance Cgd), and increases the withstand voltage characteristics of the gate and the drain end. Since the lower the gate-drain capacitance, the faster the device responds, the lower the gate-drain capacitance Cgd of the device, which helps the device be used in fields such as electricity, electric vehicles, rail transit, smart home appliances, communications, medical care, and radar.

[0034] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a schematic structural diagram of a semiconductor device provided in Embodiment 1 of the present invention; Figure 2 is a schematic structural diagram of a semiconductor device with a third dielectric layer provided in Embodiment 1 of the present invention; Figure 3 is a schematic structural diagram of a semiconductor device provided in Embodiment 2 of the present invention; Figure 3a It is a schematic structural diagram of a triangular groove of a buffer zone of a semiconductor device provided in Embodiment 2 of the present invention; Figure 3b is a schematic structural diagram of a strip-shaped groove of a buffer zone of a semiconductor device provided in Embodiment 2 of the present invention; Figure 4is a schematic structural diagram of a semiconductor device provided in Embodiment 3 of the present invention; Figure 5 is a schematic structural diagram of a semiconductor device provided by a fourth embodiment of the present invention; Figure 6 is a schematic structural diagram of a semiconductor device provided by Embodiment 5 of the present invention; Figure 7 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention; Figure 8 It is a schematic diagram of an existing conventional LDMOS structure.

[0036] Description of Reference Numerals 10-substrate, 11-substrate silicon layer, 12-insulating layer, 13-active silicon layer, 14-conductive via, 15-body region, 16-drift region, 17-shallow trench isolation region, 20-well region, 21-buffer region, 211-groove filled with strained silicon material, 22-source region, 23-drain region, 24-gate region, 25 - first dielectric layer, 26a - second dielectric layer, 26b - third dielectric layer, 27 - transition region. DETAILED DESCRIPTION

[0037] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0038] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0039] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected", "connected", "connected" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium, they can be the internal connection of two functional structural regions or the interaction relationship between two functional structural regions. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] As described in the background technology, the existing LDMOS device increases the breakdown voltage by increasing the thickness of the field oxide, but the thicker the field oxide, the greater the on-resistance, making it difficult to obtain a lower on-resistance at a higher breakdown voltage. Moreover, the thicker the field oxide, the greater the gate-drain parasitic capacitance, which is not conducive to the application of LDMOS in radio frequency communication devices.

[0041] Figure 8 It is an existing conventional LDMOS structure. Figure 8 As shown, in a conventional LDMOS structure, the source region 22 is on the surface of the body region 15, the drain region 23 is on the surface of the drift region 16, the body region 15 is connected to the drift region 16, and the gate 24 is above the body region 15 and the drift region 16. The shallow trench isolation region 17 (STI) below the gate 24 serves as a field oxide dielectric layer, and the material of the STI is usually silicon dioxide (SiO2). The STI is located in the drift region 16, and the surface electric field is reduced by the STI to increase the breakdown voltage. In order to increase the breakdown voltage, the thickness of the STI needs to be increased. However, when the device is working, the current flows from the source end along the lower surface of the STI to the drain. The thicker the STI is, the longer the outflow path of the current from the source to the drain is, and the larger the on-resistance is, and it is difficult to obtain a lower on-resistance at a higher breakdown voltage. Moreover, the gate 24 and the drain region 23 are separated by the STI. The thicker the STI is, the larger the gate-drain parasitic capacitance (Cgd), which is not conducive to the application of LDMOS in radio frequency communication devices.

[0042] In view of the above problems, an embodiment of the present invention provides a semiconductor device, which includes a substrate 10, a well region 20, a buffer region 21, a source region 22, a drain region 23, a dielectric layer and a gate 24. The well region 20, the buffer region 21, the source region 22 and the drain region 23 are located on the substrate 10, the well region 20 is connected to the source region 22, and the buffer region 21 is connected to the drain region 23. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the substrate 10 between the well region 20 and the buffer region 21, the gate 24 is located on the surface of the first dielectric layer 25, and the second dielectric layer 26a is located between the gate 24 and the drain region 23. In the first aspect, since the material of the first dielectric layer is a high dielectric constant material, compared with the field oxide dielectric layer of the conventional LDMOS structure, the first dielectric layer of the present invention can be made very thin while maintaining the same capacitance. Since the first dielectric layer is very thin, when the same current is applied to the gate, it is easier to generate inversion electrons (inversion layer) in the substrate between the well region and the buffer region below the first dielectric layer, thereby forming an inversion channel. The inversion electron concentration of the inversion layer is much higher than the electron concentration in the drift region in the conventional structure, which can reduce the on-resistance. Secondly, a buffer is designed at the drain end, and the drain current is buffered by the buffer, which can increase the breakdown voltage of the drain end. Thirdly, a second dielectric layer of low dielectric constant material is added between the gate and the drain region. Compared with the field oxygen dielectric layer of the conventional LDMOS structure, the second dielectric layer of low dielectric constant reduces the parasitic capacitance between the gate and the drain (i.e., the gate-drain capacitance Cgd), and increases the voltage resistance characteristics of the gate and the drain. The reduction of the gate-drain capacitance Cgd of the device is helpful for the application of the device in radio frequency communication devices, because the lower the gate-drain capacitance, the faster the reaction speed.

[0043] Embodiment 1 Figure 1 Schematic diagram of the structure of a semiconductor device provided by Embodiment 1 of the present invention. Figure 1As shown, the semiconductor device of the first embodiment includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22 and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and extends to the surface of the P-type well region 20. The gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23, one end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. When a current is applied to the gate 24, inverted electrons (inverted to N-type conductivity type) are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25 of the high dielectric constant material extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 close to the first dielectric layer 25 will also be inverted to form an inversion channel.

[0044] In this embodiment, the first dielectric layer uses a high dielectric constant material. High dielectric constant materials are usually called high-k materials, and their dielectric constants (k values) are usually much higher than the dielectric constant of 3.9 of traditional SiO2 materials. The high dielectric constant material of the first dielectric layer refers to a material with a k value greater than 3.9, especially a material with a dielectric constant much greater than 3.9, such as a material with a dielectric constant k greater than 20, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), etc. The dielectric constant k of hafnium oxide (HfO2) is approximately 25. The second dielectric layer uses a low dielectric constant material, and the dielectric constant k value of the low dielectric constant material is usually less than 2.8 (k≤2.8), such as carbon-doped silicon oxide.

[0045] The semiconductor device of this embodiment does not have a field oxide dielectric layer. Instead, a relatively thin high dielectric constant dielectric layer is grown on the surface of the P-type well region 20 and on the surface of the substrate 10 between the P-type well region 20 and the N-type buffer region 21. When current is applied to the gate end, the silicon in the substrate 10 below the high dielectric constant dielectric layer is more easily inverted to form an inversion channel.

[0046] In principle, the calculation formula of capacitance C is C=εS / 4πkd, where ε is a constant, S is the area facing the capacitor plates, d is the distance between the capacitor plates, and k is the electrostatic force constant. The ε of high-k dielectric material (high dielectric constant dielectric layer) is larger, and the high-k dielectric layer can be made thinner while maintaining the same capacitance. The high-k dielectric layer under the gate 24 is thinner (the thickness of the traditional STI is 200-800nm, while the thickness of the high-k dielectric layer in the present invention is 20-80Å, and the thickness of the low-k dielectric layer is 100-800Å), which makes it easier to generate inversion electrons in the substrate 10 between the P-type well region 20 and the N-type buffer region 21, forming an inversion channel connecting the P-type well region 20 and the N-type buffer region 21, and transporting electrons from the source end to the drain end through the inversion channel. The electron concentration of the inversion channel is much greater than the electron concentration of the conventional drift region 16, which can greatly reduce the on-resistance (Ron) of the device. Considering the withstand voltage characteristics of the device, an N-type buffer 21 is designed at the drain end. The N-type buffer 21 and the drain region 23 constitute the entire drain end structure to increase the breakdown voltage (BV). Furthermore, a low-k dielectric layer (a second dielectric layer 26a of a low dielectric constant material) is added between the gate 24 and the drain region 23. The ε of the low-k dielectric layer is small, and the parasitic capacitance between the gate 24 and the drain region 23 is small, which reduces the gate-drain capacitance Cgd (smaller than the gate-drain capacitance Cgd of the conventional locos / STI structure), while increasing the withstand voltage characteristics of the gate 24 and the drain end. The reduction of the gate-drain capacitance Cgd is conducive to the application of the device in radio frequency communication devices.

[0047] like Figure 2 As shown, in this embodiment, the dielectric layer also includes a third dielectric layer 26b of a low dielectric constant material, the third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22, one end of the third dielectric layer 26b is connected to the gate 24 and the other end of the first dielectric layer 25, and the other end of the third dielectric layer 26b is connected to the source region 22. The third dielectric layer 26b is a low-k dielectric layer, and the dielectric constant k of the low-k material is ≤2.8, such as carbon-doped silicon oxide. Since the ε of the low-k dielectric layer is small, the parasitic capacitance between the gate 24 and the source region 22 is small, and the gate-source capacitance Cgs of the device can be reduced.

[0048] Embodiment 2 Figure 3 Schematic diagram of the structure of the semiconductor device provided by the second embodiment of the present invention. Figure 3As shown, the semiconductor device of the second embodiment includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22 and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and extends to the surface of the P-type well region 20. The gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23, one end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of grooves 211 filled with strained silicon material, and the plurality of grooves 211 filled with strained silicon material are arranged at intervals in the buffer region 21. When a current is applied to the gate 24, inversion electrons are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 under the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25 of high dielectric constant material extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 close to the first dielectric layer 25 will also be inverted to form an inversion channel.

[0049] The difference between the second embodiment and the first embodiment is that there are multiple trenches 211 filled with strained silicon material in the buffer zone 21. Specifically, SiGe can be filled in all the trenches, or SiC can be filled in all the trenches.

[0050] In order to further improve the voltage resistance of the device, grooves of different shapes or the same shape are designed in the buffer zone 21, and strained silicon materials such as SiGe / SiC are filled in the grooves. The strained silicon material can be of the same conductivity type (N type) as the N-type buffer zone 21, or it can be of a different conductivity type (P type) than the N-type buffer zone 21. If the buffer zone 21 is of electronic conductivity type (N type), SiGe can be used to fill the grooves, and the grooves filled with SiGe help to improve the mobility of the N-type electron channel. Since the lattice coefficient of the SiGe material is different from that of conventional silicon-based materials, the SiGe lattice exerts tensile stress on the surrounding silicon lattice, the lattice structure changes, and electrons are more easily transported through the lattice, thereby improving the mobility of carriers in the buffer zone 21, thereby improving the voltage resistance of the device. Similarly, if the buffer zone 21 is of hole conductivity type (P type), SiCe can be used to fill the grooves.

[0051] In other embodiments, some of the multiple trenches may be filled with SiGe, and another part of the multiple trenches may be filled with SiC. The multiple trenches filled with SiGe and the multiple trenches filled with SiC are arranged alternately to further improve the mobility of carriers in the buffer zone.

[0052] In a specific embodiment, the multiple grooves filled with strained silicon material in the buffer zone 21 can be designed to have the same shape or different shapes. The multiple grooves of the same shape in the buffer zone 21 can be set to be rectangular, hexagonal, strip or triangular. Figure 3 As shown, the multiple grooves of the same shape in the buffer zone 21 are rectangular, and the multiple rectangular grooves are arranged in an array. Figure 3a As shown, the multiple grooves of the same shape in the buffer zone 21 are triangular, and the multiple triangular grooves are arranged in parallel. Figure 3b As shown, the plurality of grooves of the same shape in the buffer zone 21 are strip-shaped, and the strip-shaped grooves filled with SiGe and the strip-shaped grooves filled with SiC are arranged alternately.

[0053] In addition, the grooves filled with strained silicon material in the buffer zone may also be in different shapes, and a plurality of grooves in different shapes may be arranged in any combination of rectangles, hexagons, strips, and triangles.

[0054] Embodiment 3 Figure 4 Schematic diagram of the structure of the semiconductor device provided by the third embodiment of the present invention. Figure 4As shown, the semiconductor device of the third embodiment includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a transition region 27, a source region 22, a drain region 23, a dielectric layer and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22 and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23, one end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of grooves filled with strained silicon material, and the plurality of grooves filled with strained silicon material are arranged at intervals in the buffer region 21. The transition region 27 is located in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21. When a current is applied to the gate 24, inversion electrons are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25 of high dielectric constant material extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 close to the first dielectric layer 25 will also be inverted to form an inversion channel.

[0055] The buffer zone 21 has multiple grooves 211 filled with strained silicon material. Specifically, SiGe can be filled in all the multiple grooves, or SiC can be filled in all the multiple grooves. SiGe can also be filled in some of the multiple grooves, and SiC can be filled in the other part of the multiple grooves. The multiple grooves filled with SiGe and the multiple grooves filled with SiC are arranged in an interlaced manner, which further improves the mobility of carriers in the buffer zone 21.

[0056] The multiple grooves filled with strained silicon material in the buffer zone 21 can be designed to be the same shape or different shapes. The multiple grooves of the same shape in the buffer zone 21 can be set to be rectangular, hexagonal, strip or triangular. The multiple grooves of the same shape in the buffer zone 21 are arranged in an array. The multiple grooves of different shapes in the buffer zone 21 can be set to any combination of rectangles, hexagons, strips, and triangles.

[0057] The difference between the third embodiment and the second embodiment is that there is a transition region 27 in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21. The transition region 27 includes a plurality of N-type doping regions and a plurality of P-type doping regions, and the plurality of N-type doping regions and the plurality of P-type doping regions are arranged alternately. The plurality of N-type doping regions and the plurality of P-type doping regions of the transition region 27 are arranged in an array. Each N-type doping region and the P-type doping region are stacked in the form of building blocks.

[0058] like Figure 4 As shown, multiple N-type doped regions and P-type doped regions of the transition region 27 are alternately distributed in a "chessboard" pattern. In the transition region 27 with a "chessboard" distribution, the P-type doped region will invert to form a channel, and the N-type doped region can conduct electrons. At the same time, the N-type doped region effectively depletes the adjacent P-type doped region, and the N-type doped region and the adjacent P-type doped region form a depletion layer. Since the P-type doped region is surrounded by the N-type doped region in all directions, the P-type doped region can be depleted in all directions, further improving the withstand voltage characteristics and realizing a high withstand voltage device.

[0059] Specifically, the doping concentrations of the multiple N-type doping regions and the multiple P-type doping regions in the transition region 27 are different, and the doping concentrations of the N-type doping regions and the P-type doping regions decrease in sequence from near to far relative to the first dielectric layer 25. The doping concentrations of the N-type doping regions and the P-type doping regions in the transition region 27 close to the first dielectric layer 25 are greater than the doping concentrations of the N-type doping regions and the P-type doping regions in the transition region 27 far from the first dielectric layer 25.

[0060] Embodiment 4 Figure 5 Schematic diagram of the structure of the semiconductor device provided by the fourth embodiment of the present invention. Figure 5As shown, the semiconductor device of the fourth embodiment includes a substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer and a gate 24. The substrate 10 is a SOI (Silicon On Insulator) substrate 10, and the SOI substrate 10 includes, from bottom to top, a substrate silicon layer 11, an insulating layer 12 and a P-type active silicon layer 13. The P-type well region 20, the N-type buffer region 21, the source region 22 and the drain region 23 are located in the P-type active silicon layer 13, the P-type well region 20 is connected to the source region 22, the N-type buffer region 21 is connected to the drain region 23, and the P-type well region 20 and the N-type buffer region 21 are separated by an active silicon material. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23, one end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of grooves filled with strained silicon material, and the plurality of grooves filled with strained silicon material are arranged at intervals in the buffer region 21. When current is applied to the gate 24, inversion electrons are generated in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21 below the first dielectric layer 25 to form an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25 of high dielectric constant material extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 close to the first dielectric layer 25 will also be inverted to form an inversion channel.

[0061] The buffer zone 21 has multiple grooves 211 filled with strained silicon material. Specifically, SiGe can be filled in all the multiple grooves, or SiC can be filled in all the multiple grooves. SiGe can also be filled in some of the multiple grooves, and SiC can be filled in the other part of the multiple grooves. The multiple grooves filled with SiGe and the multiple grooves filled with SiC are arranged in an interlaced manner, which further improves the mobility of carriers in the buffer zone 21.

[0062] The multiple grooves filled with strained silicon material in the buffer zone 21 can be designed to be the same shape or different shapes. The multiple grooves of the same shape in the buffer zone 21 can be set to be rectangular, hexagonal, strip or triangular. The multiple grooves of the same shape in the buffer zone 21 are arranged in an array. The multiple grooves of different shapes in the buffer zone 21 can be set to any combination of rectangles, hexagons, strips, and triangles.

[0063] The difference between the fourth embodiment and the second embodiment is that conductive vias 14 are provided at both ends of the device, and the substrate silicon layer 11 is grounded through the conductive vias 14 provided at both ends. At this time, the substrate silicon layer 11 and the insulating layer 12 act as lower field plates, which can reduce the electric field on the surface of the active silicon layer 13, making its electric field distribution more uniform. The conductive via 14 at one end of the substrate silicon layer 11 penetrates the well region 20, the active silicon layer 13 and the insulating layer 12, and the conductive via 14 at the other end of the substrate silicon layer 11 penetrates the buffer region 21, the active silicon layer 13 and the insulating layer 12. The conductive via 14 is filled with metal material or conductive doped silicon material. The inner wall of the conductive via 14 is filled with insulating material.

[0064] Embodiment 5 Figure 6 Schematic diagram of the structure of the semiconductor device provided by the fifth embodiment of the present invention. Figure 6 As shown, the semiconductor device of the fifth embodiment includes a substrate 10, a P-type well region 20, an N-type buffer region 21, a transition region 27, a source region 22, a drain region 23, a dielectric layer and a gate 24. The substrate 10 is a SOI (Silicon On Insulator) substrate 10, and the SOI substrate 10 includes, from bottom to top, a substrate silicon layer 11, an insulating layer 12 and a P-type active silicon layer 13. The P-type well region 20, the N-type buffer region 21, the source region 22 and the drain region 23 are located in the P-type active silicon layer 13, the P-type well region 20 is connected to the source region 22, the N-type buffer region 21 is connected to the drain region 23, and the P-type well region 20 and the N-type buffer region 21 are separated by an active silicon material. The dielectric layer includes a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23, one end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of grooves filled with strained silicon material, and the plurality of grooves filled with strained silicon material are arranged at intervals in the buffer region 21. The transition region 27 is located in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21. When current is applied to the gate 24, inversion electrons are generated in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21 below the first dielectric layer 25 to form an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25 of high dielectric constant material extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 close to the first dielectric layer 25 will also be inverted to form an inversion channel.

[0065] The buffer zone 21 has multiple grooves 211 filled with strained silicon material. Specifically, SiGe can be filled in all the multiple grooves, or SiC can be filled in all the multiple grooves. SiGe can also be filled in some of the multiple grooves, and SiC can be filled in the other part of the multiple grooves. The multiple grooves filled with SiGe and the multiple grooves filled with SiC are arranged in an interlaced manner, which further improves the mobility of carriers in the buffer zone 21.

[0066] The multiple grooves filled with strained silicon material in the buffer zone 21 can be designed to be the same shape or different shapes. The multiple grooves of the same shape in the buffer zone 21 can be set to be rectangular, hexagonal, strip or triangular. The multiple grooves of the same shape in the buffer zone 21 are arranged in an array. The multiple grooves of different shapes in the buffer zone 21 can be set to any combination of rectangles, hexagons, strips, and triangles.

[0067] The substrate silicon layer 11 is grounded through conductive vias 14 provided at both ends. At this time, the substrate silicon layer 11 and the insulating layer 12 act as lower field plates, which can reduce the electric field on the surface of the active silicon layer 13 and make its electric field distribution more uniform. The conductive via 14 at one end of the substrate silicon layer 11 penetrates the well region 20, the active silicon layer 13 and the insulating layer 12, and the conductive via 14 at the other end of the substrate silicon layer 11 penetrates the buffer region 21, the active silicon layer 13 and the insulating layer 12. The bottom of the conductive via 14 contacts the upper surface of the substrate silicon layer 11. The conductive via 14 is filled with metal material or conductive doped silicon material. The inner wall of the conductive via 14 is filled with insulating material.

[0068] The difference between the fifth embodiment and the fourth embodiment is that there is a transition region 27 in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21. The transition region 27 includes a plurality of N-type doping regions and a plurality of P-type doping regions, and the plurality of N-type doping regions and the plurality of P-type doping regions are arranged alternately. The plurality of N-type doping regions and the plurality of P-type doping regions of the transition region 27 are arranged in an array.

[0069] The multiple N-type doped regions and P-type doped regions of the transition region 27 are alternately distributed in a "chessboard" pattern. In the transition region 27 with a "chessboard" distribution, the P-type doped region will invert to form a channel, and the N-type doped region can conduct electrons. At the same time, the N-type doped region effectively depletes the adjacent P-type doped region, and the N-type doped region and the adjacent P-type doped region form a depletion layer. Since the P-type doped region is surrounded by the N-type doped region in all directions, the P-type doped region can be depleted in all directions, further improving the withstand voltage characteristics and realizing a high withstand voltage device.

[0070] The doping concentrations of the multiple N-type doping regions and the multiple P-type doping regions in the transition region 27 are different, and the doping concentrations of the N-type doping regions and the P-type doping regions decrease in sequence from near to far relative to the first dielectric layer 25. The doping concentrations of the N-type doping regions and the P-type doping regions in the transition region 27 close to the first dielectric layer 25 are greater than the doping concentrations of the N-type doping regions and the P-type doping regions in the transition region 27 far from the first dielectric layer 25.

[0071] It should be noted that the typical structure using the concept of the present invention is the LDMOS device structure, and the concept of the present invention can also be applied to other power semiconductor devices, such as VDMOS devices and SJ-MOS devices.

[0072] The present invention also provides a method for manufacturing the semiconductor device. Figure 7 As shown, the method for manufacturing a semiconductor device provided by an embodiment of the present invention comprises the following steps: S701, forming a well region and a buffer region separated from the well region in a substrate; S702, forming a source region on the surface of the well region, and forming a drain region on the surface of the buffer region; S703, depositing a high dielectric constant material on the surface of the substrate between the well region and the buffer region to form a first dielectric layer extending to the surface of the well region; S704, depositing a low dielectric constant material on the surfaces of the buffer region and the drain region to form a second dielectric layer, so that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region; S705 , forming a gate on the surface of the first dielectric layer so that the gate is connected to one end of the second dielectric layer.

[0073] In the above step S701, a P-type substrate is selected, and photolithography and development processing are used to form graphic windows of the well area and the buffer area on the surface of the P-type substrate. P-type ions and N-type ions are respectively injected into the two graphic windows to form a P-type well area and an N-type buffer area, wherein the P-type well area is separated from the N-type buffer area.

[0074] In the above step S702, photolithography and development processing are used to form a source region graphic window and a drain region graphic window on the surface of the P-type well region and the surface of the N-type buffer region, respectively, and N-type ions are injected into the source region graphic window and the drain region graphic window to form a source region connected to the P-type well region and a drain region connected to the N-type buffer region and the drain region.

[0075] In the above step S703, an atomic layer deposition (ALD) process is used to deposit a high dielectric constant material on a portion of the surface of the P-type well region and the surface of the substrate between the P-type well region and the N-type buffer region to form a first dielectric layer with a high dielectric constant. The high dielectric constant material has a dielectric constant k>3.9, such as aluminum oxide (Al2O3) and hafnium oxide (HfO2).

[0076] In the above step S704, a plasma enhanced chemical vapor deposition (PECVD) process is used to deposit a low dielectric constant material on the surface of the N-type buffer region, the surface of the drain region, the surface of the source region, and another part of the surface of the P-type well region to form a second dielectric layer and a third dielectric layer with a low dielectric constant. The low dielectric constant material has a dielectric constant k≤2.8, such as carbon-doped silicon oxide.

[0077] In the above step S705, heavily doped polysilicon is deposited on the surface of the first dielectric layer and etched to form a polysilicon gate. The doping concentration of the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 .

[0078] In a specific embodiment, after forming a P-type well region and an N-type buffer region, a plurality of grooves are formed in the N-type buffer region, and strained silicon materials such as SiGe or SiC are filled in the plurality of grooves. The strained silicon material may be of the same conductivity type (N-type) as the N-type buffer region, or may be of a different conductivity type (P-type) than the N-type buffer region. If the buffer region is of electronic conductivity type (N-type), SiGe may be used to fill the grooves, and the grooves filled with SiGe help to improve the mobility of the N-type electron channel. Since the lattice coefficient of the SiGe material is different from that of conventional silicon-based materials, the SiGe lattice exerts tensile stress on the surrounding silicon lattices, and the lattice structure changes, making it easier for electrons to be transported through the lattice, thereby improving the mobility of carriers in the buffer region, thereby improving the voltage resistance of the device. Similarly, if the buffer region is of hole conductivity type (P-type), SiCe may be used to fill the grooves.

[0079] In other embodiments, SiGe may be filled in a part of the multiple grooves, and SiC may be filled in another part of the grooves. The multiple grooves filled with SiGe and the multiple grooves filled with SiC are arranged in an interlaced manner to further improve the mobility of carriers in the buffer zone. In addition, the multiple grooves filled with strained silicon material in the buffer zone can be designed to be the same shape or different shapes. The multiple grooves of the same shape in the buffer zone can be set to rectangles, hexagons, strips or triangles. The multiple grooves filled with strained silicon material in the buffer zone can also be different shapes, and multiple grooves of different shapes can be set to any combination of rectangles, hexagons, strips, and triangles.

[0080] In a specific embodiment, after forming the P-type well region and the N-type buffer region, a transition region is formed in the substrate between the P-type well region and the N-type buffer region. The transition region includes multiple N-type doping regions and multiple P-type doping regions, and the multiple N-type doping regions and the multiple P-type doping regions are arranged alternately. The multiple N-type doping regions and the P-type doping regions in the transition region are distributed alternately in a "chessboard" pattern. Each N-type doping region and the P-type doping region are stacked in the form of building blocks. In the process of making the transition region, the substrate between the P-type well region and the N-type buffer region is firstly subjected to photolithography and development treatment in this way to form multiple small-sized building block-type doping regions. For the building block-type N-type doping region and P-type doping region, a small-sized photolithography correction process is used for exposure, and at the same time, based on algorithm correction, optical auxiliary exposure holes are distributed around the small-sized region, and the corners or angles of the small-sized doping region morphology are repaired to obtain precisely spaced N-type doping regions and P-type doping regions. Then, high-energy, low-dose ion implantation is used to implant N-type ions into the corresponding N-type doped area in the middle of the substrate to form the N-type doped area below. High-energy, low-dose ion implantation (implantation energy of 500Kev~1000Kev, ion concentration of 1×10 12 cm -3 ~5×10 12 cm -3 ), P-type ions are implanted into the corresponding P-type doped area in the middle of the substrate to form a P-type doped area below. Low-energy, high-dose ion implantation is used (implantation energy is 100Kev~300Kev, ion concentration is 1×10 13 cm -3 ~4×10 13 cm -3 ), P-type ions are implanted into the corresponding P-type doped area on the upper part of the substrate to form the upper P-type doped area; low-energy, high-dose ion implantation is used to implant N-type ions into the corresponding N-type doped area on the upper part of the substrate to form the upper N-type doped area. Through the above methods, a transition zone with an interval distribution of N-type doped areas and P-type doped areas is formed.

[0081] In another embodiment, an SOI substrate is used, and the SOI substrate includes a substrate silicon layer, an insulating layer and a P-type active silicon layer from bottom to top. After forming a P-type well region, an N-type buffer region, a source region and a drain region in the P-type active silicon layer, the active silicon layer and the insulating layer are etched to form a conductive through hole connected to the substrate silicon layer. The substrate silicon layer is grounded through the conductive through hole and serves as a lower field plate. Specifically, the active silicon layer and the insulating layer are etched, and the etching is stopped when the lower surface of the insulating layer is etched to form a deep through hole connected to the substrate silicon layer, and silicon dioxide or silicon nitride is filled on the side wall of the deep through hole, and the excess silicon dioxide or silicon nitride is etched away, and metal or highly conductive doped silicon material is filled in the deep through hole to form a conductive through hole. Alternatively, a through deep through hole is formed at both ends of the substrate, and silicon dioxide or silicon nitride is first filled around the deep through hole, and then the silicon dioxide or silicon nitride is etched away from the back, and metal or highly conductive doped silicon material is filled in the deep through hole.

[0082] An embodiment of the present invention further provides a chip, which includes the semiconductor device of the above embodiment.

[0083] An embodiment of the present invention further provides an electronic device, which includes the semiconductor device of the above embodiment.

[0084] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer and a gate, wherein the well region, the buffer region, the source region and the drain region are located on the substrate, the source region is formed on the surface of the well region, the drain region is formed on the surface of the buffer region, and the well region and the buffer region are separated by a substrate material; The dielectric layer comprises a first dielectric layer made of a high dielectric constant material and a second dielectric layer made of a low dielectric constant material, wherein the dielectric constant k of the material of the first dielectric layer is greater than 3.9, and the dielectric constant k of the material of the second dielectric layer is less than or equal to 2.8; The first dielectric layer is located on the surface of the substrate between the well region and the buffer region, and extends to the surface of the well region; The gate is located on the surface of the first dielectric layer; The second dielectric layer is located on the surfaces of the buffer region and the drain region, one end of the second dielectric layer is connected to the gate and one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region.

2. The semiconductor device according to claim 1, wherein: The dielectric layer further comprises a third dielectric layer made of a low dielectric constant material, wherein the dielectric constant of the material of the third dielectric layer is k≤2.8; The third dielectric layer is located on the surfaces of the well region and the source region, one end of the third dielectric layer is connected to the gate and the other end of the first dielectric layer, and the other end of the third dielectric layer is connected to the source region.

3. The semiconductor device according to claim 1, wherein: The buffer zone includes a plurality of grooves filled with strained silicon material, and the plurality of grooves filled with strained silicon material are arranged at intervals in the buffer zone.

4. The semiconductor device according to claim 3, characterized in that The strained silicon materials filled in the plurality of trenches are all SiGe; or, the strained silicon materials filled in the plurality of trenches are all SiC.

5. The semiconductor device according to claim 3, characterized in that The strained silicon material filled in a portion of the plurality of trenches is SiGe, and the strained silicon material filled in another portion of the plurality of trenches is SiC.

6. The semiconductor device according to claim 5, characterized in that A plurality of trenches filled with SiGe and a plurality of trenches filled with SiC are arranged in an alternating manner.

7. The semiconductor device according to claim 3, characterized in that The groove is in the shape of a rectangle, a hexagon, a strip or a triangle.

8. The semiconductor device according to claim 1, wherein: The high dielectric constant material of the first dielectric layer is aluminum oxide or hafnium oxide, and the low dielectric constant material of the second dielectric layer is carbon-doped silicon oxide.

9. The semiconductor device according to claim 1, wherein: Also includes: A transition region is located in the substrate between the well region and the buffer region.

10. The semiconductor device according to claim 9, characterized in that The transition region includes a plurality of N-type doping regions and a plurality of P-type doping regions, and the plurality of N-type doping regions and the plurality of P-type doping regions are arranged alternately.

11. The semiconductor device according to claim 10, characterized in that The multiple N-type doping regions and the multiple P-type doping regions in the transition region are arranged in an array.

12. The semiconductor device according to claim 10, characterized in that The multiple N-type doping regions and the multiple P-type doping regions in the transition region have different doping concentrations, and the doping concentrations of the N-type doping regions and the P-type doping regions decrease in sequence from near to far relative to the first dielectric layer.

13. The semiconductor device according to claim 1, wherein: The substrate is an SOI substrate, which includes, from bottom to top, a substrate silicon layer, an insulating layer and an active silicon layer; The well region, buffer region, source region and drain region are formed in the active silicon layer.

14. The semiconductor device according to claim 13, characterized in that The substrate silicon layer is grounded through conductive vias arranged at both ends.

15. The semiconductor device according to claim 14, characterized in that The conductive through hole at one end of the substrate silicon layer penetrates the well region, the active silicon layer and the insulating layer; The conductive through hole at the other end of the substrate silicon layer penetrates the buffer zone, the active silicon layer and the insulating layer.

16. The semiconductor device according to claim 14, characterized in that The inner wall of the conductive through hole is filled with insulating material; The conductive through hole is filled with metal material or conductive doped silicon material.

17. The semiconductor device according to claim 2, characterized in that The low dielectric constant material of the third dielectric layer is carbon-doped silicon oxide.

18. A method for manufacturing a semiconductor device, characterized in that: include: forming a well region and a buffer region separated from the well region in the substrate; forming a source region on the surface of the well region and forming a drain region on the surface of the buffer region; Depositing a high dielectric constant material on the surface of the substrate between the well region and the buffer region to form a first dielectric layer extending to the surface of the well region, wherein the dielectric constant k of the high dielectric constant material is greater than 3.9; Depositing a low dielectric constant material on the surface of the buffer region and the drain region to form a second dielectric layer, so that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region, and the dielectric constant k of the low dielectric constant material is less than or equal to 2.8; A gate is formed on the surface of the first dielectric layer so that the gate is connected to one end of the second dielectric layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: A well region and a buffer region separated from the well region are formed in the substrate, including: A P-type substrate is selected, and graphic windows of a well region and a buffer region are formed on the surface of the P-type substrate. P-type ions and N-type ions are respectively injected into the two graphic windows to form a P-type well region and an N-type buffer region.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: A source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer region, including: A source region pattern window and a drain region pattern window are formed on the surface of the P-type well region and the surface of the N-type buffer region respectively, and N-type ions are injected into the source region pattern window and the drain region pattern window to form a source region and a drain region.

21. The method for manufacturing a semiconductor device according to claim 18, wherein: A high dielectric constant material is deposited on the substrate surface between the well region and the buffer region, including: Atomic layer deposition technology is adopted to deposit high dielectric constant material on a part of the surface of the well region and on the surface of the substrate between the well region and the buffer region to form a first dielectric layer with a high dielectric constant.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: Depositing low dielectric constant materials on the surface of the buffer region and the drain region includes: A plasma enhanced chemical vapor deposition process is used to deposit low dielectric constant materials on the surface of the buffer region, the surface of the drain region, the surface of the source region and another part of the surface of the well region to form a second dielectric layer and a third dielectric layer with low dielectric constants.

23. The method for manufacturing a semiconductor device according to claim 18, wherein: A gate is formed on the surface of the first dielectric layer, comprising: A heavily doped polysilicon is deposited on the surface of the first dielectric layer and etched to form a polysilicon gate. The doping concentration of the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 .

24. The method for manufacturing a semiconductor device according to claim 18, wherein: The method further comprises: forming a plurality of grooves within the buffer zone; The plurality of trenches are filled with strained silicon material, wherein the strained silicon material is SiGe or SiC.

25. The method for manufacturing a semiconductor device according to claim 18, wherein: The method further comprises: A transition region is formed in the substrate between the well region and the buffer region. The transition region includes a plurality of N-type doping regions and a plurality of P-type doping regions. The plurality of N-type doping regions and the plurality of P-type doping regions are arranged alternately.

26. The method for manufacturing a semiconductor device according to claim 25, wherein: A transition region is formed in the substrate between the well region and the buffer region, including: Using high energy and low dose ion implantation, N-type ions are implanted into the corresponding N-type doped area in the substrate to form the N-type doped area below; Using high-energy, low-dose ion implantation, P-type ions are implanted into the corresponding P-type doped area in the substrate to form a P-type doped area below; Using low-energy, high-dose ion implantation, P-type ions are implanted into the corresponding P-type doped area on the substrate to form an upper P-type doped area; Using a low-energy, high-dose ion implantation method, N-type ions are implanted into the corresponding N-type doped area on the substrate to form an upper N-type doped area, thereby obtaining a transition area where the N-type doped area and the P-type doped area are spaced apart; Among them, the high-energy, low-dose ion implantation method uses an implantation energy of 500Kev~1000Kev and an ion concentration of 1×10 12 cm -3 ~5×10 12 cm -3 ; The low-energy, high-dose ion implantation method uses an implantation energy of 100Kev~300Kev and an ion concentration of 1×10 13 cm -3 ~4×10 13 cm -3 .

27. The method for manufacturing a semiconductor device according to claim 18, wherein: The substrate is an SOI substrate, which includes, from bottom to top, a substrate silicon layer, an insulating layer and an active silicon layer.

28. The method for manufacturing a semiconductor device according to claim 27, wherein: The method further comprises: forming a well region, a buffer region, a source region and a drain region in the active silicon layer; The active silicon layer and the insulating layer are etched to form a conductive through hole connected to the substrate silicon layer.

29. The method for manufacturing a semiconductor device according to claim 28, wherein: The active silicon layer and the insulating layer are etched to form a conductive through hole connected to the substrate silicon layer, including: Etching the active silicon layer and the insulating layer, stopping the etching when the lower surface of the insulating layer is reached, and forming a deep through hole connected to the substrate silicon layer; The sidewalls of the deep through holes are filled with silicon dioxide or silicon nitride, and the inside of the deep through holes is filled with metal or doped silicon material to form conductive through holes.

30. A chip, characterized in that: The chip comprises the semiconductor device according to any one of claims 1 to 17.

31. An electronic device, characterized in that: The electronic device comprises the semiconductor device according to any one of claims 1 to 17.

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