Semiconductor device and manufacturing method, chip, electronic device

Abstract

The application relates to the field of semiconductors, and provides a semiconductor device, a manufacturing method, a chip and an electronic device. The semiconductor device comprises a substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer and a gate. The well region, the buffer region, the source region and the drain region are located on the substrate. The source region is formed on the surface of the well region, and the drain region is formed on the surface of the buffer region. The dielectric layer comprises a first dielectric layer of high dielectric constant material and a second dielectric layer of low dielectric constant material. The first dielectric layer is located on the surface of the substrate between the well region and the buffer region and extends to the surface of the well region. The gate is located on the surface of the first dielectric layer, and the second dielectric layer is located on the surfaces of the buffer region and the drain region. The first dielectric layer of high dielectric constant material is used to form an inverse channel in the substrate between the well region and the buffer region, so as to reduce the on-resistance. The breakdown voltage of the drain end is improved through the buffer region, the gate-drain capacitance is reduced through the second dielectric layer of low dielectric constant material, and the voltage resistance characteristic of the gate and the drain end is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a semiconductor device and its manufacturing method, a chip, and an electronic device. Background Technology

[0002] Power semiconductor devices possess advantages such as high power, high gain, good linearity, and high breakdown voltage, making them one of the core components of power integrated circuits. Power semiconductor devices include: Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS), Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS), and Super Junction MOSFET (SJ-MOS), among others. LDMOS devices are widely used in power, rail transportation, electric vehicles, smart home appliances, medical devices, and radar. The performance and reliability of LDMOS devices determine their effectiveness in power and related industrial applications, while their efficiency and linearity directly determine the performance of wireless communication systems. The high breakdown voltage of LDMOS devices allows them to withstand high VSWRs even under mismatch conditions. LDMOS devices are widely used in power management, isolated signal chains, switch control, driver, and wireless communication chips. They are commonly used to fabricate switching transistors and driver transistors in power management, isolated signal chains, switch control, and driver chips, as well as RF power amplifiers in communication base stations. In power, isolation, switch control, driver, communication, and related chips, LDMOS devices are required to meet the complex environmental application requirements of high output power, high breakdown voltage, large drive current, low on-resistance, low parasitic capacitance, and long reliability and lifespan.

[0003] The breakdown voltage (BV) and on-resistance (Ron) of LDMOSFET devices are important specifications. Practical applications require LDMOSFET devices with high breakdown voltage and low on-resistance. In existing technologies, the source region of an LDMOSFET device is located on the surface of the body region, the drain region is located on the surface of the drift region, and the field oxide is located below the gate. The field plate above the field oxide modulates and reduces the surface electric field of the device, thereby increasing the breakdown voltage. Typically, silicon local oxide isolation (LOCOS) and shallow trench isolation (STI) techniques are used to fabricate the field oxide isolation structure. To improve the breakdown voltage, the thickness of the STI or LOCOS needs to be increased. During device operation, current flows from the source along the lower surface of the field oxide to the drain. The thicker the field oxide, the longer the current path from the source to the drain, resulting in a larger on-resistance, making it difficult to achieve a low on-resistance at higher breakdown voltages. Furthermore, the gate and drain regions are separated by field oxygen. The thicker the field oxygen, the larger the gate-drain parasitic capacitance and related reliability issues, which are detrimental to the application of LDMOS in fields such as power, electric vehicles, rail transportation, smart home appliances, communications, medical and radar. Summary of the Invention

[0004] To address the aforementioned technical deficiencies, this invention provides a semiconductor device and a manufacturing method thereof.

[0005] The present invention provides a semiconductor device comprising: a substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer, and a gate, wherein the well region, the buffer region, the source region, and the drain region are located on the substrate, the source region is formed on the surface of the well region, the drain region is formed on the surface of the buffer region, and the well region and the buffer region are separated by a substrate material.

[0006] The dielectric layer comprises a first dielectric layer of high dielectric constant material and a second dielectric layer of low dielectric constant material, wherein the dielectric constant k of the first dielectric layer is greater than 3.9 and the dielectric constant k of the second dielectric layer is less than or equal to 2.8.

[0007] The first dielectric layer is located on the surface of the substrate between the well region and the buffer zone, and extends to the surface of the well region;

[0008] The gate is located on the surface of the first dielectric layer;

[0009] The second dielectric layer is located on the surface of the buffer and the drain region. One end of the second dielectric layer is connected to the gate and one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region.

[0010] In this embodiment of the invention, the dielectric layer further includes a third dielectric layer of a low dielectric constant material, wherein the dielectric constant k of the third dielectric layer is ≤2.8; the third dielectric layer is located on the surface of the well region and the source region, one end of the third dielectric layer is connected to the gate and the other end of the first dielectric layer, and the other end of the third dielectric layer is connected to the source region.

[0011] In this embodiment of the invention, the buffer zone includes multiple trenches filled with strained silicon material, and the multiple trenches filled with strained silicon material are arranged at intervals within the buffer zone.

[0012] In this embodiment of the invention, the strained silicon material filling the multiple trenches is SiGe; or, the strained silicon material filling the multiple trenches is SiC.

[0013] In this embodiment of the invention, a portion of the trenches are filled with strained silicon material SiGe, and another portion of the trenches are filled with strained silicon material SiC.

[0014] In this embodiment of the invention, multiple SiGe-filled trenches and multiple SiC-filled trenches are arranged in an alternating pattern.

[0015] In this embodiment of the invention, the groove is rectangular, hexagonal, strip-shaped, or triangular in shape.

[0016] In this embodiment of the invention, the high dielectric constant material of the first dielectric layer is aluminum oxide or hafnium oxide, and the low dielectric constant material of the second dielectric layer is carbon-doped silicon oxide.

[0017] In this embodiment of the invention, the semiconductor device further includes a transition region located within the substrate between the well region and the buffer region.

[0018] The transition region includes multiple N-type doped regions and multiple P-type doped regions, which are arranged alternately.

[0019] In this embodiment of the invention, the multiple N-type doped regions and multiple P-type doped regions of the transition region are arranged in an array.

[0020] In this embodiment of the invention, the doping concentrations of the multiple N-type doped regions and multiple P-type doped regions in the transition region are different, and the doping concentrations of the N-type doped regions and P-type doped regions decrease sequentially from the closest to the farthest relative to the first dielectric layer.

[0021] In this embodiment of the invention, the substrate is an SOI substrate, which includes a substrate silicon layer, an insulating layer and an active silicon layer from bottom to top; the well region, buffer region, source region and drain region are formed in the active silicon layer.

[0022] In this embodiment of the invention, the substrate silicon layer is grounded through conductive vias at both ends. The inner walls of the conductive vias are filled with an insulating material. The conductive vias are filled with a metallic material or a conductive doped silicon material.

[0023] In this embodiment of the invention, a conductive via at one end of the substrate silicon layer penetrates the well region, the active silicon layer, and the insulating layer; a conductive via at the other end of the substrate silicon layer penetrates the buffer zone, the active silicon layer, and the insulating layer.

[0024] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0025] A well region and a buffer zone separated from the well region are formed in the substrate;

[0026] A source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer zone;

[0027] A high dielectric constant material is deposited on the substrate surface between the well region and the buffer zone to form a first dielectric layer extending to the surface of the well region, wherein the dielectric constant k of the high dielectric constant material is greater than 3.9;

[0028] A low dielectric constant material is deposited on the surface of the buffer zone and the drain zone to form a second dielectric layer, such that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain zone, wherein the dielectric constant k of the low dielectric constant material is ≤2.8;

[0029] A gate is formed on the surface of the first dielectric layer, such that the gate is connected to one end of the second dielectric layer.

[0030] In this embodiment of the invention, forming a well region and a buffer zone separated from the well region in a substrate includes: selecting a P-type substrate, forming patterned windows of the well region and the buffer zone on the surface of the P-type substrate, and injecting P-type ions and N-type ions into the two patterned windows respectively to form a P-type well region and an N-type buffer zone.

[0031] In this embodiment of the invention, a source region is formed on the surface of the well region and a drain region is formed on the surface of the buffer zone, including: forming a source region pattern window and a drain region pattern window on the surface of the P-type well region and the surface of the N-type buffer zone, respectively, and injecting N-type ions into the source region pattern window and the drain region pattern window to form the source region and the drain region.

[0032] In this embodiment of the invention, depositing a high dielectric constant material on the substrate surface between the well region and the buffer zone includes: using an atomic layer deposition process to deposit a high dielectric constant material on a portion of the surface of the well region and on the substrate surface between the well region and the buffer zone to form a first dielectric layer with a high dielectric constant.

[0033] In this embodiment of the invention, depositing a low dielectric constant material on the surface of the buffer zone and the drain zone includes: using a plasma-enhanced chemical vapor deposition process to deposit a low dielectric constant material on the surface of the buffer zone, the surface of the drain zone, the surface of the source zone, and another part of the surface of the well zone, forming a second dielectric layer and a third dielectric layer with low dielectric constant.

[0034] In this embodiment of the invention, forming a gate on the surface of a first dielectric layer includes: depositing heavily doped polysilicon on the surface of the first dielectric layer and etching it to form a polysilicon gate, wherein the doping concentration of the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0035] In this embodiment of the invention, the method further includes: forming a plurality of trenches within the buffer zone;

[0036] Multiple trenches are filled with strained silicon material, wherein the strained silicon material is SiGe or SiC.

[0037] In this embodiment of the invention, the method further includes: forming a transition region in the substrate between the well region and the buffer region, the transition region including a plurality of N-type doped regions and a plurality of P-type doped regions, the plurality of N-type doped regions and the plurality of P-type doped regions being arranged alternately.

[0038] In this embodiment of the invention, a transition region is formed in the substrate between the well region and the buffer region, including:

[0039] A high-energy, low-dose ion implantation method is used to implant N-type ions into the corresponding N-type doped region in the substrate to form the N-type doped region below.

[0040] A high-energy, low-dose ion implantation method is used to implant P-type ions into the corresponding P-type doped region in the substrate to form the underlying P-type doped region.

[0041] A low-energy, high-dose ion implantation method is used to implant P-type ions into the corresponding P-type doped region on the substrate to form the P-type doped region above.

[0042] By employing a low-energy, high-dose ion implantation method, N-type ions are implanted into the corresponding N-type doped region on the substrate to form the upper N-type doped region, resulting in a transition region with an alternating distribution of N-type and P-type doped regions.

[0043] In this embodiment of the invention, the method further includes: forming a well region, a buffer region, a source region, and a drain region in the active silicon layer; etching the active silicon layer and the insulating layer to form a conductive via that is connected to the substrate silicon layer.

[0044] In this embodiment of the invention, etching is performed on the active silicon layer and the insulating layer to form a conductive via that is connected to the substrate silicon layer, including:

[0045] The active silicon layer and the insulating layer are etched, and the etching stops when the lower surface of the insulating layer is reached, forming a deep via that is connected to the substrate silicon layer.

[0046] The sidewalls of the deep via are filled with silicon dioxide or silicon nitride, and the inside of the deep via is filled with metal or silicon-doped material to form a conductive via.

[0047] The present invention also provides a chip comprising the above-described semiconductor device.

[0048] The present invention also provides an electronic device comprising the semiconductor device described above.

[0049] This invention comprises a first dielectric layer of high dielectric constant material disposed on the substrate surface between the well region and the buffer region, and a second dielectric layer of low dielectric constant material disposed between the gate and the drain region. Firstly, because the first dielectric layer is made of a high dielectric constant material, it can be made much thinner than the field oxide dielectric layer of a conventional LDMOS structure while maintaining the same capacitance. Due to the thinness of the first dielectric layer, when the same current is applied to the gate, it is easier to generate inversion electrons (inversion layer) in the substrate between the well region and the buffer region below the first dielectric layer, thereby forming an inversion channel. The inversion electron concentration in the inversion layer is much higher than the electron concentration in the drift region of a conventional structure, which can reduce the on-resistance. Secondly, by providing a buffer at the drain end, the drain current is buffered, which can improve the breakdown voltage of the drain end. Thirdly, by adding a second dielectric layer of low dielectric constant material between the gate and the drain region, compared to the field oxide dielectric layer of a conventional LDMOS structure, the low dielectric constant second dielectric layer reduces the parasitic capacitance (i.e., gate-drain capacitance Cgd) of the gate and drain ends, while increasing the breakdown voltage characteristics of the gate and drain ends. Since a lower gate-drain capacitance results in a faster device response, a lower gate-drain capacitance Cgd facilitates the application of the device in fields such as power, electric vehicles, rail transportation, smart home appliances, communications, medical, and radar.

[0050] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0051] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0052] Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 1 of the present invention;

[0053] Figure 2 This is a schematic diagram of the structure of a semiconductor device with a third dielectric layer provided in Embodiment 1 of the present invention;

[0054] Figure 3 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 2 of the present invention;

[0055] Figure 3a This is a schematic diagram of the triangular trench structure of the buffer zone of the semiconductor device provided in Embodiment 2 of the present invention;

[0056] Figure 3b This is a schematic diagram of the strip trench structure of the buffer zone of the semiconductor device provided in Embodiment 2 of the present invention;

[0057] Figure 4 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 3 of the present invention;

[0058] Figure 5 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 4 of the present invention;

[0059] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 5 of the present invention;

[0060] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram of a conventional LDMOS structure.

[0062] Explanation of reference numerals in the attached figures

[0063] 10-Substrate, 11-Substrate silicon layer, 12-Insulating layer, 13-Active silicon layer, 14-Conductive via,

[0064] 15-Body area, 16-Drift area, 17-Shallow trench isolation area,

[0065] 20 - Well region, 21 - Buffer zone, 211 - Trench filled with strained silicon material.

[0066] 22 - Source region, 23 - Drain region, 24 - Gate region

[0067] 25 - First dielectric layer, 26a - Second dielectric layer, 26b - Third dielectric layer, 27 - Transition region. Detailed Implementation

[0068] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0069] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0070] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to direct connection or indirect connection through an intermediate medium, or they can refer to the connectivity within two functional structural regions or the interaction between two functional structural regions. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0071] As described in the background section, existing LDMOS devices increase their breakdown voltage by increasing the thickness of the field oxide layer. However, the thicker the field oxide layer, the greater the on-resistance, making it difficult to achieve a low on-resistance at a high breakdown voltage. Furthermore, a thicker field oxide layer results in a larger gate-drain parasitic capacitance, which is detrimental to the application of LDMOS in radio frequency communication devices.

[0072] Figure 8 It is an existing conventional LDMOS structure. For example... Figure 8As shown, in a conventional LDMOS structure, the source region 22 is on the surface of the body region 15, the drain region 23 is on the surface of the drift region 16, the body region 15 and the drift region 16 are connected, and the gate 24 is above the body region 15 and the drift region 16. The shallow trench isolation region 17 (STI) below the gate 24 serves as a field oxide dielectric layer; the material of the STI is typically silicon dioxide (SiO2). The STI is located within the drift region 16 and reduces the surface electric field, thereby increasing the breakdown voltage. To increase the breakdown voltage, the thickness of the STI needs to be increased. However, during device operation, current flows from the source to the drain along the lower surface of the STI. The thicker the STI, the longer the current path from the source to the drain, resulting in a larger on-resistance, making it difficult to achieve a low on-resistance at higher breakdown voltages. Furthermore, the STI separates the gate 24 from the drain region 23; the thicker the STI, the larger the gate-drain parasitic capacitance (Cgd), which is detrimental to the application of LDMOS in radio frequency communication devices.

[0073] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device comprising a substrate 10, a well region 20, a buffer region 21, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The well region 20, buffer region 21, source region 22, and drain region 23 are located on the substrate 10, with the well region 20 connected to the source region 22 and the buffer region 21 connected to the drain region 23. The dielectric layer comprises a first dielectric layer 25 of a high dielectric constant material and a second dielectric layer 26a of a low dielectric constant material. The first dielectric layer 25 is located on the surface of the substrate 10 between the well region 20 and the buffer region 21, the gate 24 is located on the surface of the first dielectric layer 25, and the second dielectric layer 26a is located between the gate 24 and the drain region 23. In a first aspect, since the material of the first dielectric layer is a high dielectric constant material, compared to the field oxide dielectric layer of a conventional LDMOS structure, the first dielectric layer of the present invention can be made very thin while maintaining the same capacitance. Because the first dielectric layer is very thin, when the same current is applied to the gate, it is easier to generate inversion electrons (inversion layer) in the substrate between the well region and the buffer region below the first dielectric layer, thus forming an inversion channel. The inversion electron concentration in the inversion layer is much higher than the electron concentration in the drift region of a conventional structure, which can reduce the on-resistance. Secondly, designing a buffer at the drain end to buffer the drain current can improve the breakdown voltage of the drain end. Thirdly, adding a second dielectric layer of low dielectric material between the gate and the drain region, compared to the field oxide dielectric layer of a conventional LDMOS structure, reduces the parasitic capacitance (i.e., gate-drain capacitance Cgd) of the gate and drain ends, while increasing the breakdown voltage characteristics of the gate and drain ends. The reduction of the gate-drain capacitance Cgd of the device is beneficial for its application in radio frequency communication devices, because the lower the gate-drain capacitance, the faster the response speed.

[0074] Example 1

[0075] Figure 1This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 1 of the present invention. Figure 1 As shown, the semiconductor device of Embodiment 1 includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22, and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of high dielectric constant material and a second dielectric layer 26a of low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and extends to the surface of the P-type well region 20. The gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23. One end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. When a current is applied to the gate 24, inverted electrons (inverted to N-type conductivity) are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 located below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25, made of a high dielectric constant material, extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 near the first dielectric layer 25 also undergoes inversion, forming an inversion channel.

[0076] In this embodiment, the first dielectric layer uses a high-dielectric-constant material. High-dielectric-constant materials are commonly referred to as high-k materials, and their dielectric constant (k value) is typically much higher than the 3.9 dielectric constant of traditional SiO2 materials. A high-dielectric-constant material for the first dielectric layer refers to a material with a k value greater than 3.9, especially materials with a dielectric constant much greater than 3.9, such as materials with a k value greater than 20, such as alumina (Al2O3) and hafnium oxide (HfO2). The dielectric constant k of hafnium oxide (HfO2) is approximately 25. The second dielectric layer uses a low-dielectric-constant material, typically with a k value less than 2.8 (k ≤ 2.8), such as carbon-doped silicon oxide.

[0077] The semiconductor device in this embodiment does not have a field oxide dielectric layer. Instead, a relatively thin high dielectric constant dielectric layer is grown on the surface of the P-type well region 20 and on the surface of the substrate 10 between the P-type well region 20 and the N-type buffer zone 21. When a current is applied to the gate, the silicon in the substrate 10 below the high dielectric constant dielectric layer is more likely to invert, forming an inversion channel.

[0078] In principle, the capacitance C is calculated using the formula C = εS / 4πkd, where ε is a constant, S is the area of ​​the capacitor plates facing each other, d is the distance between the capacitor plates, and k is the electrostatic constant. The high-k dielectric material (high dielectric constant dielectric layer) has a larger ε, allowing for a thinner high-k dielectric layer while maintaining the same capacitance. The thinner high-k dielectric layer below the gate 24 (traditional STI thickness is 200-800 nm, while in this invention the high-k dielectric layer thickness is 20-80 Å, and the low-k dielectric layer thickness is 100-800 Å) makes it easier for inversion electrons to be generated within the substrate 10 between the P-type well region 20 and the N-type buffer zone 21, forming an inversion channel connecting the P-type well region 20 and the N-type buffer zone 21. Electrons from the source are transported to the drain through this inversion channel. The electron concentration in the inversion channel is much greater than that in the conventional drift region 16, significantly reducing the device's on-resistance (Ron). Considering the device's breakdown voltage characteristics, an N-type buffer 21 is designed at the drain terminal. The N-type buffer 21 and the drain region 23 constitute the entire drain terminal structure to improve the breakdown voltage (BV). Furthermore, a low-k dielectric layer (a second dielectric layer 26a of low-dielectric-constant material) is added between the gate 24 and the drain region 23. The low-k dielectric layer has a smaller ε, resulting in a smaller parasitic capacitance between the gate 24 and the drain region 23, reducing the gate-drain capacitance Cgd (smaller than the gate-drain capacitance Cgd of a conventional locos / STI structure), while simultaneously increasing the breakdown voltage characteristics of the gate 24 and drain terminal. The reduced gate-drain capacitance Cgd facilitates the device's application in RF communication devices.

[0079] like Figure 2 As shown, in this embodiment, the dielectric layer further includes a third dielectric layer 26b made of a low-dielectric-constant material. The third dielectric layer 26b is located on the surfaces of the P-type well region 20 and the source region 22. One end of the third dielectric layer 26b is connected to the gate 24 and the other end of the first dielectric layer 25, and the other end of the third dielectric layer 26b is connected to the source region 22. The third dielectric layer 26b is a low-k dielectric layer, where the dielectric constant k of the low-k material is ≤2.8, such as carbon-doped silicon oxide. Because the ε of the low-k dielectric layer is small, the parasitic capacitance between the gate 24 and the source region 22 is small, which can reduce the gate-source capacitance Cgs of the device.

[0080] Example 2

[0081] Figure 3 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 2 of the present invention. Figure 3As shown, the semiconductor device of Embodiment 2 includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22, and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and extends to the surface of the P-type well region 20. The gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23. One end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of trenches 211 filled with strained silicon material, which are spaced apart within the buffer region 21. When a current is applied to the gate 24, inverted electrons are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 located below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25, made of a high dielectric constant material, extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 near the first dielectric layer 25 is also inverted, forming an inversion channel.

[0082] The difference between Example 2 and Example 1 is that the buffer zone 21 has multiple trenches 211 filled with strained silicon material. Specifically, SiGe or SiC can be filled in all of the multiple trenches.

[0083] To further enhance the device's breakdown voltage capability, trenches of different or identical shapes are designed within the buffer buffer 21. These trenches are filled with strained silicon materials such as SiGe / SiC. The strained silicon material can be of the same conductivity type as the N-type buffer buffer 21 (N-type) or a different conductivity type (P-type). If the buffer buffer 21 is of electron conductivity type (N-type), SiGe can be used to fill the trenches. SiGe-filled trenches contribute to improved mobility of the N-type electron channel. Because the lattice coefficient of SiGe is different from that of conventional silicon-based materials, the SiGe lattice exerts tensile stress on the surrounding silicon lattice, altering the lattice structure and facilitating electron transport through the lattice, thus increasing the carrier mobility within the buffer buffer 21 and enhancing the device's breakdown voltage capability. Similarly, if the buffer buffer 21 is of hole conductivity type (P-type), SiCe can be used to fill the trenches.

[0084] In other embodiments, a portion of the trenches may be filled with SiGe, while another portion may be filled with SiC. The alternating arrangement of the SiGe-filled trenches and the SiC-filled trenches further enhances the carrier mobility within the buffer zone.

[0085] In a specific embodiment, the multiple trenches filled with strained silicon material within the buffer zone 21 can be designed with the same shape or different shapes. The multiple trenches of the same shape within the buffer zone 21 can be rectangular, hexagonal, strip-shaped, or triangular. For example... Figure 3 As shown, multiple rectangular grooves of the same shape within buffer zone 21 are arranged in an array. Figure 3a As shown, multiple trenches of the same shape within buffer zone 21 are triangular, and these triangular trenches are arranged in parallel. Figure 3b As shown, the multiple grooves of the same shape in the buffer zone 21 are strip-shaped, with strip-shaped grooves filled with SiGe and strip-shaped grooves filled with SiC arranged alternately.

[0086] In addition, the grooves filled with strained silicon material in the buffer zone can also be of different shapes, and multiple grooves of different shapes can be set as any combination of rectangles, hexagons, strips, and triangles.

[0087] Example 3

[0088] Figure 4 This is a schematic diagram of the semiconductor device provided in Embodiment 3 of the present invention. Figure 4As shown, the semiconductor device of Embodiment 3 includes a P-type substrate 10, a P-type well region 20, an N-type buffer region 21, a transition region 27, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The P-type well region 20, the N-type buffer region 21, the source region 22, and the drain region 23 are located on the P-type substrate 10. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The source region 22 is formed on the surface of the P-type well region 20, and the drain region 23 is formed on the surface of the N-type buffer region 21. The P-type well region 20 and the N-type buffer region 21 are separated by the substrate 10 material. The dielectric layer includes a first dielectric layer 25 of high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b of low dielectric constant material. The first dielectric layer 25 is located on the surface of the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23. One end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of trenches filled with strained silicon material, which are spaced apart within the buffer region 21. The transition region 27 is located within the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21. When a current is applied to the gate 24, inverted electrons are generated in the P-type substrate 10 between the P-type well region 20 and the N-type buffer region 21 below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer region 21. The first dielectric layer 25, made of a high dielectric constant material, extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 near the first dielectric layer 25 is also inverted, forming an inversion channel.

[0089] The buffer zone 21 contains multiple trenches 211 filled with strained silicon material. Specifically, SiGe or SiC can be filled in all of the trenches. Alternatively, some of the trenches can be filled with SiGe, while others can be filled with SiC. The alternating arrangement of the SiGe-filled trenches and the SiC-filled trenches further enhances the carrier mobility within the buffer zone 21.

[0090] The multiple trenches filled with strained silicon material within buffer 21 can be designed with the same shape or different shapes. Multiple trenches of the same shape within buffer 21 can be rectangular, hexagonal, strip-shaped, or triangular. Multiple trenches of the same shape within buffer 21 can be arranged in an array. Multiple trenches of different shapes within buffer 21 can be any combination of rectangular, hexagonal, strip-shaped, and triangular shapes.

[0091] The difference between Embodiment 3 and Embodiment 2 is that a transition region 27 is provided within the P-type substrate 10 between the P-type well region 20 and the N-type buffer zone 21. The transition region 27 includes multiple N-type doped regions and multiple P-type doped regions, which are staggered. The multiple N-type and P-type doped regions in the transition region 27 are arranged in an array. The individual N-type and P-type doped regions are stacked like building blocks.

[0092] like Figure 4 As shown, the multiple N-type and P-type doped regions in the transition region 27 are arranged in a checkerboard pattern. In the checkerboard-patterned transition region 27, the P-type doped regions invert to form channels, while the N-type doped regions can conduct electrons. At the same time, the N-type doped regions effectively deplete the adjacent P-type doped regions, forming a depletion layer between the N-type and adjacent P-type doped regions. Since the P-type doped regions are surrounded by N-type doped regions on all sides, the P-type doped regions can be depleted from all directions, further improving the breakdown voltage characteristics and realizing a high-voltage device.

[0093] Specifically, the multiple N-type doped regions and multiple P-type doped regions in the transition region 27 have different doping concentrations, and the doping concentrations of the N-type doped regions and P-type doped regions decrease sequentially from the closest to the farthest from the first dielectric layer 25. The doping concentrations of the N-type doped regions and P-type doped regions in the transition region 27 that are closer to the first dielectric layer 25 are greater than the doping concentrations of the N-type doped regions and P-type doped regions in the transition region 27 that are farther away from the first dielectric layer 25.

[0094] Example 4

[0095] Figure 5 This is a schematic diagram of the semiconductor device provided in Embodiment 4 of the present invention. Figure 5As shown, the semiconductor device of Embodiment 4 includes a substrate 10, a P-type well region 20, an N-type buffer region 21, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The substrate 10 is an SOI (Silicon On Insulator) substrate 10, which includes a substrate silicon layer 11, an insulating layer 12, and a P-type active silicon layer 13 from bottom to top. The P-type well region 20, the N-type buffer region 21, the source region 22, and the drain region 23 are located in the P-type active silicon layer 13. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The P-type well region 20 and the N-type buffer region 21 are separated by an active silicon material. The dielectric layer includes a first dielectric layer 25 made of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b made of low dielectric constant materials. The first dielectric layer 25 is located on the surface of the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23. One end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of trenches filled with strained silicon material, which are spaced apart within the buffer region 21. When a current is applied to the gate 24, inversion electrons are generated in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer zone 21 located below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer zone 21. The first dielectric layer 25, made of a high dielectric constant material, extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 near the first dielectric layer 25 also undergoes inversion, forming an inversion channel.

[0096] The buffer zone 21 contains multiple trenches 211 filled with strained silicon material. Specifically, SiGe or SiC can be filled in all of the trenches. Alternatively, some of the trenches can be filled with SiGe, while others can be filled with SiC. The alternating arrangement of the SiGe-filled trenches and the SiC-filled trenches further enhances the carrier mobility within the buffer zone 21.

[0097] The multiple trenches filled with strained silicon material within buffer 21 can be designed with the same shape or different shapes. Multiple trenches of the same shape within buffer 21 can be rectangular, hexagonal, strip-shaped, or triangular. Multiple trenches of the same shape within buffer 21 can be arranged in an array. Multiple trenches of different shapes within buffer 21 can be any combination of rectangular, hexagonal, strip-shaped, and triangular shapes.

[0098] The difference between Embodiment 4 and Embodiment 2 is that conductive vias 14 are provided at both ends of the device. The substrate silicon layer 11 is grounded through the conductive vias 14 at both ends. In this case, the substrate silicon layer 11 and the insulating layer 12 act as a lower field plate, which can reduce the electric field on the surface of the active silicon layer 13 and make its electric field distribution more uniform. The conductive via 14 at one end of the substrate silicon layer 11 penetrates the well region 20, the active silicon layer 13, and the insulating layer 12, while the conductive via 14 at the other end of the substrate silicon layer 11 penetrates the buffer zone 21, the active silicon layer 13, and the insulating layer 12. The conductive via 14 is filled with a metal material or a conductive doped silicon material. The inner wall of the conductive via 14 is filled with an insulating material.

[0099] Example 5

[0100] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in Embodiment 5 of the present invention. Figure 6 As shown, the semiconductor device of Embodiment 5 includes a substrate 10, a P-type well region 20, an N-type buffer region 21, a transition region 27, a source region 22, a drain region 23, a dielectric layer, and a gate 24. The substrate 10 is an SOI (Silicon On Insulator) substrate 10, which includes a substrate silicon layer 11, an insulating layer 12, and a P-type active silicon layer 13 from bottom to top. The P-type well region 20, the N-type buffer region 21, the source region 22, and the drain region 23 are located in the P-type active silicon layer 13. The P-type well region 20 is connected to the source region 22, and the N-type buffer region 21 is connected to the drain region 23. The P-type well region 20 and the N-type buffer region 21 are separated by an active silicon material. The dielectric layer includes a first dielectric layer 25 made of a high dielectric constant material and a second dielectric layer 26a and a third dielectric layer 26b made of low dielectric constant materials. The first dielectric layer 25 is located on the surface of the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21, and the gate 24 is located on the surface of the first dielectric layer 25. The second dielectric layer 26a is located on the surface of the N-type buffer region 21 and the drain region 23. One end of the second dielectric layer 26a is connected to the gate 24 and one end of the first dielectric layer 25, and the other end of the second dielectric layer 26a is connected to the drain region 23. The third dielectric layer 26b is located on the surface of the P-type well region 20 and the source region 22. The buffer region 21 includes a plurality of trenches filled with strained silicon material, which are spaced apart within the buffer region 21. The transition region 27 is located within the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer region 21. When a current is applied to the gate 24, inversion electrons are generated in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer zone 21 located below the first dielectric layer 25, forming an inversion layer, thereby forming an inversion channel between the P-type well region 20 and the N-type buffer zone 21. The first dielectric layer 25, made of a high dielectric constant material, extends to the surface of the P-type well region 20, and the surface of the P-type well region 20 near the first dielectric layer 25 also undergoes inversion, forming an inversion channel.

[0101] The buffer zone 21 contains multiple trenches 211 filled with strained silicon material. Specifically, SiGe or SiC can be filled in all of the trenches. Alternatively, some of the trenches can be filled with SiGe, while others can be filled with SiC. The alternating arrangement of the SiGe-filled trenches and the SiC-filled trenches further enhances the carrier mobility within the buffer zone 21.

[0102] The multiple trenches filled with strained silicon material within buffer 21 can be designed with the same shape or different shapes. Multiple trenches of the same shape within buffer 21 can be rectangular, hexagonal, strip-shaped, or triangular. Multiple trenches of the same shape within buffer 21 can be arranged in an array. Multiple trenches of different shapes within buffer 21 can be any combination of rectangular, hexagonal, strip-shaped, and triangular shapes.

[0103] The substrate silicon layer 11 is grounded through conductive vias 14 at both ends. In this case, the substrate silicon layer 11 and the insulating layer 12 act as a lower field plate, reducing the electric field on the surface of the active silicon layer 13 and making its electric field distribution more uniform. The conductive via 14 at one end of the substrate silicon layer 11 penetrates the well region 20, the active silicon layer 13, and the insulating layer 12. The conductive via 14 at the other end of the substrate silicon layer 11 penetrates the buffer zone 21, the active silicon layer 13, and the insulating layer 12. The bottom of the conductive via 14 contacts the upper surface of the substrate silicon layer 11. The conductive via 14 is filled with a metallic material or a conductive doped silicon material. The inner wall of the conductive via 14 is filled with an insulating material.

[0104] The difference between Embodiment 5 and Embodiment 4 is that a transition region 27 is present in the P-type active silicon layer 13 between the P-type well region 20 and the N-type buffer zone 21. The transition region 27 includes multiple N-type doped regions and multiple P-type doped regions, which are alternately arranged. The multiple N-type doped regions and multiple P-type doped regions of the transition region 27 are arranged in an array.

[0105] The transition region 27 contains multiple N-type and P-type doped regions arranged in a checkerboard pattern. Within this checkerboard pattern, the P-type doped regions invert to form channels, while the N-type doped regions conduct electrons. Simultaneously, the N-type doped regions effectively deplete the adjacent P-type doped regions, forming a depletion layer. Because the P-type doped regions are surrounded by N-type doped regions on all sides, they can be depleted from all angles, further enhancing their breakdown voltage characteristics and enabling high-voltage devices.

[0106] The multiple N-type and P-type doped regions in the transition region 27 have different doping concentrations, and their doping concentrations decrease sequentially from the closest to the first dielectric layer 25. The doping concentrations of the N-type and P-type doped regions in the transition region 27 closer to the first dielectric layer 25 are greater than the doping concentrations of the N-type and P-type doped regions in the transition region 27 farther from the first dielectric layer 25.

[0107] It should be noted that the typical structure using the concept of this invention is the LDMOS device structure. The concept of this invention can also be applied to other power semiconductor devices, such as VDMOS devices and SJ-MOS devices.

[0108] Embodiments of the present invention also provide a method for manufacturing the above-described semiconductor device. For example... Figure 7 As shown, the semiconductor device manufacturing method provided in this embodiment of the invention includes the following steps:

[0109] S701, forming a well region and a buffer zone separated from the well region in the substrate;

[0110] S702, a source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer zone;

[0111] S703, a high dielectric constant material is deposited on the substrate surface between the well region and the buffer zone to form a first dielectric layer extending to the surface of the well region;

[0112] S704, a low dielectric constant material is deposited on the surface of the buffer zone and the drain zone to form a second dielectric layer, such that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain zone.

[0113] S705, a gate is formed on the surface of the first dielectric layer, such that the gate is connected to one end of the second dielectric layer.

[0114] In step S701 above, a P-type substrate is selected, and photolithography and development are used to form patterned windows of well regions and buffer zones on the surface of the P-type substrate. P-type ions and N-type ions are injected into the two patterned windows respectively to form P-type well regions and N-type buffer zones, wherein the P-type well regions and N-type buffer zones are separated.

[0115] In step S702 above, photolithography and development processes are used to form source region pattern windows and drain region pattern windows on the surface of the P-type well region and the surface of the N-type buffer zone, respectively. N-type ions are implanted into the source region pattern windows and drain region pattern windows to form a source region connected to the P-type well region and a drain region connected to the N-type buffer zone and the drain region.

[0116] In step S703 above, atomic layer deposition (ALD) is used to deposit a high dielectric constant material on a portion of the surface of the P-type well region and on the substrate surface between the P-type well region and the N-type buffer zone, forming a first dielectric layer with a high dielectric constant. The high dielectric constant material has a dielectric constant k > 3.9, such as alumina (Al2O3) or hafnium oxide (HfO2).

[0117] In step S704 above, plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a low-dielectric-constant material on the surface of the N-type buffer region, the surface of the drain region, the surface of the source region, and another part of the surface of the P-type well region, forming a second and third dielectric layer with low dielectric constants. The dielectric constant k of the low-dielectric-constant material is ≤2.8, for example, carbon-doped silicon oxide.

[0118] In step S705 above, heavily doped polysilicon is deposited on the surface of the first dielectric layer and then etched to form a polysilicon gate. The doping concentration of the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0119] In one specific embodiment, after forming the P-type well region and the N-type buffer region, multiple trenches are formed within the N-type buffer region, and these trenches are filled with strained silicon material such as SiGe or SiC. The strained silicon material can be of the same conductivity type (N-type) as the N-type buffer region, or it can be of a different conductivity type (P-type). If the buffer region is of electron conductivity type (N-type), SiGe can be used to fill the trenches, as this helps improve the mobility of the N-type electron channel. Because the lattice coefficient of SiGe is different from that of conventional silicon-based materials, the SiGe lattice exerts tensile stress on the surrounding silicon lattice, changing the lattice structure and making it easier for electrons to transport through the lattice, thus improving the mobility of charge carriers within the buffer region and enhancing the device's breakdown voltage capability. Similarly, if the buffer region is of hole conductivity type (P-type), SiCe can be used to fill the trenches.

[0120] In other embodiments, a portion of the multiple trenches may be filled with SiGe, while another portion may be filled with SiC. The alternating arrangement of the SiGe-filled trenches and the SiC-filled trenches further enhances the carrier mobility within the buffer zone. Furthermore, the multiple trenches filled with strained silicon material within the buffer zone can be designed with the same shape or different shapes. Multiple trenches with the same shape within the buffer zone can be rectangular, hexagonal, strip-shaped, or triangular. Multiple trenches filled with strained silicon material within the buffer zone can also have different shapes; multiple trenches with different shapes can be any combination of rectangles, hexagons, stripes, and triangles.

[0121] In one specific embodiment, after forming the P-type well region and the N-type buffer region, a transition region is formed in the substrate between the P-type well region and the N-type buffer region. The transition region includes multiple N-type doped regions and multiple P-type doped regions, which are arranged alternately. The multiple N-type doped regions and P-type doped regions in the transition region are distributed in a checkerboard pattern. The individual N-type doped regions and P-type doped regions are stacked in a building block manner. In the fabrication process of the transition region, the substrate between the P-type well region and the N-type buffer region is first photolithographically lithographically and developed in this manner to form multiple small-sized building block-like doped regions. For the building block-like N-type doped regions and P-type doped regions, a small-size photolithographic correction process is used for exposure. At the same time, based on algorithm correction, optical auxiliary exposure holes are distributed around the small-size regions to repair the corners or angles of the small-size doped region morphology, thereby obtaining precisely spaced N-type doped regions and P-type doped regions. Then, using a high-energy, low-dose ion implantation method, N-type ions are implanted into the corresponding N-type doped region in the middle of the substrate to form the lower N-type doped region; the high-energy, low-dose ion implantation method is used (implantation energy of 500 KeV~1000 KeV, ion concentration of 1×10⁻⁶). 12 cm -3 ~5×10 12 cm -3 P-type ions are implanted into the corresponding P-type doped region in the middle of the substrate to form the underlying P-type doped region. A low-energy, high-dose ion implantation method is used (implantation energy of 100 KeV~300 KeV, ion concentration of 1×10⁻⁶). 13 cm -3 ~4×10 13 cm -3 P-type ions are implanted into the corresponding P-type doped region on the upper part of the substrate to form the upper P-type doped region; N-type ions are implanted into the corresponding N-type doped region on the upper part of the substrate using a low-energy, high-dose ion implantation method to form the upper N-type doped region. Through these methods, a transition region with alternating N-type and P-type doped regions is formed.

[0122] In another embodiment, an SOI substrate is used, comprising, from bottom to top, a substrate silicon layer, an insulating layer, and a P-type active silicon layer. After forming a P-type well region, an N-type buffer region, a source region, and a drain region in the P-type active silicon layer, the active silicon layer and the insulating layer are etched to form conductive vias connected to the substrate silicon layer. The substrate silicon layer is grounded through the conductive vias, serving as a lower field plate. Specifically, the active silicon layer and the insulating layer are etched, stopping when etching reaches the lower surface of the insulating layer, forming deep vias connected to the substrate silicon layer. The sidewalls of the deep vias are filled with silicon dioxide or silicon nitride. Excess silicon dioxide or silicon nitride is etched away, and the deep vias are filled with metal or highly conductive doped silicon material to form conductive vias. Alternatively, through-hole deep vias are formed at both ends of the substrate. First, silicon dioxide or silicon nitride is filled around the deep vias, then the silicon dioxide or silicon nitride is etched away from the back side, and the deep vias are filled with metal or highly conductive doped silicon material.

[0123] This invention also provides a chip that includes the semiconductor device described in the above embodiments.

[0124] The present invention also provides an electronic device, which includes the semiconductor device described in the above embodiments.

[0125] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The device comprises a substrate, a well region, a buffer region, a source region, a drain region, a dielectric layer, and a gate, wherein the well region, the buffer region, the source region, and the drain region are located on the substrate, the source region is formed on the surface of the well region, the drain region is formed on the surface of the buffer region, and the well region and the buffer region are separated by a substrate material. The dielectric layer comprises a first dielectric layer of high dielectric constant material and a second dielectric layer of low dielectric constant material, wherein the dielectric constant k of the first dielectric layer is greater than 3.9 and the dielectric constant k of the second dielectric layer is less than or equal to 2.

8. The first dielectric layer is located on the surface of the substrate between the well region and the buffer zone, and extends to the surface of the well region; The gate is located on the surface of the first dielectric layer; The second dielectric layer is located on the surface of the buffer and the drain region. One end of the second dielectric layer is connected to the gate and one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain region.

2. The semiconductor device according to claim 1, characterized in that, The dielectric layer further includes a third dielectric layer of a low dielectric constant material, wherein the dielectric constant of the third dielectric layer is k≤2.8; The third dielectric layer is located on the surface of the well region and the source region. One end of the third dielectric layer is connected to the gate and the other end of the first dielectric layer, and the other end of the third dielectric layer is connected to the source region.

3. The semiconductor device according to claim 1, characterized in that, The buffer zone includes multiple trenches filled with strained silicon material, which are spaced apart within the buffer zone.

4. The semiconductor device according to claim 3, characterized in that, The strained silicon material filling the multiple trenches is SiGe; or, the strained silicon material filling the multiple trenches is SiC.

5. The semiconductor device according to claim 3, characterized in that, A portion of the trenches are filled with strained silicon material SiGe, while another portion of the trenches are filled with strained silicon material SiC.

6. The semiconductor device according to claim 5, characterized in that, Multiple SiGe-filled trenches are arranged in an alternating pattern with multiple SiC-filled trenches.

7. The semiconductor device according to claim 3, characterized in that, The groove can be rectangular, hexagonal, strip-shaped, or triangular.

8. The semiconductor device according to claim 1, characterized in that, The high dielectric constant material of the first dielectric layer is alumina or hafnium oxide, and the low dielectric constant material of the second dielectric layer is carbon-doped silicon oxide.

9. The semiconductor device according to claim 1, characterized in that, Also includes: A transition region, located within the substrate between the well region and the buffer zone.

10. The semiconductor device according to claim 9, characterized in that, The transition region includes multiple N-type doped regions and multiple P-type doped regions, which are arranged alternately.

11. The semiconductor device according to claim 10, characterized in that, The multiple N-type doped regions and multiple P-type doped regions in the transition region are arranged in an array.

12. The semiconductor device according to claim 10, characterized in that, The multiple N-type doped regions and multiple P-type doped regions in the transition region have different doping concentrations, and the doping concentrations of the N-type doped regions and P-type doped regions decrease sequentially from the closest to the farthest relative to the first dielectric layer.

13. The semiconductor device according to claim 1, characterized in that, The substrate is an SOI substrate, which includes, from bottom to top, a substrate silicon layer, an insulating layer, and an active silicon layer; The well region, buffer region, source region, and drain region are formed in the active silicon layer.

14. The semiconductor device according to claim 13, characterized in that, The substrate silicon layer is grounded through conductive vias located at both ends.

15. The semiconductor device according to claim 14, characterized in that, The conductive via at one end of the substrate silicon layer penetrates the well region, the active silicon layer, and the insulating layer. The conductive via at the other end of the substrate silicon layer penetrates the buffer zone, the active silicon layer, and the insulating layer.

16. The semiconductor device according to claim 14, characterized in that, The inner wall of the conductive through hole is filled with insulating material; The conductive via is filled with a metallic material or a conductive doped silicon material.

17. The semiconductor device according to claim 2, characterized in that, The low dielectric constant material of the third dielectric layer is carbon-doped silicon oxide.

18. A method for manufacturing a semiconductor device, characterized in that, include: A well region and a buffer zone separated from the well region are formed in the substrate; A source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer zone; A high dielectric constant material is deposited on the substrate surface between the well region and the buffer zone to form a first dielectric layer extending to the surface of the well region, wherein the dielectric constant k of the high dielectric constant material is greater than 3.9; A low dielectric constant material is deposited on the surface of the buffer zone and the drain zone to form a second dielectric layer, such that one end of the second dielectric layer is connected to one end of the first dielectric layer, and the other end of the second dielectric layer is connected to the drain zone, wherein the dielectric constant k of the low dielectric constant material is ≤2.8; A gate is formed on the surface of the first dielectric layer, such that the gate is connected to one end of the second dielectric layer.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, Forming a well region and a buffer zone separated from the well region in the substrate includes: A P-type substrate is selected, and patterned windows of well regions and buffer zones are formed on the surface of the P-type substrate. P-type ions and N-type ions are injected into the two patterned windows respectively to form P-type well regions and N-type buffer zones.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, A source region is formed on the surface of the well region, and a drain region is formed on the surface of the buffer region, including: Source region pattern windows and drain region pattern windows are formed on the surface of the P-type well region and the surface of the N-type buffer zone, respectively. N-type ions are injected into the source region pattern windows and drain region pattern windows to form the source region and drain region.

21. The method for manufacturing a semiconductor device according to claim 18, characterized in that, A high-dielectric-constant material is deposited on the substrate surface between the well region and the buffer region, including: A high dielectric constant material is deposited on a portion of the surface of the well region and on the substrate surface between the well region and the buffer zone using an atomic layer deposition process to form a first dielectric layer with a high dielectric constant.

22. The method for manufacturing a semiconductor device according to claim 21, characterized in that, Depositing low dielectric constant materials on the surfaces of the buffer and drain regions, including: Plasma-enhanced chemical vapor deposition is used to deposit low dielectric constant materials on the surface of the buffer zone, the surface of the drain zone, the surface of the source zone, and another part of the surface of the well zone, forming a second and third dielectric layer with low dielectric constant.

23. The method for manufacturing a semiconductor device according to claim 18, characterized in that, A gate is formed on the surface of the first dielectric layer, including: Heavily doped polysilicon is deposited on the surface of the first dielectric layer and etched to form a polysilicon gate. The doping concentration of the heavily doped polysilicon is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

24. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The method further includes: Multiple trenches are formed within the buffer zone; Multiple trenches are filled with strained silicon material, wherein the strained silicon material is SiGe or SiC.

25. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The method further includes: A transition region is formed in the substrate between the well region and the buffer region. The transition region includes multiple N-type doped regions and multiple P-type doped regions, which are arranged alternately.

26. The method for manufacturing a semiconductor device according to claim 25, characterized in that, A transition region is formed within the substrate between the well region and the buffer region, including: A high-energy, low-dose ion implantation method is used to implant N-type ions into the corresponding N-type doped region in the substrate to form the N-type doped region below. A high-energy, low-dose ion implantation method is used to implant P-type ions into the corresponding P-type doped region in the substrate to form the underlying P-type doped region. A low-energy, high-dose ion implantation method is used to implant P-type ions into the corresponding P-type doped region on the substrate to form the P-type doped region above. Using a low-energy, high-dose ion implantation method, N-type ions are implanted into the corresponding N-type doped region on the substrate to form the upper N-type doped region, resulting in a transition region with an alternating distribution of N-type doped region and P-type doped region. Among them, the high-energy, low-dose ion implantation method uses an implantation energy of 500 KeV~1000 KeV and an ion concentration of 1×10⁻⁶. 12 cm -3 ~5×10 12 cm -3 ; Low-energy, high-dose ion implantation uses implantation energies of 100 KeV to 300 KeV and ion concentrations of 1 × 10⁻⁶. 13 cm -3 ~4×10 13 cm -3 .

27. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The substrate is an SOI substrate, which includes, from bottom to top, a substrate silicon layer, an insulating layer, and an active silicon layer.

28. The method for manufacturing a semiconductor device according to claim 27, characterized in that, The method further includes: Well regions, buffer regions, source regions, and drain regions are formed in the active silicon layer; The active silicon layer and the insulating layer are etched to form conductive vias that are connected to the substrate silicon layer.

29. The method for manufacturing a semiconductor device according to claim 28, characterized in that, Etching the active silicon layer and the insulating layer to form conductive vias that are connected to the substrate silicon layer includes: The active silicon layer and the insulating layer are etched, and the etching stops when the lower surface of the insulating layer is reached, forming a deep via that is connected to the substrate silicon layer. The sidewalls of the deep via are filled with silicon dioxide or silicon nitride, and the inside of the deep via is filled with metal or silicon-doped material to form a conductive via.

30. A chip, characterized in that, The chip includes the semiconductor device according to any one of claims 1-17.

31. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-17.

Images