Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof and an electronic device. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a first vertical transistor on the substrate; depositing one or more layers of interlayer insulating medium material layers on the first vertical transistor; performing plasma treatment on the one or more layers of interlayer insulating medium material layers to form one or more layers of interlayer insulating medium layers; and forming a second vertical transistor on the one or more layers of interlayer insulating medium layers; wherein a channel layer of the first vertical transistor and / or the second vertical transistor is a metal oxide semiconductor material. The manufacturing method of the semiconductor structure can improve the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0004] Using metal oxide semiconductor material as the channel material of the semiconductor device can achieve relatively small leakage current, however, these metal oxide semiconductor materials are sensitive to impurities, external water vapor, etc., and are easily affected by subsequent process processes and external environment. SUMMARY

[0005] The present application provides a semiconductor structure, a manufacturing method thereof and an electronic device.

[0006] The present application provides a manufacturing method of a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a first vertical transistor on the substrate;

[0009] depositing one or more layers of interlayer insulating medium material layers on the first vertical transistor, and performing plasma treatment on the one or more layers of interlayer insulating medium material layers to form one or more layers of interlayer insulating layers;

[0010] forming a second vertical transistor on the one or more layers of interlayer insulating layers;

[0011] wherein at least one of a first channel layer of the first vertical transistor and a second channel layer of the second vertical transistor comprises metal oxide semiconductor material.

[0012] In some embodiments, the interlayer insulating medium material layer before the plasma treatment is deposited at a low temperature, the temperature of the low temperature is not higher than 300 DEG C, the interlayer insulating medium material layer contains impurity ions, and the impurity ions include at least one of carbon ions and hydrogen ions;

[0013] The plasma treatment on the one or more layers of interlayer insulating medium material layers comprises:

[0014] performing a plasma treatment on the one or more interlayer insulating medium material layers using at least one of a nitrogen plasma, a fluorine plasma, a sulfur plasma, and an oxygen plasma.

[0015] In some embodiments, the number of the interlayer insulating medium layers is two or three; the materials of the two or three interlayer insulating medium layers are the same or not completely the same.

[0016] In some embodiments, the forming the first vertical transistor on the substrate comprises:

[0017] forming a first stack structure on the substrate, the first stack structure comprising a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer, and a third dielectric layer, which are sequentially stacked from bottom to top;

[0018] forming a first gate hole in the first stack structure, the first gate hole penetrating through the second dielectric layer, the second conductive layer, and the third dielectric layer, and extending into the first conductive layer;

[0019] forming a first gate structure in the first gate hole.

[0020] In some embodiments, before the forming the first gate structure in the first gate hole, the method further comprises:

[0021] depositing a first channel material layer on the bottom of the first gate hole, the sidewall of the first gate hole, and the upper surface of the first stack structure, and patterning the first channel material layer to form the first channel layer;

[0022] the first gate structure comprises a first gate dielectric layer and a first gate conductive layer;

[0023] forming the first gate structure in the first gate hole comprises: depositing a first gate dielectric material layer on the surface of the first channel material layer, depositing a first gate conductive material layer on the surface of the first gate dielectric material layer and in the first gate hole, and patterning the first gate dielectric material layer and the first gate conductive material layer to form the first gate dielectric layer and the first gate conductive layer.

[0024] In some embodiments, the forming the second vertical transistor on the one or more interlayer insulating medium layers comprises:

[0025] forming a second stack structure on the upper surface of the one or more interlayer insulating medium layers, the second stack structure comprising a third conductive layer, a fourth dielectric layer, a fourth conductive layer, and a fifth dielectric layer, which are sequentially stacked from bottom to top;

[0026] forming a second gate hole in the second stack structure, the second gate hole penetrating through the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer, and extending into the third conductive layer;

[0027] forming a second gate structure in the second gate hole.

[0028] In some embodiments, before forming the second gate structure in the second gate hole, further comprising:

[0029] forming a second channel material layer on a bottom of the second gate hole, a sidewall of the second gate hole, and an upper surface of the second stack structure, and patterning the second channel material layer to form the second channel layer;

[0030] the second gate structure comprises a second gate dielectric layer and a second gate conductive layer;

[0031] forming the second gate structure in the second gate hole comprises: forming a second gate conductive material layer on a surface of the second gate dielectric material layer and in the second gate hole, and patterning the second gate dielectric material layer and the second gate conductive material layer to form the second gate dielectric layer and the second gate conductive layer.

[0032] In some embodiments, the number of the interlayer insulating dielectric layers is multiple, and the plasma treatment on the multiple interlayer insulating dielectric material layers comprises:

[0033] after the deposition of the upper interlayer insulating dielectric material layer is completed, the plasma treatment is performed on the upper interlayer insulating dielectric material layer, and then the deposition of the next interlayer insulating dielectric material layer is performed, so that the multiple interlayer insulating dielectric material layers are all subjected to the plasma treatment; or

[0034] after the deposition of the multiple interlayer insulating dielectric material layers is completed, the plasma treatment is simultaneously performed on the multiple interlayer insulating dielectric material layers.

[0035] Embodiments of the present application provide a semiconductor structure, which comprises a substrate, and further comprises a first vertical transistor and a second vertical transistor stacked on the substrate, and one or more interlayer insulating dielectric layers between the first vertical transistor and the second vertical transistor; the interlayer insulating dielectric layer is subjected to plasma treatment; wherein the material of at least one of a first channel layer of the first vertical transistor and a second channel layer of the second vertical transistor is metal oxide semiconductor material.

[0036] In some embodiments, the plasma used in the plasma treatment comprises at least one of nitrogen plasma, fluorine plasma, sulfur plasma, and oxygen plasma.

[0037] In some embodiments, the first vertical transistor comprises:

[0038] The first stack structure comprises, from bottom to top, a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer, and a third dielectric layer; the first conductive layer serves as a first electrode of the first vertical transistor, and the second conductive layer serves as a second electrode of the second vertical transistor.

[0039] The first gate hole penetrates through the second dielectric layer, the second conductive layer, and the third dielectric layer, and extends to the first conductive layer.

[0040] The first gate structure fills the first gate hole; the first gate structure comprises a first gate dielectric layer and a first gate conductive layer.

[0041] In some embodiments, the second vertical transistor comprises:

[0042] The second stack structure comprises, from bottom to top, a third conductive layer, a fourth dielectric layer, a fourth conductive layer, and a fifth dielectric layer; the third conductive layer serves as a first electrode of the second vertical transistor, and the fourth conductive layer serves as a second electrode of the second vertical transistor.

[0043] The second gate hole penetrates through the fifth dielectric layer, the fourth conductive layer, and the fourth dielectric layer, and extends to the third conductive layer.

[0044] The second gate structure fills the second gate hole; the second gate structure comprises a second gate dielectric layer and a second gate conductive layer.

[0045] Embodiments of the present application provide an electronic device comprising the semiconductor structure or the semiconductor structure formed by the manufacturing method.

[0046] The present application relates to a semiconductor structure and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor structure comprises: providing a substrate; forming a first vertical transistor on the substrate; depositing one or more layers of interlayer insulating dielectric material layers on the first vertical transistor; performing plasma treatment on the one or more layers of interlayer insulating dielectric material layers to form one or more layers of interlayer insulating dielectric layers; and forming a second vertical transistor on the one or more layers of interlayer insulating dielectric layers; wherein a channel layer of the first vertical transistor and / or the second vertical transistor is a metal oxide semiconductor material. The manufacturing method of the semiconductor structure can improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0048] Figure 1 Flow chart of the method for manufacturing the semiconductor structure provided in an embodiment;

[0049] Figure 2 Cross-sectional structure diagram of the structure obtained in step S10 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0050] Figure 3 Flow chart of step S20 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0051] Figure 4 Cross-sectional structure diagram of the structure obtained in step S201 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0052] Figure 5 Cross-sectional structure diagram of the structure obtained in step S202 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0053] Figure 6 Cross-sectional structure diagram of the structure obtained in step S203 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0054] Figure 7 Flow chart of step S203 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0055] Figure 8 Cross-sectional structure diagram of the structure obtained in step S2031 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0056] Figure 9 Cross-sectional structure diagram of the structure obtained in step S2032 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0057] Figure 10 Cross-sectional structure diagram of the structure obtained in step S2033 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0058] Figure 11 Cross-sectional structure diagram of the structure obtained in step S2034 in the method for manufacturing the semiconductor structure provided in an embodiment;

[0059] Figure 12A cross-sectional view of the structure obtained in step S30 of the method of fabricating a semiconductor structure according to an embodiment;

[0060] Figure 13 A cross-sectional view of the structure before plasma treatment in step S30 of the method of fabricating a semiconductor structure according to another embodiment;

[0061] Figure 14 A cross-sectional view of the structure obtained in step S30 of the method of fabricating a semiconductor structure according to another embodiment;

[0062] Figure 15 A cross-sectional view of the structure obtained in step S40 of the method of fabricating a semiconductor structure according to another embodiment;

[0063] Figure 16 A flow chart of step S40 of the method of fabricating a semiconductor structure according to an embodiment;

[0064] Figure 17 A cross-sectional view of the structure obtained in step S401 of the method of fabricating a semiconductor structure according to an embodiment;

[0065] Figure 18 A cross-sectional view of the structure obtained in step S402 of the method of fabricating a semiconductor structure according to an embodiment;

[0066] Figure 19 A cross-sectional view of the structure obtained in step S403 of the method of fabricating a semiconductor structure according to an embodiment;

[0067] Figure 20 A flow chart of step S403 of the method of fabricating a semiconductor structure according to an embodiment;

[0068] Figure 21 A cross-sectional view of the structure obtained in step S4031 of the method of fabricating a semiconductor structure according to an embodiment;

[0069] Figure 22 A cross-sectional view of the structure obtained in step S4032 of the method of fabricating a semiconductor structure according to an embodiment;

[0070] Figure 23 A cross-sectional view of the structure obtained in step S4033 of the method of fabricating a semiconductor structure according to an embodiment;

[0071] Figure 24 A cross-sectional view of the structure obtained in step S4034 of the method of fabricating a semiconductor structure according to an embodiment.

[0072] Explanation of reference signs: 1-substrate, 2-first vertical transistor, 20-first stack structure, 201-first dielectric layer, 202-first conductive layer, 203-second dielectric layer, 204-second conductive layer, 205-third dielectric layer, 21-first gate structure, 211-first gate hole, 212-first channel layer, 2121-first channel material layer, 213-first gate dielectric layer, 2131-first gate dielectric material layer, 214-first gate conductive layer, 2141-first gate conductive material layer, 30-interlayer insulating dielectric layer, 301-interlayer insulating dielectric material layer, 31-second vertical transistor, 311-second stack structure, 3111-third conductive layer, 3112-fourth dielectric layer, 3113-fourth conductive layer, 3114-fifth dielectric layer, 312-second gate structure, 3121-second gate hole, 3122-second channel layer, 3122a-second channel material layer, 3123-second gate dielectric layer, 3123a-second gate dielectric material layer, 3124-second gate conductive layer, 3124a-second gate conductive material layer. DETAILED DESCRIPTION

[0073] For the purpose of promoting an understanding of the application, the application will be described in greater detail below with reference to the drawings. The embodiments of the application are illustrated in the drawings. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0075] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type or portion discussed below may be represented as the second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0076] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0078] Embodiments of the application are described herein with reference to the drawings, which show schematic cross-sectional views of preferred embodiments (and intermediate structures) of the application, it being contemplated that variations in the shapes shown can occur as a result of, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the application should not be construed as limited to the precise shapes shown herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an implanted region that is shown as a rectangle will typically have rounded or curved features at its edges and / or an implant concentration gradient rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the figures are intended to be schematic only and their shapes are not intended to represent the actual shape of a region of a device and are not intended to limit the scope of the application.

[0079] Referring now to the drawings, wherein like reference numerals refer to similar or identical elements throughout the several views, and initially to FIG. 1, there is shown a semiconductor structure 100 according to an embodiment of the application. The semiconductor structure 100 includes a substrate 110, a first vertical transistor 120, and a second vertical transistor 130. The first vertical transistor 120 is formed on the substrate 110. The second vertical transistor 130 is formed on the first vertical transistor 120. Figure 1 The application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0080] S10: providing a substrate;

[0081] S20: forming a first vertical transistor on the substrate;

[0082] S30: depositing one or more layers of interlayer dielectric material on the first vertical transistor at a predetermined temperature, and performing plasma treatment on the one or more layers of interlayer dielectric material to form one or more layers of interlayer dielectric layer; the predetermined temperature is not higher than 300°C.

[0083] The one or more layers of interlayer dielectric material deposited at a temperature not higher than 300°C have relatively more impurities, but the application is not limited to depositing the interlayer dielectric material at a temperature of 300°C or below. Depositing the interlayer dielectric material at a temperature higher than 300°C to fabricate a 2T stacked transistor according to an embodiment of the application is also within the scope of the application.

[0084] S40: forming a second vertical transistor on the one or more layers of interlayer dielectric layer.

[0085] In some embodiments, when the channel of the underlying transistor is a metal oxide material, the performance of the underlying transistor is relatively obviously improved by using the one or more layers of interlayer dielectric material and performing plasma treatment according to the application.

[0086] In some embodiments, when the channel of the underlying transistor is a metal oxide material, the performance of the underlying transistor is relatively obviously improved by using the one or more layers of interlayer dielectric material and performing plasma treatment according to the application.

[0087] The method for manufacturing the semiconductor structure includes: forming a first vertical transistor on a substrate; depositing one or more layers of interlayer insulating medium material on the first vertical transistor at a preset temperature not greater than 300 DEG C; performing plasma treatment on the one or more layers of interlayer insulating medium material to form one or more layers of interlayer insulating medium; and forming a second vertical transistor on the one or more layers of interlayer insulating medium, wherein the channel layer of the first vertical transistor and the channel layer of the second vertical transistor are both metal oxide semiconductor material. The plasma treatment can effectively improve the impurity ions formed in the interlayer insulating medium material deposited at low temperature, thereby preventing the impurity ions from diffusing into the channel, and improving the performance of the device.

[0088] In addition, the interlayer insulating medium layer obtained after the plasma treatment has better compactness and hardness than the interlayer insulating medium layer without the plasma treatment, thereby further improving the performance of the device.

[0089] In step S10, please refer to Figure 1 and Figure 2 , a substrate 1 is provided.

[0090] The material of the substrate 1 can be a common substrate material, such as a silicon-containing substrate, glass, a flexible substrate, etc.

[0091] For example, the material can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, germanium silicon (silicon germanium), silicon carbide (SiC), carbon germanium silicon (silicon germanium C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including a multilayer structure formed by these semiconductors, etc., or a silicon-on-insulator (SOI), a silicon-on-silicon-on-insulator (SSOI), a silicon-on-silicon germanium-on-insulator (S-silicon germanium OI), a silicon germanium-on-insulator (silicon germanium OI), and a germanium-on-insulator (GeOI), or can also be a double-side polished wafer (DSP), a ceramic substrate such as an aluminum oxide, a quartz or glass substrate, etc. The present embodiment is not limited thereto.

[0092] In step S20, please refer to Figure 1 and Figure 6 , a first vertical transistor 2 is formed on the substrate 1.

[0093] In one embodiment, as shown in Figure 3 , the step S20 includes:

[0094] S201: Form a first stack structure 20 on the substrate 1, the first stack structure 20 comprising a first dielectric layer 201, a first conductive layer 202, a second dielectric layer 203, a second conductive layer 204 and a third dielectric layer 205 which are sequentially stacked from bottom to top.

[0095] As shown in FIG. 2, the first stack structure 20 can be formed on the substrate 1 by a multi-pass deposition process. The multi-pass deposition process can include an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process. Figure 4 As shown in FIG. 2, the first stack structure 20 can be formed on the substrate 1 by a multi-pass deposition process. The multi-pass deposition process can include an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process.

[0096] The first vertical transistor 2 can have a source as the first pole and a drain as the second pole, or the first vertical transistor 2 can have a drain as the first pole and a source as the second pole.

[0097] The first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 can be made of an insulating material, such as silicon oxide, silicon nitride or the like, or other suitable insulating material. In order to reduce the influence of parasitic capacitance, the first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 can be made of an insulating material with a small dielectric constant. The first dielectric layer 201, the second dielectric layer 203 and the third dielectric layer 205 can be made of the same material or different materials.

[0098] The first conductive layer 202 and the second conductive layer 204 can be made of a conductive material, such as titanium nitride, tungsten metal, molybdenum metal or the like, or other suitable conductive material. In order to reduce the influence of parasitic capacitance, the first conductive layer 202 and the second conductive layer 204 can be made of a conductive material with a low resistivity. The first conductive layer 202 and the second conductive layer 204 can be made of the same material or different materials.

[0099] S202: A first gate hole 211 is formed in the first stacked structure 20. The first gate hole 211 penetrates the second dielectric layer 203, the second conductive layer 204 and the third dielectric layer 205, and extends into the first conductive layer 202.

[0100] like Figure 5 As shown, a combination of photolithography and etching can be used to remove part of the first stacked structure 20 to form a first gate hole 211 within the first stacked structure 20.

[0101] S203: A first gate structure 21 is formed in the first gate hole 211, and the first gate structure 21 extends to the upper surface of the first stacked structure 20.

[0102] like Figure 6 As shown, the first gate via 211 penetrates the second dielectric layer 203, the second conductive layer 204, and the third dielectric layer 205, and extends into the first conductive layer 202. Furthermore, the thickness of the second dielectric layer 203 determines the length of the channel of the first vertical transistor 2.

[0103] In one embodiment, such as Figure 7 As shown, step S203 above includes:

[0104] S2031: A first channel material layer 2121 is formed at the bottom of the first gate hole 211, the sidewall of the first gate hole 211, and the upper surface of the first stacked structure 20.

[0105] like Figure 8As shown, the first channel material layer 2121 can be formed using a deposition process. The material of the first channel material layer 2121 can include a metal-oxide-semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal-oxide-semiconductor material is IGZO, the leakage current of the transistor is relatively small (less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the electronic device. It should be noted that the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor meets the requirements. The specific materials can be adjusted according to the actual situation.

[0106] S2032: A first gate dielectric material layer 2131 is formed on the surface of the first channel material layer 2121.

[0107] like Figure 9 As shown, a first gate dielectric material layer 2131 can be formed using a deposition process. The material of the first gate dielectric material layer 2131 may include a high dielectric material, such as at least one of HfO2, Al2O3, HfAlO, and HfLaO.

[0108] S2033: A first gate conductive material layer 2141 is formed on the surface of the first gate dielectric material layer 2131 and inside the first gate hole 211.

[0109] like Figure 10 As shown, the first gate conductive material layer 2141 can be formed using a deposition process. The first gate conductive material layer 2141 may include a conductive material, such as at least one selected from ITO, W, TiN, TiAl, and TaN.

[0110] S2034: remove the part of the first channel material layer 2121, the part of the first gate dielectric material layer 2131 and the part of the first gate conductive material layer 2141 located above the first stack structure 20 and around the first gate hole 211, to form the first channel layer 212, the first gate dielectric layer 213 and the first gate conductive layer 214; wherein the first gate dielectric layer 213 and the first gate conductive layer 214 collectively constitute the first gate structure 21, and the first channel layer 212 serves as the channel layer of the first vertical transistor.

[0111] As shown in Figure 11 , the removal process combining photolithography and etching can be used to remove the part of the first channel material layer 2121, the part of the first gate dielectric material layer 2131 and the part of the first gate conductive material layer 2141, so that the first channel layer 212, the first gate dielectric layer 213 and the first gate conductive layer 214 not only include the part located in the first gate hole 211, but also include the extended part located at the opening of the first gate hole 211, which can prevent impurities in the external environment from directly entering the first gate hole 211.

[0112] In step S30, please refer to Figure 1 and Figure 12 , at a preset temperature, form one or more layers of interlayer insulating dielectric material layers 301 on the first vertical transistor 2, and perform plasma treatment on the one or more layers of interlayer insulating dielectric material layers 301 to form one or more layers of interlayer insulating dielectric layers 30; the preset temperature is not greater than 300°C.

[0113] As shown in Figure 13 , deposition process can be used to form the interlayer insulating dielectric material layer 301, and the deposition process can include PVD, CVD, PECVD or ALD process. The material of the interlayer insulating dielectric material layer 301 can include silicon oxide, silicon nitride, etc. The type of impurity ions can be determined based on the specific deposition process and the material of the interlayer insulating dielectric material layer, which is not limited in the embodiment.

[0114] In related technologies, the formation temperature of the interlayer insulating dielectric material layer 301 is usually between 300°C and 500°C, which is done to prevent the formation of impurity ions in the interlayer insulating dielectric material layer 301 as much as possible under high temperature conditions. However, under high temperature conditions, the channel formed by the metal-oxide semiconductor material of the transistor is unstable, which can cause the transistor to fail easily. For example, in Figure 13 , after the first vertical transistor 2 is formed, before the second vertical transistor 31 is formed, if the interlayer insulating dielectric material layer 301 is formed under high temperature conditions, the first channel layer 212 in the first vertical transistor 2 is unstable, which can easily cause the entire first vertical transistor 2 to fail.

[0115] Therefore, in this embodiment, to ensure the stability of the channel in the transistor, the interlayer insulating dielectric material layer 301 can be formed at a preset temperature not exceeding 300°C during the deposition process. For example, the preset temperature can be between 200°C and 300°C, more specifically, between 230°C and 280°C, such as 250°C. At such a relatively low preset temperature, the stability of the channel layer of the first vertical transistor 2 can be guaranteed. However, compared to high-temperature conditions, the interlayer insulating dielectric material layer 301 formed in this application will contain a relatively large number of impurity ions. Once these impurity ions diffuse into the channel layers of the stacked transistors, the performance of each device structure layer will degrade. Furthermore, the interlayer insulating dielectric material layer 301 formed at a lower preset temperature has lower density, which may allow impurities such as moisture in the environment to enter the channel layer through the interlayer insulating dielectric material layer 301, also easily leading to a degradation in the performance of each device.

[0116] Generally, impurity ions exist in a free state within the interlayer insulating dielectric material layer 301, without being bonded to it. For example, taking PECVD as the deposition process and silicon oxide as the material of the interlayer insulating dielectric material layer 301, the impurity ions within the interlayer insulating dielectric material layer 301 include at least one of carbon ions and hydrogen ions. Carbon ions and / or hydrogen ions exist in a free state within the silicon oxide serving as the interlayer insulating dielectric material layer 301, without being bonded to it.

[0117] like Figure 13 As shown, during the plasma treatment of the interlayer insulating dielectric material layer 301, the plasma reduces or eliminates impurity ions within the interlayer insulating dielectric material layer 301, thereby obtaining the interlayer insulating dielectric layer 30. Furthermore, the interlayer insulating dielectric layer 30 obtained after plasma treatment of the interlayer insulating dielectric material layer 301 exhibits superior density and hardness compared to the interlayer insulating dielectric material layer 301 that has not undergone plasma treatment.

[0118] Therefore, this embodiment can improve the stability of each channel layer when forming the interlayer insulating dielectric material layer 301. At the same time, the use of plasma treatment can reduce or eliminate impurity ions in the interlayer insulating dielectric material layer 301, thereby reducing or preventing the diffusion of impurity ions into the channel.

[0119] Optionally, after step S30, a step of planarizing the upper surface of the interlayer insulating dielectric layer 30 by chemical mechanical polishing (CMP) may be included.

[0120] In one embodiment, the interlayer dielectric material layer 301 before plasma treatment contains impurity ions, which include at least one of carbon ions and hydrogen ions. The step S30 includes: using at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma to perform plasma treatment on the one or more interlayer dielectric material layers 301. Preferably, the nitrogen plasma or fluorine plasma is used to perform plasma treatment on the interlayer dielectric material layer 301.

[0121] In the present embodiment, when at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma is used to perform plasma treatment on the one or more interlayer dielectric material layers 301, at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma can form a bond with at least one of carbon ions and hydrogen ions, thereby inhibiting the diffusion of the impurity ions and improving the device performance.

[0122] In one embodiment, the number of the interlayer dielectric layers 30 is two or three, and the materials of the two or three interlayer dielectric layers 30 are the same or different. For example, the number of the interlayer dielectric layers 30 can be three as shown in FIG. 1. Figure 14

[0123] In one embodiment, the number of the interlayer dielectric layers 30 is multiple, and the step of performing plasma treatment on the multiple interlayer dielectric material layers 301 in the step S30 includes:

[0124] After the deposition of the last interlayer dielectric material layer 301, the last interlayer dielectric material layer 301 is subjected to plasma treatment, and then the deposition of the next interlayer dielectric material layer 301 is performed, so that the multiple interlayer dielectric material layers 301 are all subjected to plasma treatment; or,

[0125] After the deposition of the multiple interlayer dielectric material layers 301, the multiple interlayer dielectric material layers 301 are subjected to plasma treatment.

[0126] After the deposition of each interlayer dielectric material layer 301, the interlayer dielectric material layer 301 is subjected to plasma treatment to reduce or eliminate the impurity ions, and then the growth of the next interlayer dielectric material layer 301 is performed, so that the impurity ions in each interlayer dielectric layer 30 are all reduced or eliminated by plasma. Alternatively, the multiple interlayer dielectric material layers 301 can be formed first, and then subjected to plasma treatment to reduce or eliminate the impurity ions. Meanwhile, the multiple interlayer dielectric layers 30 after plasma treatment all have good compactness and hardness.

[0127] In the step S40, please refer to Figure 1 ​step S40 in the method and Figure 15 The second vertical transistor 31 is formed on the one or more interlayer insulating medium layers 30.

[0128] In one embodiment, as shown in FIG. 4, the step S40 comprises: Figure 16

[0129] S401: Forming a second stack structure 311 on the upper surface of the one or more interlayer insulating medium layers 30, the second stack structure 311 comprising a third conductive layer 3111, a fourth medium layer 3112, a fourth conductive layer 3113 and a fifth medium layer 3114 stacked in order from bottom to top.

[0130] As shown in FIG. 4, the second stack structure 311 can be formed on the substrate 1 by a multi-pass deposition process, the second stack structure 311 comprising a third conductive layer 3111, a fourth medium layer 3112, a fourth conductive layer 3113 and a fifth medium layer 3114 stacked in order from bottom to top. Each pass of the deposition process can comprise an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a Low Pressure Chemical Vapor Deposition (LPCVD) process. Figure 17 The first pole of the second vertical transistor 31 can be the source pole, and the second pole of the second vertical transistor 31 can be the drain pole, or the first pole of the second vertical transistor 31 can be the drain pole, and the second pole of the second vertical transistor 31 can be the source pole.

[0131] The material of the fourth medium layer 3112 and the fifth medium layer 3114 can comprise an insulating material, such as silicon oxide, silicon nitride, etc., or other suitable insulating material. In order to reduce the influence of parasitic capacitance, the fourth medium layer 3112 and the fifth medium layer 3114 can be selected as insulating materials with small dielectric constant as much as possible. The material of the fourth medium layer 3112 and the fifth medium layer 3114 can be the same or different.

[0132]

[0133] ​​The materials of the third conductive layer 3111 and the fourth conductive layer 3113 can be conductive materials, such as titanium nitride, tungsten metal, molybdenum metal, etc., or they can be materials that can conduct electricity after ion doping, or other suitable conductive materials. To reduce the influence of parasitic capacitance, the third conductive layer 3111 and the fourth conductive layer 3113 can be made of conductive materials with low resistivity. The materials of the third conductive layer 3111 and the fourth conductive layer 3113 can be the same or different.

[0134] S402: A second gate hole 3121 is formed in the second stacked structure 311. The second gate hole 3121 penetrates the fifth dielectric layer 3114, the fourth conductive layer 3113, the fourth dielectric layer 3112, and extends into the third conductive layer 3111.

[0135] like Figure 18 As shown, a combination of photolithography and etching can be used to remove part of the second stacked structure 311 to form a second gate hole 3121 within the second stacked structure 311.

[0136] S403: A second gate structure 312 is formed in the second gate hole 3121, and the second gate structure 312 extends to the upper surface of the second stacked structure 311.

[0137] like Figure 19 As shown, the second gate hole 3121 penetrates the fifth dielectric layer 3114, the fourth conductive layer 3113, and the fourth dielectric layer 3112, and extends into the third conductive layer 3111. Furthermore, the thickness of the fourth dielectric layer 3112 determines the length of the channel of the second vertical transistor 31.

[0138] In one embodiment, such as Figure 20 As shown, step S403 above includes:

[0139] S4031: A second channel material layer 3122a is formed at the bottom of the second gate hole 3121, the sidewall of the second gate hole 3121, and the upper surface of the second stacked structure 311.

[0140] like Figure 21 As shown, a second channel material layer 3122a can be formed using a deposition process. The material of the second channel material layer 3122a may be the same as or not exactly the same as the material of the first channel material layer 2121.

[0141] S4032: A second gate dielectric material layer 3123a is formed on the surface of the second channel material layer 3122a.

[0142] like Figure 22As shown, the second gate dielectric material layer 3123a can be formed by using a deposition process. The material of the second gate dielectric material layer 3123a can be the same as or different from the material of the first gate dielectric material layer 2131.

[0143] S4033: Forming a second gate conductive material layer 3124a on the surface of the second gate dielectric material layer 3123a and in the second gate hole 3121.

[0144] As shown, the second gate conductive material layer 3124a can be formed by using a deposition process. The material of the second gate conductive material layer 3124a can be the same as or different from the material of the first gate conductive material layer 2141. Figure 23

[0145] S4034: Removing part of the second channel material layer 3122a, part of the second gate dielectric material layer 3123a and part of the second gate conductive material layer 3124a located above the second stack structure 311 and around the second gate hole 3121 to form a second channel layer 3122, a second gate dielectric layer 3123 and a second gate conductive layer 3124; the second gate dielectric layer 3123 and the second gate conductive layer 3124 together constitute a second gate structure 312, and the second channel layer 3122 serves as a channel layer of a second vertical transistor.

[0146] As shown, part of the second channel material layer 3122a, part of the second gate dielectric material layer 3123a and part of the second gate conductive material layer 3124a can be removed by using a photolithography and etching combined removal process, so that the second channel layer 3122, the second gate dielectric layer 3123 and the second gate conductive layer 3124 not only include the parts located in the second gate hole 3121, but also include extended parts located at the openings of the second gate hole 3121, which can prevent impurities in the external environment from directly entering the second gate hole 3121. Figure 24

[0147] The application further provides a semiconductor structure, which can be formed by using the above process.

[0148] As shown, the semiconductor structure includes a substrate 1, and further includes a first vertical transistor 2 and a second vertical transistor 31 stacked on the substrate 1, and has one or more interlayer insulating dielectric layers 30 between the first vertical transistor 2 and the second vertical transistor 31; the interlayer insulating dielectric layer 30 is deposited at a preset temperature and subjected to plasma treatment; the preset temperature is not greater than 300 DEG C; and the materials of the channel layers of the first vertical transistor 2 and the second vertical transistor 31 are both metal oxide semiconductor materials. Figure 15

[0149] ​​​The semiconductor structure comprises a substrate 1, and further comprises a first vertical transistor 2 and a second vertical transistor 31 stacked on the substrate 1, and one or more interlayer insulating medium layers 30 between the first vertical transistor 2 and the second vertical transistor 31; the interlayer insulating medium layer 30 is deposited at a preset temperature and is subjected to plasma treatment; the preset temperature is not greater than 300 DEG C; and the channel layer of the first vertical transistor 2 and the second vertical transistor 31 is made of metal oxide semiconductor material. The plasma treatment can reduce or eliminate impurity ions in the interlayer insulating medium layer 30, thereby preventing the impurity ions from diffusing into the channel, and improving the device performance.

[0150] In addition, the interlayer insulating medium layer 30 obtained by subjecting the interlayer insulating medium layer 301 to plasma treatment has better compactness and hardness than the interlayer insulating medium layer 301 without plasma treatment, thereby further improving the device performance.

[0151] The application further provides an electronic device comprising the semiconductor structure in any of the above embodiments. The electronic device can comprise a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device or a smart mobile terminal. The plasma treatment can reduce or eliminate impurity ions in the interlayer insulating medium layer deposited at a low temperature between the vertical transistors, and can improve the compactness of the interlayer insulating medium layer, thereby reducing or preventing the impurity ions in the interlayer insulating medium layer from diffusing into the channel, and improving the device performance.

[0152] The technical features of the above embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations of the technical features of the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0153] The above embodiments only express several implementation manners of the application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope. It should be pointed out that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the application, and these all belong to the protection scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The application relates to a vertical transistor structure and a manufacturing method thereof. The application provides a substrate; a first vertical transistor is formed on the substrate; one or more layers of interlayer insulating medium material are deposited on the first vertical transistor, and the one or more layers of interlayer insulating medium material are subjected to plasma treatment to form one or more layers of interlayer insulating medium; a second vertical transistor is formed on the one or more layers of interlayer insulating medium; at least one of a first channel layer of the first vertical transistor and a second channel layer of the second vertical transistor comprises a metal oxide semiconductor material.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The interlayer insulating medium material before the plasma treatment is deposited at a low temperature, the temperature range of the low temperature deposition is not higher than 300 DEG C, the interlayer insulating medium material comprises impurity ions, and the impurity ions comprise at least one of carbon ions and hydrogen ions; the plasma treatment of the one or more layers of interlayer insulating medium material comprises: at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma is used to perform the plasma treatment on the one or more layers of interlayer insulating medium material.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein The number of the interlayer insulating medium layers is two or three; the materials of the two or three layers of interlayer insulating medium layers are the same or not completely the same.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein the first vertical transistor is formed on the substrate, comprising: a first stack structure is formed on the substrate, the first stack structure comprises a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer which are sequentially stacked from bottom to top; a first gate hole is formed in the first stack structure, the first gate hole penetrates through the second dielectric layer, the second conductive layer and the third dielectric layer and extends into the first conductive layer; a first gate structure is formed in the first gate hole.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein before the first gate structure is formed in the first gate hole, further comprising: a first channel material layer is deposited on the bottom of the first gate hole, the sidewall of the first gate hole and the upper surface of the first stack structure, and the first channel material layer is subjected to patterning treatment to form the first channel layer; the first gate structure comprises a first gate dielectric layer and a first gate conductive layer; the first gate structure is formed in the first gate hole, comprising: a first gate dielectric material layer is deposited on the surface of the first channel material layer, a first gate conductive material layer is deposited on the surface of the first gate dielectric material layer and in the first gate hole, and the first gate dielectric material layer and the first gate conductive material layer are subjected to patterning treatment to form the first gate dielectric layer and the first gate conductive layer.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein the second vertical transistor is formed on the one or more layers of interlayer insulating medium, comprising: a second stack structure is formed on the upper surface of the one or more layers of interlayer insulating medium, the second stack structure comprises a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer which are sequentially stacked from bottom to top; a second gate hole is formed in the second stack structure, the second gate hole penetrates through the fifth dielectric layer, the fourth conductive layer, the fourth dielectric layer and extends into the third conductive layer; a second gate structure is formed in the second gate hole.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein Before forming the second gate structure in the second gate hole, further comprising: forming a second channel material layer on the bottom of the second gate hole, the sidewall of the second gate hole and the upper surface of the second stack structure, and patterning the second channel material layer to form the second channel layer; the second gate structure comprises a second gate dielectric layer and a second gate conductive layer; forming the second gate structure in the second gate hole comprises: forming a second gate dielectric material layer on the surface of the second channel material layer; forming a second gate conductive material layer on the surface of the second gate dielectric material layer and in the second gate hole; and patterning the second gate dielectric material layer and the second gate conductive material layer to form the second gate dielectric layer and the second gate conductive layer.

8. The method of manufacturing a semiconductor structure according to claim 1, wherein The number of the interlayer insulating dielectric layers is multiple, and the plasma treatment on the multiple interlayer insulating dielectric material layers comprises: after the deposition of the last interlayer insulating dielectric material layer is completed, the plasma treatment is performed on the last interlayer insulating dielectric material layer, and then the deposition of the next interlayer insulating dielectric material layer is performed, so that the plasma treatment is performed on the multiple interlayer insulating dielectric material layers; or after the deposition of the multiple interlayer insulating dielectric material layers is completed, the plasma treatment is simultaneously performed on the multiple interlayer insulating dielectric material layers.

9. A semiconductor structure, characterized by The semiconductor structure comprises a substrate, and further comprises a first vertical transistor and a second vertical transistor stacked on the substrate, and the first vertical transistor and the second vertical transistor have one or more interlayer insulating dielectric layers therebetween; the interlayer insulating dielectric layer is subjected to plasma treatment; wherein the material of at least one of the first channel layer of the first vertical transistor and the second channel layer of the second vertical transistor is metal oxide semiconductor material.

10. The semiconductor structure of claim 9, wherein, The plasma used in the plasma treatment comprises at least one of nitrogen plasma, fluorine plasma, sulfur plasma and oxygen plasma.

11. The semiconductor structure of claim 9, wherein, The first vertical transistor comprises: a first stack structure comprising a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer and a third dielectric layer stacked in order from bottom to top; the first conductive layer serves as a first electrode of the first vertical transistor, and the second conductive layer serves as a second electrode of the second vertical transistor; a first gate hole penetrating through the second dielectric layer, the second conductive layer and the third dielectric layer and extending to the first conductive layer; a first gate structure filling the first gate hole; the first gate structure comprises a first gate dielectric layer and a first gate conductive layer.

12. The semiconductor structure of claim 9, wherein, The second vertical transistor comprises: a second stack structure comprising a third conductive layer, a fourth dielectric layer, a fourth conductive layer and a fifth dielectric layer stacked in order from bottom to top; the third conductive layer serves as a first electrode of the second vertical transistor, and the fourth conductive layer serves as a second electrode of the second vertical transistor; a second gate hole penetrating through the fifth dielectric layer, the fourth conductive layer and the fourth dielectric layer and extending to the third conductive layer; A second gate structure fills the second gate hole; the second gate structure includes a second gate dielectric layer and a second gate conductive layer.

13. An electronic device, comprising: The electronic device includes the semiconductor structure of any of claims 9-12.

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