Method for forming semiconductor device
By covering the metal layer on the surface of the semiconductor structure and doping silicon, a thicker self-aligned silicide layer is formed during the annealing process, which solves the problem of thickening of the self-aligned silicide layer in the prior art, resulting in the downward movement of the lower surface and excessive contact resistance, and achieves a higher top surface position of the self-aligned silicide layer and better contact plug performance.
Patent Information
- Application Number
- CN202311305709.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-10
- Publication Date
- 2025-04-15
AI Technical Summary
When the prior art thickens the self-aligned silicide layer, it is easy to cause its lower surface to move downward, affecting device reliability. Moreover, the self-aligned silicide layer formed on the source/drain region surface of the NMOS transistor is thin, resulting in excessive contact resistance of the contact plug, affecting device reliability.
By covering the metal layer on the surface of the semiconductor structure and doping silicon in the silicon-containing conductive region, annealing is performed to react the metal layer with silicon in the silicon-containing conductive region and silicon doped in the metal layer to form a thicker self-aligned silicide layer. Optionally, pre-amorphic ion implantation is performed in the silicon-containing conductive region to form an amorphous silicon-rich region to limit the range of the silicification reaction.
It is achieved without affecting the reliability of the device, thickening the self-aligned silicide layer, improving the position of its top surface relative to the silicon-containing conductive region, expanding the process window of the contact hole, reducing the risk of the contact plug passing through the self-aligned silicide layer, and improving the contact area and contact resistance of the contact plug.
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Figure CN119835994A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for forming a semiconductor device. Background Art
[0002] In the existing self-aligned silicide manufacturing process, a metal layer (such as nickel) is covered on the surface of the substrate, and then annealing is performed to react the silicon-containing conductive area (such as the source area, the drain area or the polysilicon gate) covered by the metal layer to form a self-aligned silicide layer. The self-aligned silicide layer is mainly formed below the interface between the metal layer and the silicon-containing conductive area.
[0003] By using the above existing process, a self-aligned silicide layer can be formed on the source region, the drain region and the surface of the polysilicon gate of the NMOS transistor and the PMOS transistor on the same substrate. However, research has found that in a 40nm process, the thickness of the self-aligned silicide layer in the source / drain region of the NMOS transistor is different from that in the source / drain region of the PMOS transistor, wherein the self-aligned silicide layer formed on the surface of the source / drain region of the NMOS transistor is usually thinner. Furthermore, when making contact plugs connected to the source / drain regions respectively, on the one hand, the contact area between the contact plug formed corresponding to the source / drain region of the NMOS transistor and the self-aligned silicide layer may be insufficient, resulting in a large contact resistance. On the other hand, the process window for the contact plug formed corresponding to the source / drain region of the NMOS transistor to contact the thinner self-aligned silicide layer without penetrating the self-aligned silicide layer is very small, and the process difficulty is high. After the contact plug penetrates the corresponding self-aligned silicide layer, the contact plug forms direct contact with the source / drain region of the NMOS transistor, resulting in excessive contact resistance between the contact plug and the substrate, affecting device reliability.
[0004] Although the reaction amount between the metal layer and silicon can be increased by thickening the metal layer in the self-aligned silicide formation process to achieve the effect of thickening the self-aligned silicide layer, since the self-aligned silicide layer formed by the above-mentioned self-aligned silicide manufacturing process is mainly formed below the interface between the metal layer and the silicon-containing conductive region, the thickening of the self-aligned silicide layer will be reflected in the downward movement of its lower surface toward the silicon-containing conductive region (such as the polysilicon gate and the source region and the drain region), there is a risk of destroying the doping in the corresponding silicon-containing conductive region, affecting the performance of the corresponding silicon-containing conductive region, and easily causing the reliability of the device to deteriorate.
[0005] The aforementioned problems caused by the thin salicide layer formed on the surface of the source / drain region of the NMOS transistor (such as the problem that the contact plug easily penetrates the salicide layer, and the problem of excessive contact resistance caused by the insufficient contact area between the contact plug and the salicide layer or the contact plug penetrating the salicide layer and directly contacting the source / drain region) may also exist for other silicon-containing conductive regions on the substrate (such as the source / drain region of the PMOS transistor). In general, there is still a need to thicken the salicide layer, and at the same time, the lower surface of the salicide layer should be prevented from moving downward to affect the reliability of the device. Summary of the invention
[0006] In order to avoid affecting device reliability while increasing the thickness of a salicide layer, the present invention provides a method for forming a semiconductor device.
[0007] In one aspect, the present invention provides a method for forming a semiconductor device, the method comprising:
[0008] Providing a semiconductor structure having a plurality of silicon-containing conductive regions whose top surfaces are exposed;
[0009] Covering the surface of the semiconductor structure with a metal layer for reacting with silicon;
[0010] doping silicon in a portion of the metal layer covering the silicon-containing conductive region; and
[0011] Annealing is performed to make the metal layer react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer, so as to form a self-aligned silicide layer on the surface area of the silicon-containing conductive region.
[0012] Optionally, before the surface of the semiconductor structure is covered with a metal layer for reacting with silicon, the forming method further comprises:
[0013] Pre-amorphization ion implantation is performed on at least one of the silicon-containing conductive regions to form an amorphized silicon-rich region on the surface of the silicon-containing conductive region, wherein the amorphized silicon-rich region is used to react with the metal layer.
[0014] Optionally, the pre-amorphization ion implantation is maskless ion implantation.
[0015] Optionally, performing annealing to make the metal layer react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer, and forming a self-aligned silicide layer on the surface area of the silicon-containing conductive region comprises:
[0016] Performing a first annealing process to cause the metal layer to initially react with the silicon in the amorphized silicon-rich region and the silicon doped in the metal layer;
[0017] removing the unreacted metal layer; and
[0018] A second annealing process is performed to allow the product of the preliminary reaction to further react with silicon in the amorphized silicon-rich region and silicon doped in the metal layer to form the salicide layer.
[0019] Optionally, doping silicon in a portion of the metal layer covering the silicon-containing conductive region comprises:
[0020] forming a patterned mask layer on the metal layer, an opening in the mask layer being formed above the silicon-containing conductive region; and
[0021] The mask layer is used as an implantation mask to perform ion implantation to implant silicon into the metal layer.
[0022] Optionally, the semiconductor structure comprises:
[0023] a substrate including an active region; and
[0024] At least one MOS transistor is formed on the surface of the active area, the MOS transistor includes a polysilicon gate formed on the active area, a sidewall formed on the side of the polysilicon gate, and a source region and a drain region formed in the active area and located on both sides of the polysilicon gate, respectively, and the silicon-containing conductive area includes the polysilicon gate, the source region and the drain region.
[0025] Optionally, a distance between a sidewall of an opening in the mask layer above the source region and an adjacent sidewall is greater than 0, and a distance between a sidewall of an opening in the mask layer above the drain region and an adjacent sidewall is greater than 0.
[0026] Optionally, a longitudinal section of the self-aligned silicide layer formed on the surface areas of the source region and the drain region is in a convex shape.
[0027] Optionally, after forming the self-aligned silicide layer on the surface region of the silicon-containing conductive region, the forming method further comprises:
[0028] Covering the semiconductor structure and the salicide layer with an etch stop layer, and covering the etch stop layer with an interlayer dielectric layer;
[0029] forming a contact hole penetrating the interlayer dielectric layer, wherein the contact hole is formed corresponding to the silicon-containing conductive region and exposes a portion of the surface of the etch stop layer;
[0030] etching the etch stop layer exposed by the contact hole to deepen the contact hole so that the contact hole exposes the salicide layer; and
[0031] The contact hole is filled with a conductive material to form a contact plug.
[0032] Optionally, an exposure range of the contact hole formed above the same silicon-containing conductive region is smaller than an exposure range of the opening in the mask layer.
[0033] Optionally, before silicon is doped into the portion of the metal layer covering the silicon-containing conductive region, a titanium nitride layer is further covered on the surface of the metal layer.
[0034] Optionally, the thickness of the salicide layer is greater than or equal to
[0035] In the method for forming a semiconductor device provided by the present invention, silicon is doped in the portion of the metal layer covering the silicon-containing conductive region, so that when annealing is performed, the metal layer reacts with both the silicon in the silicon-containing conductive region and the silicon doped in the metal layer, that is, the metal silicidation reaction is performed both in the silicon-containing conductive region and in the metal layer, so that a thicker self-aligned silicide layer can be obtained. Compared with the situation in the prior art where the metal layer only reacts with the silicon in the silicon-containing conductive region, the present invention mainly increases the thickness of the self-aligned silicide layer due to the silicidation reaction in the metal layer. Compared with the prior art, the top surface of the self-aligned silicide layer is higher than the silicon-containing conductive region, and the impact on the silicon-containing conductive region is small. When forming a contact hole exposing the self-aligned silicide layer, the process window is larger, which reduces the risk that the bottom of the contact hole penetrates the self-aligned silicide layer and affects the reliability of the device.
[0036] Furthermore, before the surface of the semiconductor structure is covered with a metal layer for reacting with silicon, the silicon-containing conductive region can be pre-amorphized by ion implantation to form an amorphized silicon-rich region on the surface of the silicon-containing conductive region. The amorphized silicon-rich region is used to react with the metal layer and has the effect of limiting the scope of the silicidation reaction, so that the portion of the self-aligned silicide layer formed in the silicon-containing conductive region is located within the scope of the amorphized silicon-rich region, thereby further reducing the influence of the self-aligned silicide layer on the performance of the silicon-containing conductive region and avoiding affecting the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 It is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention.
[0038] Figures 2A to 2M is a schematic cross-sectional view of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0039] The following is a further detailed description of the method for forming a semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.
[0040] In the semiconductor manufacturing process, a self-aligned silicide layer (salicide) can be formed on the surface of exposed silicon-containing conductive areas such as source areas, drain areas, and polysilicon gates by utilizing the characteristics that metals such as nickel, titanium, or cobalt can react with silicon but not with materials such as silicon oxide, silicon nitride, or silicon nitride oxide. Common self-aligned silicides include nickel silicide (NiSi), titanium silicide (TiSi2), and cobalt silicide (CoSi2).
[0041] Research has found that due to the different doping ions of the source / drain region of the NMOS transistor and the source / drain region of the PMOS transistor, when a self-aligned silicide layer is formed on the surface of the source / drain region of the NMOS transistor and the PMOS transistor on the same substrate, the different doping conditions of the source / drain region will have different effects on the diffusion of metal atoms, which will in turn cause the thickness of the self-aligned silicide layer formed on the surface of the source / drain region of the NMOS transistor to be thin; however, the contact plug formed on the source / drain region and the self-aligned silicide layer need to form a sufficient contact area to ensure that the contact resistance between the two is not too large, otherwise it will affect the device performance. A further impact caused by the thin thickness of the self-aligned silicide layer on the surface of the source / drain region of the NMOS transistor is that when contact holes are formed corresponding to the source / drain regions on the substrate to make contact plugs, the process window in which the contact holes formed corresponding to the source / drain regions of the NMOS transistor expose the corresponding self-aligned silicide layer but do not penetrate the self-aligned silicide layer is very small, and the process difficulty is high. When the contact hole passes through the thinner self-aligned silicide layer, the corresponding contact plug is in direct contact with the source / drain region of the NMOS transistor, resulting in excessive contact resistance and poor device reliability.
[0042] The embodiment of the present invention relates to a method for forming a semiconductor device, which can prevent the lower surface of the self-aligned silicide layer from being too low and affecting the reliability of the device while thickening the self-aligned silicide layer. Figures 1 to 2MA method for forming a semiconductor device according to an embodiment of the present invention is described in detail.
[0043] Reference Figure 1 and Figure 2A , performing step S1, providing a semiconductor structure 10, wherein the semiconductor structure 10 has a plurality of silicon-containing conductive regions with exposed top surfaces.
[0044] The semiconductor structure 10 may include a substrate 100 and electronic components formed in the surface area of the substrate 100. The substrate 100 includes silicon. The substrate 100 is, for example, a silicon substrate or an SOI (Silicon On Insulator) substrate, or the substrate 100 is a stack of other semiconductor layers of different types and a silicon layer (for example, a stack of a silicon germanium layer and a silicon layer). The electronic components formed in the surface area of the substrate 100 may include at least one of a MOS transistor, a sensor device, a memory device and a passive device. The sensor device may be a photosensitive device, etc. The memory device may include a non-volatile memory or a random access memory, etc. The passive device may include a resistor or a capacitor, etc. An active area and an isolation area for isolating the active area may be provided in the substrate 100. The substrate 100 may also be implanted with certain doping ions to change electrical parameters according to design requirements.
[0045] The top surfaces of the plurality of silicon-containing conductive regions in the semiconductor structure 10 are exposed so as to form a self-aligned silicide layer on the surface regions of the plurality of silicon-containing conductive regions using the method described in this embodiment. As an example, the semiconductor structure 10 includes a substrate 100 and at least one MOS transistor formed on the surface region of the substrate 100. Further, the substrate 100 includes an active region, at least one NMOS transistor and at least one PMOS transistor are formed on the surface of the corresponding active region, and each of the MOS transistors includes a gate dielectric layer 101 and a polysilicon gate G formed on the corresponding active region, a sidewall SP formed on the side of the gate dielectric layer 101 and the polysilicon gate G, and a source region S and a drain region D formed in the active region on both sides of the polysilicon gate G, respectively. Figure 2A As an example, two NMOS transistors with a common source region S are shown. It should be understood that Figure 2A Only a part of the semiconductor structure 10 is shown. In other areas of the semiconductor structure 10, PMOS transistors or other types of electronic components may be formed. The silicon-containing conductive region in the PMOS transistor may be exposed or covered by a silicide barrier layer so as not to be exposed.
[0046] In this embodiment, the multiple silicon-containing conductive regions in the semiconductor structure 10 include a source region S, a drain region D and a polysilicon gate G of at least one MOS transistor formed in the surface area of the substrate 100, and the top surfaces of the source region S, the drain region D and the polysilicon gate G are exposed.
[0047] Reference Figure 2B In a preferred embodiment, before step S2, at least one of the silicon-containing conductive regions is pre-amorphized by ion implantation to form an amorphized silicon-rich region 11 on the surface of the silicon-containing conductive region, and the amorphized silicon-rich region 11 is used to react with a metal layer subsequently covering the surface thereof.
[0048] As an example, the pre-amorphization ion implantation is maskless ion implantation, that is, the pre-amorphization ion implantation is performed on the surface of the semiconductor structure 10. When performing the pre-amorphization ion implantation, the implantation depth and implantation amount can be controlled by controlling the energy and dose used. For example, the implantation energy used is 1keV to 3keV, and the implantation dose is 1E14 / cm 2 ~1E14 / cm 2 . Silicon is implanted into the surface layer of the semiconductor structure 10 by means of pre-amorphization ion implantation, and an amorphized silicon-rich region 11 is formed on the surface layer of the silicon-containing conductive region (such as the source region S, the drain region D and the polysilicon gate G of the MOS transistor). In this embodiment, no mask is used when performing the pre-amorphization ion implantation, and silicon is implanted into the sidewall SP in addition to the silicon-containing conductive region. In other embodiments, a mask may also be used for pre-amorphization ion implantation, so that the amorphized silicon-rich region 11 is formed only on the surface layer of the silicon-containing conductive region.
[0049] Through pre-amorphization ion implantation, the surface layer of the substrate 100 and the polysilicon gate G can be amorphized. When the silicon in the silicon-containing conductive region is subsequently reacted with the metal layer, the amorphized silicon-rich region 11 is conducive to metal diffusion and thus accelerates the silicidation reaction. Amorphization causes the structure in the substrate 100 to become loose, making the amorphized region easier to react with the metal than the non-amorphized region, and provides more silicon sources, so that the silicidation reaction mainly occurs within the range of the amorphized silicon-rich region 11. Therefore, through the pre-amorphization ion implantation, the amorphized silicon-rich region 11 formed has the effect of limiting the range of the silicidation reaction. By limiting the range of the silicidation reaction, the silicidation reaction can be prevented from affecting the silicon-containing conductive region (such as the source region S and the drain region D of the MOS transistor) below the amorphized silicon-rich region 11. Since the amorphized silicon-rich region 11 is formed shallowly, the damage to the doping performance of the silicon-containing conductive region can be reduced, thereby ensuring the performance of the silicon-containing conductive region.
[0050] Reference Figure 1 and Figure 2C, performing step S2 , covering the surface of the semiconductor structure 10 with a metal layer 110 for reacting with silicon.
[0051] The metal layer 110 provides the metal material required to form a self-aligned silicide layer, and the metal material is used to react with silicon. For example, the metal layer 110 includes at least one metal selected from nickel (Ni), titanium (Ti), cobalt (Co), tantalum (Ta) and tungsten (W). As an example, the metal layer 110 uses a NiPt alloy, which is less active than nickel (Ni) to facilitate limiting the diffusion of the silicide reaction in the silicon-containing conductive area. The metal layer 110, for example, conformally covers the surface of the semiconductor structure 10, including each exposed silicon-containing conductive area and other areas in the semiconductor structure 10. The thickness of the metal layer 110 can be set as needed.
[0052] like Figure 2B As shown, optionally, after the metal layer 110 is formed on the surface of the semiconductor structure 10, a titanium nitride layer 120 (TiN) is stacked on the surface of the metal layer 110. The titanium nitride layer 120 has the function of protecting the metal layer 110, which can prevent the metal layer 110 from being oxidized (oxidation of the metal layer 110 will affect the diffusion of metal atoms). The titanium nitride layer 120 can also prevent the metal layer 110 from flowing during subsequent annealing, thereby reducing the risk of uneven thickness of the self-aligned silicide layer and corresponding uneven local resistance value caused by the flow of the metal layer 110. The titanium nitride layer 120, for example, conformally covers the surface of the metal layer 110.
[0053] Reference Figure 1 Then, step S3 is performed to dope silicon in the portion of the metal layer 110 covering the silicon-containing conductive region.
[0054] Specifically, Figure 2D As shown, a patterned mask layer 130 is first formed on the semiconductor structure 10, and an opening in the mask layer 130 is formed above the silicon-containing conductive region, thereby exposing a portion of the surface of the titanium nitride layer 120. When the titanium nitride layer 120 is not formed on the metal layer 110, the opening in the mask layer 130 exposes the metal layer 110 covering the surface of the silicon-containing conductive region.
[0055] The mask layer 130 may be formed by a photoresist layer or a stack of a bottom anti-reflective layer (BARC) and a photoresist layer. As an example, the mask layer 130 is a photoresist layer. When patterning, a photoresist is first applied on the semiconductor structure 10, and then an exposure process is performed to define the area where the opening is to be formed, and then development is performed to form an opening in the photoresist layer. In this embodiment, the silicon-containing conductive region in the semiconductor structure 10 includes a source region S, a drain region D and a polysilicon gate G of at least one MOS transistor. The openings in the mask layer 130 are formed above the polysilicon gate G, the source region S and the drain region D, respectively. In order to avoid silicon implantation of the sidewall SP, the sidewall SP of the MOS transistor is covered by the mask layer 130.
[0056] In this embodiment, the width of the opening formed in the mask layer 130 corresponding to the source region S is smaller than the width of the gap between adjacent sidewalls SP located on the corresponding source region S, and the width of the opening formed in the mask layer 130 corresponding to the drain region D is smaller than the width of the gap between adjacent sidewalls SP located on the corresponding drain region D. The spacing between the sidewall of the opening formed in the mask layer 130 corresponding to the source region S and the adjacent sidewall SP (for example, the sidewall SP located on the same side of the corresponding source region S as the sidewall) is greater than 0, for example, greater than or equal to 10nm. The spacing between the sidewall of the opening formed in the mask layer 130 corresponding to the drain region D and the adjacent sidewall SP (for example, the sidewall SP located on the same side of the corresponding drain region D as the sidewall) is greater than 0, for example, greater than or equal to 10nm. The width of the opening formed in the mask layer 130 corresponding to the source region S is smaller than the width of the amorphous silicon-rich region 11 formed on the surface of the corresponding source region S. The width of the opening formed in the mask layer 130 corresponding to the drain region D is smaller than the width of the amorphous silicon-rich region 11 formed on the surface of the corresponding drain region D.
[0057] like Figure 2E and Figure 2F As shown, the mask layer 130 is used as an implantation mask to perform an ion implantation process, implanting silicon into the metal layer 110, and forming a silicon-doped metal region 111 in the metal layer 110. The ion implantation process uses silicon as an implant, and a certain concentration of silicon doping can be formed within a certain depth range in the metal layer 110 by adjusting the implantation energy and dose. Since the metal layer 110 is covered by the titanium nitride layer 120, silicon may also be implanted into the titanium nitride layer 120 after the ion implantation process, which does not affect the protective effect of the silicon nitride layer 120 on the metal layer 110. After completing the ion implantation process, the mask layer 130 is removed, as shown in FIG. Figure 2F shown.
[0058] In this embodiment, since the width of the opening formed in the mask layer 130 corresponding to the source region S and the drain region D is smaller than the width of the corresponding amorphous silicon-rich region 11, the width of the silicon-doped metal region 111 formed in the metal layer 110 is smaller than the width of the amorphous silicon-rich region 11 located on the surface of the source region S or the drain region D below.
[0059] Reference Figure 1 , executing step S4, performing annealing to make the metal layer 110 react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer 110, and forming a self-aligned silicide layer on the surface area of the silicon-containing conductive region.
[0060] Specifically, annealing is performed to allow the metal atoms and silicon atoms in the metal layer 110 to diffuse and react with each other, wherein the silicon doped in the metal layer 110 can react with the surrounding metal atoms, and the silicon in the silicon-containing conductive region (more specifically, the silicon in the amorphous silicon-rich region 11) diffuses and reacts with the metal atoms in the metal layer 110.
[0061] Research has found that although only one annealing can make the nickel (Ni) in the NiPt layer react with silicon, the temperature required for only one annealing is relatively high, and the nickel silicide (NiSi) formed by direct diffusion and reaction of nickel and silicon has the problem of difficulty in controlling the morphology. To facilitate process control, this embodiment adopts a method of two annealings in step S4, which may specifically include the following process.
[0062] First, a first annealing process is performed to allow the metal layer 110 to initially react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer 110. Figure 2G In this embodiment, after the first annealing process, the nickel in the metal layer 110 reacts with the silicon in the amorphous silicon-rich region 11, and a first NiSi2 layer 102a with high impedance is formed on the top of the silicon-containing conductive region (such as the source region S, the drain region D and the polysilicon gate G of the MOS transistor), and the lower surface of the first NiSi2 layer 102a is lower than the interface between the metal layer 110 and the silicon-containing conductive region (such as the interface Figure 2GIndicated by the dotted line in the middle, it refers to the interface between the two before annealing, the same below). In addition, the nickel in the metal layer 110 also directly reacts with the internally doped silicon to form a second NiSi2 layer 102b on the first NiSi2 layer 102a. In this embodiment, since the width of the silicon-doped metal region 111 formed in the metal layer 110 is smaller than the width of the amorphous silicon-rich region 11 located on the surface of the source region S or the drain region D below, the width of the first NiSi2 layer 102a formed in the source region S and the drain region D is greater than the width of the second NiSi2 layer 102b, and the first NiSi2 layer 102a is exposed from both ends of the second NiSi2 layer 102b above. The longitudinal section of the stacked structure of the first NiSi2 layer 102a and the second NiSi2 layer 102b formed in the surface area of the source region S and the drain region D is a convex shape that is narrow at the top and wide at the bottom.
[0063] Next, refer to Figure 2H , remove the unreacted metal layer 110. In this embodiment, since the metal layer 110 is covered by the titanium nitride layer 120, the titanium nitride layer 120 can be removed first and then the unreacted metal layer 110 can be removed.
[0064] Afterwards, a second annealing process is performed to allow the product of the preliminary reaction to further react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer 110 to form a self-aligned silicide layer 140. The second annealing process is, for example, rapid thermal annealing, and its annealing temperature is, for example, greater than the annealing temperature of the first annealing process.
[0065] Reference Fig.2I In this embodiment, after the second annealing process, the first NiSi2 layer 102a and the second NiSi2 layer 102b formed on the surface of the silicon-containing conductive region further react with silicon to generate a NiSi layer with lower impedance. Compared with the one-time annealing, the NiSi layer formed by the two-time annealing process has a better morphology, and the NiSi layer is used as a self-aligned silicide layer 140. The longitudinal section of the self-aligned silicide layer 140 formed on the surface of the source region S and the drain region D is a convex shape with a narrow top and a wide bottom.
[0066] In step S4, the metal atoms in the metal layer 110 react with the silicon in the silicon-containing conductive region and the doped silicon in the metal layer 110, that is, the metal silicidation reaction is carried out in the metal layer 110 and the silicon-containing conductive region and in the metal layer 110, so that a thicker self-aligned silicide layer 140 can be obtained. Optionally, the thickness of the self-aligned silicide layer 140 formed on the surface area of the silicon-containing conductive region is greater than or equal to
[0067] The embodiment of the present invention may further form a contact plug electrically connected to the silicon-containing conductive region on the semiconductor structure 10, which may specifically include the following process:
[0068] First, refer to Figure 2J , covering the semiconductor structure 10 and the self-aligned silicide layer 140 with an etch stop layer 103 and an interlayer dielectric layer 104 stacked on the surface of the etch stop layer 103. As an example, the etch stop layer 103 is made of silicon nitride, and the interlayer dielectric layer 104 is made of silicon oxide;
[0069] Next, refer to Figure 2K , forming a contact hole 30 penetrating the interlayer dielectric layer 104, wherein the contact hole 30 is formed above the silicon-containing conductive region and exposes a portion of the surface of the etch stop layer 103;
[0070] Afterwards, refer to Figure 2L , the etch stop layer 103 exposed by the contact hole 30 is etched to deepen the contact hole 30 so that the contact hole 30 exposes the self-aligned silicide layer 140. When etching the etch stop layer 103, the contact hole 30 can be exposed without penetrating the self-aligned silicide layer 140 by controlling the degree of over-etching. Therefore, when the self-aligned silicide 140 is higher than the surface of the substrate 100 compared with the prior art, the etch stop layer 103 is also higher than the position of the etch stop layer in the prior art, so the position of the bottom of the contact hole 30 is also higher than the bottom position of the contact hole formed in the prior art, further reducing the depth of the contact hole 30 into the substrate 100, and reducing the risk of the contact plug CT being inserted into the substrate 100 and piercing the self-aligned silicide layer 140. Optionally, the exposure range of the contact hole 30 formed on the same silicon-containing conductive region is smaller than the exposure range of the opening in the mask layer 130, and after the salicide layer 140 is exposed, the bottom surface of the contact hole 30 is the top surface of the salicide layer 140;
[0071] Next, refer to Figure 2M , a conductive material is filled in the contact hole 30 to form a contact plug CT, and the contact plug CT is electrically connected to the corresponding silicon-containing conductive region (such as the source region S, drain region D or polysilicon gate G of the MOS transistor) through the self-aligned silicide layer 140.
[0072] In this embodiment, since the metal silicide reaction is carried out in the metal layer 110 in addition to the silicon-containing conductive region, the top surface of the self-aligned silicide layer 140 is higher than the silicon-containing conductive region compared with the prior art, the total thickness is increased, and there is no problem of excessive penetration of the self-aligned silicide layer 140 into the silicon-containing conductive region (such as the source region S and the drain region D of the NMOS transistor), which can avoid affecting the doping state of the silicon-containing conductive region, and thus has little impact on the performance of the silicon-containing conductive region. In addition, before the surface of the semiconductor structure 10 is covered with the metal layer 110, the silicon-containing conductive region can be pre-amorphized ion implanted to form an amorphized silicon-rich region 11 on the surface of the silicon-containing conductive region. The amorphized silicon-rich region 11 has the function of limiting the scope of the silicide reaction, so that the part of the self-aligned silicide layer 140 formed in the silicon-containing conductive region is located within the scope of the amorphized silicon-rich region 11, which can further reduce the impact of the self-aligned silicide layer 140 on the performance of the silicon-containing conductive region and avoid affecting the device reliability.
[0073] By using the above method, the top surface of the self-aligned silicide layer 140 is higher than the silicon-containing conductive region compared with the prior art. When forming the contact hole 30 exposing the self-aligned silicide layer 140, the process window is larger, which can prevent the bottom of the contact hole 30 from penetrating the self-aligned silicide layer 140; and the top surface of the self-aligned silicide layer 140 exposed by the contact hole 30 is also higher than that of the prior art. After the contact plug CT is formed corresponding to the contact hole 30, the bottom of the contact plug CT is higher than the silicon-containing conductive region compared with the prior art. Therefore, the risk of the contact plug CT penetrating the self-aligned silicide layer 140 is reduced. Moreover, the longitudinal section of the self-aligned silicide layer 140 formed on the surface areas of the source region S and the drain region D has a wider lower portion and a narrower upper portion, that is, a convex shape. The wider lower portion can further reduce the risk of the contact plug CT penetrating the self-aligned silicide layer 140. The contact plug CT can easily form a sufficient contact area with the salicide layer 140 to achieve good ohmic contact, which can reduce contact resistance and help improve device performance.
[0074] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: include: Providing a semiconductor structure having a plurality of silicon-containing conductive regions whose top surfaces are exposed; Covering the surface of the semiconductor structure with a metal layer for reacting with silicon; doping silicon in a portion of the metal layer covering the silicon-containing conductive region; as well as Annealing is performed to make the metal layer react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer, so as to form a self-aligned silicide layer on the surface area of the silicon-containing conductive region.
2. The forming method according to claim 1, characterized in that: Before the surface of the semiconductor structure is covered with a metal layer for reacting with silicon, the method further comprises: Pre-amorphization ion implantation is performed on at least one of the silicon-containing conductive regions to form an amorphized silicon-rich region on the surface of the silicon-containing conductive region, wherein the amorphized silicon-rich region is used to react with the metal layer.
3. The forming method according to claim 2, characterized in that: The pre-amorphization ion implantation is maskless ion implantation.
4. The forming method according to claim 2, characterized in that: Annealing is performed to make the metal layer react with the silicon in the silicon-containing conductive region and the silicon doped in the metal layer, and forming a self-aligned silicide layer in the surface area of the silicon-containing conductive region, comprising: Performing a first annealing process to cause the metal layer to initially react with the silicon in the amorphized silicon-rich region and the silicon doped in the metal layer; removing the unreacted metal layer; and A second annealing process is performed to allow the product of the preliminary reaction to further react with silicon in the amorphized silicon-rich region and silicon doped in the metal layer to form the salicide layer.
5. The forming method according to claim 1, characterized in that: Doping silicon in a portion of the metal layer covering the silicon-containing conductive region comprises: forming a patterned mask layer on the metal layer, an opening in the mask layer being formed above the silicon-containing conductive region; and The mask layer is used as an implantation mask to perform ion implantation to implant silicon into the metal layer.
6. The forming method according to claim 5, characterized in that: The semiconductor structure comprises: a substrate including an active region; and At least one MOS transistor is formed on the surface of the active area, the MOS transistor includes a polysilicon gate formed on the active area, a sidewall formed on the side of the polysilicon gate, and a source region and a drain region formed in the active area and located on both sides of the polysilicon gate, respectively, and the silicon-containing conductive area includes the polysilicon gate, the source region and the drain region.
7. The forming method according to claim 6, characterized in that: The spacing between the sidewall of the opening in the mask layer above the source region and the adjacent sidewall is greater than 0, and the spacing between the sidewall of the opening in the mask layer above the drain region and the adjacent sidewall is greater than 0.
8. The forming method according to claim 6, characterized in that: The longitudinal section of the self-aligned silicide layer formed on the surface areas of the source region and the drain region is in a convex shape.
9. The forming method according to claim 5, characterized in that: After forming the self-aligned silicide layer on the surface area of the silicon-containing conductive region, the method further comprises: Covering the semiconductor structure and the salicide layer with an etch stop layer, and covering the etch stop layer with an interlayer dielectric layer; forming a contact hole penetrating the interlayer dielectric layer, wherein the contact hole is formed above the silicon-containing conductive region and exposes a portion of the surface of the etch stop layer; etching the etch stop layer exposed by the contact hole to deepen the contact hole so that the contact hole exposes the salicide layer; and The contact hole is filled with a conductive material to form a contact plug.
10. The forming method according to claim 9, characterized in that: The exposure range of the contact hole formed above the same silicon-containing conductive region is smaller than the exposure range of the opening in the mask layer.
11. The forming method according to any one of claims 1 to 10, characterized in that: Before silicon is doped into the portion of the metal layer covering the silicon-containing conductive region, a titanium nitride layer is further covered on the surface of the metal layer.
12. The forming method according to any one of claims 1 to 10, characterized in that: The thickness of the salicide layer is greater than or equal to