Heterogeneous integrated Ga2O3 high-mobility inverter and preparation method thereof

Abstract

The invention discloses an out-of-phase integrated Ga2O3 high-mobility phase inverter and a preparation method of the out-of-phase integrated Ga2O3 high-mobility phase inverter. Comprising a semi-insulating beta-Ga2O3 substrate, an unintentionally doped beta-Ga2O3 drift layer, a kappa-(Al < x > Ga < 1-x >) 2O3 layer and a kappa-Ga2O3 layer which are sequentially arranged from bottom to top, isolation grooves are formed in the middles of the unintentionally doped beta-Ga2O3 drift layer, the kappa-Ga2O3 layer and the kappa-(Al < x > Ga < 1-x >) 2O3 layer, and the upper surface area of the kappa-(Al < x > Ga < 1-x >) 2O3 layer is divided into a depletion type device area and an enhancement type device area by the isolation grooves; the depletion type device region comprises a depletion type drain electrode metal layer, a depletion type grid electrode metal layer and a depletion type source electrode metal layer; the enhanced device region comprises an enhanced source metal layer, a p-type heterogeneous medium, an enhanced gate metal combination layer and an enhanced drain metal layer; the inverter provided by the invention realizes high mobility and high breakdown field strength.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a heterogeneously integrated Ga2O3 high-mobility inverter and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga2O3) material has the advantages of large bandgap and high breakdown field strength. It is superior to semiconductor materials such as Si (1.12 eV), SiC (3.3 eV) and GaN (3.4 eV). It is one of the third-generation semiconductor materials that has attracted much attention from academia and industry.

[0003] Ga2O3 has five isomers, α, β, γ, δ and ε (κ), showing rich physical and chemical properties. Among them, β-Ga2O3 has good thermal stability, its single crystal substrate can be grown by melting method, and epitaxial thin films with controllable doping concentration can be prepared by mist-CVD, MBE, MOCVD, HVPE and other methods, with low cost, and has been widely used in the preparation of transistors and diode devices.

[0004] The band gap of β-Ga2O3 is 4.9 eV, the breakdown field strength reaches 8 MV / cm, and the Baliga's Figure of Merit is as high as 3444, which can effectively improve the breakdown voltage of the device and reduce energy loss. Due to its excellent physical properties, the metastable phase Ga2O3 has attracted much attention recently. Among them, κ-Ga2O3 has spontaneous polarization characteristics, which can induce the formation of a high concentration of two-dimensional electron gas at the heterogeneous interface to realize high-mobility transistors. However, due to the lack of homogeneous substrates, it needs to be prepared by heteroepitaxial growth, which greatly limits its device application.

[0005] In the research of Ga2O3 devices, the research in the field of power electronics is relatively rich, but the research on the extremely important inverter and logic circuit is still insufficient. Due to the lack of effective p-type doping in β-Ga2O3, traditional CMOS inverters cannot be directly applied, and the preparation process is complex and difficult to achieve. Therefore, unipolar inverters need to be studied more deeply to avoid the problem of p-type doping difficulties in order to expand the further application of Ga2O3 materials in circuits. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a heterogeneously integrated Ga2O3 high-mobility inverter and a preparation method thereof. x Ga 1-x )2O3 / κ-Ga2O3 layer and β-Ga2O3 layer, taking advantage of their high mobility characteristics and using p-type heterogeneous material as enhanced gate dielectric to realize enhancement-mode devices to achieve inverter functions and expand their applications in the field of logic circuits.

[0007] To achieve the above purpose, the technical solution designed by the present invention is as follows: The present invention provides a heterogeneously integrated Ga2O3 high mobility inverter, the inverter comprising a semi-insulating β-Ga2O3 substrate, an unintentionally doped β-Ga2O3 drift layer, a κ-Ga2O3 layer, a κ-(Al x Ga 1-x )2O3 layer, unintentionally doped β-Ga2O3 drift layer, κ-Ga2O3 layer and κ-(Al x Ga 1-x ) An isolation trench is provided in the middle of the 2O3 layer; The isolation trench will be κ-(Al x Ga 1-x ) The upper surface area of ​​the 2O3 layer is divided into a depletion-type device area and an enhancement-type device area; The depletion-type device region is provided with a depletion-type drain region, a depletion-type gate region and a depletion-type source region which are sequentially arranged far from the isolation trench, and the enhancement-type device region is provided with an enhancement-type source region, an enhancement-type gate region and an enhancement-type drain region which are sequentially arranged far from the isolation trench; The depletion type device region is provided with a depletion type drain metal layer, a depletion type gate metal layer and a depletion type source metal layer in order from the distance to the isolation trench; The depletion type drain metal layer, the depletion type gate metal layer and the depletion type source metal layer are respectively arranged in the depletion type drain region, the depletion type gate region and the depletion type source region; The enhanced device region is provided with an enhanced source metal layer, a p-type heterogeneous dielectric and an enhanced gate metal combination layer, and an enhanced drain metal layer in sequence from the isolation trench; the p-type heterogeneous dielectric and enhanced gate metal combination layer is composed of a lower p-type heterogeneous dielectric and an upper enhanced gate metal layer. The enhanced source metal layer, the p-type heterogeneous dielectric and enhanced gate metal composite layer, and the enhanced drain metal layer are respectively arranged in the enhanced source region, the enhanced gate region, and the enhanced drain region; The depletion type source metal layer is interconnected with the enhancement type drain metal layer, and the depletion type source metal layer is interconnected with the depletion type gate metal layer.

[0008] Furthermore, the surfaces of the depletion type drain metal layer, the depletion type source metal layer, the depletion type gate metal layer, the enhanced gate metal layer, the enhanced drain metal layer and the enhanced source metal layer are all provided with pin pads; The depletion type source metal layer and the enhancement type drain metal layer are respectively arranged at two edges of the isolation trench, or the depletion type source metal layer and the enhancement type drain metal layer are extended and arranged on the surface of the isolation trench.

[0009] Further, the depletion type drain metal layer, the depletion type source metal layer, the enhanced drain metal layer and the enhanced source metal layer are Ti, Au and Ni metal layers arranged in sequence from bottom to top, and the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium is any one of p-NiO, p-GaN, and p-SnO; The depletion-type gate metal layer and the enhancement-type gate metal layer are both Pt and Au metal layers arranged in sequence from bottom to top, and the thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively; The pin pads are Ti and Au metal layers arranged in sequence from bottom to top, and the thicknesses of Ti and Au are 150~250 nm and 200~300 nm respectively.

[0010] Furthermore, in the depletion type drain metal layer, the depletion type source metal layer, the enhanced drain metal layer and the enhanced source metal layer, the thicknesses of Ti, Au and Ni are 50 nm, 100 nm and 100 nm respectively; The p-type heterogeneous medium is p-NiO; In the depletion-type gate metal layer and the enhancement-type gate metal layer, the thickness of Pt and Au is 150-250 nm and 200-300 nm respectively; In the pin pad, the thickness of Ti and Au is 150~250 nm and 200~300 nm respectively.

[0011] Furthermore, the thickness of the unintentionally doped β-Ga2O3 drift layer is 50-200 nm, and the κ-(Al x Ga 1-x )2O3 layer has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer has a thickness of 20~50 nm.

[0012] Furthermore, the thickness of the unintentionally doped β-Ga2O3 drift layer is 150 nm, and the κ-(Al x Ga 1-x )2O3 layer has a thickness of 20 nm and the thickness of κ-Ga2O3 layer is 30 nm.

[0013] The present invention also provides a method for preparing the inverter, comprising the following steps: S1: Preparation of unintentionally doped β-Ga2O3 drift layer on semi-insulating β-Ga2O3 substrate using MOCVD technology; S2: Using the lift-off transfer technique or epitaxial growth technique, a κ-Ga2O3 layer and a κ-(Al2O3) layer are sequentially prepared on the surface of the unintentionally doped β-Ga2O3 drift layer. x Ga 1-x )2O3 layer, κ-Ga2O3 layer and κ-(Al x Ga 1-x ) Two-dimensional electron gas is formed between 2O3 layers through polarization induction; S3: Using RIE-ICP etching technology to κ-(Al x Ga 1-x ) The middle part of the surface of the 2O3 layer is etched to the surface of the semi-insulating β-Ga2O3 substrate to form an isolation trench; S4: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer surface defines a depletion type drain region, a depletion type source region, an enhanced type drain region and an enhanced type source region, and Ti, Au and Ni metal layers are grown in sequence by electron beam evaporation technology to form a depletion type drain metal layer, a depletion type source metal layer, an enhanced type drain metal layer and an enhanced type source metal layer, and the depletion type drain metal layer, the depletion type source metal layer, the enhanced type drain metal layer and the enhanced type source metal layer are respectively connected with κ-(Al x Ga 1-x )2O3 layer forms ohmic contact; S5: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer surface defines the depletion gate region, and electron beam evaporation technology is used to grow Pt and Au metal layers in sequence to form a depletion gate metal layer, which is then bonded to the κ-(Al x Ga 1-x )2O3 layer forms Schottky contact; S6: Using photolithography technology to x Ga 1-x ) The surface of the 2O3 layer defines an enhanced gate region, and a p-type heterogeneous medium is grown using magnetron sputtering technology; S7: using electron beam evaporation technology to sequentially grow Pt and Au metal layers on the surface of the p-type heterogeneous medium in a self-aligned manner to form an enhanced gate metal layer; S8: Use electron beam evaporation technology to sequentially grow Ti and Au metal layers on the depletion drain metal layer, the depletion source metal layer, the depletion gate metal layer, the enhancement drain metal layer, the enhancement source metal layer and the enhancement gate metal layer to form pin pads. The depletion source metal layer and the enhancement drain metal layer are interconnected with the pin pads and connected to the depletion gate metal layer together to obtain a heterogeneously integrated Ga2O3 high-mobility inverter.

[0014] Furthermore, in step S2, the peeling transfer technology specifically includes the following steps: 1) Using Sn-assisted pulsed laser deposition technology, a κ-Ga2O3 layer with a thickness of 100-200 nm, a κ-(Al2O3 layer with a thickness of 100-500 nm) and a sapphire substrate with a thickness of 100-200 nm were grown from bottom to top. x Ga 1-x )2O3 layer and a κ-Ga2O3 layer with a thickness of 20~50 nm; 2) Implant hydrogen ions into κ-(Al x Ga 1-x )2O3 layer, using a bonding machine to bond a κ-Ga2O3 layer with a thickness of 20-50 nm to an unintentionally doped β-Ga2O3 drift layer; 3) Finally, high temperature annealing is performed to bond the κ-Ga2O3 layer with a thickness of 100~200 nm and the sapphire substrate to the κ-(Al x Ga 1-x )2O3 layer separation, for κ-(Al x Ga 1-x )The surface of the 2O3 layer is smoothed and polished to a thickness of 10~50 nm.

[0015] Furthermore, the high temperature annealing conditions are: annealing temperature is 1100° C., 30-60 min.

[0016] Furthermore, in the depletion type drain metal layer, the depletion type source metal layer, the enhanced drain metal layer and the enhanced source metal layer, the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium is any one of p-NiO, p-GaN, and p-SnO; In the depletion-mode gate metal layer and the enhancement-mode gate metal layer, the thickness of Pt and Au is 150-250 nm and 200-300 nm, respectively; In the pin pad, the thickness of Ti and Au is 150~250 nm and 200~300 nm respectively; The thickness of the unintentionally doped β-Ga2O3 drift layer is 50-200 nm, and the κ-(Al x Ga 1-x )2O3 layer has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer has a thickness of 20~50 nm.

[0017] Beneficial effects of the present invention: 1. The gallium oxide inverter designed by the present invention adopts monolithically integrated depletion-mode and enhancement-mode devices, which has a simpler preparation process than its CMOS inverter and effectively broadens the prospect of gallium oxide devices in logic circuits.

[0018] 2. β-Ga2O3 substrate can be grown by melting method, which is low-cost. Its epitaxial film can be prepared by a variety of methods. However, κ-Ga2O3, as a metastable Ga2O3 material, lacks homogeneous substrate and high-quality epitaxial film, which limits its application in devices. Heterogeneous integration can alleviate the difficulty of using κ-Ga2O3 in devices, so that its excellent properties, such as polarization properties, can be reasonably applied to devices.

[0019] 3. The κ-(Al x Ga 1-x There is a polarization-induced two-dimensional electron gas at the interface between the )2O3 layer and the κ-Ga2O3 layer, and the electron mobility is much higher than that of the β-Ga2O3 bulk material. Its high mobility can realize inverters with high switching speeds, which can be subsequently applied to high-speed circuits and other fields.

[0020] 4. The present invention adopts p-type heterogeneous dielectric as enhanced gate dielectric to avoid the difficulty of lack of p-type doping in Ga2O3 material, and realizes enhanced Ga2O3 high-mobility transistor, laying a foundation for its subsequent other circuit applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of the heterogeneously integrated Ga2O3 high-mobility inverter; Figure 2 Schematic diagram of the steps for preparing a semi-insulating β-Ga2O3 substrate and an unintentionally doped β-Ga2O3 drift layer; Figure 3 κ-Ga2O3 / κ-(Al x Ga 1-x ) Schematic diagram of 2O3 / κ-Ga2O3 layer structure; Figure 4 To transfer κ-Ga2O3 / κ-(Al x Ga 1-x )2O3 / κ-Ga2O3 layer process diagram; Figure 5 A schematic diagram of forming isolation trenches between devices; Figure 6 A schematic diagram of preparing source and drain metal layers; Figure 7 A schematic diagram of preparing a depletion-type gate metal layer; Figure 8 Schematic diagram of preparing p-type heterogeneous medium; Fig. 9A schematic diagram of preparing an enhanced gate metal layer; Fig.10 A schematic diagram for realizing interconnection between devices; Figure 1: Semi-insulating β-Ga2O3 substrate; 2: Unintentionally doped β-Ga2O3 drift layer; 3: κ-(Al x Ga 1-x )2O3 layer; 4, κ-Ga2O3 layer; 5, p-type heterogeneous dielectric; 6, depletion type drain metal layer; 7, depletion type source metal layer; 8, depletion type gate metal layer; 9, enhanced drain metal layer; 10, enhanced source metal layer; 11, enhanced gate metal layer; 12, sapphire substrate; 13, pin pad; 14, isolation trench; Fig.11 The energy band structure diagram of the heterogeneously integrated Ga2O3 high-mobility inverter; Fig.12 The simulated structure diagram of κ-Ga2O3 / β-Ga2O3 electron mobility Fig.13 This is the transfer characteristic simulation result diagram of the depletion type device; Fig.14 This is the simulation result diagram of the transfer characteristics of the enhanced device; Fig.15 This is a simulation result diagram of the voltage transfer characteristics of the heterogeneously integrated Ga2O3 high-mobility inverter. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with specific embodiments so that those skilled in the art can understand.

[0023] Example 1 This embodiment provides a Ga2O3 high mobility inverter with heterogeneous integration. Figure 1 As shown, the inverter includes a semi-insulating β-Ga2O3 substrate 1, an unintentionally doped β-Ga2O3 drift layer 2, a κ-Ga2O3 layer 4, a κ-(Al x Ga 1-x )2O3 layer 3, unintentionally doped β-Ga2O3 drift layer 2, κ-Ga2O3 layer 4 and κ-(Al x Ga 1-x ) An isolation trench 14 is provided in the middle of the 2O3 layer 3; The isolation trench 14 is a κ-(Al x Ga 1-x ) The upper surface area of ​​the 2O3 layer 3 is divided into a depletion type device area and an enhancement type device area; The depletion type device region is provided with a depletion type drain metal layer 6, a depletion type gate metal layer 8 and a depletion type source metal layer 7 in order from the distance to the isolation trench 14; The enhanced device region is provided with an enhanced source metal layer 10, a p-type heterogeneous dielectric and an enhanced gate metal combination layer, and an enhanced drain metal layer 9 in sequence from the isolation trench 14; the p-type heterogeneous dielectric and the enhanced gate metal combination layer is composed of a lower p-type heterogeneous dielectric 5 and an upper enhanced gate metal layer 11. The depletion type source metal layer 7 and the enhancement type drain metal layer 9 are interconnected, and the depletion type source metal layer 7 and the depletion type gate metal layer 8 are interconnected.

[0024] Among them, the surfaces of the depletion type drain metal layer 6, the depletion type source metal layer 7, the depletion type gate metal layer 8, the enhanced gate metal layer 11, the enhanced type drain metal layer 9 and the enhanced type source metal layer 10 are all provided with pin pads 13; The depletion type source metal layer 7 and the enhancement type drain metal layer 9 are respectively arranged at two edges of the isolation trench 14 , or the depletion type source metal layer 7 and the enhancement type drain metal layer 9 are extended and arranged on the surface of the isolation trench 14 .

[0025] In the heterogeneously integrated Ga2O3 high mobility inverter of this embodiment: (1) The depletion type drain metal layer 6, the depletion type source metal layer 7, the enhanced drain metal layer 9 and the enhanced source metal layer 10 are all Ti, Au and Ni metal layers arranged in sequence from bottom to top, and the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium 5 is any one of p-NiO, p-GaN, and p-SnO; The depletion-type gate metal layer 8 and the enhancement-type gate metal layer 11 are both Pt and Au metal layers arranged in sequence from bottom to top, and the thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively; The pin pad 13 is a Ti and Au metal layer arranged in sequence from bottom to top, and the thickness of Ti and Au are 150-250 nm and 200-300 nm respectively.

[0026] Preferably, in the depletion type drain metal layer 6, the depletion type source metal layer 7, the enhanced drain metal layer 9 and the enhanced source metal layer 10, the thicknesses of Ti, Au and Ni are 50 nm, 100 nm and 100 nm respectively; The p-type heterogeneous medium 5 is p-NiO; In the depletion-type gate metal layer 8 and the enhancement-type gate metal layer 11, the thicknesses of Pt and Au are 200 nm and 250 nm, respectively; In the lead pad 13, the thicknesses of Ti and Au are 200 nm and 250 nm, respectively.

[0027] (2) The thickness of the unintentionally doped β-Ga2O3 drift layer 2 is 50~200 nm, and the κ-(Al x Ga 1-x )2O3 layer 3 has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer 4 has a thickness of 20~50 nm.

[0028] Preferably, the thickness of the unintentionally doped β-Ga2O3 drift layer 2 is 150 nm, and the thickness of the κ-(Al x Ga 1-x )2O3 layer 3 has a thickness of 20 nm, and κ-Ga2O3 layer 4 has a thickness of 30 nm.

[0029] Example 2 This embodiment provides a method for preparing the heterogeneous integrated Ga2O3 high mobility inverter of embodiment 1, combined with Figure 2~Figure 10 As shown, the following steps are included: 1. If Figure 2 As shown, an unintentionally doped β-Ga2O3 drift layer 2 with a thickness of 50-200 nm is prepared on a semi-insulating β-Ga2O3 substrate 1 using MOCVD technology.

[0030] 2. If Figure 3 As shown, a 100-200 nm thick κ-Ga2O3 layer 4, a 100-500 nm thick κ-(Al2O3) layer 5 and a 100-200 nm thick κ-Ga2O3 layer 6 are sequentially grown from bottom to top on a sapphire substrate 12 using a tin-assisted pulsed laser deposition technique. x Ga 1-x )2O3 layer 3 and κ-Ga2O3 layer 4 with a thickness of 20~50 nm.

[0031] 3. If Figure 4 As shown, H + Implanted into κ-(Al x Ga 1-x )2O3 layer 3, a κ-Ga2O3 layer 4 with a thickness of 20-50 nm is bonded to the unintentionally doped β-Ga2O3 drift layer 2 using a bonding machine in combination with the lift-off transfer technology, and finally a high-temperature annealing is performed to bond the upper κ-Ga2O3 layer 4 with a thickness of 100-200 nm and the sapphire substrate 12 to the κ-(Al x Ga 1-x )2O3 layer 3 is separated, and the high temperature annealing conditions are annealing temperature of 1100℃, 30~60 min. Chemical mechanical polishing is used to x Ga 1-x )2O3 layer 3 is flattened and polished to a thickness of 10~50 nm. x Ga 1-x)2O3 layer 3 is located on top of κ-Ga2O3 layer 4, and two-dimensional electron gas is formed at the interface between the two through polarization induction.

[0032] 4. If Figure 5 As shown, after photolithography selection, the sample is etched using RIE-ICP etching technology to the surface of the semi-insulating β-Ga2O3 substrate 1 to form an isolation groove 14 between the depletion mode device and the enhancement mode device. The excess photoresist is stripped off using a degumming solution, and the sample is cleaned. The isolation groove 14 between the devices isolates the depletion mode device from the enhancement mode device.

[0033] 5. If Figure 6 As shown, photolithography technology is used in κ-(Al x Ga 1-x )2O3 layer 3, after selecting the depletion drain region, depletion source region, enhanced drain region and enhanced source region on the surface, Ti, Au and Ni metal layers are grown in the depletion drain region, depletion source region, enhanced drain region and enhanced source region respectively by electron beam evaporation technology to form a depletion drain metal layer 6, a depletion source metal layer 7, an enhanced drain metal layer 9 and an enhanced source metal layer 10, and the thicknesses of Ti, Au and Ni are 20~100nm, 50~150nm and 50~150nm respectively. Use a stripping solution to remove excess photoresist and metal, and clean the sample. Subsequently, rapid thermal annealing is performed at 800℃ for 30 seconds, and the depletion drain metal layer 6, the depletion source metal layer 7, the enhanced drain metal layer 9 and the enhanced source metal layer 10 are respectively bonded with κ-(Al x Ga 1-x )2O3 layer 3 realizes ohmic contact. In this embodiment, the depletion type source metal layer 7 and the enhancement type drain metal layer 9 are extended and arranged on the surface of the isolation trench 14, and the depletion type source metal layer 7 and the enhancement type drain metal layer 9 are in contact with each other.

[0034] 6. If Figure 7 As shown, photolithography technology is used in κ-(Al x Ga 1-x )2O3 layer 3 is surface-selected for a depletion-type gate region, and Pt and Au metal layers are sequentially grown in the depletion-type gate region using electron beam evaporation technology. The thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively, to form a depletion-type gate metal layer 8, which is then bonded to the κ-(Al x Ga 1-x )2O3 layer 3 forms a Schottky contact. Use a stripping solution to remove excess photoresist and metal, and clean the sample.

[0035] 7. If Figure 8 As shown, photolithography technology is used in κ-(Al x Ga 1-xAn enhanced gate region is selected on the surface of the )2O3 layer 3, and a p-type heterogeneous medium 5 is grown in the enhanced gate region by magnetron sputtering technology. The p-type heterogeneous medium 5 is any one of p-NiO, p-GaN, and p-SnO. The p-type heterogeneous medium 5 is used to deplete gate carriers to form an enhanced device.

[0036] 8. If Fig. 9 As shown, Pt and Au metal layers are grown sequentially and self-aligned on the surface of the p-type heterogeneous medium 5 by electron beam evaporation technology, and the thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively, to form an enhanced gate metal layer 11. The excess photoresist and metal are stripped off using a stripping solution, and the sample is cleaned.

[0037] 9. If Fig.10 As shown, after the pin pad (PAD) area is selected by photolithography, Ti and Au metal layers are grown in sequence on the depletion type drain metal layer 6, the depletion type source metal layer 7, the depletion type gate metal layer 8, the enhanced drain metal layer 9, the enhanced source metal layer 10 and the enhanced gate metal layer 11 by electron beam evaporation technology to form a pin pad 13, and the thickness of Ti and Au are 150~250 nm and 200~300 nm respectively. The depletion type source metal layer 7 and the enhanced drain metal layer 9 are interconnected by PAD, and the depletion type source metal layer 7 and the depletion type gate metal layer 8 are interconnected (the depletion type source metal layer 7 and the enhanced drain metal layer 9 are connected to the depletion type gate metal layer 8 together), realizing the interconnection between devices. The excess photoresist and metal are stripped off by using a degumming liquid, and the sample is cleaned. A heterogeneously integrated Ga2O3 high-mobility inverter is prepared.

[0038] Example 3 This embodiment provides a method for preparing a heterogeneously integrated Ga2O3 high-mobility inverter. The preparation method is the same as that of Embodiment 2, except that the κ-Ga2O3 layer 4 and the κ-(Al x Ga 1-x )2O3 layer 3 is different from the method (i.e., step 2 and step 3 in Example 2). In this example, κ-Ga2O3 layer 4 and κ-(Al x Ga 1-x )2O3 layer 3 method is as follows: On the unintentionally doped β-Ga2O3 drift layer 2, a 20-50 nm κ-Ga2O3 layer 4 and a 10-50 nm κ-(Al x Ga 1-x )2O3 layer 3, κ-(Al x Ga 1-x )2O3 layer 3 and κ-Ga2O3 layer 4 interface to form a two-dimensional electron gas by polarization induction.

[0039] Example 4 1. The heterogeneously integrated Ga2O3 high-mobility inverter of Example 1 was simulated by Silvaco TCAD simulation software, and its band structure diagram was extracted, as shown in FIG. Fig.11 As shown, the reference numeral 1 in the figure is κ-(Al x Ga 1-x )2O3 layer, number 2 is κ-Ga2O3 layer, number 3 is β-Ga2O3 layer. x Ga 1-x )2O3 layer and κ-Ga2O3 layer generate two-dimensional electron gas through polarization induction, which has high mobility, such as Fig.12 As shown, the reference numeral 1 in the figure is κ-(Al x Ga 1-x )2O3 layer mobility, label 2 is the two-dimensional electron gas mobility in the κ-Ga2O3 layer, and label 3 is the mobility of the β-Ga2O3 layer, so the inverter has a high switching speed.

[0040] 2. The transfer characteristics of the depletion-mode device and the enhancement-mode device in the heterogeneously integrated Ga2O3 high-mobility inverter of Example 1 are analyzed. Fig.13 and Fig.14 As shown, the threshold voltage of the depletion-mode device is about -5.8 V, and the threshold voltage of the enhancement-mode device is about 2 V, which proves the feasibility of realizing the inverter by monolithic integration of this scheme.

[0041] 3. The voltage transfer characteristics of the heterogeneously integrated Ga2O3 high-mobility inverter of Example 1 are analyzed. Fig.15 The input voltage V in Switching from low voltage to high voltage, the output voltage V out Switching from high voltage to low voltage realizes the function of logic inversion.

[0042] Although the above embodiments have been described in detail, they are only a part of the embodiments of the present invention, not all of them. People can also obtain other embodiments based on this embodiment without creativity, and these embodiments all belong to the protection scope of the present invention.

Claims

1. A heterogeneously integrated Ga2O3 high-mobility inverter, characterized in that: The inverter comprises, arranged in order from bottom to top, a semi-insulating β-Ga2O3 substrate (1), an unintentionally doped β-Ga2O3 drift layer (2), a κ-Ga2O3 layer (4), a κ-(Al x Ga 1-x )2O3 layer (3), unintentionally doped β-Ga2O3 drift layer (2), κ-Ga2O3 layer (4) and κ-(Al x Ga 1-x ) An isolation groove (14) is provided in the middle of the 2O3 layer (3); The isolation trench (14) is κ-(Al x Ga 1-x ) The upper surface area of ​​the 2O3 layer (3) is divided into a depletion type device area and an enhancement type device area; The depletion-type device region is provided with a depletion-type drain metal layer (6), a depletion-type gate metal layer (8) and a depletion-type source metal layer (7) in order of distance from the isolation trench (14); The enhanced device region comprises an enhanced source metal layer (10), a p-type heterogeneous medium and an enhanced gate metal combination layer, and an enhanced drain metal layer (9) which are arranged in sequence from the isolation trench (14); the p-type heterogeneous medium and the enhanced gate metal combination layer are composed of a lower p-type heterogeneous medium (5) and an upper enhanced gate metal layer (11); The depletion type source metal layer (7) and the enhanced drain metal layer (9) are interconnected, and the depletion type source metal layer (7) and the depletion type gate metal layer (8) are interconnected.

2. The inverter according to claim 1, characterized in that: The surfaces of the depletion-type drain metal layer (6), the depletion-type source metal layer (7), the depletion-type gate metal layer (8), the enhanced gate metal layer (11), the enhanced drain metal layer (9) and the enhanced source metal layer (10) are all provided with pin pads (13); The depletion type source metal layer (7) and the enhancement type drain metal layer (9) are respectively arranged at two edges of the isolation groove (14), or the depletion type source metal layer (7) and the enhancement type drain metal layer (9) are extended and arranged on the surface of the isolation groove (14).

3. The inverter according to claim 1, characterized in that: The depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced drain metal layer (9) and the enhanced source metal layer (10) are all Ti, Au and Ni metal layers arranged in sequence from bottom to top, and the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium (5) is any one of p-NiO, p-GaN, and p-SnO; The depletion-type gate metal layer (8) and the enhancement-type gate metal layer (11) are both Pt and Au metal layers arranged in sequence from bottom to top, with the thicknesses of Pt and Au being 150-250 nm and 200-300 nm respectively; The pin pad (13) is a Ti and Au metal layer arranged in sequence from bottom to top, and the thickness of Ti and Au are 150-250 nm and 200-300 nm respectively.

4. The inverter according to claim 3, characterized in that: In the depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced drain metal layer (9) and the enhanced source metal layer (10), the thicknesses of Ti, Au and Ni are 50 nm, 100 nm and 100 nm respectively; The p-type heterogeneous medium (5) is p-NiO; In the depletion-type gate metal layer (8) and the enhancement-type gate metal layer (11), the thicknesses of Pt and Au are 200 nm and 250 nm respectively; In the pin pad (13), the thickness of Ti and Au is 200 nm and 250 nm, respectively.

5. The inverter according to claim 1, characterized in that: The thickness of the unintentionally doped β-Ga2O3 drift layer (2) is 50-200 nm, and the κ-(Al x Ga 1-x )2O3 layer (3) has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer (4) has a thickness of 20~50 nm.

6. The inverter according to claim 5, characterized in that: The thickness of the unintentionally doped β-Ga2O3 drift layer (2) is 150 nm, and the κ-(Al x Ga 1-x )2O3 layer (3) has a thickness of 20 nm, and the thickness of κ-Ga2O3 layer (4) has a thickness of 30 nm.

7. A method for preparing a heterogeneously integrated Ga2O3 high-mobility inverter, characterized in that: The following steps are involved: S1: Preparing an unintentionally doped β-Ga2O3 drift layer (2) on a semi-insulating β-Ga2O3 substrate (1) using MOCVD technology; S2: Sequentially prepare a κ-Ga2O3 layer (4) and a κ-(Al x Ga 1-x )2O3 layer (3), κ-Ga2O3 layer (4) and κ-(Al x Ga 1-x )2O3 layers (3) form a two-dimensional electron gas through polarization induction; S3: Using RIE-ICP etching technology to κ-(Al x Ga 1-x ) etching the middle part of the surface of the β-Ga2O3 layer (3) until the surface of the semi-insulating β-Ga2O3 substrate (1) is reached to form an isolation groove (14); S4: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer (3) defines a depletion type drain region, a depletion type source region, an enhanced type drain region and an enhanced type source region on the surface, and Ti, Au and Ni metal layers are grown in sequence by electron beam evaporation technology to form a depletion type drain metal layer (6), a depletion type source metal layer (7), an enhanced type drain metal layer (9) and an enhanced type source metal layer (10), and the depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced type drain metal layer (9) and the enhanced type source metal layer (10) are respectively connected to κ-(Al x Ga 1-x )2O3 layer (3) forms an ohmic contact; S5: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer (3) defines a depletion gate region on the surface, and Pt and Au metal layers are grown in sequence using electron beam evaporation technology to form a depletion gate metal layer (8), which is then bonded to the κ-(Al x Ga 1-x )2O3 layer (3) forms a Schottky contact; S6: Using photolithography technology to x Ga 1-x ) The surface of the 2O3 layer (3) defines an enhanced gate region, and a p-type heterogeneous medium (5) is grown by magnetron sputtering technology; S7: using electron beam evaporation technology to sequentially grow Pt and Au metal layers on the surface of the p-type heterogeneous medium (5) in a self-aligned manner to form an enhanced gate metal layer (11); S8: Ti and Au metal layers are grown in sequence on the depletion type drain metal layer (6), the depletion type source metal layer (7), the depletion type gate metal layer (8), the enhanced type drain metal layer (9), the enhanced type source metal layer (10) and the enhanced type gate metal layer (11) using electron beam evaporation technology to form a pin pad (13). The depletion type source metal layer (7) and the enhanced type drain metal layer (9) are interconnected by the pin pad and are connected to the depletion type gate metal layer (8) together, thereby obtaining a heterogeneously integrated Ga2O3 high-mobility inverter.

8. The method according to claim 7, characterized in that: In step S2, the peeling transfer technology specifically includes the following steps: 1) Using Sn-assisted pulsed laser deposition technology, a κ-Ga2O3 layer (4) with a thickness of 100-200 nm, a κ-(Al2O3) layer with a thickness of 100-500 nm, and a κ-(Al2O3) layer with a thickness of 100-200 nm were grown on a sapphire substrate (12) from bottom to top. x Ga 1-x )2O3 layer (3) and a κ-Ga2O3 layer with a thickness of 20~50 nm (4); 2) Implant hydrogen ions into κ-(Al x Ga 1-x )2O3 layer (3), using a bonding machine to bond a κ-Ga2O3 layer (4) with a thickness of 20 to 50 nm to an unintentionally doped β-Ga2O3 drift layer (2); 3) Finally, high temperature annealing is performed to bond the κ-Ga2O3 layer (4) with a thickness of 100-200 nm and the sapphire substrate (12) to the κ-(Al x Ga 1-x )2O3 layer (3) separation, for κ-(Al x Ga 1-x The surface of the SiO2O3 layer (3) is flattened and polished to a thickness of 10-50 nm.

9. The method according to claim 8, characterized in that: The high temperature annealing conditions are: annealing temperature is 1100° C., 30-60 min.

10. The method according to claim 7, characterized in that: In the depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced drain metal layer (9) and the enhanced source metal layer (10), the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium (5) is any one of p-NiO, p-GaN, and p-SnO; In the depletion-type gate metal layer (8) and the enhancement-type gate metal layer (11), the thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively; In the pin pad (13), the thickness of Ti and Au is 150~250 nm and 200~300 nm, respectively; The thickness of the unintentionally doped β-Ga2O3 drift layer (2) is 50-200 nm, and the κ-(Al x Ga 1-x )2O3 layer (3) has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer (4) has a thickness of 20~50 nm.

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