A heterogeneous integrated Ga 2 O 3 high mobility inverter and its manufacturing method

Abstract

The present invention discloses a heterogeneous integrated Ga2O3 high-mobility inverter and a preparation method thereof. It includes a semi-insulating β-Ga2O3 substrate, an unintentionally doped β-Ga2O3 drift layer, a κ-(Al x Ga 1‑x )2O3 layer, a κ-Ga2O3 layer, an unintentionally doped β-Ga2O3 drift layer, a κ-Ga2O3 layer, and an isolation trench is provided in the middle of the κ-(Al x Ga 1‑x )2O3 layer. The isolation trench divides the upper surface area of the κ-(Al x Ga 1‑x )2O3 layer into a depletion-mode device area and an enhancement-mode device area; the depletion-mode device area includes a depletion-mode drain metal layer, a depletion-mode gate metal layer, and a depletion-mode source metal layer; the enhancement-mode device area includes an enhancement-mode source metal layer, a p-type heterogeneous dielectric and an enhancement-mode gate metal composite layer, and an enhancement-mode drain metal layer; the inverter of the present invention achieves high mobility and high breakdown field strength.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and particularly to a Ga with heterogeneous integration 2 O 3 high mobility inverter and a preparation method thereof. Background Art

[0002] Gallium oxide (Ga 2 O 3 ) material has advantages such as a large band gap and a high breakdown field strength, and is superior to semiconductor materials such as Si (1.12 eV), SiC (3.3 eV), and GaN (3.4 eV). It is one of the third-generation semiconductor materials that have attracted much attention from the academic and industrial circles at present.

[0003] Ga 2 O 3 has five isomers of α, β, γ, δ, and ε (κ), showing rich physical and chemical properties. Among them, β-Ga 2 O 3 has good thermal stability. Its single crystal substrate can be grown by the melting method, and an epitaxial film with a controllable doping concentration can be prepared by methods such as mist-CVD, MBE, MOCVD, and HVPE. The cost is low, and it has been widely used in the preparation of transistor and diode devices.

[0004] β-Ga 2 O 3 has a band gap of 4.9 eV, a breakdown field strength of up to 8 MV / cm, and a high Baliga's Figure of Merit of 3444, which can effectively increase the breakdown voltage of the device and reduce energy loss. Due to its excellent physical properties, the metastable phase Ga 2 O 3 has attracted much attention recently. Among them, κ-Ga 2 O 3 has spontaneous polarization characteristics, can induce the formation of a high-concentration two-dimensional electron gas at the heterointerface, and realize a high-mobility transistor. However, due to the lack of a homogeneous substrate, it needs to be prepared by heteroepitaxy, which greatly limits its device application.

[0005] In the research of Ga 2 O 3 devices, the research in the field of power electronics is relatively rich, but the research on extremely important inverters and logic circuits is still insufficient. Since β-Ga 2 O 3 lacks effective p-type doping, traditional CMOS inverters cannot be directly applied, and the preparation process is relatively complex and difficult to achieve. Therefore, unipolar inverters need to be further studied to avoid the problem of difficult p-type doping, so as to expand Ga 2 O3 Further applications of the material in circuits. Summary of the Invention

[0006] The object of the present invention is to overcome the deficiencies of the prior art and provide a hetero-integrated Ga 2 O 3 high-mobility inverter and its manufacturing method. Through hetero-integration of the κ-(Al x Ga 1-x ) 2 O 3 / κ-Ga 2 O 3 layer and the β-Ga 2 O 3 layer, utilizing their high-mobility characteristics and using a p-type heteromaterial as the enhancement-mode gate dielectric to implement an enhancement-mode device, so as to achieve the inverter function and expand its applications in the field of logic circuits.

[0007] To achieve the above object, the technical solution designed by the present invention is as follows:

[0008] The present invention provides a hetero-integrated Ga 2 O 3 high-mobility inverter, the inverter comprising a semi-insulating β-Ga 2 O 3 substrate, an unintentionally doped β-Ga 2 O 3 drift layer, a κ-Ga 2 O 3 layer, a κ-(Al x Ga 1-x ) 2 O 3 layer, an unintentionally doped β-Ga 2 O 3 drift layer, a κ-Ga 2 O 3 layer and a κ-(Al x Ga 1-x ) 2 O 3 layer, and an isolation trench is provided in the middle of the κ-(Al

[0009] The isolation trench divides the upper surface area of the κ-(Al x Ga 1-x ) 2 O 3 layer into a depletion-mode device area and an enhancement-mode device area;

[0010] On the depletion-type device region, a depletion-type drain region, a depletion-type gate region, and a depletion-type source region are sequentially arranged from far to near from the isolation trench; on the enhancement-type device region, an enhancement-type source region, an enhancement-type gate region, and an enhancement-type drain region are sequentially arranged from far to near from the isolation trench;

[0011] The depletion-type device region is sequentially provided with a depletion-type drain metal layer, a depletion-type gate metal layer, and a depletion-type source metal layer from far to near from the isolation trench;

[0012] The depletion-type drain metal layer, the depletion-type gate metal layer, and the depletion-type source metal layer are respectively arranged in the depletion-type drain region, the depletion-type gate region, and the depletion-type source region;

[0013] The enhancement-type device region is sequentially provided with an enhancement-type source metal layer, a p-type hetero-dielectric and an enhancement-type gate metal composite layer, and an enhancement-type drain metal layer from far to near from the isolation trench; the p-type hetero-dielectric and the enhancement-type gate metal composite layer are composed of a lower p-type hetero-dielectric and an upper enhancement-type gate metal layer.

[0014] The enhancement-type source metal layer, the p-type hetero-dielectric and the enhancement-type gate metal composite layer, and the enhancement-type drain metal layer are respectively arranged in the enhancement-type source region, the enhancement-type gate region, and the enhancement-type drain region;

[0015] The depletion-type source metal layer is interconnected with the enhancement-type drain metal layer, and the depletion-type source metal layer is interconnected with the depletion-type gate metal layer.

[0016] Further, pin pads are provided on the surfaces of the depletion-type drain metal layer, the depletion-type source metal layer, the depletion-type gate metal layer, the enhancement-type gate metal layer, the enhancement-type drain metal layer, and the enhancement-type source metal layer;

[0017] The depletion-type source metal layer and the enhancement-type drain metal layer are respectively arranged on two edges of the isolation trench, or the depletion-type source metal layer and the enhancement-type drain metal layer extend and are arranged on the surface of the isolation trench.

[0018] Still further, the depletion-type drain metal layer, the depletion-type source metal layer, the enhancement-type drain metal layer, and the enhancement-type source metal layer are all Ti, Au, and Ni metal layers sequentially arranged from bottom to top, and the thicknesses of Ti, Au, and Ni are 20 - 100 nm, 50 - 150 nm, and 50 - 150 nm respectively;

[0019] The p-type hetero-dielectric is any one of p-NiO, p-GaN, and p-SnO;

[0020] The depletion-mode gate metal layer and the enhancement-mode gate metal layer are both Pt and Au metal layers sequentially arranged from bottom to top, and the thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively;

[0021] The pin pad is Ti and Au metal layers sequentially arranged from bottom to top, and the thicknesses of Ti and Au are 150 - 250 nm and 200 - 300 nm respectively.

[0022] Furthermore, in the depletion-mode drain metal layer, depletion-mode source metal layer, enhancement-mode drain metal layer, and enhancement-mode source metal layer, the thicknesses of Ti, Au, and Ni are 50 nm, 100 nm, and 100 nm respectively;

[0023] The p-type hetero dielectric is p-NiO;

[0024] In the depletion-mode gate metal layer and the enhancement-mode gate metal layer, the thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively;

[0025] In the pin pad, the thicknesses of Ti and Au are 150 - 250 nm and 200 - 300 nm respectively.

[0026] Furthermore, the unintentionally doped β-Ga 2 O 3 drift layer has a thickness of 50 - 200 nm, the κ-(Al x Ga 1-x ) 2 O 3 layer has a thickness of 10 - 50 nm, and the κ-Ga 2 O 3 layer has a thickness of 20 - 50 nm.

[0027] Furthermore, the unintentionally doped β-Ga 2 O 3 drift layer has a thickness of 150 nm, the κ-(Al x Ga 1-x ) 2 O 3 layer has a thickness of 20 nm, and the κ-Ga 2 O 3 layer has a thickness of 30 nm.

[0028] The present invention also provides a method for manufacturing the inverter described above, including the following steps:

[0029] S1: Using MOCVD technology to prepare unintentionally doped β-Ga 2 O 3 on a semi-insulating β-Ga2 O 3 Drift layer;

[0030] S2: Use the lift-off transfer technology or epitaxial growth technology to sequentially fabricate κ-Ga 2 O 3 on the surface of the drift layer, κ-(Al 2 O 3 layer and κ-(Al x Ga 1-x ) 2 O 3 layer, κ-Ga 2 O 3 layer and κ-(Al x Ga 1-x ) 2 O 3 layer to form a two-dimensional electron gas through polarization induction;

[0031] S3: Use the RIE-ICP etching technology to etch the middle part of the surface of the κ-(Al x Ga 1-x ) 2 O 3 layer until reaching the surface of the semi-insulating β-Ga 2 O 3 substrate surface to form isolation trenches;

[0032] S4: Use photolithography technology to define the depletion-type drain region, depletion-type source region, enhancement-type drain region, and enhancement-type source region on the surface of the κ-(Al x Ga 1-x ) 2 O 3 layer. Sequentially grow Ti, Au, and Ni metal layers through electron beam evaporation technology to form a depletion-type drain metal layer, a depletion-type source metal layer, an enhancement-type drain metal layer, and an enhancement-type source metal layer. The depletion-type drain metal layer, depletion-type source metal layer, enhancement-type drain metal layer, and enhancement-type source metal layer respectively form ohmic contacts with the κ-(Al x Ga 1-x ) 2 O 3 layer;

[0033] S5: Use photolithography technology to define the depletion-type gate region on the surface of the κ-(Al x Ga 1-x ) 2 O 3 layer. Sequentially grow Pt and Au metal layers through electron beam evaporation technology to form a depletion-type gate metal layer, and form an ohmic contact with the κ-(Al x Ga 1-x ) 2 O 3A Schottky contact is formed on the layer;

[0034] S6: Use photolithography technology to define the enhanced gate region on the surface of the κ-(Al x Ga 1-x ) 2 O 3 layer, and grow a p-type hetero-dielectric using magnetron sputtering technology;

[0035] S7: Use electron beam evaporation technology to sequentially grow Pt and Au metal layers on the surface of the p-type hetero-dielectric in a self-aligned manner to form an enhanced gate metal layer;

[0036] S8: Use electron beam evaporation technology to sequentially grow Ti and Au metal layers on the depletion-type drain metal layer, depletion-type source metal layer, depletion-type gate metal layer, enhanced-type drain metal layer, enhanced-type source metal layer, and enhanced-type gate metal layer to form pin pads. The depletion-type source metal layer is interconnected with the enhanced-type drain metal layer through the pin pads and is connected to the depletion-type gate metal layer together, thus obtaining a Ga 2 O 3 high-mobility inverter.

[0037] Furthermore, in the step S2, the peeling and transfer technology specifically includes the following steps:

[0038] 1) Use tin-assisted pulsed laser deposition technology to sequentially grow a κ-Ga 2 O 3 layer with a thickness of 100 - 200 nm, a κ-(Al x Ga 1-x ) 2 O 3 layer with a thickness of 100 - 500 nm, and a κ-Ga 2 O 3 layer with a thickness of 20 - 50 nm on the sapphire substrate from bottom to top;

[0039] 2) Inject hydrogen ions into the κ-(Al x Ga 1-x ) 2 O 3 layer, and use a bonder to bond the κ-Ga 2 O 3 layer with a thickness of 20 - 50 nm to the unintentionally doped β-Ga 2 O 3 drift layer;

[0040] 3) Finally, perform high-temperature annealing to separate the κ-Ga 2 O 3 layer with a thickness of 100 - 200 nm and the sapphire substrate from the κ-(Al x Ga1-x ) 2 O 3 Layer separation is performed on κ-(Al x Ga 1-x ) 2 O 3 The surface of the layer is flattened and polished until its thickness is 10 - 50 nm.

[0041] Furthermore, the conditions for the high - temperature annealing are: the annealing temperature is 1100 °C for 30 - 60 min.

[0042] Furthermore, in the depletion - type drain metal layer, depletion - type source metal layer, enhancement - type drain metal layer, and enhancement - type source metal layer, the thicknesses of Ti, Au, and Ni are 20 - 100 nm, 50 - 150 nm, and 50 - 150 nm respectively;

[0043] The p - type heterojunction medium is any one of p - NiO, p - GaN, p - SnO;

[0044] In the depletion - type gate metal layer and enhancement - type gate metal layer, the thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively;

[0045] In the pin pad, the thicknesses of Ti and Au are 150 - 250 nm and 200 - 300 nm respectively;

[0046] The non - intentionally doped β - Ga 2 O 3 drift layer has a thickness of 50 - 200 nm, and the κ-(Al x Ga 1-x ) 2 O 3 layer has a thickness of 10 - 50 nm, and the κ - Ga 2 O 3 layer has a thickness of 20 - 50 nm.

[0047] Advantages of the present invention:

[0048] 1. The designed gallium oxide inverter of the present invention adopts monolithic integrated depletion - type and enhancement - type devices, and its manufacturing process is simpler than that of the CMOS inverter, effectively broadening the prospects of gallium oxide devices in logic circuits.

[0049] 2. The β - Ga 2 O 3 substrate can be grown by the melting method with low cost. Its epitaxial thin film can be prepared by various methods. And κ - Ga 2 O 3 as a metastable phase of Ga 2 O 3Materials, lacking a homogeneous substrate and high-quality epitaxial thin films, limit their application in devices. Through heterogeneous integration, the difficulties in the application of κ-Ga 2 O 3 in devices can be alleviated, enabling its excellent properties, such as polarization properties, to be reasonably utilized in devices.

[0050] 3. There is a polarization-induced two-dimensional electron gas at the interface between the κ-(Al x Ga 1-x ) 2 O 3 layer and the κ-Ga 2 O 3 layer, and the electron mobility is much higher than that of the β-Ga 2 O 3 bulk material. Its high mobility can enable inverters with high switching speeds, which can be subsequently applied in fields such as high-speed circuits.

[0051] 4. The present invention uses a p-type heterogeneous dielectric as an enhanced gate dielectric to avoid the difficulty of lacking p-type doping in Ga 2 O 3 materials, and an enhanced Ga 2 O 3 high-mobility transistor is achieved, laying a foundation for its subsequent other circuit applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic structural diagram of a high-mobility inverter of hetero-integrated Ga 2 O 3 ;

[0053] Figure 2 is a schematic diagram of the steps for preparing a semi-insulating β-Ga 2 O 3 substrate and an unintentionally doped β-Ga 2 O 3 drift layer;

[0054] Figure 3 is a schematic diagram of the κ-Ga 2 O 3 / κ-(Al x Ga 1-x ) 2 O 3 / κ-Ga 2 O 3 layer structure;

[0055] Figure 4 is for transferring κ-Ga 2 O 3 / κ-(Al x Ga 1-x ) 2 O3 / κ-Ga 2 O 3 Schematic diagram of the layer process

[0056] Figure 5 Schematic diagram for forming isolation trenches between devices

[0057] Figure 6 Schematic diagram for preparing source and drain metal layers

[0058] Figure 7 Schematic diagram for preparing depletion-mode gate metal layer

[0059] Figure 8 Schematic diagram for preparing p-type heterojunction dielectric

[0060] Figure 9 Schematic diagram for preparing enhancement-mode gate metal layer

[0061] Figure 10 Schematic diagram for realizing interconnection between devices

[0062] In the figure, 1. Semi-insulating β-Ga 2 O 3 substrate; 2. Unintentionally doped β-Ga 2 O 3 drift layer; 3. κ-(Al x Ga 1-x ) 2 O 3 layer; 4. κ-Ga 2 O 3 layer; 5. p-type heterojunction dielectric; 6. Depletion-mode drain metal layer; 7. Depletion-mode source metal layer; 8. Depletion-mode gate metal layer; 9. Enhancement-mode drain metal layer; 10. Enhancement-mode source metal layer; 11. Enhancement-mode gate metal layer; 12. Sapphire substrate; 13. Pin pad; 14. Isolation trench

[0063] Figure 11 Energy band structure diagram of a Ga 2 O 3 high-mobility inverter with heterogeneous integration

[0064] Figure 12 For κ-Ga 2 O 3 / β-Ga 2 O 3 Simulation structure diagram of electron mobility

[0065] Figure 13 Simulation result diagram of the transfer characteristics of depletion-mode devices

[0066] Figure 14 Simulation result diagram of the transfer characteristics of enhancement-mode devices

[0067] Figure 15 For the Ga of heterogeneous integration 2 O 3 The simulation result diagram of the voltage transfer characteristics of a high mobility inverter. Specific implementation manners

[0068] The present invention will be further described in detail below in conjunction with specific embodiments, so that those skilled in the art can understand.

[0069] Embodiment 1

[0070] This embodiment provides a high mobility inverter of heterogeneous integrated Ga 2 O 3 Combined with Figure 1 As shown, the inverter includes a semi-insulating β-Ga 2 O 3 substrate 1, an unintentionally doped β-Ga 2 O 3 drift layer 2, a κ-Ga 2 O 3 layer 4, a κ-(Al x Ga 1-x ) 2 O 3 layer 3, an unintentionally doped β-Ga 2 O 3 drift layer 2, a κ-Ga 2 O 3 layer 4 and a κ-(Al x Ga 1-x ) 2 O 3 There is an isolation trench 14 provided in the middle of layer 3;

[0071] The isolation trench 14 divides the upper surface area of the κ-(Al x Ga 1-x ) 2 O 3 layer 3 into a depletion type device area and an enhancement type device area;

[0072] The depletion type device area is successively provided with a depletion type drain metal layer 6, a depletion type gate metal layer 8 and a depletion type source metal layer 7 from far to near the isolation trench 14;

[0073] The enhancement type device area is successively provided with an enhancement type source metal layer 10, a p-type heterogeneous medium and an enhancement type gate metal combination layer, and an enhancement type drain metal layer 9 from far to near the isolation trench 14; the p-type heterogeneous medium and the enhancement type gate metal combination layer are composed of a lower layer of p-type heterogeneous medium 5 and an upper layer of enhancement type gate metal layer 11.

[0074] There is an interconnection between the depletion-mode source metal layer 7 and the enhancement-mode drain metal layer 9, and an interconnection between the depletion-mode source metal layer 7 and the depletion-mode gate metal layer 8.

[0075] Among them, pin pads 13 are provided on the surfaces of the depletion-mode drain metal layer 6, the depletion-mode source metal layer 7, the depletion-mode gate metal layer 8, the enhancement-mode gate metal layer 11, the enhancement-mode drain metal layer 9, and the enhancement-mode source metal layer 10;

[0076] The depletion-mode source metal layer 7 and the enhancement-mode drain metal layer 9 are respectively disposed on two edges of the isolation trench 14, or the depletion-mode source metal layer 7 and the enhancement-mode drain metal layer 9 extend and are disposed on the surface of the isolation trench 14.

[0077] In the hetero-integrated Ga 2 O 3 high-mobility inverter of this embodiment:

[0078] (1) The depletion-mode drain metal layer 6, the depletion-mode source metal layer 7, the enhancement-mode drain metal layer 9, and the enhancement-mode source metal layer 10 are all Ti, Au, and Ni metal layers sequentially arranged from bottom to top, and the thicknesses of Ti, Au, and Ni are 20 - 100 nm, 50 - 150 nm, and 50 - 150 nm respectively;

[0079] The p-type hetero-dielectric 5 is any one of p-NiO, p-GaN, and p-SnO;

[0080] The depletion-mode gate metal layer 8 and the enhancement-mode gate metal layer 11 are both Pt and Au metal layers sequentially arranged from bottom to top, and the thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively;

[0081] The pin pad 13 is a Ti and Au metal layer sequentially arranged from bottom to top, and the thicknesses of Ti and Au are 150 - 250 nm and 200 - 300 nm respectively.

[0082] Preferably, among the depletion-mode drain metal layer 6, the depletion-mode source metal layer 7, the enhancement-mode drain metal layer 9, and the enhancement-mode source metal layer 10, the thicknesses of Ti, Au, and Ni are 50 nm, 100 nm, and 100 nm respectively;

[0083] The p-type hetero-dielectric 5 is p-NiO;

[0084] Among the depletion-mode gate metal layer 8 and the enhancement-mode gate metal layer 11, the thicknesses of Pt and Au are 200 nm and 250 nm respectively;

[0085] Among the pin pads 13, the thicknesses of Ti and Au are 200 nm and 250 nm respectively.

[0086] (2)Unintentional doping of β-Ga 2 O 3 The thickness of the drift layer 2 is 50 - 200 nm, κ-(Al x Ga 1-x ) 2 O 3 The thickness of layer 3 is 10 - 50 nm, κ-Ga 2 O 3 The thickness of layer 4 is 20 - 50 nm.

[0087] Preferably, the unintentional doping of β-Ga 2 O 3 The thickness of the drift layer 2 is 150 nm, κ-(Al x Ga 1-x ) 2 O 3 The thickness of layer 3 is 20 nm, κ-Ga 2 O 3 The thickness of layer 4 is 30 nm.

[0088] Example 2

[0089] This example provides a method for fabricating a heterogeneously integrated Ga 2 O 3 high-mobility inverter, which includes the following steps in combination with Figures 2 to 10 as shown:

[0090] 1. As Figure 2 shown, use the MOCVD technology to fabricate an unintentionally doped β-Ga 2 O 3 drift layer 2 with a thickness of 50 - 200 nm on the semi-insulating β-Ga 2 O 3 substrate 1.

[0091] 2. As Figure 3 shown, use the tin-assisted pulsed laser deposition technology to grow, from bottom to top, a κ-Ga 2 O 3 layer 4 with a thickness of 100 - 200 nm, a κ-(Al x Ga 1-x ) 2 O 3 layer 3 with a thickness of 100 - 500 nm, and a κ-Ga 2 O 3 layer 4 with a thickness of 20 - 50 nm on the sapphire substrate 12.

[0092] 3. As Figure 4 shown, inject H + into κ-(Alx Ga 1-x ) 2 O 3 In layer 3, a bonding machine is used in combination with the peel-and-transfer technology to bond the κ-GaO layer with a thickness of 20 - 50 nm 2 O 3 layer 4 to the unintentionally doped β-GaO drift layer 2. Finally, through high-temperature annealing, the κ-GaO layer 4 with a thickness of 100 - 200 nm on the upper layer and the sapphire substrate 12 are separated from the κ-(AlGa)O layer 3. The conditions for high-temperature annealing are an annealing temperature of 1100 °C for 30 - 60 min. Chemical mechanical polishing is used to planarize and polish the surface of the κ-(AlGa)O layer 3 until its thickness is 10 - 50 nm. The κ-(AlGa)O layer 3 is located at the top of the κ-GaO layer 4, and a two-dimensional electron gas is formed at the interface between the two through polarization induction. 2 O 3 In layer 3, a bonding machine is used in combination with the peel-and-transfer technology to bond the κ-GaO layer with a thickness of 20 - 50 nm 2 O 3 layer 4 to the unintentionally doped β-GaO drift layer 2. Finally, through high-temperature annealing, the κ-GaO layer 4 with a thickness of 100 - 200 nm on the upper layer and the sapphire substrate 12 are separated from the κ-(AlGa)O layer 3. The conditions for high-temperature annealing are an annealing temperature of 1100 °C for 30 - 60 min. Chemical mechanical polishing is used to planarize and polish the surface of the κ-(AlGa)O layer 3 until its thickness is 10 - 50 nm. The κ-(AlGa)O layer 3 is located at the top of the κ-GaO layer 4, and a two-dimensional electron gas is formed at the interface between the two through polarization induction. x Ga 1-x ) 2 O 3 layer 3. The conditions for high-temperature annealing are an annealing temperature of 1100 °C for 30 - 60 min. Chemical mechanical polishing is used to planarize and polish the surface of the κ-(AlGa)O layer 3 until its thickness is 10 - 50 nm. The κ-(AlGa)O layer 3 is located at the top of the κ-GaO layer 4, and a two-dimensional electron gas is formed at the interface between the two through polarization induction. x Ga 1-x ) 2 O 3 layer 3. The κ-(AlGa)O layer 3 is located at the top of the κ-GaO layer 4, and a two-dimensional electron gas is formed at the interface between the two through polarization induction. x Ga 1-x ) 2 O 3 layer 3 is located at the top of the κ-GaO 2 O 3 layer 4, and a two-dimensional electron gas is formed at the interface between the two through polarization induction.

[0093] 4. As shown in Figure 5 , after lithographic selection, the sample is etched using the RIE-ICP etching technology until it reaches the surface of the semi-insulating β-GaO substrate 1, forming an isolation trench 14 between the depletion-type device and the enhancement-type device. A stripping solution is used to remove the excess photoresist, and the sample is cleaned. The device isolation trench 14 isolates the depletion-type device from the enhancement-type device. 2 O 3 , after lithographic selection, the sample is etched using the RIE-ICP etching technology until it reaches the surface of the semi-insulating β-GaO substrate 1, forming an isolation trench 14 between the depletion-type device and the enhancement-type device. A stripping solution is used to remove the excess photoresist, and the sample is cleaned. The device isolation trench 14 isolates the depletion-type device from the enhancement-type device.

[0094] 5. As shown in Figure 6 , lithography technology is used on the κ-(AlGa)O x Ga 1-x ) 2 O 3After selecting the depletion-mode drain region, depletion-mode source region, enhancement-mode drain region, and enhancement-mode source region on the surface of layer 3, Ti, Au, and Ni metal layers are sequentially grown in the depletion-mode drain region, depletion-mode source region, enhancement-mode drain region, and enhancement-mode source region through electron beam evaporation technology to form a depletion-mode drain metal layer 6, a depletion-mode source metal layer 7, an enhancement-mode drain metal layer 9, and an enhancement-mode source metal layer 10. The thicknesses of Ti, Au, and Ni are 20 - 100 nm, 50 - 150 nm, and 50 - 150 nm respectively. Use a stripping solution to remove the excess photoresist and metal, and clean the sample. Subsequently, rapid thermal annealing is performed at 800 °C for 30 seconds, and the depletion-mode drain metal layer 6, depletion-mode source metal layer 7, enhancement-mode drain metal layer 9, and enhancement-mode source metal layer 10 respectively form ohmic contacts with κ-(Al x Ga 1-x ) 2 O 3 layer 3. In this embodiment, the depletion-mode source metal layer 7 and the enhancement-mode drain metal layer 9 extend and are disposed on the surface of the isolation trench 14, and the depletion-mode source metal layer 7 and the enhancement-mode drain metal layer 9 are in contact with each other.

[0095] 6. As shown in Figure 7 , lithography technology selects a depletion-mode gate region on the surface of κ-(Al x Ga 1-x ) 2 O 3 layer 3. The Pt and Au metal layers are sequentially grown in the depletion-mode gate region by electron beam evaporation technology. The thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively to form a depletion-mode gate metal layer 8, and a Schottky contact is formed with κ-(Al x Ga 1-x ) 2 O 3 layer 3. Use a stripping solution to remove the excess photoresist and metal, and clean the sample.

[0096] 7. As shown in Figure 8 , lithography technology selects an enhancement-mode gate region on the surface of κ-(Al x Ga 1-x ) 2 O 3 layer 3. The p-type hetero medium 5 is grown in the enhancement-mode gate region by magnetron sputtering technology. The p-type hetero medium 5 is any one of p-NiO, p-GaN, and p-SnO. The p-type hetero medium 5 is used to deplete the carriers under the gate to form an enhancement-mode device.

[0097] 8. As shown in Figure 9As shown, Pt and Au metal layers are sequentially grown self-aligned on the surface of the p-type heterogeneous medium 5 by electron beam evaporation technology. The thicknesses of Pt and Au are 150 - 250 nm and 200 - 300 nm respectively, forming the enhanced gate metal layer 11. Use a stripping solution to remove the excess photoresist and metal, and clean the sample.

[0098] 9. As Figure 10 shown, after lithographically selecting the pin pad (PAD) area, use electron beam evaporation technology to sequentially grow Ti and Au metal layers on the depletion-type drain metal layer 6, depletion-type source metal layer 7, depletion-type gate metal layer 8, enhanced drain metal layer 9, enhanced source metal layer 10, and enhanced gate metal layer 11 respectively, to form the pin pad 13. The thicknesses of Ti and Au are 150 - 250 nm and 200 - 300 nm respectively. The depletion-type source metal layer 7 is interconnected with the enhanced drain metal layer 9 through the PAD, and the depletion-type source metal layer 7 is interconnected with the depletion-type gate metal layer 8 (the depletion-type source metal layer 7 and the enhanced drain metal layer 9 are jointly connected to the depletion-type gate metal layer 8), realizing the interconnection between devices. Use a stripping solution to remove the excess photoresist and metal, and clean the sample. A heterogeneous integrated Ga 2 O 3 high-mobility inverter is prepared.

[0099] Example 3

[0100] This example provides a method for preparing a heterogeneous integrated Ga 2 O 3 high-mobility inverter. The preparation method is the same as that in Example 2, except that the methods for preparing the κ-Ga 2 O 3 layer 4 and the κ-(Al x Ga 1-x ) 2 O 3 layer 3 are different (i.e., steps 2 and 3 in Example 2). In this example, the methods for preparing the κ-Ga 2 O 3 layer 4 and the κ-(Al x Ga 1-x ) 2 O 3 layer 3 are as follows:

[0101] On the unintentionally doped β-Ga 2 O 3 drift layer 2, sequentially epitaxially grow a 20 - 50 nm κ-Ga 2 O 3 layer 4 and a 10 - 50 nm κ-(Al x Ga 1-x ) 2 O3 Layer 3, κ-(Al x Ga 1-x ) 2 O 3 Layer 3 and κ-Ga 2 O 3 At the interface of layer 4, a two-dimensional electron gas is formed by polarization induction.

[0102] Example 4

[0103] 1. Simulate the heterogeneously integrated Ga 2 O 3 high-mobility inverter in Silvaco TCAD simulation software, and extract its energy band structure diagram, as Figure 11 shown. In the figure, label 1 is the κ-(Al x Ga 1-x ) 2 O 3 layer, label 2 is the κ-Ga 2 O 3 layer, and label 3 is the β-Ga 2 O 3 layer. Between the κ-(Al x Ga 1-x ) 2 O 3 layer and the κ-Ga 2 O 3 layer, a two-dimensional electron gas is generated by polarization induction, which has a relatively high mobility, as Figure 12 shown. In the figure, label 1 is the mobility of the κ-(Al x Ga 1-x ) 2 O 3 layer, label 2 is the mobility of the two-dimensional electron gas in the κ-Ga 2 O 3 layer, and label 3 is the mobility of the β-Ga 2 O 3 layer. The inverter thus has a high switching speed.

[0104] 2. Analyze the transfer characteristics of the depletion-type device and the enhancement-type device in the heterogeneously integrated Ga 2 O 3 high-mobility inverter of Example 1, as Figure 13 and Figure 14 shown. The threshold voltage of the depletion-type device is about -5.8 V, and the threshold voltage of the enhancement-type device is about 2 V, which proves the feasibility of implementing the inverter by monolithic integration of this scheme.

[0105] 3. Analyze the voltage transfer characteristics of the heterogeneously integrated Ga 2 O 3 high-mobility inverter of Example 1, asFigure 15 The input voltage V shown in Switches from a low voltage to a high voltage, and the output voltage V out Switches from a high voltage to a low voltage to achieve the function of logical negation.

[0106] Other parts not described in detail are all prior arts. Although the above embodiments have made a detailed description of the present invention, they are only a part of the embodiments of the present invention, rather than all embodiments. People can also obtain other embodiments based on these embodiments without creative efforts, and these embodiments all fall within the protection scope of the present invention.

Claims

1. A method for preparing a heterogeneously integrated Ga2O3 high-mobility inverter, characterized in that: The following steps are involved: S1: Preparing an unintentionally doped β-Ga2O3 drift layer (2) on a semi-insulating β-Ga2O3 substrate (1) using MOCVD technology; S2: Sequentially prepare a κ-Ga2O3 layer (4) and a κ-(Al x Ga 1-x )2O3 layer (3), κ-Ga2O3 layer (4) and κ-(Al x Ga 1-x )2O3 layers (3) form a two-dimensional electron gas through polarization induction; S3: Using RIE-ICP etching technology to κ-(Al x Ga 1-x ) etching the middle part of the surface of the β-Ga2O3 layer (3) until the surface of the semi-insulating β-Ga2O3 substrate (1) is reached to form an isolation groove (14); S4: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer (3) defines a depletion type drain region, a depletion type source region, an enhanced type drain region and an enhanced type source region on the surface, and Ti, Au and Ni metal layers are grown in sequence by electron beam evaporation technology to form a depletion type drain metal layer (6), a depletion type source metal layer (7), an enhanced type drain metal layer (9) and an enhanced type source metal layer (10), and the depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced type drain metal layer (9) and the enhanced type source metal layer (10) are respectively connected to κ-(Al x Ga 1-x )2O3 layer (3) forms an ohmic contact; S5: Using photolithography technology, κ-(Al x Ga 1-x )2O3 layer (3) defines a depletion gate region on the surface, and Pt and Au metal layers are grown in sequence using electron beam evaporation technology to form a depletion gate metal layer (8), which is then bonded to the κ-(Al x Ga 1-x )2O3 layer (3) forms a Schottky contact; S6: Using photolithography technology to x Ga 1-x ) The surface of the 2O3 layer (3) defines an enhanced gate region, and a p-type heterogeneous medium (5) is grown by magnetron sputtering technology; S7: using electron beam evaporation technology to sequentially grow Pt and Au metal layers on the surface of the p-type heterogeneous medium (5) in a self-aligned manner to form an enhanced gate metal layer (11); S8: Ti and Au metal layers are grown in sequence on the depletion type drain metal layer (6), the depletion type source metal layer (7), the depletion type gate metal layer (8), the enhanced type drain metal layer (9), the enhanced type source metal layer (10) and the enhanced type gate metal layer (11) using electron beam evaporation technology to form a pin pad (13). The depletion type source metal layer (7) and the enhanced type drain metal layer (9) are interconnected by the pin pad and are connected to the depletion type gate metal layer (8) together, thereby obtaining a heterogeneously integrated Ga2O3 high-mobility inverter.

2. The method according to claim 1, characterized in that: In step S2, the peeling transfer technology specifically includes the following steps: 1) Using Sn-assisted pulsed laser deposition technology, a κ-Ga2O3 layer (4) with a thickness of 100-200 nm, a κ-(Al2O3) layer with a thickness of 100-500 nm, and a κ-(Al2O3) layer with a thickness of 100-200 nm were grown on a sapphire substrate (12) from bottom to top. x Ga 1-x )2O3 layer (3) and a κ-Ga2O3 layer with a thickness of 20~50 nm (4); 2) Implant hydrogen ions into κ-(Al x Ga 1-x )2O3 layer (3), using a bonding machine to bond a κ-Ga2O3 layer (4) with a thickness of 20 to 50 nm to an unintentionally doped β-Ga2O3 drift layer (2); 3) Finally, high temperature annealing is performed to bond the κ-Ga2O3 layer (4) with a thickness of 100-200 nm and the sapphire substrate (12) to the κ-(Al x Ga 1-x )2O3 layer (3) separation, for κ-(Al x Ga 1-x The surface of the SiO2O3 layer (3) is flattened and polished to a thickness of 10-50 nm.

3. The method according to claim 2, characterized in that: The high temperature annealing conditions are: annealing temperature is 1100° C., 30-60 min.

4. The method according to claim 1, characterized in that: In the depletion type drain metal layer (6), the depletion type source metal layer (7), the enhanced drain metal layer (9) and the enhanced source metal layer (10), the thicknesses of Ti, Au and Ni are 20-100 nm, 50-150 nm and 50-150 nm respectively; The p-type heterogeneous medium (5) is any one of p-NiO, p-GaN, and p-SnO; In the depletion-type gate metal layer (8) and the enhancement-type gate metal layer (11), the thicknesses of Pt and Au are 150-250 nm and 200-300 nm, respectively; In the pin pad (13), the thickness of Ti and Au is 150~250 nm and 200~300 nm, respectively; The thickness of the unintentionally doped β-Ga2O3 drift layer (2) is 50-200 nm, and the κ-(Al x Ga 1-x )2O3 layer (3) has a thickness of 10~50 nm, and the thickness of κ-Ga2O3 layer (4) has a thickness of 20~50 nm.

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