Adjustable polarized photoelectric detector and preparation method thereof

Abstract

The invention relates to an adjustable polarized photoelectric detector and a preparation method thereof. A tunable polarized photoelectric detector may include: a substrate serving as a gate; the gate insulating layer is formed on the substrate; a charge trapping layer formed on the gate insulating layer; a tunneling layer formed on the charge trapping layer; a first semiconductor layer formed on the tunneling layer and including an isotropic two-dimensional semiconductor layer; a second semiconductor layer formed on the tunneling layer, including an anisotropic two-dimensional semiconductor layer, and partially overlapping the first semiconductor layer to form a first semiconductor heterojunction; a first electrode and a second electrode formed on the tunneling layer and connected to the first semiconductor layer and the second semiconductor layer, respectively; and a back gate electrode formed on a side of the substrate opposite to the gate insulating layer.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detectors, and more particularly to a polarization photoelectric detector with adjustable operating characteristics and a preparation method thereof. Background Art

[0002] In the field of modern optical communications, traditional photodetectors can often only realize a single photoelectric conversion function. In practical applications, photodetectors are also expected to have more functions, such as integrating optical signal detection, amplification, and signal processing functions in the photodetector. Taking high-speed optical fiber communication as an example, a photodetector with integrated signal amplification function can directly amplify and detect weak optical signals, reducing the impact of losses during signal transmission and improving the quality and distance of communication. Therefore, it is expected that the operating characteristics of the photodetector, such as light responsiveness, carrier concentration, threshold voltage, etc., can be regulated. In addition, in some application scenarios, the photodetector is also expected to have polarization sensitivity, and it is expected that the operating characteristics of the polarization photodetector can be regulated as needed. Summary of the invention

[0003] In view of this, one aspect of the present invention is to provide an adjustable polarization photodetector device, which can realize polarization photodetection, and can also realize the regulation of light response and linear polarization degree, and has the characteristics of non-volatile regulation. Another aspect of the present invention is to provide a method for preparing an adjustable polarization photodetector device.

[0004] According to one embodiment, an adjustable polarization photodetector may include: a substrate, which is used as a gate; a gate insulating layer, which is formed on the substrate; a charge trapping layer, which is formed on the gate insulating layer; a tunneling layer, which is formed on the charge trapping layer; a first semiconductor layer, which is formed on the tunneling layer and includes an isotropic two-dimensional semiconductor layer; a second semiconductor layer, which is formed on the tunneling layer, includes an anisotropic two-dimensional semiconductor layer, and partially overlaps with the first semiconductor layer to form a first semiconductor heterojunction; a first electrode and a second electrode, which are formed on the tunneling layer and are connected to the first semiconductor layer and the second semiconductor layer, respectively; and a back gate electrode, which is formed on the side of the substrate opposite to the gate insulating layer.

[0005] In one example, the adjustable polarization photodetector may further include: a third semiconductor layer, wherein the first semiconductor layer partially overlaps the second semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the first semiconductor layer to form a second semiconductor heterojunction, and the third semiconductor layer includes an anisotropic two-dimensional semiconductor layer and is connected to the second electrode.

[0006] In one example, a photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the third semiconductor layer and a photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the second semiconductor layer are oriented in the same direction.

[0007] In one example, the adjustable polarization photodetector may also include: a third semiconductor layer, wherein the second semiconductor layer partially overlaps the first semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the second semiconductor layer to form a second semiconductor heterojunction, and the third semiconductor layer includes an isotropic two-dimensional semiconductor layer and is connected to the first electrode.

[0008] In one example, the isotropic two-dimensional semiconductor layer includes MoS2, MoSe2, WS2, WSe2 or graphene, and the anisotropic two-dimensional semiconductor layer includes PdSe2, ReS2 or black phosphorus.

[0009] In one example, the back gate electrode is configured to receive a pulse signal so that electrons pass through the tunneling layer and enter the charge trapping layer, and the trapped electrons adjust the built-in electric field of the semiconductor heterojunction on the tunneling layer to regulate the photoresponsivity and linear polarization degree of the polarization photodetector.

[0010] According to another embodiment, a method for preparing an adjustable polarization photodetector may include: providing a substrate used as a gate; forming a gate insulating layer, a charge trapping layer and a tunneling layer in sequence on the substrate; forming a first semiconductor layer and a second semiconductor layer on the tunneling layer, the first semiconductor layer including an isotropic two-dimensional semiconductor layer, the second semiconductor layer including an anisotropic two-dimensional semiconductor layer, the first semiconductor layer and the second semiconductor layer partially overlap to form a first semiconductor heterojunction; forming a first electrode and a second electrode connected to the first semiconductor layer and the second semiconductor layer, respectively, on the tunneling layer; and forming a back gate electrode on the side of the substrate opposite to the gate insulating layer.

[0011] In one example, the method may further include: forming a third semiconductor layer on the tunneling layer, the first semiconductor layer partially overlapping the second semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlapping the first semiconductor layer to form a second semiconductor heterojunction, the third semiconductor layer including an anisotropic two-dimensional semiconductor layer and connected to the second electrode.

[0012] In one example, a photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the third semiconductor layer and a photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the second semiconductor layer are oriented in the same direction.

[0013] In one example, the method may further include: forming a third semiconductor layer on the tunneling layer, the second semiconductor layer partially overlapping the first semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlapping the second semiconductor layer to form a second semiconductor heterojunction, the third semiconductor layer including an isotropic two-dimensional semiconductor layer and connected to the first electrode.

[0014] The present invention has the following beneficial effects:

[0015] (1) It is difficult for traditional polarization photodetectors to achieve non-volatile polarization information regulation. Therefore, it is of great practical significance to develop a polarization photodetector device that can achieve non-volatile regulation. The present invention uses the charge trapping structure and the two-dimensional material heterostructure to cooperate with each other to prepare a composite structure. By applying a pulse voltage to the gate, the charge trapping layer can capture the channel carriers, thereby changing the carrier concentration and band structure of the device, and realizing the regulation of transport characteristics such as light response and linear polarization degree.

[0016] (2) Traditional polarization photodetectors usually use a combination of multiple optical elements to detect polarized light. This method is not conducive to the miniaturization and integration of devices, and it is impossible to achieve non-volatile regulation of photoresponsivity and linear polarization, which limits its application in polarization photodetection. The present invention uses the anisotropic photoelectric response of anisotropic two-dimensional materials to achieve polarization photodetection. The present invention uses the polarization-sensitive light absorption of anisotropic two-dimensional materials, and by forming a semiconductor heterostructure with anisotropic two-dimensional materials, the built-in electric field of the heterojunction is used to separate carriers, and self-driven polarization photodetection is achieved in the visible light band (420 nanometers to 650 nanometers). The present invention uses the charge trapping structure to store charges to achieve regulation of the semiconductor band structure and carrier concentration, thereby changing the intensity of the built-in electric field and achieving active regulation of polarization and photoresponsivity. Relying on the different amounts of charge captured in the charge trapping layer, the energy band of the semiconductor material is regulated, and the characteristics of the device, such as the switching ratio, can be changed. The polarization photodetector of the present invention has the characteristic of non-volatility, can store control data for a long time, can realize the control of both light response degree and linear polarization degree, and can flexibly realize polarization photodetection.

[0017] (3) In addition, the preparation process of the polarization photodetector device of the present invention is simple, time-saving, low-cost, and suitable for large-area preparation, and has great application value.

[0018] The above and other features and advantages of the present invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is a schematic structural diagram of a polarization photodetector according to an embodiment of the present invention.

[0020] Figure 1B is a schematic structural diagram of a polarization photodetector according to another embodiment of the present invention.

[0021] Figure 1C is a schematic structural diagram of a polarization photodetector according to another embodiment of the present invention.

[0022] Figure 1D is a schematic structural diagram of a polarization photodetector according to another embodiment of the present invention.

[0023] Figure 2 is an output characteristic curve of a polarization photodetector according to an embodiment of the present invention.

[0024] Figure 3A 1 is a storage characteristic curve of a polarization photodetector under different gate voltages according to an embodiment of the present invention.

[0025] Figure 3B is a curve showing the relationship between the storage window and the gate voltage of the polarization photodetector according to an embodiment of the present invention.

[0026] Figure 4A 1 is an output characteristic curve of a polarization photodetector under different gate pulse widths according to an embodiment of the present invention.

[0027] Figure 4B 1 is an output characteristic curve of a polarization photodetector according to an embodiment of the present invention at different gate pulse amplitudes.

[0028] Figure 5A 1 is a photoelectric characteristic curve of a polarization photodetector in a polarization direction under a positive pulse and a negative pulse according to an embodiment of the present invention.

[0029] Figure 5B 1 is a photoelectric characteristic curve of a polarization photodetector according to an embodiment of the present invention in a direction perpendicular to the polarization direction under positive pulses and negative pulses.

[0030] Fig. 6A 1 is a measurement result of the photoresponsivity of the polarization photodetector under different gate voltages according to an embodiment of the present invention.

[0031] Figure 6B 1 is a measurement result of the linear polarization degree of the polarization photodetector under different gate voltages according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the accompanying drawings may not be drawn to scale.

[0033] In the context of the present invention, the term "non-volatile" means that after a pulse voltage is applied to the gate, the charge trapping layer can capture electrons or holes in the channel material, and when the gate voltage is removed, the electrons and holes captured in the channel can still be retained.

[0034] In the context of the present invention, the term "photoresponsivity" refers to the ratio of the device photocurrent to the laser power under a specific wavelength laser. The higher the photoresponsivity, the more sensitive the device is to light irradiation.

[0035] In the context of the present invention, the term "linear polarization degree" refers to the ratio of the difference between the maximum and minimum current values ​​of the device and the sum of the maximum and minimum current values ​​under a laser of a specific wavelength. The higher the linear polarization degree, the greater the resolution of the device for linearly polarized light.

[0036] Figure 1A 1 is a schematic diagram of the structure of a polarization photodetector according to an embodiment of the present invention. As shown in FIG1 , the photodetector includes an insulating layer 120, a charge trapping layer 130, and a tunneling layer 140 stacked in sequence on a substrate 110. A first two-dimensional semiconductor layer 150 and a second two-dimensional semiconductor layer 160 are formed on the tunneling layer 140 and partially overlap each other. The substrate 110 is used as a gate layer, and a gate electrode 101, also referred to as a back gate electrode, is formed on its back side. The first electrode 102 is formed on the tunneling layer 140 and is in contact with the first two-dimensional semiconductor layer 150, and the second electrode 103 is formed on the tunneling layer 140 and is in contact with the second two-dimensional semiconductor layer 160. In one embodiment, the first electrode 102 may be formed on the first two-dimensional semiconductor layer 150, or the first two-dimensional semiconductor layer 150 may cover the first electrode 102. Similarly, the second electrode 103 may be formed on the second two-dimensional semiconductor layer 160, or the second two-dimensional semiconductor layer 160 may cover the second electrode 103.

[0037] The substrate 110 used as a gate may include a semiconductor material, such as but not limited to Si, or may also include a material suitable for forming a metal gate, such as TiN, TaN, W, Co, Au, Al, etc. The substrate 110 may have an appropriate thickness, such as in the range of 100 microns to 1000 microns, preferably in the range of 200 microns to 800 microns, such as about 500 microns. The gate electrode 101 may be used to apply a voltage to the substrate 110 to perform related operations, which will be discussed in further detail below.

[0038] The insulating layer 120, which may also be referred to as a gate insulating layer, may be formed of a single layer or a multi-layer insulating film, wherein a single layer is preferred, and it may include commonly used insulating materials, such as but not limited to SiO2, Al2O3, MgO, etc. Depending on different materials, the thickness of the insulating layer 120 may be in the range of 4 nm to 100 nm, preferably in the range of 10 nm to 50 nm, or more preferably in the range of 20 nm to 40 nm.

[0039] The charge trapping layer 130 may be formed of a material suitable for trapping / storing charges, examples of which include but are not limited to SiN, HfO2, etc. The charge trapping layer 130 may be formed as a single layer, or as a multi-layer structure, wherein the total thickness of the charge trapping layer 130 may be in the range of 4 nm to 20 nm, preferably in the range of 5 nm to 10 nm.

[0040] The tunneling layer 140 may include insulating materials such as SiO2, Al2O3, MgO, etc., and is preferably formed into a single-layer structure with a relatively thin thickness so that carriers can tunnel through the layer and be captured by the charge trapping layer 130. For example, the thickness of the tunneling layer 140 may be in the range of 2nm to 10nm, preferably in the range of 4nm to 8nm. It should be understood that under the control of the gate voltage, carriers such as electrons pass through the tunneling layer and are captured / stored in the charge trapping layer. This structure and principle have been widely used in, for example, non-volatile flash memories, and therefore will not be described in detail here. In the present invention, by integrating this structure in a photodetector, the performance of the photodetector can be controlled, and this control can be non-volatile, which will be further described in detail below.

[0041] like Figure 1A As shown, the overlapping first two-dimensional semiconductor layer 150 and the second two-dimensional semiconductor layer 160 form a semiconductor heterojunction for performing photoelectric conversion and detection. In an embodiment of the present invention, any one of the first two-dimensional semiconductor layer 150 and the second two-dimensional semiconductor layer 160 may be an isotropic two-dimensional semiconductor layer, and the other may be an anisotropic two-dimensional semiconductor layer. For the convenience of description, it is assumed here that the first two-dimensional semiconductor layer 150 is an isotropic two-dimensional semiconductor layer and the second two-dimensional semiconductor layer 160 is an anisotropic two-dimensional semiconductor layer. As an example, the isotropic two-dimensional semiconductor layer may include but is not limited to MoS2, MoSe2, WS2, WSe2 or graphene, etc., and the anisotropic two-dimensional semiconductor layer may include but is not limited to PdSe2, ReSe2 or black phosphorus, etc.

[0042] The inventors of the present application have found that when an anisotropic two-dimensional semiconductor material is combined with an isotropic two-dimensional semiconductor material to form a semiconductor heterojunction, due to the difference in Fermi levels, electrons will move in a directional manner at the contact interface, thereby generating a built-in electric field, which can accelerate the separation of carriers, thereby realizing self-driven photoelectric detection. In addition, by combining the heterostructure with a charge trapping structure, the charge trapping structure can be used to control the carrier concentration of the device, thereby adjusting the intensity of the built-in electric field to achieve control of the photoresponsivity and linear polarization, and depending on the characteristics of the charge trapping structure, this control can be non-volatile. In an embodiment of the present invention, by selecting and using appropriate anisotropic two-dimensional semiconductor materials and isotropic two-dimensional semiconductor materials, for example, the isotropic two-dimensional semiconductor layer can be selected from MoS2, MoSe2, WS2, WSe2 and graphene, etc., and the anisotropic two-dimensional semiconductor layer can be selected from PdSe2, ReSe2 and black phosphorus, etc., self-driven polarization photoelectric detection can be achieved in the visible light band, such as the wavelength range of 420 nanometers to 650 nanometers, which has broad practical value.

[0043] In the embodiment of the present invention, the charge trapping layer 130 can capture electrons or holes by applying appropriate pulses to the back gate electrode 101, and the threshold voltage of the semiconductor device can be regulated by using the electric field shielding effect, thereby achieving non-volatile regulation of the transport characteristics. In addition, the charge trapping layer 130 can also capture charges by applying an appropriate constant voltage.

[0044] In the embodiments of the present invention, the role of the anisotropic two-dimensional semiconductor material is to utilize the anisotropy of the material's own structure. For incident light with different polarization directions, the material generates different numbers of photogenerated carriers. This property can be used to achieve anisotropic photoelectric response. For excitation light with different polarization directions, the device can generate photocurrents of different magnitudes.

[0045] In an embodiment of the present invention, the role of the isotropic two-dimensional semiconductor material is to form a semiconductor heterojunction together with the anisotropic two-dimensional semiconductor material. The built-in electric field generated by the isotropic two-dimensional semiconductor material can accelerate the separation of electron-hole pairs generated by the photoelectric effect, and the energy band of the material can be regulated by the back gate voltage to achieve the regulation of the carrier concentration and the size of the built-in electric field.

[0046] In the embodiment of the present invention, the charge trapping structure cooperates with the two-dimensional material heterojunction, and the charge trapping structure is used to capture the carriers. The charge trapping layer can change the carrier concentration and the built-in electric field of the heterojunction by capturing the charges, so as to achieve the regulation of the characteristics such as the photoresponsivity and the linear polarization degree. The specific regulation will be referred to below. Figure 2-6B Describe in detail.

[0047] Figure 1B, Figure 1C and Figure 1D Shows Figure 1A Some variations of the polarization photodetector shown in the figure, in which the same layers are indicated by the same reference numerals, the repeated description of the same parts will be omitted below, and the different parts will be described in detail. Figure 1B ,and Figure 1A The second two-dimensional semiconductor layer 160 overlaps the first two-dimensional semiconductor layer 150. Figure 1B In the illustrated embodiment, the first two-dimensional semiconductor layer 150 may overlap the second two-dimensional semiconductor layer 160. It is understood that, according to the material selection in practical applications, the layer with higher transparency in the first two-dimensional semiconductor layer 150 and the second two-dimensional semiconductor layer 160 may overlap one another to promote visible light irradiation to the vicinity of the interface of the heterojunction and improve the photoelectric conversion efficiency.

[0048] Continue to refer to Figure 1C , two second two-dimensional semiconductor layers 160a and 160b may be formed, which overlap above and below the first two-dimensional semiconductor layer 150, respectively, to form two semiconductor heterojunctions. The two second two-dimensional semiconductor layers 160a and 160b may be formed of the same or different anisotropic two-dimensional semiconductor materials, and they may both be connected to the second electrode 103. In this way, the photoelectric conversion efficiency may be further improved.

[0049] Similarly, in Figure 1D In the illustrated embodiment, two first two-dimensional semiconductor layers 150a and 150b may be formed, which overlap above and below the second two-dimensional semiconductor layer 160, respectively, to form two semiconductor heterojunctions. The two first two-dimensional semiconductor layers 150a and 150b may be formed of the same or different isotropic two-dimensional semiconductor materials, and they may both be connected to the first electrode 102. In this way, the photoelectric conversion efficiency may be further improved.

[0050] The following describes a method for preparing a controllable polarization photodetector of the present invention. According to one embodiment, the preparation method may include the following steps:

[0051] (1) Providing a substrate 110 used as a gate;

[0052] (2) forming a gate insulating layer 120, a charge trapping layer 130 and a tunneling layer 140 in sequence on the substrate 110;

[0053] (3) forming a first semiconductor layer 150 and a second semiconductor layer 160 on the tunneling layer 140, wherein the first semiconductor layer 150 may include an isotropic two-dimensional semiconductor material, the second semiconductor layer 160 may include an anisotropic two-dimensional semiconductor material, and the first semiconductor layer 150 and the second semiconductor layer 160 partially overlap to form a first semiconductor heterojunction;

[0054] (4) forming a first electrode 102 and a second electrode 103 connected to the first semiconductor layer 150 and the second semiconductor layer 160 respectively on the tunneling layer 140; and

[0055] (5) The back gate electrode 101 is formed on the side of the substrate 110 opposite to the gate insulating layer 120 .

[0056] In one embodiment, the first semiconductor layer 150 may partially overlap the second semiconductor layer 160 (see Figure 1B ), a third semiconductor layer 160b may be formed on the tunneling layer 140 (see Figure 1C , wherein the second semiconductor layer is shown as 160a), which may partially overlap the first semiconductor layer 150 to form a second semiconductor heterojunction. The third semiconductor layer 160b may include an anisotropic two-dimensional semiconductor layer and is connected to the second electrode 103, wherein the photosensitive axis of the anisotropic two-dimensional semiconductor layer of the third semiconductor layer 160b and the photosensitive axis of the anisotropic two-dimensional semiconductor layer of the second semiconductor layer 160a are oriented in the same direction.

[0057] In another embodiment, the second semiconductor layer 160 may partially overlap the first semiconductor layer 150 (see Figure 1A ), a third semiconductor layer 150b may be formed on the tunneling layer 140 (see Figure 1D , wherein the first semiconductor layer is shown as 150a), the third semiconductor layer 150b may partially overlap the second semiconductor layer 160 to form a second semiconductor heterojunction. The third semiconductor layer 150b may include an isotropic two-dimensional semiconductor layer and is connected to the first electrode 102.

[0058] In some embodiments, the gate insulating layer 120 can be formed by any one of the following methods: physical vapor deposition methods such as electron beam evaporation deposition and magnetron sputtering deposition, chemical vapor deposition methods such as plasma enhanced chemical vapor deposition and atomic layer deposition, and thin film coating methods including spin coating, spray coating, etc.

[0059] In some embodiments, the charge trapping layer 130 can be formed by any one of the following methods: physical vapor deposition methods such as electron beam evaporation deposition and magnetron sputtering deposition, chemical vapor deposition methods such as plasma enhanced chemical vapor deposition and atomic layer deposition, and thin film coating methods including spin coating, spray coating, etc.

[0060] In some embodiments, the tunneling layer 140 can be formed by any one of the following methods: physical vapor deposition methods such as electron beam evaporation deposition and magnetron sputtering deposition, chemical vapor deposition methods such as plasma enhanced chemical vapor deposition and atomic layer deposition, and thin film coating methods including spin coating and spray coating.

[0061] The isotropic and anisotropic two-dimensional semiconductor material layers can be formed by a separate process such as chemical vapor deposition, and then transferred to the tunneling layer 140 by a dry transfer process. The two-dimensional semiconductor material layer can be transferred after the first electrode 102 and the second electrode 103 are formed on the tunneling layer 140, or the first electrode 102 and the second electrode 103 can be formed after the two-dimensional semiconductor material layer is transferred. The back gate electrode 101, the first electrode 102 and the second electrode 103 can be formed by physical vapor deposition methods such as electron beam evaporation deposition and magnetron sputtering deposition. For example, a photoresist pattern layer with an opening can be formed first, and then an electrode metal layer can be deposited, and finally the photoresist layer and the metal layer portion thereon can be removed by a lift-off process, leaving the metal layer in the opening as the formed electrode.

[0062] An example is described below. Figure 1AAs shown, the polarization photodetector of this example includes a silicon wafer substrate, a 30-nanometer aluminum oxide (Al2O3) insulating layer, an 8-nanometer hafnium oxide (HfO2) charge trapping layer, a 5-nanometer aluminum oxide (Al2O3) tunneling layer, a 50-nanometer metal electrode, a 5-nanometer molybdenum disulfide (MoS2) layer, and a 20-nanometer palladium diselenide (PdSe2) layer. The specific preparation method of the composite thin film structure includes the following steps: depositing a layer of aluminum oxide film on the surface of the silicon substrate by atomic layer deposition technology, wherein the deposition temperature is 200 degrees Celsius. Then, depositing a layer of hafnium oxide film on the aluminum oxide film by atomic layer deposition technology, wherein the deposition temperature is 200 degrees Celsius. Then, depositing a layer of aluminum oxide film on the hafnium oxide film by atomic layer deposition technology, wherein the deposition temperature is 200 degrees Celsius. Then, forming a photoresist layer on the aluminum oxide film by spin coating process, and forming a photoresist pattern by exposure and development process, wherein the pattern includes an opening corresponding to the predetermined electrode position. A gold electrode layer is deposited on the photoresist pattern by electron beam evaporation technology, wherein the electron gun acceleration power is 10 kilowatts and the deposition rate is 3 nanometers / minute, and then the photoresist layer and the gold electrode layer thereon are removed using an acetone solution, leaving the gold electrode in the opening. Then, a layer of molybdenum disulfide material is transferred on the alumina tunneling layer by dry transfer technology, and a layer of palladium diselenide material is transferred on the molybdenum disulfide material by dry transfer technology, and the two are partially overlapped and contact the first electrode and the second electrode respectively. It can be understood that in another example, the molybdenum disulfide material and the palladium diselenide material can also be transferred first, and then the first electrode and the second electrode are formed. Finally, a back gate electrode layer can be formed on the back side of the silicon substrate, or it can be formed when the silicon substrate is provided.

[0063] Figure 2 The output characteristic curve of the polarization photodetector of the above example is shown. Figure 2 As shown, when a -3V back gate voltage is applied, the current-voltage curve between the first electrode 102 and the second electrode 103 is measured. It can be seen that the current under the positive voltage is significantly lower than the current under the negative voltage, indicating that the device exhibits obvious rectification characteristics, indicating that there is a built-in electric field inside the device. By utilizing the built-in electric field in the heterojunction region, self-driven photoelectric detection can be achieved.

[0064] Figure 3Ais the storage characteristic curve of the polarized photodetector of the above example under different gate voltages. A bias voltage of 1V is applied between the first electrode 102 and the second electrode 103, and the voltage applied to the back gate electrode 101 is increased from -10V to a predetermined maximum value, and then reduced to -10V. The change in the current between the first electrode 102 and the second electrode 103 is tested, and the characteristic curve is shown in the figure. The results show that the curves in the rising stage are relatively close, but the threshold voltages corresponding to the change in the switching state in the falling stage are different, indicating that the storage window of the device can be controlled by changing the size of the applied back gate voltage. When the maximum back gate voltage applied is increased from 5V to 25V, the storage window of the device increases from 2.5V to 20V, as shown in FIG. Figure 3B This characteristic can be used to control the carrier concentration of the channel material.

[0065] Figure 4A The output characteristic curve of the polarized photodetector of the above example under different gate pulse widths. First, a negative pulse with a pulse amplitude of -14V and a pulse width of 0.5s is applied to the gate of the device to erase the electrons captured in the charge trapping layer 130, and the current-voltage curve (IV curve) of the device is measured. Then, pulses with a pulse amplitude of 14V and a width ranging from 0.01s to 0.2s are applied to the gate 110 to allow the charge trapping layer 130 to capture electrons, and the current-voltage curve (IV curve) of the device is measured. Figure 4A The measurement results shown show that as the pulse width increases from 0.01s to 0.2s, the on / off ratio of the device increases. The on / off ratio is the ratio of the current between the on state and the off state of the diode formed by the semiconductor heterojunction.

[0066] Figure 4B The output characteristic curve of the polarized photodetector of the above example under different gate pulse amplitudes. First, a negative pulse with a pulse amplitude of -14V and a pulse width of 0.5s is applied to the gate of the device to erase the electrons trapped in the charge trapping layer 130. Then, voltages with a pulse width of 0.5s and different pulse amplitudes are applied to the gate to measure the current-voltage curve (IV curve) of the device. Figure 4B The measurement results shown show that as the pulse amplitude increases from 4V to 12V, the on / off ratio of the device increases. Figure 4A and Figure 4B It shows that the switching characteristics of the polarization photodetector can be regulated by controlling the width and amplitude of the pulse signal applied to the gate.

[0067] Figure 5AIt is the photoelectric characteristic curve of the polarization photodetector of the above example in the polarization direction under positive pulse and negative pulse. First, a negative pulse with a pulse amplitude of -14V and a pulse width of 0.5s is applied to the gate of the device to erase the electrons captured in the charge trapping layer 130, and in the erased state, the polarization direction of the incident light is controlled to 90 degrees, and the open circuit voltage and short circuit current of the device are measured. When measuring the open circuit voltage, the source is grounded and the drain voltage is measured. In addition, a positive pulse with a pulse amplitude of 14V and a pulse width of 0.5s is applied to the gate of the device to capture electrons in the charge trapping layer 130, which is called a write state, or a programming state, and in the write state, the polarization direction of the incident light is controlled to 90 degrees, and the open circuit voltage and short circuit current of the device are measured. It can be seen that the photocurrent of the device under the action of the negative pulse is higher than the photocurrent of the device under the action of the positive pulse.

[0068] Figure 5B The test conditions and Figure 5A The same method is used, except that the polarization direction of the incident light is controlled to be 0 degrees, and the open circuit voltage and short circuit current of the device are tested under the action of positive and negative pulses. Figure 5B It shows that the photocurrent of the device under the action of negative pulse is higher than that under the action of positive pulse. Figure 5A and Figure 5B The measurement results show that the photodetector generates different currents for polarized light in different directions, showing polarization sensitivity.

[0069] Fig. 6A It is the measurement result of the light responsivity of the polarization photodetector under different gate voltages in the above-mentioned erasing and writing states. First, a pulse signal is applied as described above to put the polarization photodetector in the erasing or writing state, and then a predetermined gate voltage is applied to measure the responsivity of the polarization photodetector, that is, the ratio between the photocurrent and the laser power. Fig. 6A As shown, as the back gate voltage increases, the photoresponsivity of the device increases. Figure 6B It is the measurement result of the linear polarization degree of the polarization photodetector under different gate voltages. As the back gate voltage of the device increases, the linear polarization degree of the device also increases.

[0070] Refer to above Figures 2 to 6B It can be seen from the measurement results that the switching characteristics, responsiveness, linear polarization degree and other characteristics of the polarization photodetector can be regulated by adjusting the amplitude and width of the pulse signal applied to the gate and the amplitude of the constant voltage signal applied to the gate.

[0071] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", "including", "comprising", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense. That is, the meaning is "including but not limited to". The word "connected" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. As generally used herein, the word "connected" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when used in this application, the words "herein", "above", "below" and words of similar meanings should refer to the entirety of this application rather than to any particular part of this application. Where the context permits, the word "or" refers to a list of two or more items, which covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0072] Furthermore, unless otherwise specifically stated or understood in the context of use, conditional language used herein, such as "can," "may," "might," "could," "for example," "for example," "such as," and the like, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or that one or more embodiments must include logic for making decisions, with or without author input or prompting, that such features, elements, and / or states are included or will be performed in any particular embodiment.

[0073] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the novel facilities, methods, and systems described herein may be embodied in various other forms; in addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform functions similar to different components and / or circuit topologies, and may delete, move, add, subdivide, combine, and / or modify some blocks. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments. The attached claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of the present disclosure.

[0074] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A controllable polarization photodetector, comprising: a substrate, which serves as a gate; a gate insulating layer formed on the substrate; a charge trapping layer formed on the gate insulating layer; a tunneling layer formed on the charge trapping layer; a first semiconductor layer formed on the tunneling layer and comprising an isotropic two-dimensional semiconductor layer; a second semiconductor layer, formed on the tunneling layer, comprising an anisotropic two-dimensional semiconductor layer, and partially overlapping the first semiconductor layer to form a first semiconductor heterojunction; A first electrode and a second electrode, which are formed on the tunneling layer and are connected to the first semiconductor layer and the second semiconductor layer respectively; as well as A back gate electrode is formed on a side of the substrate opposite to the gate insulating layer.

2. The adjustable polarization photodetector according to claim 1, further comprising: A third semiconductor layer, wherein the first semiconductor layer partially overlaps the second semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the first semiconductor layer to form a second semiconductor heterojunction, and the third semiconductor layer includes an anisotropic two-dimensional semiconductor layer and is connected to the second electrode.

3. The adjustable polarization photodetector according to claim 2, wherein: The photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the third semiconductor layer and the photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the second semiconductor layer are oriented in the same direction.

4. The adjustable polarization photodetector according to claim 1, further comprising: A third semiconductor layer, wherein the second semiconductor layer partially overlaps the first semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the second semiconductor layer to form a second semiconductor heterojunction, and the third semiconductor layer includes an isotropic two-dimensional semiconductor layer and is connected to the first electrode.

5. The adjustable polarization photodetector according to any one of claims 1 to 4, wherein: The isotropic two-dimensional semiconductor layer includes MoS2, MoSe2, WS2, WSe2 or graphene, and the anisotropic two-dimensional semiconductor layer includes PdSe2, ReSe2 or black phosphorus.

6. The adjustable polarization photodetector according to any one of claims 1 to 4, wherein: The back gate electrode is configured to receive a pulse signal so that electrons pass through the tunneling layer and enter the charge trapping layer. The trapped electrons adjust the built-in electric field of the semiconductor heterojunction on the tunneling layer to regulate the photoresponsivity and linear polarization degree of the polarization photodetector.

7. A method for preparing a controllable polarization photodetector, comprising: providing a substrate for use as a gate; forming a gate insulating layer, a charge trapping layer and a tunneling layer in sequence on the substrate; forming a first semiconductor layer and a second semiconductor layer on the tunneling layer, wherein the first semiconductor layer comprises an isotropic two-dimensional semiconductor layer, the second semiconductor layer comprises an anisotropic two-dimensional semiconductor layer, and the first semiconductor layer and the second semiconductor layer partially overlap to form a first semiconductor heterojunction; forming a first electrode and a second electrode respectively connected to the first semiconductor layer and the second semiconductor layer on the tunneling layer; as well as A back gate electrode is formed on a side of the substrate opposite to the gate insulating layer.

8. The method of claim 7, further comprising: A third semiconductor layer is formed on the tunneling layer, the first semiconductor layer partially overlaps the second semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the first semiconductor layer to form a second semiconductor heterojunction, the third semiconductor layer includes an anisotropic two-dimensional semiconductor layer and is connected to the second electrode.

9. The method of claim 8, wherein: The photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the third semiconductor layer and the photosensitive axis of the anisotropic two-dimensional semiconductor layer included in the second semiconductor layer are oriented in the same direction.

10. The method of claim 7, further comprising: A third semiconductor layer is formed on the tunneling layer, the second semiconductor layer partially overlaps the first semiconductor layer to form a first semiconductor heterojunction, the third semiconductor layer partially overlaps the second semiconductor layer to form a second semiconductor heterojunction, the third semiconductor layer includes an isotropic two-dimensional semiconductor layer and is connected to the first electrode.

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