Display device

Abstract

A display device is provided. The display device includes a display unit defined by a display area and a non-display area positioned outside the display area, and a sensing unit including pixels arranged in the display area, first sensing wirings electrically connected to the pixels, and auxiliary voltage wirings electrically separated from the pixels, the first sensing wires and the auxiliary voltage wires extend in a first direction and are sequentially arranged at a first interval in a second direction perpendicular to the first direction, the first sensing wires are spaced apart from each other at a second interval larger than the first interval in the second direction and are electrically separated from each other, and the second sensing wires are electrically connected to the auxiliary voltage wires. The auxiliary voltage wires are electrically connected to each other.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201910583392.1 and invention name “Display Device” filed on July 1, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0076362, filed on July 2, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The inventive concept relates to a display device, and more particularly, to an organic light emitting display device that compensates for degradation of pixels and variations in characteristics of a driving transistor using an external compensation technique. Background Art

[0005] The organic light emitting display device displays images using an organic light emitting diode that emits light through recombination of electrons and holes. The organic light emitting display device includes pixels, and each of the pixels includes an organic light emitting diode and a driving transistor that supplies current to the organic light emitting diode.

[0006] Organic light emitting diodes may be degraded due to use, and the characteristics (e.g., threshold voltage / mobility) of the driving transistor included in each of the pixels may be non-uniform. Therefore, a compensation technology for compensating a data signal applied to a pixel by measuring the characteristics of the transistor has been developed, and the compensation technology may be classified into an external compensation technology or an internal compensation technology according to whether a circuit for measuring the characteristics of the transistor or compensating the characteristics thereof is provided outside or inside another transistor.

[0007] A characteristic difference may occur between pixels adjacent to a sensing wiring for external compensation of pixels and pixels spaced apart from the sensing wiring. Summary of the invention

[0008] Aspects of the inventive concept provide a display device that eliminates differences in characteristics between pixels due to sensing wirings.

[0009] According to one aspect of the present disclosure, a display device is provided, the display device including a display unit and a sensing unit, the display unit being defined by a display area and a non-display area positioned outside the display area, the display unit including pixels arranged in the display area, first sensing wirings electrically connected to the pixels, and auxiliary voltage wirings electrically separated from the pixels, and the sensing unit being electrically connected to the first sensing wirings, wherein the first sensing wirings and the auxiliary voltage wirings extend in a first direction and are sequentially arranged at a first interval along a second direction perpendicular to the first direction, the first sensing wirings are spaced apart from each other at a second interval greater than the first interval along the second direction and are electrically separated from each other, and the auxiliary voltage wirings are electrically connected to each other.

[0010] In the non-display area, the auxiliary voltage wirings are electrically connected to each other.

[0011] The DC auxiliary power is applied to the auxiliary voltage wiring.

[0012] The display device further includes second sensing wirings extending in a second direction and arranged to be spaced apart from each other along the second direction, wherein the second sensing wirings are respectively connected to the first sensing wirings and the second sensing wirings are directly connected to the pixels.

[0013] The first sensing wirings intersect the second sensing wirings, respectively, and the first sensing wirings are connected to the second sensing wirings at crossing regions of the first sensing wirings and the second sensing wirings, respectively.

[0014] The auxiliary voltage wiring crosses the second sensing wiring and is electrically separated from the second sensing wiring.

[0015] The second sensing wirings are spaced apart from each other with respect to some of the auxiliary voltage wirings.

[0016] The first sensing wirings are connected to ends of the second sensing wirings, respectively.

[0017] The pixels include a first pixel configured to emit light of a first color and a second pixel configured to emit light of a second color, and the first sensing wiring is directly connected to the first pixel adjacent to the first sensing wiring and indirectly connected to the second pixel adjacent thereto.

[0018] The pixels further include a third pixel configured to emit light of a third color, and the second pixel, the first pixel, the third pixel, and the first pixel are sequentially and repeatedly arranged along the second direction.

[0019] Each of the pixels includes a light emitting element, a drive transistor configured to supply current to the light emitting element, and a sense transistor including a first electrode electrically connected to a first electrode of the drive transistor and a second electrode electrically connected to one of the first sense wirings.

[0020] The driving transistor includes a polysilicon semiconductor, and the sensing transistor includes an oxide semiconductor.

[0021] The first electrode and the second electrode of the sensing transistor are arranged on a first conductive layer, the first sensing wiring and the auxiliary voltage wiring are arranged on a second conductive layer different from the first conductive layer, the first conductive layer and the second conductive layer are insulated from each other by a first insulating layer, each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap with the second electrode of the sensing transistor, and the protrusion is electrically connected to the second electrode of the sensing transistor through a contact hole.

[0022] The display device also includes a conductive pattern having the same shape as the protrusion of each of the first sensing wirings and arranged on a third conductive layer different from the first conductive layer and the second conductive layer, wherein the conductive pattern overlaps with the second electrode of the sensing transistor and one of the auxiliary voltage wirings, and the conductive pattern is electrically connected to the second electrode of the sensing transistor and electrically separated from the auxiliary voltage wiring.

[0023] A body connected to the protrusion of the sensing unit has a width greater than an average width of the first sensing wirings, and each of the auxiliary voltage wirings has the same shape as the body of each of the first sensing wirings.

[0024] The first electrode and the second electrode of the sensing transistor are arranged on the first conductive layer, the first sensing wiring is arranged on the second conductive layer different from the first conductive layer, the auxiliary voltage wiring is arranged on the third conductive layer different from the first conductive layer and the second conductive layer, and the first conductive layer to the third conductive layer are insulated from each other by the insulating layer.

[0025] Each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap the second electrode of the sensing transistor, and each of the auxiliary voltage wirings has the same shape as each of the first sensing wirings.

[0026] Each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap with the second electrode of the sensing transistor, each of the auxiliary voltage wirings has the same shape as the body, the second conductive layer is provided with a conductive pattern overlapping with the second electrode of the sensing transistor and the auxiliary voltage wiring, and the conductive pattern is electrically connected to the second electrode of the sensing transistor and is electrically separated from the auxiliary voltage wiring.

[0027] The display device also includes a second sensing wiring, which extends in the second direction and is arranged to be spaced apart from each other in the second direction, wherein the second sensing wiring is electrically connected to the first sensing wiring, the second sensing wiring is arranged in different directions relative to the first auxiliary voltage wiring of the auxiliary voltage wiring, and the first auxiliary voltage wiring also includes a protrusion extending in the second direction and overlapping with the second sensing wiring.

[0028] The first electrode and the second electrode of the sensing transistor are arranged on the first conductive layer, the first auxiliary voltage wiring and the first sensing wiring of the auxiliary voltage wiring are arranged on the second conductive layer different from the first conductive layer, the second auxiliary voltage wiring of the auxiliary voltage wiring is arranged on the third conductive layer different from the first conductive layer and the second conductive layer, and the first conductive layer to the third conductive layer are insulated from each other by the insulating layer.

[0029] According to another aspect of the present disclosure, a display device is provided, the display device including a substrate, a driving circuit layer, a first insulating layer and a first conductive layer, the substrate being defined by a display area and a non-display area positioned outside the display area, the driving circuit layer including a transistor arranged on the display area of ​​the substrate, the first insulating layer being arranged on the driving circuit layer, and the first conductive layer including a first sensing wiring and an auxiliary voltage wiring arranged on the first insulating layer, wherein the first sensing wiring and the auxiliary voltage wiring extend in a first direction and are sequentially arranged at a first interval along a second direction perpendicular to the first direction, the first sensing wirings are spaced apart from each other at a second interval greater than the first interval in the second direction, the first sensing wirings are electrically connected to the transistors through contact holes and are electrically separated from each other, and the auxiliary voltage wirings are electrically connected to each other in the non-display area.

[0030] The first sensing wiring is electrically connected to an external sensing circuit, and a DC auxiliary power is applied to the auxiliary voltage wiring.

[0031] The display device also includes a light emitting element arranged on the first conductive layer, wherein the driving circuit layer includes a driving transistor configured to provide a driving current to the light emitting element and a sensing transistor including a first electrode connected to the first electrode of the driving transistor and a second electrode connected to a first sensing wiring, and each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap with the second electrode of the sensing transistor, and the protrusion is electrically connected to the second electrode of the sensing transistor through a contact hole.

[0032] The display device also includes a conductive pattern and a second conductive layer, the conductive pattern having the same shape as the protrusion of each of the first sensing wirings and arranged on the driving circuit layer, and the second conductive layer is located between the first conductive layer and the light emitting element, wherein the conductive pattern overlaps with the second electrode of the sensing transistor and one of the auxiliary voltage wirings, is electrically connected to the second electrode of the sensing transistor, and is electrically separated from the auxiliary voltage wiring.

[0033] A body connected to the protrusion of the sensing unit has a width greater than an average width of the first sensing wiring, and each of the auxiliary voltage wirings has the same shape as the body.

[0034] According to another aspect of the present disclosure, a display device is provided, the display device including a substrate, a driving circuit layer, a first insulating layer, a first conductive layer, and a second conductive layer, the substrate being defined by a display area and a non-display area positioned outside the display area, the driving circuit layer including a transistor arranged on the display area of ​​the substrate, the first insulating layer being arranged on the driving circuit layer, the first conductive layer including a first sensing wiring, the first sensing wiring being arranged on the first insulating layer, the first sensing wiring extending in a first direction and being spaced apart from each other at a first interval along a second direction perpendicular to the first direction, and the second conductive layer including an auxiliary voltage wiring, the auxiliary voltage wiring being arranged on the first conductive layer, the auxiliary voltage wiring extending in the first direction, the auxiliary voltage wiring being spaced apart from the first sensing wiring at a second interval smaller than the first interval along the second direction, and the auxiliary voltage wirings being spaced apart from each other at a second interval, wherein the first sensing wiring is electrically connected to the transistor through a contact hole and is electrically separated from each other, and the auxiliary voltage wirings are electrically connected to each other in the non-display area.

[0035] The display device also includes a light emitting element arranged on the second conductive layer, wherein the driving circuit layer includes a driving transistor configured to provide a driving current to the light emitting element and a sensing transistor including a first electrode connected to the first electrode of the driving transistor and a second electrode connected to a first sensing wiring, and each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap with the second electrode of the sensing transistor, and the protrusion is electrically connected to the second electrode of the sensing transistor through a contact hole.

[0036] Each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap the second electrode of the sensing transistor, and each of the auxiliary voltage wirings has the same shape as the body.

[0037] Each of the first sensing wirings includes a body extending in a first direction and a protrusion protruding from the body in a second direction to partially overlap with the second electrode of the sensing transistor, and each of the auxiliary voltage wirings has the same shape as the body, the first conductive layer is provided with a conductive pattern overlapping with the second electrode of the sensing transistor and the auxiliary voltage wiring, and the conductive pattern is electrically connected to the second electrode of the sensing transistor and electrically separated from the auxiliary voltage wiring.

[0038] The display device also includes a fourth conductive layer arranged between the driving circuit layer and the first conductive layer, wherein the fourth conductive layer includes second sensing wirings extending in the second direction and arranged to be spaced apart from each other in the second direction, the second sensing wirings are electrically connected to the first sensing wirings, and the second sensing wirings are arranged in directions different from each other relative to the first auxiliary voltage wirings of the auxiliary voltage wirings, and each of the first auxiliary voltage wirings also includes a protrusion extending in the second direction to overlap with one of the second sensing wirings.

[0039] The display device also includes a second auxiliary voltage wiring, which is arranged on the first conductive layer, extends in the first direction, and is spaced apart from the first sensing wiring and the auxiliary voltage wiring by a third interval smaller than the first interval and the second interval, wherein the second auxiliary voltage wiring is electrically connected to the first auxiliary voltage wiring on the non-display area.

[0040] However, aspects of the inventive concept are not limited to the aspects set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept belongs by referring to the detailed description of the inventive concept given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects and features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0042] Figure 1 is a block diagram of a display device according to an embodiment;

[0043] Figure 2A , Figure 2B and Figure 2C It is shown that the Figure 1 A circuit diagram of an example of a display unit in a display device;

[0044] Figure 3 It is shown that the Figure 2A A circuit diagram of an example of a pixel in a display unit;

[0045] Figure 4 yes Figure 3 A layout diagram of pixels;

[0046] Figure 5 is along Figure 4 A cross-sectional view taken along line AA' and line BB';

[0047] Figure 6 It is shown that the Figure 4 A view of a lower semiconductor layer in a pixel of FIG.

[0048] Figure 7 It is shown that the Figure 4 a view of a fourth conductive layer and a fifth conductive layer in a pixel of FIG.

[0049] Figure 8 It is shown that the Figure 4 a view of a light emitting element in a pixel;

[0050] Fig. 9 It is shown that the Figure 4 A view of another example of a fifth conductive layer in a pixel of FIG. 1 ;

[0051] Fig.10 It is shown that the Figure 4 A layout diagram of another example of auxiliary voltage wiring in a pixel of FIG.

[0052] Fig.11 It is shown that the Figure 4 A layout diagram of another example of auxiliary voltage wiring in a pixel of FIG.

[0053] Fig.12 is along Fig.11 A cross-sectional view taken along line C-C' and line D-D';

[0054] Fig.13 , Fig.14 and Fig.15 It is shown that the Figure 4 Layout diagrams of various embodiments of auxiliary voltage wiring in pixels of FIG. 1 ;

[0055] Fig.16 It is shown that the Figure 1 A cross-sectional view of another example of a display unit in a display device;

[0056] Fig.17 It is shown that the Figure 1 A circuit diagram of yet another example of a display unit in a display device of ; and

[0057] Fig.18 and Fig.19 It is shown Figure 1 Circuit diagrams of various embodiments of a display unit in a display device. DETAILED DESCRIPTION

[0058] The inventive concept will now be described more fully below with reference to the accompanying drawings showing preferred embodiments of the inventive concept. However, the inventive concept can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Throughout the specification, the same reference numerals indicate the same components. In the accompanying drawings, for clarity, the thickness of the layers and zones is exaggerated.

[0059] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0060] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0061] Figure 1 is a block diagram of a display device according to an embodiment.

[0062] Reference Figure 1 The display device 1 may include a display unit 10 (or a display panel), a data driver 20, a scan driver 30, a light emission control driver 40, a sensing unit 50 (or a sensing driver), and a controller 60 (or a T-con).

[0063] The display device 1 (and the display unit 10) may include scan lines SL11 to SL1n and SL21 to SL2n (n is an integer of 2 or more), data lines DL1 to DLm (m is an integer of 2 or more), emission control lines EML1 to EMLn, and pixels PX1, PX2, PX3, and PX4.

[0064] Each of the scan lines SL11 to SL1n and SL21 to SL2n may extend in a row direction. Each of the light emission control lines EML1 to EMLn may extend in a row direction (a first direction or a horizontal direction). Each of the data lines DL1 to DLm may extend in a column direction (a second direction or a vertical direction). Here, the column direction is perpendicular to the row direction, and the row direction and the column direction may be reversed to each other.

[0065] Pixels PX1, PX2, PX3, and PX4 may be arranged in the cross regions of scan lines SL11 to SL1n and SL21 to SL2n (n is an integer of 2 or more), data lines DL1 to DLm (m is an integer of 2 or more), and light emission control lines EML1 to EMLn. Pixels PX1, PX2, PX3, and PX4 may be arranged in a matrix form. Hereinafter, in the description of common characteristics of pixels PX1, PX2, PX3, and PX4, pixels PX1, PX2, PX3, and PX4 will be referred to as pixels PX and / or a plurality of pixels PX.

[0066] The pixel PX may be connected to two scan lines, one data line, and one light emission control line. In addition, the pixel PX may be connected to horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk, which will be described later. For example, the pixel PX positioned in the first row (or first pixel row) and the first column (or first pixel column) may be connected to the eleventh scan line SL11 and the twenty-first scan line SL21, the first data line DL1, the first light emission control line EML1, and the eleventh horizontal sensing wiring SH11.

[0067] The pixels PX1, PX2, PX3, and PX4 may emit light in mutually different monochromatic colors and / or mutually identical colors. The first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may be included in one unit pixel group (e.g., the first pixel group PXG1 to the third pixel group PXG3). That is, according to the arrangement pattern of the pixels PX1, PX2, PX3, and PX4, all the pixels PX in the display unit 10 may be grouped into pixel groups PXG1, PXG2, and PXG3. This will be referred to later. FIG. 2A to FIG. 2C The arrangement of the pixels PX1 , PX2 , PX3 , and PX4 is described.

[0068] The display device 1 (and the display unit 10) may further include horizontal sensing wirings (or second sensing wirings) SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk (k is an integer of 2 or more), vertical sensing wirings SV1 to SVk (or first sensing wirings), and auxiliary voltage wirings DML1 to DMLj (j is an integer of 2 or more). Here, the vertical sensing wirings SV1 to SVk (or first sensing wirings) and the auxiliary voltage wirings DML1 to DMLj may be collectively referred to as vertical wirings, and the vertical wirings may be spaced apart from each other at regular intervals.

[0069] The horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk may extend in the row direction and may be arranged in the column direction. For example, the 11th horizontal sensing wiring SH11 to the 1kth horizontal sensing wiring SH1k may be sequentially arranged along the first row and may be separated or spaced apart from each other. Similarly, the 21st horizontal sensing wiring SH21 to the 2kth horizontal sensing wiring SH2k may be sequentially arranged along the second row, and the n1th horizontal sensing wiring SHn1 to the nkth horizontal sensing wiring SHnk may be sequentially arranged along the nth row.

[0070] The horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk may be connected to the pixels PX. For example, the 11th horizontal sensing wiring SH11 may be connected to the pixels PX included in (or positioned in) the first column to the eighth column in the first row, and the 1kth horizontal sensing wiring SH1k may be connected to the pixels PX included in the m-7th column to the mth column. That is, each of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk may be connected to eight pixels PX or two pixel groups, and two pixel groups may share one horizontal sensing wiring (i.e., one of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk). However, this is exemplary, and the inventive concept is not limited thereto. For example, each of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, . . . , SHn1 to SHnk may be connected to two pixels PX, four pixels PX, six pixels PX, eight pixels PX or more pixels PX, or to three or more pixel groups.

[0071] The vertical sensing wirings SV1 to SVk may each extend in the column direction and may be arranged to be spaced apart from each other at a first interval in the row direction. The vertical sensing wirings SV1 to SVk correspond one-to-one to the horizontal sensing wirings (e.g., the 11th to 1kth horizontal sensing wirings SH11 to 1kth horizontal sensing wirings SH1k) included in one row, and thus similarly to the 11th to 1kth horizontal sensing wirings SH11 to 1kth horizontal sensing wirings SH1k, the vertical sensing wirings SV1 to SVk may be arranged to be spaced apart from each other at intervals corresponding to eight pixels PX.

[0072] The vertical sensing wirings SV1 to SVk may be connected to the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk. For example, the first vertical sensing wiring SV1 may be connected to the 11th horizontal sensing wiring SH11, the 21st horizontal sensing wiring SH21, and the n1th horizontal sensing wiring SHn1.

[0073] Will refer to later FIG. 2A to FIG. 2CDescription is given of the arrangement of the vertical sensing wires SV1 to SVk and the horizontal sensing wires SH11 to SH1k, SH21 to SH2k, . . . , SHn1 to SHnk in the display unit 10 and the connection relationship therebetween.

[0074] The auxiliary voltage wirings DML1, DML2 to DMLj may extend in the column direction and may be arranged to be spaced apart from each other at a second interval along the row direction between the vertical sensing wirings SV1 to SVk. The arrangement interval of the auxiliary voltage wirings DML1, DML2 to DMLj may be equal to or smaller than the arrangement interval of the vertical sensing wirings SV1 to SVk. For example, the auxiliary voltage wirings DML1, DML2 to DMLj may be arranged to be spaced apart from each other at an interval corresponding to two pixels PX between the vertical sensing wirings SV1 to SVk (i.e., adjacent to and not overlapping the vertical sensing wirings SV1 to SVk).

[0075] The auxiliary voltage VAUX may be applied to the auxiliary voltage wirings DML1, DML2 to DMLj. Here, the auxiliary voltage VAUX may be a DC voltage. For example, the auxiliary voltage wirings DML1, DML2 to DMLj may be connected to an external power supply unit (or power supply unit) to receive the auxiliary voltage VAUX. As another example, the auxiliary voltage wirings DML1, DML2 to DMLj may be connected to a first power supply voltage wiring to be described later at the periphery of the display unit 10 (or a non-display area of ​​the display unit 10 where the pixels PX are not arranged) to receive the first power supply voltage ELVDD.

[0076] As the vertical sensing wirings SV1 to SVk are arranged to be spaced apart at certain intervals (e.g., intervals corresponding to eight pixels PX), some pixels PX (e.g., pixels PX included in the fourth pixel column) arranged adjacent to the vertical sensing wirings SV1 to SVk may have characteristics (e.g., light emitting characteristics) different from characteristics of other pixels PX (e.g., pixels PX included in the second pixel column and pixels PX included in the sixth pixel column) spaced apart from the vertical sensing wirings SV1 to SVk, and may cause a vertical line of a specific color to appear on an image displayed by the display unit 10 due to such a characteristic difference. Therefore, as the auxiliary voltage wirings DML1, DML2 to DMLj are arranged between the vertical sensing wirings SV1 to SVk in a manner similar to the arrangement of the vertical sensing wirings SV1 to SVk, the corresponding pixels PX (e.g., pixels PX included in the second pixel column, the fourth pixel column, and the sixth pixel column) may have the same characteristics, and thus degradation of image quality (e.g., the appearance of a vertical line of a specific color) may be prevented.

[0077] Although not in Figure 1, but the display unit 10 may include a first power supply voltage wiring (or a first power supply voltage supply line) and a second power supply voltage wiring (or a second power supply voltage supply line). Figure 4 As described, the first power supply voltage wiring may supply the first power supply voltage ELVDD to the pixel PX, and the first power supply voltage wiring may be arranged in a grid form. The second power supply voltage wiring may supply the second power supply voltage ELVSS to the pixel PX, and the second power supply voltage wiring may also be arranged in a grid form. However, the inventive concept is not limited thereto, and the extension direction of the first power supply voltage wiring and the extension direction of the second power supply voltage wiring may be changed differently.

[0078] The data driver 20 may provide data signals to the pixels PX through the data lines DL1 to DLm.

[0079] The scan driver 30 may generate a first scan signal and a second scan signal, and may provide the first scan signal and the second scan signal to the pixel PX through the scan lines SL11 to SL1n and SL21 to SL2n. For example, when the first scan signal is supplied to the first pixel PX1 through the first scan line SL11, the data signal may be provided to the first pixel PX1 through the first data line DL1. Figure 3 A first scanning signal and a second scanning signal are described.

[0080] The light emission control driver 40 may generate a light emission control signal and may provide the light emission control signal to the pixel PX through the light emission control lines EML1 to EMLn. The light emission control driver 40 (or the display device 1) may adjust the light emission time of the pixel PX based on the light emission control signal. Meanwhile, although the light emission control driver 40 is shown in the figure as being implemented separately from the scan driver 30, the inventive concept is not limited thereto. For example, the light emission control driver 40 may be included in the scan driver 30 and integrated with the scan driver 30. As another example, the light emission control driver 40 may be omitted depending on the circuit configuration of the pixel PX.

[0081] The sensing unit 50 may apply a sensing voltage to the pixel PX through the vertical sensing wiring SV1 to SVk (and the horizontal sensing wiring SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk), and may measure the sensing current. The characteristics of the transistor in the pixel PX (e.g., threshold voltage and mobility) may be measured based on the sensing current. Meanwhile, although the sensing unit 50 is shown in the figure to be implemented separately from the data driver 20, the inventive concept is not limited thereto. For example, the sensing unit 50 may be included in the data driver 20 and integrated with the data driver 20, or may be arranged adjacent to the data driver 20, thereby being located on the same side of the display unit 10 as the data driver 20.

[0082] The sensing unit 50 may measure the characteristics (or average characteristics) of the pixels PX included in a specific area (e.g., eight pixels PX included in two pixel groups) according to the connection configuration of the vertical sensing wirings SV1 to SVk and the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk. Since the pixels PX located adjacent to each other display similar images or receive similar voltages (e.g., power supply voltages or signals with similar voltage drops), the pixels PX adjacent to each other may have similar characteristics. Accordingly, compared with the technology of sensing each of the pixels PX and compensating for the variation in the characteristics of each of the pixels PX, the sensing efficiency (i.e., the capacitance of the sensing unit 50) may be greatly reduced while the compensation efficiency is not reduced too much.

[0083] The controller 60 may convert a video signal DATA1 transmitted from an external device (e.g., an application processor) into a video data signal DATA2, and transmit the video data signal DATA2 to the data driver 20. The controller 60 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, generate a control signal for controlling the operation (or driving) of the scan driver 30, the data driver 20, and the light emission control driver 40, and provide the control signal to the scan driver 30, the data driver 20, and the light emission control driver 40, respectively. Here, the control signal may include a scan drive control signal SCS for controlling the scan driver 30, a data drive control signal DCS for controlling the data driver 20, and a light emission drive control signal LCS for controlling the light emission control driver 40.

[0084] Meanwhile, the display device 1 may further include a power supply unit (not shown). The power supply unit may generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and provide the first power supply voltage ELVDD and the second power supply voltage ELVSS to the pixel PX through a first power supply voltage wiring and a second power supply voltage wiring, respectively. Here, the first power supply voltage ELVDD may be a predetermined high level voltage, the second power supply voltage ELVSS may be a predetermined low level voltage, and the voltage level of the second power supply voltage ELVSS may be lower than the voltage level of the first power supply voltage ELVDD. Meanwhile, the power supply unit may be implemented as an external voltage source.

[0085] In addition, the power supply unit may generate an auxiliary voltage VAUX and apply the auxiliary voltage VAUX to the auxiliary voltage wirings DML1 to DMLj.

[0086] As above Figure 1As described above, the display device 1 can sense the characteristics of the pixel PX through the sensing unit 50 positioned outside the display unit 10, and can group a plurality of pixels PX (for example, eight pixels PX included in two pixel groups) and sense the characteristics (or average characteristics) of these pixels PX. Therefore, the vertical sensing wirings SV1 to SVk can be arranged to be spaced apart from each other at specific intervals (for example, intervals corresponding to eight pixels PX). Since the auxiliary voltage wirings DML1 to DMLj are arranged between the vertical sensing wirings SV1 to SVk in a manner similar to the arrangement of the vertical sensing wirings SV1 to SVk, the spatial frequency of the display unit 10 can be improved, and the pixels PX can have the same or similar characteristics regardless of whether they are adjacent to the vertical sensing wirings SV1 to SVk, thereby preventing the degradation of display quality (for example, the appearance of vertical lines of a specific color).

[0087] FIG. 2A to FIG. 2C It is shown that the Figure 1 A circuit diagram of an example of a display unit in a display device.

[0088] Reference FIG. 2A to FIG. 2C , the first pixel PX1 (or the first sub-pixel, the first type pixel or the first color pixel) may be a red pixel emitting light of the first color R (e.g., red), the second pixel PX2 (or the second sub-pixel, the second type pixel or the second color pixel) may be a green pixel emitting light of the second color G (e.g., green), the third pixel PX3 (or the third sub-pixel, the third type pixel or the third color pixel) may be a blue pixel emitting light of the third color B (e.g., blue), and the fourth pixel PX4 (or the fourth sub-pixel, the fourth type pixel or the fourth color pixel) may be a green pixel emitting light of the second color G (e.g., green). The fourth pixel PX4 may be substantially the same as the second pixel PX2. The first pixel groups PXG1_1 each including the first pixel PX1 to the fourth pixel PX4 may be repeatedly arranged in the row direction. That is, the display unit 10 may have an RGBG pentile pixel arrangement.

[0089] The vertical sensing wirings SV1 to SVk and the auxiliary voltage wirings DML1 to DMLj may be arranged adjacent to green pixels or pixel columns including only green pixels.

[0090] like Figure 2A As shown in , the first vertical sensing wiring SV1 may be arranged between the fourth pixel column and the fifth pixel column, the second vertical sensing wiring SV2 may be arranged between the twelfth pixel column and the thirteenth pixel column, and the third vertical sensing wiring SV3 may be arranged between the twentieth pixel column and the twenty-first pixel column. That is, the kth vertical sensing wiring SVk may be arranged between the (8*k-4)th pixel column and the (8*k-3)th pixel column.

[0091] Similarly, the first auxiliary voltage wiring DML1 may be arranged between the second pixel column and the third pixel column, the second auxiliary voltage wiring DML2 may be arranged between the sixth pixel column and the seventh pixel column, and the third auxiliary voltage wiring DML3 may be arranged between the eighth pixel column and the ninth pixel column. That is, the auxiliary voltage wirings DML1 to DML9 may be respectively arranged adjacent to the remaining green pixels (or pixel columns including only the remaining green pixels) that are not directly adjacent to (i.e., neighboring) the first vertical sensing wiring SV1.

[0092] The vertical sensing wirings SV1 to SVk may be connected to the center of each of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk. That is, the corresponding horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk may be symmetrical with respect to the corresponding (i.e., connected and / or intersecting) vertical sensing wirings. However, the inventive concept is not limited thereto. For example, the vertical sensing wirings SV1 to SVk may be connected to one end of each of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk.

[0093] Reference Figure 1 , Figure 2A and Figure 2B , in addition to the arrangement of pixels PX1 to PX4 and the arrangement of vertical sensing wirings SV1_1 to SV3_1, Figure 2B The display unit 10_1 can be connected with the reference Figure 2A The display unit 10 described is substantially the same. Therefore, a redundant description will not be repeated.

[0094] The first pixel PX1 may be a red pixel, the second pixel PX2 may be a blue pixel, the third pixel PX3 may be a green pixel, and the fourth pixel PX4 may be a blue pixel. The second pixel PX2 and the fourth pixel PX4 may be substantially identical to each other. The first pixel group PXG1_2 includes RBGB pixels, and the first pixel group PXG1_2 may be repeatedly arranged in a row direction. That is, the display unit 10_1 may have a RBGB pentile pixel arrangement.

[0095] The vertical sensing wirings SV1_1 to SV3_1 and the auxiliary voltage wirings DML1_1 to DML9_1 may be arranged adjacent to blue pixels or pixel columns including only blue pixels.

[0096] like Figure 2BAs shown in , the first vertical sensing wiring SV1_1 may be arranged between the eighth pixel column and the ninth pixel column, the second vertical sensing wiring SV2_1 may be arranged between the sixteenth pixel column and the seventeenth pixel column, and the third vertical sensing wiring SV3_1 may be arranged between the twenty-fourth pixel column and the twenty-fifth pixel column. That is, the kth vertical sensing wiring SVk_1 may be arranged between the (8*k)th pixel column and the (8*k+1)th pixel column.

[0097] Similarly, the first auxiliary voltage wiring DML1_1 may be arranged between the second pixel column and the third pixel column, the second auxiliary voltage wiring DML2_1 may be arranged between the fourth pixel column and the fifth pixel column, and the third auxiliary voltage wiring DML3_1 may be arranged between the sixth pixel column and the seventh pixel column. That is, the auxiliary voltage wirings DML1_1 to DML9_1 may be respectively arranged to be adjacent to the remaining blue pixels (or pixel columns including only the remaining blue pixels) that are not directly adjacent to (i.e., neighboring) the first vertical sensing wiring SV1_1.

[0098] The vertical sensing wires SV1_1 to SV3_1 may be connected to one end of each of the horizontal sensing wires SH11 to SH1k, SH21 to SH2k, . . . , SHn1 to SHnk. However, the inventive concept is not limited thereto.

[0099] Reference Figure 1 , Figure 2A and Figure 2C , in addition to the arrangement of pixels PX1 to PX4 and the arrangement of vertical sensing wires SV1_2 to SV3_2, Figure 2C The display unit 10_2 can be compared with the reference Figure 2A The display unit 10 described is substantially the same. Therefore, a redundant description will not be repeated.

[0100] The first pixel PX1 may be a red pixel, the second pixel PX2 may be a blue pixel, the third pixel PX3 may be a red pixel, and the fourth pixel PX4 may be a green pixel. The first pixel PX1 and the third pixel PX3 may be substantially identical to each other. The first pixel group PXG1_3 includes RBRG pixels, and the first pixel group PXG1_3 may be repeatedly arranged in a row direction. That is, the display unit 10_2 may have a RBRG pentile pixel arrangement.

[0101] The vertical sensing wirings SV1_2 to SV3_2 and the auxiliary voltage wirings DML1_1 to DML9_2 may be arranged adjacent to blue pixels or pixel columns including only blue pixels.

[0102] like Figure 2CAs shown in , the first vertical sensing wiring SV1_2 may be arranged between the third pixel column and the fourth pixel column, the second vertical sensing wiring SV2_2 may be arranged between the eleventh pixel column and the twelfth pixel column, and the third vertical sensing wiring SV3_2 may be arranged between the nineteenth pixel column and the twentieth pixel column. That is, the kth vertical sensing wiring SVk_1 may be arranged between the (8*k-5)th pixel column and the (8*k-4)th pixel column.

[0103] Similarly, the first auxiliary voltage wiring DML1_2 may be arranged between the first pixel column and the second pixel column, the second auxiliary voltage wiring DML2_2 may be arranged between the fifth pixel column and the sixth pixel column, and the third auxiliary voltage wiring DML3_2 may be arranged between the seventh pixel column and the eighth pixel column. That is, the auxiliary voltage wirings DML1_2 to DML9_2 may be arranged adjacent to the remaining blue pixels (or pixel columns including only the remaining blue pixels) that are not adjacent to the first vertical sensing wiring SV1_1, respectively.

[0104] The vertical sensing wirings SV1_2 to SV3_2 may be connected to the center of each of the horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk. The horizontal sensing wirings SH11 to SH1k, SH21 to SH2k, ..., SHn1 to SHnk may be symmetrical with respect to the corresponding vertical sensing wirings. However, the inventive concept is not limited thereto.

[0105] As mentioned above FIG. 2A to FIG. 2C As described above, the display units 10, 10_1, and 10_2 may have RGBG, RBGB, and RBRG pentile pixel arrangements, respectively. The vertical sensing wiring and the auxiliary voltage wiring may be arranged adjacent to any pixel (e.g., a green pixel, a blue pixel, or a red pixel), and may also be connected to any portion (e.g., the center or an end) of each of the horizontal sensing wirings.

[0106] Figure 3 It is shown that the Figure 2A A circuit diagram of an example of a pixel in a display unit.

[0107] Reference Figure 3, the pixel PX (or each of the second pixel PX2, the third pixel PX3, and the fourth pixel PX4) may include a light emitting element EL (or an organic light emitting diode), a first transistor T1 to a fourth transistor T4, and a storage capacitor CST. The data signal DATA, the first scan signal SCAN1, the second scan signal SCAN2, and the light emitting control signal EM may be provided to the pixel PX. Here, each of the first scan signal SCAN1 and the second scan signal SCAN2 may have a pulse waveform. For example, each of the first scan signal SCAN1 and the second scan signal SCAN2 may have a logic high level (a high voltage level or a potential of a turn-on voltage) in a pulse portion, and may have a logic low level (i.e., a voltage level lower than a logic high level, or a low voltage level or a potential of a turn-off voltage) in the remaining portion. The second scan signal SCAN2 may be substantially the same as the first scan signal SCAN1. The light emitting control signal EM may have a pulse waveform, and may have a logic low level in a pulse portion and a logic high level in the remaining portion. That is, the waveform of the light emitting control signal EM may be similar to a signal in which the first scan signal SCAN1 and the second scan signal SCAN2 are inverted.

[0108] Each of the first to fourth transistors T1 to T4 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0109] Each of the first to fourth transistors T1 to T4 may be a thin film transistor. Each of the first to fourth transistors T1 to T4 may include an oxide semiconductor or a polysilicon semiconductor.

[0110] In an embodiment, each of the first transistor T1 and the fourth transistor T4 may include a polysilicon semiconductor, and each of the second transistor T2 and the third transistor T3 may include an oxide semiconductor. Compared with a transistor including a polysilicon semiconductor, a transistor including an oxide semiconductor has a relatively excellent turn-off characteristic. When each of the third transistor T3 and the fourth transistor T4 includes an oxide semiconductor, leakage of a driving current in a light emission period of the light emitting element EL may be reduced.

[0111] Hereinafter, each of the configurations of the pixel PX will be described in detail.

[0112] First, the light emitting element EL may include an anode electrode and a cathode electrode. The cathode electrode of the light emitting element EL may be connected to a second power supply voltage wiring (i.e., a power supply voltage wiring supplying a second power supply voltage ELVSS). Here, the light emitting element EL is collectively referred to as a first light emitting element (not shown), a second light emitting element EL2, and a third light emitting element EL3, and the first light emitting element, the second light emitting element EL2, and the third light emitting element EL3 may emit light of different colors.

[0113] The first transistor T1 (or driving transistor) may include a first electrode indirectly connected to a first power supply voltage wiring (i.e., a power supply voltage wiring supplying a first power supply voltage ELVDD), a second electrode connected to an anode electrode of the light emitting element EL (e.g., an anode electrode of the second light emitting element EL2), and a gate electrode connected to a second electrode of the second transistor T2. The first transistor T1 may provide a driving current to the light emitting element EL based on a gate voltage (or a data voltage stored in a storage capacitor CST to be described later).

[0114] The second transistor T2 (or the switching transistor) may include a first electrode connected to the data line (or receiving data DATA), a second electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first scan line (eg, Figure 1 The second transistor T2 may be turned on in response to the first scan signal SCAN1 and may transmit the data signal DATA to the gate electrode of the first transistor T1.

[0115] The fourth transistor T4 (or light emission control transistor) may include a first electrode connected to the first power voltage wiring to receive the first power voltage ELVDD, a second electrode connected to the first electrode of the first transistor T1, and a second electrode connected to the light emission control line (eg, Figure 1 The first light emitting control line EML1 shown in FIG. 8 or the gate electrode receiving the light emitting control signal EM.

[0116] The fourth transistor T4 is turned on in response to the light emitting control signal EM. In this case, the driving current is supplied to the light emitting element EL, and the light emitting element EL may emit light having a brightness corresponding to the driving current.

[0117] The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a first electrode connected to the horizontal sensing wiring LSEN1 (eg, Figure 1 The second electrode of the eleventh horizontal sensing wiring SH11 shown in FIG. 1 and the second electrode of the eleventh horizontal sensing wiring SH11 connected to the second scan line (eg, Figure 1 The twenty-first scan line SL21 shown in FIG. 8 is provided to receive a gate electrode of the second scan signal SCAN2.

[0118] The third transistor T3 is turned on in response to the second scan signal SCAN2. In this case, a sensing voltage is applied from the sensing unit 50 to the first transistor T1, a sensing current flows from the sensing unit 50 to the first transistor T1, and the sensing unit 50 can measure the sensing current.

[0119] At the same time, the vertical sensing wiring LSEN2 can be connected to Figure 1 . The vertical sensing wiring LSEN2 may be arranged adjacent to one side of the fourth pixel PX4 (e.g., the right side spaced apart from the third pixel PX3), and may be connected to the second electrode of the third transistor T3 of the fourth pixel PX4. That is, the vertical sensing wiring LSEN2 is not directly connected to the horizontal sensing wiring LSEN1, and may be connected to the horizontal sensing wiring LSEN1 through the second electrode of the third transistor T3 (or a pattern or line connected between the third transistor T3 and the horizontal sensing wiring LSEN1). However, the inventive concept is not limited thereto, and the vertical sensing wiring LSEN2 may be directly connected to the horizontal sensing wiring LSEN1 at the intersection with the horizontal sensing wiring LSEN1.

[0120] Similar to the vertical sensing wiring LSEN2 , the auxiliary voltage wiring DML1 may be arranged adjacent to one side of the second pixel PX2 , which is substantially identical to the fourth pixel PX4 .

[0121] At the same time, despite Figure 3 4 shows that the pixel PX includes 4T1C (ie, four transistors T1 to T4 and one capacitor CST), but this is exemplary and the pixel PX is not limited thereto. For example, the pixel PX may have a 5T1C, 6T1C or similar structure, and will be referred to later. Fig.17 Describe its details.

[0122] As above Figure 3 As described above, the pixel PX includes the second transistor T2 and the third transistor T3 including an oxide semiconductor, thereby reducing leakage of a driving current.

[0123] Figure 4 yes Figure 3 Layout diagram of pixels. Figure 5 is along Figure 4 A cross-sectional view taken along line AA' and line BB'. Figure 6 It is shown that the Figure 4 View of the lower semiconductor layer in a pixel. Figure 7 It is shown that the Figure 4 View of the fourth conductive layer and the fifth conductive layer in a pixel of FIG. Figure 8 It is shown that the Figure 4 View of the light-emitting elements in a pixel.

[0124] In the following embodiments, although some components are Figure 1 and FIG. 2A to FIG. 2C The components mentioned in are substantially the same, but new reference numerals have been given to facilitate description of the arrangement and coupling relationship between the components.

[0125] Reference Figures 3 to 8 , the pixel PX may include first to fourth transistors T1 to T4 , a storage capacitor CST, and a light emitting element EL.

[0126] The first to fourth transistors T1 to T4 may include a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. The first to fourth transistors T1 to T4 may be top-gate transistors in which a gate electrode is disposed above the semiconductor layer.

[0127] The storage capacitor CST may include a conductive layer constituting an electrode and an insulating layer arranged between the conductive layers. The light emitting element EL may include a conductive layer constituting an anode electrode and a cathode electrode and an organic light emitting layer arranged between the conductive layers. The electrical connection between the components may be achieved by wiring formed by the conductive layer and / or a through hole formed by a conductive material. The above-mentioned conductive layer, semiconductor layer, insulating layer, organic light emitting layer, etc. are arranged on the substrate 910.

[0128] The pixel PX may include a substrate 910, a buffer layer 920, a lower semiconductor layer 100, a first insulating layer 810, a first conductive layer 200, a second insulating layer 820, a second conductive layer 300, a third insulating layer 830, an upper semiconductor layer 400, a third conductive layer 500, a fourth insulating layer 840, a fourth conductive layer 600, a fifth insulating layer 850, and a fifth conductive layer 700. The substrate 910, the buffer layer 920, the lower semiconductor layer 100, the first insulating layer 810, the first conductive layer 200, the second insulating layer 820, the second conductive layer 300, the third insulating layer 830, the upper semiconductor layer 400, the third conductive layer 500, the fourth insulating layer 840, the fourth conductive layer 600, the fifth insulating layer 850, and the fifth conductive layer 700 may be sequentially arranged or stacked. Meanwhile, the lower semiconductor layer 100, the first insulating layer 810, the first conductive layer 200, the second insulating layer 820, the second conductive layer 300, the third insulating layer 830, the upper semiconductor layer 400 and the third conductive layer 500 may be referred to as a driving circuit layer (i.e., a layer in which transistors are formed).

[0129] Each of the above-mentioned layers may be formed of a single film, but may also be formed of a laminated film including a plurality of films. Another layer may be further arranged between the respective layers.

[0130] The substrate 910 supports layers arranged thereon. When the display device 1 is a rear or dual-side emission type display device, a transparent substrate may be used. When the display device 1 is a front emission type display device, a semi-transparent or opaque substrate may be used as well as a transparent substrate.

[0131] The substrate 910 may be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The substrate 910 may include a metal material.

[0132] The substrate 910 may be a rigid substrate or a flexible substrate capable of being bent, folded, rolled, etc. An example of a material constituting the flexible substrate is polyimide (PI), but is not limited thereto.

[0133] The buffer layer 920 may be arranged on the entire surface of the substrate 910. The buffer layer 920 may prevent the diffusion of impurity ions, may prevent the penetration of moisture or external air, and may perform a surface planarization function. The buffer layer 920 may include silicon nitride, silicon oxide, and / or silicon oxynitride. Depending on the type of the substrate 910, process conditions, etc., the buffer layer 920 may be omitted.

[0134] The lower semiconductor layer 100 is an active layer constituting channels of the first transistor T1 and the fourth transistor T4. The lower semiconductor layers 100 may be separated from each other for each pixel, but are not limited thereto. For example, two adjacent pixels in a row direction may share one lower semiconductor layer 100.

[0135] The lower semiconductor layer 100 may include first and second longitudinal portions 110 and 120 extending substantially in a column direction, and may further include transverse portions 130 extending substantially in a row direction. The first and second longitudinal portions 110, 120, and 130 may be physically connected to form one lower semiconductor pattern.

[0136] The first longitudinal portion 110 may be disposed adjacent to the left side of the pixel PX, and the second longitudinal portion 120 may be disposed adjacent to the right side of the pixel PX. The length of the first longitudinal portion 110 in the column direction may be longer than the length of the second longitudinal portion 120 in the column direction.

[0137] The transverse portion 130 may connect one end (eg, an upper end) of the first longitudinal portion 110 and the other end (eg, a lower end) of the second longitudinal portion 120 .

[0138] The transverse portion 130 may connect the first longitudinal portion 110 and the second longitudinal portion 120 at the shortest distance, but may include curved portions at the left and right sides thereof, such as Figure 6 The total length of the transverse portion 130 can be increased by multiple bends.

[0139] A channel of the first transistor T1 may be disposed at the transverse portion 130 , and a channel of the fourth transistor T4 may be disposed at the first longitudinal portion 110 .

[0140] The lower semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization methods may include rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS), but are not limited thereto. As another example, the lower semiconductor layer 100 may include single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon.

[0141] In the lower semiconductor layer 100, the region (source region / drain region) connected to the source electrode / drain electrode of each of the first transistor T1 and the fourth transistor T4 may be doped with impurity ions (p-type impurity ions in the case of a PMOS transistor). As the p-type impurity ions, a trivalent dopant such as boron (B) may be used.

[0142] The first insulating layer 810 may be disposed on the lower semiconductor layer 100, and may generally be disposed over the entire surface of the substrate 910. The first insulating layer 810 may be a gate insulating film having a gate insulating function.

[0143] The first insulating layer 810 may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer 810 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These may be used alone or in combination with each other. The first insulating layer 810 may be a single film or a multilayer film composed of stacked films of different materials.

[0144] The first conductive layer 200 is disposed on the first insulating layer 810. The first conductive layer 200 may include a light emission control line 210 for transmitting a light emission control signal EM and a gate electrode 220 of the first transistor T1. Figure 1 The light emission control lines EML1 to EMLn shown in FIG. 1 are substantially the same.

[0145] In a plan view, the light emission control line 210 may be disposed below the pixel PX. The light emission control line 210 may overlap the first longitudinal portion 110 of the lower semiconductor layer 100.

[0146] The gate electrode of the fourth transistor T4 may be formed in an overlapping region where the light emission control line 210 overlaps the first longitudinal portion 110 of the lower semiconductor layer 100. The first longitudinal portion 110 of the lower semiconductor layer 100 positioned on the upper side of the overlapping region may become a first electrode region of the fourth transistor T4, and the first longitudinal portion 110 of the lower semiconductor layer 100 positioned on the lower side of the overlapping region may become a second electrode region of the fourth transistor T4.

[0147] The gate electrode 220 of the first transistor T1 may be positioned at the center of the pixel PX. The gate electrode 220 of the first transistor T1 may be positioned between the light emission control line 210 and a first scan line 510 to be described later. The gate electrode 220 of the first transistor T1 may be separated for each pixel and may be arranged in an island shape.

[0148] The gate electrode 220 of the first transistor T1 may overlap the second longitudinal portion 120 and the transverse portion 130 of the lower semiconductor layer 100. The second longitudinal portion 120 of the lower semiconductor layer 100 positioned on the upper side of the overlapped region where the gate electrode 220 of the first transistor T1 overlaps the transverse portion 130 of the lower semiconductor layer 100 may become the first electrode region of the first transistor T1, and the transverse portion 130 (or the first longitudinal portion 110) positioned on the left side of the overlapped region may become the second electrode region of the first transistor T1.

[0149] The first conductive layer 200 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 200 may be a single film or a multi-layer film.

[0150] The second insulating layer 820 may be disposed on the first conductive layer 200, and may be disposed over the entire surface of the substrate 910. The second insulating layer 820 serves to insulate the first conductive layer 200 from the second conductive layer 300, and may be an interlayer insulating film.

[0151] The second insulating layer 820 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, and / or may include an organic insulating layer such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The second insulating layer 820 may be a single film or a multilayer film made of stacked films of different materials.

[0152] The second conductive layer 300 is disposed on the second insulating layer 820. The second conductive layer 300 may include a horizontal sensing wiring 310 and an electrode line 320 of the storage capacitor CST. Figure 1 The horizontal sense wirings SH11 to SHnk shown in FIG. 5 are substantially the same.

[0153] Each of the horizontal sensing wiring 310 and the electrode line 320 of the storage capacitor CST may extend in a row direction. Each of the horizontal sensing wiring 310 and the electrode line 320 of the storage capacitor CST may extend in a row direction to an adjacent pixel outside a boundary of the pixel PX.

[0154] In a plan view, the horizontal sensing wiring 310 may be positioned at the uppermost side (or the lowermost side) of the pixel PX.

[0155] In a plan view across the center of the pixel PX, the electrode line 320 of the storage capacitor CST may be arranged between the first scan line 510 and the light emission control line 210. The electrode line 320 of the storage capacitor CST may be arranged to overlap with the gate electrode 220 of the first transistor T1, with the second insulating layer 820 interposed therebetween. The gate electrode 220 of the first transistor T1 may become a first electrode of the storage capacitor CST, an extension region of the electrode line 320 of the storage capacitor CST overlapping the first electrode of the storage capacitor CST may become a second electrode of the storage capacitor CST, and the second insulating layer 820 interposed therebetween may become a dielectric of the storage capacitor CST. The first power supply voltage ELVDD may be applied to the electrode line 320 of the storage capacitor CST.

[0156] The electrode line 320 of the storage capacitor CST may have an extended width in a region overlapping the gate electrode 220 of the first transistor T1. The electrode line 320 of the storage capacitor CST may include an opening overlapping the gate electrode 220 of the first transistor T1 in the extended region.

[0157] Similar to the first conductive layer 200, the second conductive layer 300 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu).

[0158] The third insulating layer 830 may be arranged on the second conductive layer 300 to cover the second conductive layer 300. The third insulating layer 830 may be generally arranged over the entire surface of the substrate 910. The third insulating layer 830 may be a gate insulating film having a gate insulating function. The third insulating layer 830 may include the same material as the first insulating layer 810, or may include at least one material selected from the exemplified constituent materials of the first insulating layer 810. The third insulating layer 830 may be a single film or a multilayer film consisting of stacked films of different materials.

[0159] The upper semiconductor layer 400 may be disposed on the third insulating layer 830. The upper semiconductor layer 400 may include a first upper semiconductor pattern 410 and a second upper semiconductor pattern 420 that are separated from each other in the pixel PX.

[0160] The first upper semiconductor pattern 410 may be arranged to overlap with the gate electrode of the second transistor T2 to form a channel of the second transistor T2. Similarly, the second upper semiconductor pattern 420 may be arranged to overlap with the gate electrode of the third transistor T3 to form a channel of the third transistor T3. The first upper semiconductor pattern 410 may have a rectangular shape, but its shape is not limited thereto.

[0161] The upper semiconductor layer 400 may include an oxide semiconductor. For example, the upper semiconductor layer 400 may include a two-component compound (AB) each selectively containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and magnesium (Mg). x ), three-component compound (AB x C y ) or four-component compound (AB x C y D z In an implementation, the upper semiconductor layer 400 may include ITZO (an oxide including indium, tin, and zinc) or IGZO (an oxide including indium, gallium, and zinc).

[0162] The gate insulating film GI3 may be disposed on the upper semiconductor layer 400. The gate insulating film GI3 may be disposed in a region where the upper semiconductor layer 400 overlaps with a first scan line 510 to be described later. The gate insulating film GI3 may include the same material as the first insulating layer 810, or may include at least one material selected from the exemplified constituent materials of the first insulating layer 810.

[0163] The third conductive layer 500 may include a first scan line 510 for transmitting a first scan signal SCAN1. In addition, the third conductive layer 500 may include gate wirings of the second transistor T2 and the third transistor T3. Here, the first scan line 510 may be connected to Figure 1 The scan lines SL11 to SL1n shown in FIG. 1 are substantially the same.

[0164] The first scan line 510 may extend in a row direction. The first scan line 510 may extend in a row direction to an adjacent pixel outside a boundary of the pixel PX.

[0165] In a plan view, the first scan line 510 may be positioned above the electrode line 320 of the storage capacitor CST, and in a plan view, may be positioned below the horizontal sensing wiring 310. The first scan line 510 may include a gate electrode of the second transistor T2 and a gate electrode of the third transistor T3. The gate electrode of the second transistor T2 and the gate electrode of the third transistor T3 may be wider than the peripheral line, but the inventive concept is not limited thereto.

[0166] At the same time, despite Figure 4 5 shows that the third conductive layer 500 includes a first scanning line 510, but this corresponds to the reference Figure 3 The case where the first scan signal SCAN1 and the second scan signal SCAN2 are identical to each other is described. When the first scan signal SCAN1 and the second scan signal SCAN2 are different from each other, the third conductive layer 500 may further include a second scan line in addition to the first scan line 510. The second scan line may be arranged between the horizontal sensing wiring 310 and the first scan line 510, or the second scan line may be arranged between the first scan line 510 and the electrode line 320 of the storage capacitor CST.

[0167] The third conductive layer 500 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 500 may be a single film or a multilayer film. For example, the third conductive layer 500 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0168] The fourth insulating layer 840 may be disposed on the third conductive layer 500, and may be disposed over the entire surface of the substrate 910. The fourth insulating layer 840 may be an interlayer insulating film for insulating the third conductive layer 500 from the fourth conductive layer 600. The fourth insulating layer 840 may include the same material as the second insulating layer 820, or may include at least one material selected from the constituent materials of the second insulating layer 820 listed above. The fourth insulating layer 840 may be a single film or a multilayer film made of stacked films of different materials.

[0169] The fourth conductive layer 600 is disposed on the fourth insulating layer 840. The fourth conductive layer 600 may include first, second and third data patterns 610, 620 and 630, a data wiring 640, a vertical sensing wiring 650 and an auxiliary voltage wiring 660. Here, the data wiring 640 may be connected to the first data pattern 610, the second data pattern 620 and the third data pattern 630. Figure 1 The data lines DL1 to DLm shown in FIG. 1 are substantially the same, and the vertical sensing wiring 650 may be Figure 1 The vertical sensing wirings SV1 to SVk shown in FIG. 1 are substantially the same, and the auxiliary voltage wiring 660 may be Figure 1 The auxiliary voltage wirings DML1 to DMLj shown in FIG. 1 are substantially the same.

[0170] The first data pattern 610, the second data pattern 620, and the third data pattern 630 may be physically spaced apart from each other. Each of the first data pattern 610, the second data pattern 620, and the third data pattern 630 may electrically connect portions that are distant from each other between the first transistor T1, the second transistor T2, and the third transistor T3, and may constitute a first electrode or a second electrode of a transistor (e.g., the third transistor T3) including an oxide semiconductor. When the fourth conductive layer 600 overlaps the upper semiconductor layer 400, the fourth conductive layer 600 may directly contact the upper surface of the upper semiconductor layer 400, or may contact the upper surface of the upper semiconductor layer 400 through an ohmic contact layer.

[0171] The first data pattern 610 may overlap the gate electrode 220 of the first transistor T1. A first contact hole CNT1 penetrating the fourth insulating layer 840, the third insulating layer 830, and the second insulating layer 820 to expose the gate electrode 220 of the first transistor T1 may be formed in the overlap region (i.e., a region where the first data pattern 610 overlaps the gate electrode 220 of the first transistor T1). The first data pattern 610 may be electrically connected to the gate electrode 220 of the first transistor T1 through the first contact hole CNT1.

[0172] The first contact hole CNT1 may be formed in the opening of the electrode line 320 of the storage capacitor CST. In the first contact hole CNT1, the first data pattern 610 and the electrode line 320 of the storage capacitor CST adjacent to the first data pattern 610 may be insulated from each other by the third insulating layer 830.

[0173] The first data pattern 610 may extend upward from an overlapping region with the gate electrode 220 of the first transistor T1 , and may overlap with the first upper semiconductor pattern 410 .

[0174] In the overlapping area where the first data pattern 610 overlaps with the first upper semiconductor pattern 410, an eleventh contact hole CNT11 penetrating the fourth insulating layer 840 to expose the first upper semiconductor pattern 410 may be formed, and the first data pattern 610 may be electrically connected to the first electrode region of the second transistor T2 through the eleventh contact hole CNT11, or a portion of the first data pattern 610 overlapping with the first upper semiconductor pattern 410 may constitute the first electrode region of the second transistor T2.

[0175] The second data pattern 620 may overlap the second longitudinal portion 120 of the lower semiconductor layer 100. In a region where the second data pattern 620 overlaps the second longitudinal portion 120 of the lower semiconductor layer 100, a second contact hole CNT2 may be formed that penetrates the first insulating layer 810, the second insulating layer 820, and the third insulating layer 830 to expose the second longitudinal portion 120 of the lower semiconductor layer 100. The second data pattern 620 may be electrically connected to the second electrode of the first transistor T1 through the second contact hole CNT2.

[0176] The second data pattern 620 may extend upward, and may overlap the second upper semiconductor pattern 420. In an overlapping region where the second data pattern 620 overlaps the second upper semiconductor pattern 420, a fourteenth contact hole CNT14 penetrating the fourth insulating layer 840 to expose the second upper semiconductor pattern 420 may be formed, and the second data pattern 620 may be electrically connected to the first electrode region of the third transistor T3 through the fourteenth contact hole CNT14, or a portion of the second data pattern 620 overlapping the second upper semiconductor pattern 420 may constitute the first electrode region of the third transistor T3.

[0177] The third data pattern 630 may overlap the second upper semiconductor pattern 420. In the overlapped region where the third data pattern 630 overlaps the second upper semiconductor pattern 420, a thirteenth contact hole CNT13 penetrating the fourth insulating layer 840 to expose the second upper semiconductor pattern 420 may be formed, and the third data pattern 630 may be electrically connected to the second electrode region of the third transistor T3 through the thirteenth contact hole CNT13, or a portion of the third data pattern 630 overlapping the second upper semiconductor pattern 420 may constitute the second electrode region of the third transistor T3.

[0178] The third data pattern 630 may extend upward and may overlap with the protrusion of the horizontal sensing wiring 310. In the overlapped region with the protrusion of the horizontal sensing wiring 310, a fifth contact hole CNT5 may be formed penetrating the third insulating layer 830 and the fourth insulating layer 840 to expose the protrusion of the horizontal sensing wiring 310. The third data pattern 630 may be electrically connected to the horizontal sensing wiring 310 through the fifth contact hole CNT5.

[0179] The data wiring 640 may include a protrusion overlapping the first upper semiconductor pattern 410. The width of the protrusion of the data wiring 640 may be greater than the average width of the data wiring 640. A twelfth contact hole CNT12 penetrating the fourth insulating layer 840 to expose the first upper semiconductor pattern 410 (or the second data pattern 620) may be formed in the protrusion of the data wiring 640 (or a region where the data wiring 640 overlaps the first upper semiconductor pattern 410). The data wiring 640 may be electrically connected to the first upper semiconductor pattern 410 through the twelfth contact hole CNT12.

[0180] The vertical sensing wiring 650 may include a body 651 and a protrusion 652 .

[0181] The body 651 of the vertical sensing wiring 650 may extend in the column direction between the pixel PX and another pixel adjacent to the pixel PX, and the protrusion 652 thereof may protrude from the body 651 in the row direction and overlap the third data pattern 630. The vertical sensing wiring 650 may be electrically connected to the third data pattern 630. In this case, the vertical sensing wiring 650 may be connected to the horizontal sensing wiring 310 through the third data pattern 630.

[0182] The auxiliary voltage wiring 660 may extend in a vertical direction, may be spaced apart from the vertical sensing wiring 650 at a certain interval (eg, an interval corresponding to two pixels) in a horizontal direction, and may be arranged between pixels.

[0183] The auxiliary voltage wiring 660 may not be connected to the third data pattern 630. Figure 4 , the auxiliary voltage wiring 660 may not include a configuration corresponding to the protrusion 652 of the vertical sensing wiring 650 .

[0184] The fourth conductive layer 600 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 600 may be a single film or a multilayer film. For example, the fourth conductive layer 600 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0185] The fifth insulating layer 850 may be disposed on the fourth conductive layer 600, and may be disposed over the entire surface of the substrate 910. The fifth insulating layer 850 may insulate the fourth conductive layer 600 from the fifth conductive layer 700. The fifth insulating layer 850 may include the same material as the second insulating layer 820, or may include at least one material selected from the exemplified constituent materials of the second insulating layer 820. The fifth insulating layer 850 may be a single film or a multi-layer film made of stacked films of different materials.

[0186] The fifth conductive layer 700 is disposed on the fifth insulating layer 850. The fifth conductive layer 700 may include a through-hole electrode 710 and a first vertical power supply voltage wiring 720 and a first horizontal power supply voltage wiring 730. Here, the first vertical power supply voltage wiring 720 and the first horizontal power supply voltage wiring 730 may be included in the first power supply voltage wiring described with reference to FIG. 2 .

[0187] The via electrode 710 may overlap the second data pattern 620. A 22nd contact hole CNT22 penetrating the fifth insulating layer 850 to expose the second data pattern 620 may be formed in a region where the via electrode 710 overlaps the second data pattern 620. In this case, the via electrode 710 may be electrically connected to the second data pattern 620 through the 22nd contact hole CNT22, and may be electrically connected to the first electrode of the first transistor T1 through the 12th contact hole CNT12.

[0188] The first vertical power supply voltage wiring 720 may extend in a vertical direction and may be arranged adjacent to the data wiring 640 but may not overlap the data wiring 640. Also, the first vertical power supply voltage wiring 720 may extend in a column direction to an adjacent pixel outside a boundary of the pixel.

[0189] The first vertical power supply voltage wiring 720 may overlap with the first longitudinal portion 110 of the lower semiconductor layer 100 (or the first electrode region of the fourth transistor T4). In the overlap region where the first vertical power supply voltage wiring 720 overlaps with the lower end of the first longitudinal portion 110 of the lower semiconductor layer 100, a fourth contact hole CNT4 may be formed that penetrates the first insulating layer 810, the second insulating layer 820, and the third insulating layer 830 to expose the lower end of the first longitudinal portion 110 of the lower semiconductor layer 100. In addition, a twenty-first contact hole CNT21 that penetrates the fourth insulating layer 840 and the fifth insulating layer 850 may be formed in the overlap region. The first vertical power supply voltage wiring 720 may be electrically connected to the first electrode region of the fourth transistor T4 through the fourth contact hole CNT4 and the twenty-first contact hole CNT21.

[0190] The first vertical power supply voltage wiring 720 may be partially reduced in the row direction and may not overlap the first data pattern 610 , the second data pattern 620 , and the gate electrode 220 of the first transistor T1 .

[0191] The first horizontal power supply voltage wiring 730 may extend substantially in the row direction and may be arranged to partially overlap the light emission control line 210. The first horizontal power supply voltage wiring 730 may extend substantially in the row direction and may be arranged to partially overlap the light emission control line 210. Figure 8 The edge of the light emitting element EL shown in has a zigzag pattern (or a pattern including concave portions and convex portions), and may not overlap with the light emitting element EL.

[0192] In addition, the first horizontal power supply voltage wiring 730 may extend in the row direction to an adjacent pixel outside the boundary of the pixel.

[0193] In the overlapping area where the first vertical power supply voltage wiring 720, the first horizontal power supply voltage wiring 730 and the electrode line 320 of the storage capacitor CST overlap with each other, a third contact hole CNT3 penetrating the second insulating layer 820, the third insulating layer 830, the fourth insulating layer 840 and the fifth insulating layer 850 to expose the electrode line 320 of the storage capacitor CST can be formed, and the first vertical power supply voltage wiring 720 (or the first horizontal power supply voltage wiring 730) can be electrically connected to the electrode line 320 of the storage capacitor CST through the third contact hole CNT3.

[0194] The fifth conductive layer 700 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fifth conductive layer 700 may be a single film or a multilayer film. For example, the fifth conductive layer 700 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0195] The sixth insulating layer 860 may be disposed on the fifth conductive layer 700, and may be disposed over the entire surface of the substrate 910. The sixth insulating layer 860 may insulate the fifth conductive layer 700 from the light emitting element EL. The sixth insulating layer 860 may include the same material as the second insulating layer 820, or may include at least one material selected from the exemplified constituent materials of the second insulating layer 820. The sixth insulating layer 860 may be a single film or a multilayer film made of stacked films of different materials.

[0196] The anode electrode ANODE of the light emitting element EL may be disposed on the sixth insulating layer 860. The anode electrode ANODE may overlap the through-hole electrode 710. In a region where the anode electrode ANODE overlaps the through-hole electrode 710, a contact hole penetrating the sixth insulating layer 860 to expose the through-hole electrode 710 may be formed, and the anode electrode ANODE may be electrically connected to the through-hole electrode 710 through the contact hole.

[0197] The pixel defining layer PDL is disposed along the edge of the anode electrode ANODE, and the light emitting layer ELL may be disposed on the anode electrode ANODE and the pixel defining layer PDL. The cathode electrode CATHODE of the light emitting element EL may be disposed on the light emitting layer ELL.

[0198] As above Figures 4 to 8 As described above, each of the first transistor T1 and the fourth transistor T4 may include a polysilicon semiconductor, and each of the second transistor T2 and the third transistor T3 may include an oxide semiconductor. The vertical sensing wiring 650 may be electrically connected to the second electrode of the fourth transistor T4 through the protrusion 652, and may be electrically connected to the horizontal sensing wiring 310. The auxiliary voltage wiring 660 may be arranged corresponding to the vertical sensing wiring 650, but may not be electrically connected to the second electrode of the fourth transistor T4.

[0199] At the same time, despite Figure 5 , the first transistor T1 to the fourth transistor T4 are shown to be top-gate transistors, but the present inventive concept is not limited thereto. For example, the first transistor T1 and the fourth transistor T4 may be top-gate transistors, and the second transistor T2 and the third transistor T3 may be bottom-gate transistors whose gate electrodes are arranged below the semiconductor layer. In this case, the first scan line 510 (i.e., the first scan line 510 including the gate electrodes of the second transistor T2 and the third transistor T3) may be included in the second conductive layer 300 instead of the third conductive layer 500, and may be arranged on the second insulating layer 820.

[0200] Fig. 9 It is shown that the Figure 4 View of another example of a fifth conductive layer in a pixel of FIG.

[0201] Reference Figure 4 , Figure 7 and Fig. 9 , the fifth conductive layer 700 may further include a protruding pattern 740 (or a conductive pattern).

[0202] The protrusion pattern 740 may have substantially the same shape as the protrusion 652 of the vertical sensing wiring 650 , and may overlap the auxiliary voltage wiring 660 and the third data pattern 630 .

[0203] The protrusion pattern 740 may be connected to only one selected from the auxiliary voltage wiring 660 , the third data pattern 630 , and the via electrode 710 , and may not be connected to the remaining portions thereof that are not selected.

[0204] For example, the protruding pattern 740 may not be electrically connected to the auxiliary voltage wiring 660, and the protruding pattern 740 and the auxiliary voltage wiring 660 may be insulated from each other by the fifth insulating layer 850. In this case, the protruding pattern 740 may be electrically connected to the third data pattern 630 through a separate contact hole.

[0205] As another example, the protrusion pattern 740 may be electrically connected to the auxiliary voltage wiring 660 through a separate contact hole, but may not be electrically connected to the third data pattern 630 .

[0206] In this case, the pixel regions have layouts similar to each other in a plan view, so that the pixels can have characteristics similar to each other.

[0207] Fig.10 It is shown that the Figure 4 Layout diagram of another example of auxiliary voltage wiring in a pixel of FIG.

[0208] Reference Figure 8 and Fig.10 , the auxiliary voltage wiring 660_1 and the reference Figure 4 and Figure 8 The auxiliary voltage wiring 660 described is different in that the width of the auxiliary voltage wiring 660_1 changes in the row direction.

[0209] In the first overlapping region overlapping with the horizontal sensing wiring 310, the first width W1 of the auxiliary voltage wiring 660_1 may be greater than the average width of the auxiliary voltage wiring 660_1. In the second overlapping region overlapping with the first scan line 510, the second width W2 of the auxiliary voltage wiring 660_1 may be less than the average width of the auxiliary voltage wiring 660_1. In the third overlapping region overlapping with the light emitting control line 210, the third width W3 of the auxiliary voltage wiring 660_1 may be similar to or the same as the average width of the auxiliary voltage wiring 660_1, or may be equal to the first width W1. The first width W1 of the auxiliary voltage wiring 660_1 may be equal to or greater than the third width W3, and the third width W3 may be greater than the second width W2. However, the first width W1 of the auxiliary voltage wiring 660_1 is less than the width (or length) of the protrusion 652 of the vertical sensing wiring 650_1, and the auxiliary voltage wiring 660_1 may not overlap with the third data pattern 630 or may not be connected to the third data pattern 630.

[0210] The third transistor T3 is formed on the first scan line 510, and the via electrode 710 is formed to be connected to the light emitting element EL, so that the second width W2 of the auxiliary voltage wiring 660_1 may be relatively small.

[0211] When the auxiliary voltage wiring 660_1 is connected in parallel with the first power supply voltage wiring (or the first vertical power supply voltage wiring 720), the resistance of the first power supply voltage wiring may be reduced, and the voltage drop of the first power supply voltage ELVDD may be further mitigated.

[0212] Meanwhile, the vertical sensing wiring 650_1 may include a body 651_1, and the body 651_1 may have substantially the same shape as the auxiliary voltage wiring 660_1. That is, a fourth width W4 of the vertical sensing wiring 650_1 in the first overlap region, a fifth width W5 of the vertical sensing wiring 650_1 in the second overlap region, and a sixth width W6 of the vertical sensing wiring 650_1 in the third overlap region may be equal to the first width W1, the second width W2, and the third width W3 of the auxiliary voltage wiring 660_1, respectively.

[0213] Fig.11 It is shown that the Figure 4 Layout diagram of another example of auxiliary voltage wiring in a pixel of FIG. Fig.12 is along Fig.11 Cross-sectional view taken along line CC' and line D-D'.

[0214] Reference Figure 4 , Figure 5 , Fig.11 and Fig.12 , the auxiliary voltage wiring 760 and Figure 4 The auxiliary voltage wiring 660 shown in FIG. 7 is different in that the auxiliary voltage wiring 760 includes a body 761 and a protrusion 762 .

[0215] The body 761 may have the same shape as the body 651 of the vertical sensing wiring 650 , and the protrusion 762 may have the same shape as the protrusion 652 of the vertical sensing wiring 650 .

[0216] In addition, the auxiliary voltage wiring 760 may be formed on a fifth conductive layer 700 (ie, a conductive layer on which the power supply voltage wiring is formed) different from the fourth conductive layer 600 on which the vertical sensing wiring 650 is formed.

[0217] In this case, the influence of the auxiliary voltage wiring 760 on the characteristics of the pixel PX may be slightly different from that of the vertical sensing wiring 650, but the difference may be very slight according to the thickness of the fifth insulating layer 850. Therefore, the pixel PX adjacent to the auxiliary voltage wiring 760 may have substantially the same characteristics as those of the pixel adjacent to the vertical sensing wiring 650.

[0218] Figures 13 to 15 It is shown that the Figure 4 Layout diagrams of various implementations of auxiliary voltage wiring in pixels.

[0219] Reference Fig.11 and Fig.13 , the auxiliary voltage wiring 760_1 and Fig.11 The auxiliary voltage wiring 760_1 is different from the auxiliary voltage wiring 760_1 in that the auxiliary voltage wiring 760_1 does not include the protrusion 762 .

[0220] Meanwhile, the protruding pattern 662_1 (or reference Fig. 9 The protrusion pattern 740_1 is described as being formed to overlap the auxiliary voltage wiring 760_1, but the protrusion pattern 662_1 may be formed on the fourth conductive layer 600. The protrusion pattern 662_1 may be connected to the third data pattern 630.

[0221] That is, in a plan view, the auxiliary voltage wiring 760_1 and the protrusion pattern 662_1 each have a similar shape to the vertical sensing wiring 650 so that the pixel PX adjacent to the auxiliary voltage wiring 760_1 may have substantially the same characteristics as the pixel adjacent to the vertical sensing wiring 650 .

[0222] Reference Fig.11 and Fig.14 , the auxiliary voltage wiring 760_2 and Fig.11 The auxiliary voltage wiring 760_2 is different from the auxiliary voltage wiring 760_2 in that the auxiliary voltage wiring 760_2 further includes a lateral portion 763 .

[0223] As above Figure 1 As described above, in one row, the horizontal sensing wires (eg, the eleventh to 1kth horizontal wires SH11 to 1kth horizontal wires SH1k) may be arranged along the row direction to be spaced apart from each other.

[0224] like Fig.14 As shown in , the horizontal sensing wiring 310 may include a first horizontal sensing wiring 311 and a second horizontal sensing wiring 312. The first horizontal sensing wiring 311 and the second horizontal sensing wiring 312 may be arranged in one line, and may be arranged to be spaced apart from each other in the row direction (or horizontal direction). The first horizontal sensing wiring 311 and the second horizontal sensing wiring 312 may be arranged in different directions from each other relative to the body 761 of the auxiliary voltage wiring 760_2. For example, Figure 1 The eleventh horizontal sensing wiring SH11 shown in FIG. 1 may be arranged on one side (eg, left side) of the first auxiliary voltage wiring DML1, and the twelfth horizontal sensing wiring (not shown) may be arranged on the other side (eg, right side) of the first auxiliary voltage wiring DML2.

[0225] In this case, the auxiliary voltage wiring 760_2 disposed between the first horizontal sensing wiring 311 and the second horizontal sensing wiring 312 may include a lateral portion 763. The lateral portion 763 of the auxiliary voltage wiring 760_2 may extend in a horizontal direction (or left-right direction) relative to the body 761 and may overlap the first horizontal sensing wiring 311 and the second horizontal sensing wiring 312.

[0226] Therefore, pixels connected to the ends of the first and second horizontal sensing wirings 311 and 312 may have substantially the same characteristics as pixels connected to other portions of the first and second horizontal sensing wirings 311 and 312 .

[0227] Reference Fig.10 , Fig.11 and Fig.15 , the auxiliary voltage wiring 760_3 and Fig.11 The auxiliary voltage wiring 760_3 is different from the auxiliary voltage wiring 760_3 in that the auxiliary voltage wiring 760_3 has a width that varies along the row direction.

[0228] In the area where the auxiliary voltage wiring 760_3 overlaps with the horizontal sensing wiring 310, the first width W1 of the auxiliary voltage wiring 760_3 may be greater than the average width of the auxiliary voltage wiring 760_3. In addition, the first width W1 of the auxiliary voltage wiring 760_3 may be equal to or greater than the width of the protrusion 652 of the vertical sensing wiring 650. Accordingly, the auxiliary voltage wiring 760_3 may completely cover the third data pattern 630. In this case, since the cross-sectional area of ​​the auxiliary voltage wiring 760_3 is partially increased, the resistance value of the auxiliary voltage wiring 760_3 may be reduced. When the auxiliary voltage wiring 760_3 is connected to the first power supply voltage wiring, the voltage drop of the first power supply voltage ELVDD may be further reduced.

[0229] At the same time, refer to Fig.15 , the vertical sensing wiring 650_3 may have substantially the same shape as the auxiliary voltage wiring 760_3. That is, the fourth width W4 of the vertical sensing wiring 650_3 in the first overlap region, the fifth width W5 of the vertical sensing wiring 650_3 in the second overlap region, and the sixth width W6 of the vertical sensing wiring 650_3 in the third overlap region may be equal to the first width W1, the second width W2, and the third width W3 of the auxiliary voltage wiring 760_3, respectively.

[0230] Fig.16 It is shown that the Figure 1 A cross-sectional view of another example of a display unit in a display device. Fig.16 Can correspond to along Figure 2A A cross-sectional view taken along line XVI-XVI'.

[0231] Reference Figure 1 , Figure 2A and Fig.16 , display unit 10_3 and Figure 2A The display unit 10_3 is different from the display unit 10_3 in that the display unit 10_3 includes auxiliary voltage wirings DML1b to DML9b and vertical sensing wirings SV1b to SV3b.

[0232] The auxiliary voltage wirings DML1b to DML9b may be formed in the same manner as those described above except for the layers in which these auxiliary voltage wirings DML1b to DML9b are formed. Figure 1 and Figure 2A The auxiliary voltage wirings DML1 to DML9 described above are substantially the same. The vertical sensing wirings SV1b to SV3b may be the same as those already described with reference to Figure 1 and Figure 2A The vertical sensing wirings SV1 to SV3 described are substantially the same, and therefore, redundant descriptions will not be repeated.

[0233] like Fig.16 2 , the first auxiliary voltage wiring DML1b, the second auxiliary voltage wiring DML2b, the fourth auxiliary voltage wiring DML4b, the fifth auxiliary voltage wiring DML5b, the seventh auxiliary voltage wiring DML7b, and the eighth auxiliary voltage wiring DML8b may be formed in the fourth conductive layer 600, and the third auxiliary voltage wiring DML3b, the sixth auxiliary voltage wiring DML6b, and the ninth auxiliary voltage wiring DML9b may be formed in the fifth conductive layer 700. That is, the auxiliary voltage wiring intersecting (or overlapping) the horizontal sensing wiring shown in FIG. 2 may be formed in the fourth conductive layer 600, and the auxiliary voltage wiring not intersecting (or not overlapping) the horizontal sensing wiring shown in FIG. 2 may be formed in the fifth conductive layer 700.

[0234] In this case, the third auxiliary voltage wiring DML3b, the sixth auxiliary voltage wiring DML6b, and the ninth auxiliary voltage wiring DML9b may be connected to Fig.14 That is, the third auxiliary voltage wiring DML3 b , the sixth auxiliary voltage wiring DML6 b , and the ninth auxiliary voltage wiring DML9 b include a transverse portion 763 , and may overlap with the horizontal sensing wiring through the transverse portion 763 .

[0235] Therefore, pixels connected to the ends of the first and second horizontal sensing wirings 311 and 312 may have substantially the same characteristics as pixels connected to other portions of the first and second horizontal sensing wirings 311 and 312 .

[0236] Fig.17 It is shown that the Figure 1 A circuit diagram of yet another example of a display unit in a display device.

[0237] Reference Figure 1 , Figure 2A and Fig.17 , the display unit 10_4 and Figure 2A The display unit 10_4 is different from the display unit 10_4 in that the display unit 10_4 includes vertical sensing wirings SV1_3 to SV6_3 and auxiliary voltage wirings DML1_3 to DML6_3.

[0238] The vertical sensing wirings SV1_3 to SV6_3 are connected to Figure 2A The vertical sensing wirings SV1 to SV3 are similar to the vertical sensing wirings SV1 to SV3, but may be arranged to be spaced apart from each other at intervals corresponding to four pixels. Meanwhile, the auxiliary voltage wirings DML1_3 to DML6_3 are arranged between the vertical sensing wirings SV1_3 to SV6_3, and may be arranged to be spaced apart from each other at intervals corresponding to four pixels. That is, the vertical sensing wirings SV1_3 to SV6_3 and the auxiliary voltage wirings DML1_3 to DML6_3 may be alternately arranged along the row direction at intervals corresponding to two pixels.

[0239] Meanwhile, the vertical sensing wirings SV1_3 to SV6_3 may be connected to four pixels in one row, and for this purpose, the horizontal sensing wiring may extend in a row direction by a length corresponding to four pixels.

[0240] Fig.18 and Fig.19 It is shown Figure 1 Circuit diagrams of various embodiments of a display unit in a display device. Fig.18 and Fig.19 is with Figure 3 The corresponding circuit diagram.

[0241] Reference Figure 3 and Fig.18 , the display unit 10_5 and Figure 3 The difference between the display unit 10 and the display unit 10_5 is that the display unit 10_5 further includes a pixel PX_2, wherein the pixel PX_2 further includes a fifth transistor T5. In addition to the fifth transistor T5, the pixel PX_2 can be connected to the reference Figure 3 The described pixels PX are substantially the same or similar.

[0242] Similar to the second transistor T2 and the third transistor T3 , the fifth transistor T5 may include an oxide semiconductor.

[0243] The fifth transistor T5 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1 (or the anode electrode of the light emitting element EL), and a gate electrode receiving the third scan signal SCAN3. Here, the third scan signal SCAN3 may have a waveform substantially the same as or similar to that of the first scan signal SCAN1.

[0244] The fifth transistor T5 may be turned on in response to the third scan signal SCAN3 and may serve to compensate for a threshold voltage of the first transistor T1 .

[0245] Reference Figure 3 and Fig.19 , display unit 10_6 and Figure 3 The display unit 10 is different in that the display unit 10_6 includes a pixel PX_3.

[0246] The pixel PX_3 may include a light emitting element EL, first to sixth transistors T1 to T6, and a storage capacitor CST. That is, the pixel PX_3 may have a 6T1C structure.

[0247] The first transistor T1, the second transistor T2, and the fourth transistor T4 and the storage capacitor CST may be connected to the Figure 3 The first transistor T1, the second transistor T2, and the fourth transistor T4 and the storage capacitor CST described are substantially the same, and therefore, redundant descriptions will not be repeated.

[0248] Similar to the first transistor T1, the third transistor T3 and the sixth transistor T6 may include polysilicon semiconductors and may be top-gate transistors. Similar to the second transistor T2, the fifth transistor T5 may include an oxide semiconductor and may be a top-gate transistor.

[0249] The third transistor T3 may include a first electrode connected to the first electrode of the first transistor T1, a second electrode connected to the horizontal sensing wiring LSEN1, and a gate electrode receiving the second scan signal SCAN2. The third transistor T3 may be turned on in response to the second scan signal SCAN2, and in this case, the sensing unit 50 may measure the characteristics of the pixel PX.

[0250] The fifth transistor T5 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode electrode of the light emitting element EL, and a gate electrode receiving the second light emitting control signal EM2. Similar to the fourth transistor T4, the fifth transistor T5 may be turned on in response to the second light emitting control signal EM2, and a driving current may be provided to the light emitting element EL.

[0251] The sixth transistor T6 may include a first electrode connected to the anode electrode of the light emitting element EL, a second electrode receiving the initialization voltage VINT, and a gate electrode receiving the third scan signal SCAN3. Before or after the light emitting element EL emits light, the sixth transistor T6 may be turned on in response to the third scan signal SCAN3, and the anode electrode (or parasitic capacitance) of the light emitting element EL may be initialized by the initialization voltage VINT.

[0252] The initialization voltage VINT can be obtained from Figure 1 The power supply unit (or external voltage) described above generates and provides In this case, the auxiliary voltage VAUX applied to the auxiliary voltage wirings DL2 to DL4 may be equal to the initialization voltage VINT.

[0253] As above Fig.18 and Fig.19 As described above, in addition to 4T1C, the display units 10_5 and 10_6 may include pixels PX_2 and PX_3 having a 5T1C or 6T1C structure. Even in this case, the vertical sensing wirings may be spaced apart from each other at a specific interval (e.g., an interval corresponding to eight pixels) in the row direction, and the auxiliary voltage wirings may be spaced apart from each other at a specific interval (e.g., an interval corresponding to two pixels) in the row direction between the vertical sensing wirings. Therefore, the pixels arranged in the display units 10_5 and 10_6 have similar characteristics regardless of the distance of the vertical sensing wiring LSEN2, and degradation of display quality can be prevented.

[0254] As described above, according to the display device of the embodiment, the difference in characteristics between pixels due to the sensing wiring can be eliminated by the auxiliary voltage wiring simulating the sensing wiring.

[0255] The effects of the inventive concept are not limited to the foregoing, and other various effects are expected herein.

[0256] Although the preferred embodiments of the inventive concept have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.

Claims

1. A display device, comprising: a plurality of scan lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a plurality of data lines extending in the second direction and arranged in the first direction; a plurality of pixel groups, each of the plurality of pixel groups comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; a plurality of sensing lines extending in the second direction and arranged in the first direction; as well as a plurality of auxiliary voltage lines extending in the second direction and arranged in the first direction, and Among them, a first sensing line among the plurality of sensing lines and one of a first auxiliary voltage line among the plurality of auxiliary voltage lines are arranged between the second pixel of a first pixel group among the plurality of pixel groups and the third pixel of the first pixel group.

2. The display device according to claim 1, wherein: The first auxiliary voltage line is arranged between the second pixel of the first pixel group and the third pixel of the first pixel group, and The first sensing line is arranged between the fourth pixel of the first pixel group and the first pixel of the second pixel group among the plurality of pixel groups, and The second pixel group is adjacent to the first pixel group in the first direction.

3. The display device according to claim 1, wherein: The first sensing line is arranged between the second pixel of the first pixel group and the third pixel of the first pixel group, and The first auxiliary voltage line is arranged between the fourth pixel of the first pixel group and the first pixel of the second pixel group among the plurality of pixel groups, and The second pixel group is adjacent to the first pixel group in the first direction.

4. The display device according to claim 1, wherein: A second sensing line among the plurality of sensing lines and one of the second auxiliary voltage lines among the plurality of auxiliary voltage lines are arranged between the fourth pixel of a second pixel group among the plurality of pixel groups and the first pixel of a third pixel group among the plurality of pixel groups adjacent to the second pixel group in the first direction.

5. The display device according to claim 4, wherein: The second auxiliary voltage line is arranged between the fourth pixel of the second pixel group and the first pixel of the third pixel group, and Wherein, a third auxiliary voltage line among the plurality of auxiliary voltage lines is arranged between the second pixel of the third pixel group and the third pixel of the third pixel group.

6. The display device according to claim 4, wherein: The second sensing voltage line is arranged between the fourth pixel of the second pixel group and the first pixel of the third pixel group, and The second auxiliary voltage line is arranged between the second pixel of the third pixel group and the third pixel of the third pixel group.

7. The display device according to claim 1, wherein: The first sensing line is disposed between two adjacent auxiliary voltage lines among the plurality of auxiliary voltage lines.

8. The display device according to claim 1, wherein: The first pixel is configured to emit light of a first color, and wherein the second pixel and the fourth pixel are configured to emit light of a second color, and Wherein, the third pixel is configured to emit light of a third color.

9. The display device according to claim 1, wherein: The first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in a first row in the order of the first pixel, the second pixel, the third pixel, and the fourth pixel in the first direction.

10. The display device according to claim 9, wherein: The first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in a second row adjacent to the first row in the order of the third pixel, the fourth pixel, the first pixel, and the second pixel in the first direction.

11. The display device according to claim 1, wherein: The plurality of sensing lines and the plurality of auxiliary voltage lines are arranged on the same layer.

12. The display device according to claim 1, wherein: Each of the plurality of sensing lines includes a body and a protrusion protruding from the body.

13. The display device according to claim 12, further comprising: A protruding pattern is formed, and the protruding pattern overlaps the plurality of auxiliary voltage lines.

14. The display device according to claim 13, wherein: The protrusion pattern is arranged on a different layer from the plurality of sensing lines and the plurality of auxiliary voltage lines.

15. The display device according to claim 1, wherein: The plurality of sensing lines and the plurality of auxiliary voltage lines are arranged on different layers.

16. The display device according to claim 15, wherein: Each of the plurality of sensing lines includes a first body and a first protrusion protruding from the first body, and Each of the plurality of auxiliary voltage lines includes a second body and a second protrusion protruding from the second body.

17. The display device according to claim 1, further comprising: a power supply unit that supplies an auxiliary voltage to the plurality of auxiliary voltage lines, and A sensing unit supplies a sensing voltage to the plurality of sensing lines and measures a sensing current from each of the plurality of sensing lines.

18. A display device comprising: a plurality of scan lines extending in a first direction and arranged in a second direction perpendicular to the first direction; a plurality of data lines extending in the second direction and arranged in the first direction; a plurality of pixel groups, each of the plurality of pixel groups comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; a plurality of sensing lines extending in the second direction and arranged in the first direction; as well as a plurality of auxiliary voltage lines extending in the second direction and arranged in the first direction, and The first sensing line among the plurality of sensing lines and one of the first auxiliary voltage line among the plurality of auxiliary voltage lines are arranged between the first pixel of the first pixel group among the plurality of pixel groups and the second pixel of the first pixel group.

19. The display device according to claim 18, wherein: The first auxiliary voltage line is arranged between the first pixel of the first pixel group and the second pixel of the first pixel group, and The first sensing line is arranged between the third pixel of the first pixel group and the fourth pixel of the first pixel group.

20. The display device according to claim 18, wherein: The first sensing line is arranged between the first pixel of the first pixel group and the second pixel of the first pixel group, and The first auxiliary voltage line is arranged between the third pixel of the first pixel group and the fourth pixel of the first pixel group.

21. The display device according to claim 18, wherein: The first pixel is configured to emit light of a first color, and wherein the second pixel and the fourth pixel are configured to emit light of a second color, and Wherein, the third pixel is configured to emit light of a third color.

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