Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof, and the method comprises the steps: forming a multi-layer structure which at least comprises a lower metal layer, a first dielectric layer located on the lower metal layer, an upper metal layer located on the first dielectric layer, and a welding layer located on the upper metal layer; etching the multi-layer structure in a patterning manner to form a first structure and a second structure which are separated from each other; a part of the welding layer in the second structure is etched to expose a part of the upper surface of the upper metal layer, the reserved welding layer is an electrode of the thin film resistor, and a group of conductive channels correspondingly connected with the first structure and the second structure are formed, the lower metal layer of the first structure is a lower pole plate of the MIM capacitor, the upper metal layer of the first structure is an upper pole plate of the MIM capacitor, and the upper metal layer of the second structure is a thin film metal layer of the thin film resistor.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device and a method for forming a semiconductor device. Background Art

[0002] Resistors and capacitors are widely used in analog circuits and their basic circuit modules. In some high-precision analog integrated circuits, such as multi-bit digital-to-analog converters, resistors are generally implemented using thin-film resistors with low mismatch, low temperature coefficient of resistance (TCR) and low voltage coefficient of resistance (VCR). Capacitors are implemented using metal-insulator-metal (MIM) capacitors. MIM capacitors are equivalent to parallel plate capacitors. MIM capacitors are generally composed of a layer of metal and a special metal layer in the middle. The dielectric layer between the two layers of metal is relatively thin, and the capacitance density formed is relatively high. In existing technologies, the formation of thin-film resistors and MIM capacitors is two independent steps. After forming the MIM capacitor, the formation of thin-film resistors requires two additional photolithography and etching processes, which increases the cost of the process. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a semiconductor device and a method for forming the same to solve the problems existing in the prior art.

[0004] According to a first aspect of the present invention, a method for forming a semiconductor device is provided, wherein the semiconductor device includes a metal-insulator-metal (MIM) capacitor and a thin film resistor, and wherein the method includes: forming a multilayer structure, including at least a lower metal layer, a first dielectric layer located on the lower metal layer, an upper metal layer located on the first dielectric layer, and a welding layer located on the upper metal layer; patterning the multilayer structure to form a first structure and a second structure separated from each other; etching a portion of the welding layer in the second structure to expose a portion of the upper surface of the upper metal layer, the retained welding layer being an electrode of the thin film resistor, and forming a group of conductive paths respectively connected to the first structure and the second structure, wherein the lower metal layer of the first structure is a lower plate of the MIM capacitor, the upper metal layer of the first structure is an upper plate of the MIM capacitor, and the upper metal layer of the second structure is a thin film metal layer of the thin film resistor.

[0005] Preferably, the method for forming the first structure and the second structure includes: forming a patterned first photoresist on the upper surface of the multilayer structure; using the patterned first photoresist as a mask, etching from the upper surface of the multilayer structure and stopping at the upper surface of the lower metal layer to form a first part and a second part with the lower metal layer as a common bottom; forming a patterned second photoresist on the etched multilayer structure; using the patterned second photoresist as a mask, etching the lower metal layer to form the first structure including the first part and the second structure including the second part.

[0006] Preferably, a width of an etching window of the second photoresist is smaller than a distance between the first portion and the second portion.

[0007] Preferably, the multi-layer structure is etched in a patterned manner so that the upper surface of at least one side of the lower metal layer of the first structure is exposed.

[0008] Preferably, the multilayer structure further comprises a protective layer formed on the upper surface of the welding layer.

[0009] Preferably, the welding layer in the second structure is etched using a wet etching process.

[0010] Preferably, before etching part of the welding layer in the second structure, the protective layer is first etched using a dry etching process.

[0011] Preferably, before forming the conductive channel, the step includes forming an interlayer dielectric layer covering the first structure and the second structure.

[0012] Preferably, the method for forming the conductive path includes: forming a group of first through holes connecting the first structure and a group of second through holes connecting the second structure, wherein one first through hole starts from the upper surface of the interlayer dielectric layer and extends to the welding layer of the first structure, another first through hole starts from the upper surface of the interlayer dielectric layer, passes through the interlayer dielectric layer, and extends to the lower metal layer of the first structure, two second through holes respectively start from the upper surface of the interlayer dielectric layer and extend to the thin film resistor electrode, and the first through holes and the second through holes are filled with conductive material to form a conductive path.

[0013] According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a metal-insulator-metal (MIM) capacitor and a thin film resistor: the MIM capacitor comprises a lower metal layer, an upper metal layer, a first dielectric layer located between the upper metal layer and the lower metal layer, and a first welding layer located on the upper metal layer; the thin film resistor comprises a thin film resistor metal layer and a second welding layer located thereon, the second welding layer comprising an opening exposing the upper surface of the thin film resistor metal layer; wherein the thin film resistor metal layer and the upper metal layer are of the same metal layer separated from each other, and the thin film resistor metal layer further comprises a pseudo dielectric layer located at the same layer as the first dielectric layer and separated from each other, and a pseudo lower metal layer located at the same layer as the lower metal layer and separated from each other.

[0014] Preferably, the width of the first dielectric layer of the MIM capacitor is smaller than the width of the lower metal layer, and at least an upper surface of one side of the lower metal layer is exposed.

[0015] Preferably, the width of the first dielectric layer of the MIM capacitor is the same as that of the upper metal layer, and they are aligned left and right.

[0016] Preferably, the MIM capacitor and the thin film resistor include protective layers separated from each other and located on the first welding layer and the second welding layer, respectively.

[0017] Preferably, it also includes an interlayer dielectric layer covering the MIM capacitor and the thin film resistor.

[0018] Preferably, the MIM capacitor includes a first conductive channel extending from the upper surface of the interlayer dielectric layer to the upper surface of the lower metal layer, and a second conductive channel extending from the upper surface of the interlayer dielectric layer to the upper surface of the first welding layer of the MIM capacitor, and the thin-film resistor includes two third conductive channels extending from the upper surface of the interlayer dielectric layer to the upper surface of the second welding layer of the thin-film resistor.

[0019] Preferably, the semiconductor device further comprises a plurality of second metal layers separated from each other, and the plurality of second metal layers are respectively in contact with the upper surfaces of the first conductive channel, the second conductive channel and the third conductive channel.

[0020] Preferably, the material of the thin film resistor metal layer and the upper metal layer is set to be a combination of one or more of CrSi, SiCCr, TaN, NiCr, AlNiCr, and TiNiC.

[0021] Preferably, the material of the welding layer is set to be TiN material. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0024] Figure 2a-2e It is a cross-sectional structural diagram of certain steps of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0026] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0027] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0028] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0029] Figure 1 A flow chart showing a method for forming a semiconductor device according to an embodiment of the present invention is shown, and the specific steps are as follows:

[0030] Step S101: forming a multi-layer structure, wherein the multi-layer structure at least comprises a lower metal layer, a first dielectric layer located on the lower metal layer, an upper metal layer located on the first dielectric layer, and a welding layer located on the upper metal layer.

[0031] Specifically, Figure 2aAs shown, the lower metal layer 101 is first formed, and then a first dielectric layer 102 is formed on the lower metal layer 101, an upper metal layer 103 is formed on the first dielectric layer 102, and a welding layer 104 is formed on the upper metal layer 103. The lower metal layer 101 is generally an aluminum layer, which serves as the lower metal of the MIM capacitor, i.e., the lower plate. The dielectric layer 102 can be an oxide layer, a nitride layer or other insulating layer. In this embodiment, the dielectric layer 102 is set as a medium between the upper and lower plates of the MIM capacitor. The upper metal layer 103 serves as the upper metal of the MIM capacitor, i.e., the upper plate, and can also be used as the metal layer of the thin film resistor of the thin film resistor in the subsequent process. The upper metal layer 103 is preferably a CrSi material, and can also be set to other metal materials, such as SiCCr, TaN, NiCr, AlNiCr, TiNiC or any other suitable thin film resistor material. One or more combinations thereof. The welding layer 104 is set as a stop layer for the subsequent through-hole of the thin film resistor. Because the metal layer (upper metal layer) of the thin film resistor is generally very thin, it is easy to be penetrated during the process of forming the through-hole. Therefore, a barrier layer is formed on it, which can serve as the welding layer of the thin film resistor and protect the surface of the thin film resistor from being damaged. In this embodiment, the welding layer is preferably titanium nitride.

[0032] In this embodiment, the multi-layer structure further includes a protective layer 105 located on the welding layer 104 , and the protective layer 105 is preferably silicon oxynitride.

[0033] It should be noted that the lower metal layer may be any layer from the first metal layer to the second top metal layer in the semiconductor integrated circuit or device manufacturing process.

[0034] Step S102: etching the multilayer structure in a patterned manner to form a first structure and a second structure separated from each other.

[0035] Step S102 includes the following two steps: Figure 2b As shown, using the patterned photoresist as a mask, etching is started from the upper surface of the multi-layer structure downwards and stops at the upper surface of the lower metal layer 101 .

[0036] Specifically, a first photoresist is coated on the multilayer structure. After the first photoresist is exposed and developed through the mask of the MIM capacitor and the thin film resistor, the patterned first photoresist is used as a mask and the multilayer structure is etched by a reactive ion etching process to form a first part 201 and a second part 202 with the lower metal layer 101 as a common bottom, wherein the first part 201 corresponds to the MIM capacitor structure part, and the second part 202 corresponds to the thin film resistor structure part. The first part 201 and the second part 202 are separated from each other on the lower metal layer 101. Furthermore, the structures on the two side edges of the lower metal layer 101 are also etched, that is, the upper surfaces of the two side edges of the lower metal layer 101 are also exposed.

[0037] Step 2: Continue etching the lower metal layer to form a first structure and a second structure separated from each other. The specific steps are as follows: Figure 2d As shown, it will be explained in detail later.

[0038] Step S103: etching a portion of the welding layer in the second structure to expose a portion of the upper surface of the upper metal layer, and the remaining welding layer serves as an electrode of the thin-film resistor.

[0039] like Figure 2c As shown, taking the protective layer 105 as an example, the patterned third photoresist is used as a mask to etch part of the protective layer and the welding layer of the second part 202 to expose part of the upper surface of the upper metal layer.

[0040] Specifically, in Figure 2b A layer of photoresist is coated on the structure shown, and after the third photoresist is exposed and developed through a patterned mask, the protective layer 105 is etched by a dry etching process to form a patterned protective layer, and then the welding layer 104 is etched by a wet etching process to expose a portion of the upper surface of the upper metal layer. In this embodiment, the upper metal layer of the second part is set as the thin film resistor metal layer 301 of the thin film resistor. In other embodiments, the dry etching process can also be used to directly etch the protective layer and the welding layer to expose a portion of the upper surface of the upper metal layer. In the present application, the process method for etching the protective layer and the welding layer is not limited, as long as the patterned structure required by the present application can be obtained.

[0041] like Figure 2d As shown, the lower metal layer is etched to form a first structure and a second structure separated from each other.

[0042] Specifically, in Figure 2cA patterned second photoresist is formed on the structure, and the patterned second photoresist is used as a mask to etch the lower metal layer to form two separated parts 1011 and 1012. The first structure 401 includes a part 1011 of the lower metal layer and a first part 201 located on 1011, and the second structure 402 includes a part 1012 of the lower metal layer and a second part 202 located on 1012. The first part 201 exposes at least one side of the upper surface of the lower metal layer.

[0043] The distance between the portions 1011 and 1012 of the lower metal layer (i.e., the etching window of the second photoresist) is smaller than the distance between the first portion 201 and the second portion 202. In this embodiment, the first portion 201 exposes the upper surface of the portion 1011 of the lower metal layer on both sides, and the second portion 202 exposes the upper surface of the portion 1012 of the lower metal layer on both sides.

[0044] It should be noted that Figure 2c and Figure 2d The process steps can be interchanged without affecting the final structure diagram, that is, Figure 2d The step of etching the lower metal layer and then performing Figure 2c The protective layer and the welding layer of the second part are etched in the step of, which is not limited here.

[0045] Step S104: forming a group of conductive channels respectively connected to the first structure and the second structure.

[0046] Specifically, Figure 2e As shown, an interlayer dielectric layer 503 covering the first structure and the second structure is first formed, and then the interlayer dielectric layer is etched by laser or reactive ion etching to form a first conductive via connecting the first structure and a second conductive via connecting the second structure, and then metal is filled in the first conductive via and the second conductive via to form a first conductive channel 601 and 602 and a second conductive channel 603. The first conductive channel 601 starts from the upper surface of the interlayer dielectric layer, passes through the interlayer dielectric layer 503 and extends to the upper surface of the lower metal layer 1011 of the first structure, the first conductive channel 602 starts from the upper surface of the interlayer dielectric layer 503, passes through the interlayer dielectric layer 503 and the protective layer 1051 of the first structure and extends to the upper surface of the welding layer 1041 of the first structure, and the second conductive channel 603 starts from the upper surface of the interlayer dielectric layer 503, passes through the interlayer dielectric layer and the protective layer 1052 of the two structures and extends to the upper surface of the welding layer 1042 of the second structure.

[0047] The method further includes forming a plurality of second metal layers 701 separated from each other, the second metal layers contacting the upper surface of the conductive path, wherein each conductive path is connected to a different second metal layer. The lower metal layer 101 is the nth metal layer in the semiconductor integrated circuit or device manufacturing process, and the second metal layer 701 is the n+1th metal layer in the semiconductor integrated circuit or device manufacturing process.

[0048] The present invention proposes a method for simultaneously manufacturing MIM capacitors and thin-film resistors. The MIM capacitor module and the thin-film resistor module can be manufactured using only two-step photolithography and etching processes (the first etching process defines the MIM capacitor area and the thin-film resistor area, and the second etching process defines the specific structure of the thin-film resistor). This method has one less photolithography and etching process than the traditional method, thereby reducing the process cost.

[0049] The present invention also provides a semiconductor device, such as Figure 2e As shown, the semiconductor device is formed according to the above method. The semiconductor device includes a metal-insulator-metal (MIM) capacitor 501 and a thin film resistor 502:

[0050] The MIM capacitor 501 includes a lower metal layer 1011, an upper metal layer 1031, a first dielectric layer 1021 between the upper metal layer 1031 and the lower metal layer 1011, and a first welding layer 1041 on the upper metal layer 1031. Furthermore, the MIM capacitor 501 includes a first protective layer 1051 on the first welding layer 1041.

[0051] The thin film resistor 502 includes a thin film resistor metal layer 301 and a second welding layer 1042 located thereon, wherein the second welding layer 1042 includes an opening exposing the upper surface of the thin film resistor metal layer. Further, the thin film resistor 502 includes a second protective layer 1052 located on the second welding layer 1042, wherein the second protective layer 1052 has an opening of the same width as the second welding layer 1042, wherein the second welding layer 1042 and the second protective layer 1052 expose a portion of the upper surface of the thin film resistor metal layer 301.

[0052] The thin film resistor metal layer 301 and the upper metal layer 1031 are located in the same metal layer and are separated from each other. The thin film resistor metal layer 301 also includes a pseudo dielectric layer located in the same layer and separated from each other as the first dielectric layer 1021, and a pseudo lower metal layer 1012 located in the same layer and separated from each other as the lower metal layer 1011. The first welding layer 1041 and the second welding layer 1042 are located in the same layer and are separated from each other, and the first protective layer 1051 and the second protective layer 1052 are located in the same layer and are separated from each other. The upper metal layer 1031 and the thin film resistor metal layer 301 are preferably CrSi materials, and can also be set to other metal materials, such as SiCCr, TaN, NiCr, AlNiCr, TiNiC or any other suitable thin film resistor material. One or more combinations thereof. The second welding layer 1042 is set as a stop layer for the subsequent through-hole of the thin film resistor. Because the metal layer (upper metal layer) of the thin film resistor is generally very thin, it is easy to be penetrated during the process of forming the through-hole. Therefore, a barrier layer is formed thereon, which can serve as a welding layer for the thin film resistor and protect the surface of the thin film resistor from being damaged. In this embodiment, the first welding layer 1041 and the second welding layer 1042 are preferably titanium nitride.

[0053] The width of the first dielectric layer 1021 of the MIM capacitor is smaller than the width of the lower metal layer 1011, and at least one side of the lower metal layer 1011 is exposed. The width of the first dielectric layer 1021 of the MIM capacitor is the same as the width of the upper metal layer 1031, and they are aligned left and right. The semiconductor device also includes an interlayer dielectric layer 503 covering the MIM capacitor 501 and the thin film resistor 502. The MIM capacitor includes a conductive channel 601 extending from the upper surface of the interlayer dielectric layer 503, through the interlayer dielectric layer, to the upper surface of the lower metal layer 1011, and also includes a conductive channel 602 extending from the upper surface of the interlayer dielectric layer 503, through the interlayer dielectric layer and the first protective layer 1051 of the MIM capacitor, to the upper surface of the first welding layer of the MIM capacitor. The thin film resistor includes a conductive path 603 extending from the upper surface of the interlayer dielectric layer 503 , through the interlayer dielectric layer and the second protection layer 1052 of the thin film resistor to the upper surface of the second welding layer 1042 of the thin film resistor.

[0054] The semiconductor device also includes a plurality of second metal layers 701 separated from each other, the second metal layers 701 being in contact with the upper surface of the conductive channel, wherein each conductive channel is connected to a different second metal layer 701. It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0055] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for forming a semiconductor device, wherein the semiconductor device comprises a metal-insulator-metal (MIM) capacitor and a thin film resistor, characterized in that: The method comprises: forming a multilayer structure, comprising at least a lower metal layer, a first dielectric layer located on the lower metal layer, an upper metal layer located on the first dielectric layer, and a welding layer located on the upper metal layer; Patterned etching of the multilayer structure to form a first structure and a second structure separated from each other; etching a portion of the welding layer in the second structure to expose a portion of the upper surface of the upper metal layer, and the remaining welding layer serves as an electrode of the thin film resistor; and forming a group of conductive channels connected to the first structure and the second structure respectively; The lower metal layer of the first structure is the lower plate of the MIM capacitor, the upper metal layer of the first structure is the upper plate of the MIM capacitor, and the upper metal layer of the second structure is the thin film metal layer of the thin film resistor.

2. The method according to claim 1, characterized in that The method of forming the first structure and the second structure includes: forming a patterned first photoresist on the upper surface of the multilayer structure; Using the patterned first photoresist as a mask, etching starts from the upper surface of the multilayer structure and stops at the upper surface of the lower metal layer to form a first portion and a second portion with the lower metal layer as a common bottom; forming a patterned second photoresist on the etched multilayer structure; The lower metal layer is etched using the patterned second photoresist as a mask to form the first structure including the first portion and the second structure including the second portion.

3. The method according to claim 2, characterized in that A width of an etching window of the second photoresist is smaller than a distance between the first portion and the second portion.

4. The method according to claim 1, characterized in that: The multi-layer structure is pattern-etched to expose at least one upper surface of the lower metal layer of the first structure.

5. The method according to claim 1, characterized in that The multi-layer structure further includes a protection layer formed on an upper surface of the welding layer.

6. The method according to claim 1, characterized in that The welding layer in the second structure is etched using a wet etching process.

7. The method according to claim 5, characterized in that Before etching part of the welding layer in the second structure, the protective layer is first etched using a dry etching process.

8. The method according to claim 1, characterized in that: The method includes forming an interlayer dielectric layer covering the first structure and the second structure before forming the conductive channel.

9. The method according to claim 8, characterized in that The method of forming the conductive path comprises: forming a group of first through holes connecting the first structure and a group of second through holes connecting the second structure, wherein one first through hole starts from the upper surface of the interlayer dielectric layer and extends to the welding layer of the first structure, another first through hole starts from the upper surface of the interlayer dielectric layer, passes through the interlayer dielectric layer, and extends to the lower metal layer of the first structure, and two second through holes respectively start from the upper surface of the interlayer dielectric layer and extend to the thin film resistor electrode, and The first through hole and the second through hole are filled with a conductive material to form a conductive path.

10. A semiconductor device, characterized in that: Includes: Metal-Insulator-Metal (MIM) Capacitors and Thin Film Resistors: The MIM capacitor comprises a lower metal layer, an upper metal layer, a first dielectric layer located between the upper metal layer and the lower metal layer, and a first welding layer located on the upper metal layer; The thin film resistor comprises a thin film resistor metal layer and a second welding layer located thereon, wherein the second welding layer comprises an opening exposing the upper surface of the thin film resistor metal layer; Among them, the thin film resistor metal layer and the upper metal layer belong to the same layer of metal separated from each other, and below the thin film resistor metal layer there is also a pseudo dielectric layer located in the same layer as the first dielectric layer and separated from each other, and a pseudo lower metal layer located in the same layer as the lower metal layer and separated from each other.

11. The semiconductor device according to claim 10, characterized in that The width of the first dielectric layer of the MIM capacitor is smaller than the width of the lower metal layer, and at least one upper surface of the lower metal layer is exposed.

12. The semiconductor device according to claim 10, characterized in that The width of the first dielectric layer of the MIM capacitor is the same as that of the upper metal layer, and they are aligned left and right.

13. The semiconductor device according to claim 10, characterized in that The MIM capacitor and the thin film resistor include protective layers separated from each other and located on the first welding layer and the second welding layer respectively.

14. The semiconductor device according to claim 10, characterized in that It also includes an interlayer dielectric layer covering the MIM capacitor and the thin film resistor.

15. The semiconductor device according to claim 14, characterized in that The MIM capacitor includes a first conductive channel extending from the upper surface of the interlayer dielectric layer to the upper surface of the lower metal layer, and a second conductive channel extending from the upper surface of the interlayer dielectric layer to the upper surface of the first welding layer of the MIM capacitor, and the thin-film resistor includes two third conductive channels extending from the upper surface of the interlayer dielectric layer to the upper surface of the second welding layer of the thin-film resistor.

16. The semiconductor device according to claim 15, characterized in that The semiconductor device further includes a plurality of second metal layers separated from each other, and the plurality of second metal layers are respectively in contact with the upper surfaces of the first conductive channel, the second conductive channel and the third conductive channel.

17. The semiconductor device according to claim 10, characterized in that The material of the thin film resistance metal layer and the upper metal layer is set to be a combination of one or more of CrSi, SiCCr, TaN, NiCr, AlNiCr, and TiNiC.

18. The semiconductor device according to claim 10, characterized in that The material of the welding layer is set to be TiN material.

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