High voltage driver for digital power amplifier

Abstract

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

Description

Technical Field

[0001] The present application relates to amplifiers, and more particularly to a high voltage driver for a digital power amplifier. Background Art

[0002] A power amplifier amplifies a radio frequency (RF) signal for transmission via an antenna. For example, a mobile device includes a power amplifier to amplify an RF signal having a relatively low power. The power amplifier requires a very large gain to adequately amplify this low power RF signal. Managing the amplification of the RF signal can be important because the desired transmit power level can depend on the user's distance from the base station and / or the mobile environment. A power amplifier can also be used to help regulate the power level of the RF signal over time to prevent signal interference caused by transmission during a designated receive time slot. Summary of the invention

[0003] A high voltage driver is disclosed, the high voltage driver comprising: a plurality of p-type metal oxide semiconductor (PMOS) transistors, the plurality of p-type metal oxide semiconductor (PMOS) transistors being arranged in series from a first PMOS transistor to an (N-1)th PMOS transistor, wherein N is an integer of 3 or greater than 3; an Nth PMOS transistor, the Nth PMOS transistor having a source coupled to a power supply voltage node and having a drain coupled to a source of the (N-1)th PMOS transistor; a first n-type metal oxide semiconductor (NMOS) transistor, the first n-type metal oxide semiconductor (NMOS) transistor having a source coupled to ground; a plurality of NMOS transistors, the plurality of NMOS transistors being arranged in series from a second NMOS transistor to an Nth PMOS transistor. The NMOS transistors are arranged in series, the NMOS transistor having a drain coupled to the output node of the voltage driver and the second NMOS transistor having a source coupled to the drain of the first NMOS transistor; a first clock source, which is configured to drive the gate of the first NMOS transistor with a first clock signal, and the first clock signal cycles between a supply voltage (Vdd) during a first clock phase and a ground during a second clock phase; and a second clock source, which is configured to drive the gate of the NPMOS transistor with a second clock signal, and the second clock signal cycles between N*Vdd during the first clock phase and (N-1)*Vdd during the second clock phase.

[0004] In addition, a power amplifier is provided, which includes: a plurality of first voltage drivers, each of which includes N PMOS transistors coupled between a power supply node and an output node and includes N NMOS transistors coupled between the output node and ground, wherein N is a positive integer of 3 or greater; a decoder configured to decode a baseband signal to select whether each first voltage driver is inactive or active based on the magnitude of the baseband signal and to phase a first clock signal and a second clock signal based on the phase of the baseband signal, wherein the first clock signal is configured to cycle between ground and a power supply voltage (Vdd) to drive a gate of a first NMOS transistor among a plurality of N NMOS transistors in each activated first voltage driver in the first voltage drivers, and the second clock signal is configured to cycle between (N-1)*Vdd and N*Vdd to drive a gate of an Nth PMOS transistor among a plurality of N PMOS transistors in each activated first voltage driver in the first voltage drivers; and a voltage summing circuit coupled to each output node and configured to sum the output voltages at each output node.

[0005] In addition, an operating method of a high voltage driver is provided, the operating method comprising: during a first clock phase of a clock signal, disconnecting a plurality of N PMOS transistors arranged in series in a first sequence by charging the gate of each PMOS transistor in a first sequence from a first PMOS transistor coupled to an output node to an Nth PMOS transistor coupled to a power supply node to the product of a power supply voltage (Vdd) and the order of the PMOS transistors in the first sequence, wherein N is an integer of 3 or greater and wherein the power supply node is charged to N*Vdd; and grounding the output node by turning on a plurality of N NMOS transistors arranged in series in a second sequence by charging the gate of each NMOS transistor in a second sequence from a first NMOS transistor coupled to a ground to an Nth NMOS transistor coupled to the output node to Vdd during the first clock phase.

[0006] Finally, a voltage driver is provided, which includes: a plurality of PMOS transistors arranged in series from a first PMOS transistor to an Nth PMOS transistor, wherein the first PMOS transistor has a drain coupled to an output node and the Nth PMOS transistor has a source coupled to a power supply node, wherein N is an integer of 3 or greater than 3; a plurality of NMOS transistors arranged in series from a first NMOS transistor to an Nth NMOS transistor, wherein the first NMOS transistor has a source coupled to a ground and the Nth NMOS transistor has a drain coupled to the output node; a first multiplexer configured to select between a first power supply voltage and a second power supply voltage to drive a gate of the first PMOS transistor; and a second multiplexer configured to select between the first power supply voltage and the second power supply voltage to drive a gate of the Nth NMOS transistor.

[0007] These and other advantageous features will be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit diagram of a high voltage driver according to one aspect of the present disclosure.

[0009] Figure 2 According to one aspect of the present disclosure, the NMOS stack and the PMOS stack each have three transistors. Figure 1 A circuit diagram of a specific implementation of a high voltage driver.

[0010] Figure 3A According to one aspect of the present disclosure Figure 2 0026] A circuit diagram of a high voltage driver of FIG. 1 showing gate voltages of an NMOS stack and a PMOS stack during a first clock phase and also showing a gate voltage of a sleep circuit.

[0011] Figure 3B According to one aspect of the present disclosure Figure 2 0026] A circuit diagram of a high voltage driver of FIG. 10, showing the gate voltages of the NMOS stack and the PMOS stack during the second clock phase and also showing the gate voltage of the sleep circuit.

[0012] Figure 3C According to one aspect of the present disclosure Figure 2 0014] A circuit diagram of a high voltage driver of FIG. 10, which shows gate voltages of an NMOS stack and a PMOS stack during a sleep mode of the high voltage driver and also shows a gate voltage of a sleep circuit.

[0013] Figure 4According to one aspect of the present disclosure, the NMOS stack and the PMOS stack each have four transistors. Figure 1 A circuit diagram of a specific implementation of a high voltage driver.

[0014] Figure 5 is a circuit diagram of a transmitter including a plurality of high voltage drivers according to an aspect of the present disclosure.

[0015] Figure 6 is a flow chart of an example high voltage driver operating method according to an aspect of the present disclosure.

[0016] Embodiments of the present disclosure and their advantages may be best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures in the drawings. DETAILED DESCRIPTION

[0017] To improve efficiency, power amplifiers for high frequency applications are typically constructed using III-V semiconductors such as gallium nitride (GaN). However, the digital and baseband portions of wireless devices are typically constructed using silicon-based technologies such as complementary metal oxide semiconductors (CMOS). Therefore, a wireless device such as a cell phone or WiFi station will require one or more integrated circuits for the CMOS portion and a separate GaN-based integrated circuit for the power amplifier. Such use of separate integrated circuits increases manufacturing cost and complexity. Therefore, it would be advantageous if the transceiver could be implemented in a single CMOS-based integrated circuit. However, such integration has limitations in delivering high output power. For example, an output power of 35 dBm requires a peak-to-peak signal voltage of approximately 35.6 volts at the transmit antenna. However, CMOS transistors at modern process nodes use relatively low supply voltages, such as 1 volt or less. Therefore, using a CMOS-based power amplifier typically requires the use of a set transformer. For example, a CMOS-based transistor that can accommodate a 1 volt supply voltage may be able to output a 1 volt peak-to-peak sinusoidal output signal. Then, a setting transformer with a 1:35 turns ratio can set this relatively low output signal to the desired 35 volt peak-to-peak signal to drive the antenna. But integrating a transformer with so many turns into an integrated circuit is cumbersome, requires a large area, and results in significant power losses during operation.

[0018] In some modern process nodes, when the supply voltage is limited to 1V or less than 1V, the transistor can only generate a peak-to-peak output voltage (Vpp) that is also limited to 1 volt or less than 1 volt. Therefore, in order to provide a larger peak-to-peak output voltage, the power amplifier can stack the transistors. For example, a common-gate transistor stack power amplifier uses a series stack of transistors each having a common-gate configuration. If the stack has four transistors in series, the peak-to-peak output voltage Vpp can be about 4 times Vdd. When the output voltage rises and falls, the gate voltage of the transistors in the stack must also rise and fall sufficiently to limit the gate-source / drain voltage of each transistor in the stack to not exceed the supply voltage Vdd. Therefore, the gate voltage of each transistor in the stack must fully follow the drain / source voltage (within the difference of Vdd) to prevent transistor damage or strain. In a common-gate configuration, this voltage following at the gate of each transistor in the stack can be implemented by a capacitive voltage divider formed by a corresponding gate capacitor coupled to the gate of the transistor. This gate capacitor combines with the parasitic gate-source / drain capacitance of the transistor to form a capacitive voltage divider. When increasing the stack height to increase the peak-to-peak output voltage, the capacitance of each gate capacitor needs to be reduced to achieve the desired voltage following. It is difficult to implement such relatively small gate capacitors, which limits the achievable stack height. In addition, the capacitive voltage divider can distort the output signal. More generally, the common-gate configuration is an example of a transistor stack-based amplifier architecture in which voltage following is controlled in an analog manner.

[0019] In order to provide high output power without the specific implementation issues and distortions of analog approaches, a high voltage driver for a digital power amplifier is disclosed. Figure 1 An example high voltage driver 100 is shown in FIG. 1 . In the high voltage driver 100, a series stack 105 of p-type metal oxide semiconductor (PMOS) transistors is coupled between a supply voltage node and an output node 115 of an output signal. A series stack 110 of n-type metal oxide semiconductor (NMOS) transistors is coupled between the output node 115 and ground. Each of the NMOS stack and the PMOS stack includes a plurality of N transistors, where N is a complex positive integer. The NMOS stack 110 ranges from a first NMOS transistor M1 having a source coupled to ground to an Nth NMOS transistor MN having a drain coupled to the output node 115. All remaining transistors in the NMOS stack 110 are coupled in series between the drain of the first NMOS transistor M1 and the source of the Nth NMOS transistor MN. A first clock source 130 generates a first clock signal DN that drives the gate of the first NMOS transistor M1. In a first clock phase, the first clock signal DN is grounded, and in a second clock phase, the first clock signal DN is charged to a supply voltage Vdd.

[0020] The PMOS stack 105 includes an Nth PMOS transistor PN having a source coupled to a power supply node 125, which is charged to N*Vdd. The first PMOS transistor P1 in the PMOS stack 105 has a drain coupled to an output node 115. All remaining transistors in the PMOS stack 105 are coupled in series between the drain of the Nth PMOS transistor PN and the source of the first PMOS transistor P1. In the following discussion, it will be assumed that N is at least 3. If N is equal to 3, the power supply node is therefore charged to 3*Vdd. Similarly, if N is equal to four, the power supply node is charged to 4*Vdd, and so on. The second clock source 135 generates a clock signal DP that drives the gate of the NPMOS transistor PN. The second clock signal DP cycles at the same frequency as the first clock signal. In the first clock phase in which the first clock signal DN is charged to the power supply voltage Vdd, the second clock signal is charged to N*Vdd. As will be further explained herein, during the first clock phase, the output node 115 is discharged to ground, and during the second clock phase, the output node is charged to N*Vdd. In the second clock phase, when the first clock signal DN is discharged to ground, the second clock signal DP decreases to a voltage of (N-1)*Vdd.

[0021] The NMOS stack 110 and the PMOS stack 105 have complementary characteristics with respect to the first clock phase and the second clock phase. During the first clock phase, the NMOS stack 110 is turned on, while the PMOS stack 105 is turned off. Conversely, during the second clock phase, the NMOS stack 110 is turned off, while the PMOS stack 105 is turned on. Since the PMOS stack 105 has N transistors arranged in series, its transistors can be considered to be indexed or numbered in order from the first PMOS transistor P1 coupled to the output node 115 at the drain to the Nth PMOS transistor PN coupled to the source at the power supply node. The NPMOS transistor PN has a drain coupled to the source of the (N-1)th PMOS transistor (not illustrated), and so on, so that the second PMOS transistor (not illustrated) in the PMOS stack 105 has a drain coupled to the source of the first PMOS transistor P1. Similarly, the NMOS stack 110 has N transistors arranged in series such that its transistors may be considered indexed or numbered starting from the first NMOS transistor M1 and extending to the NMOS transistor MN having a drain coupled to the output node 115. The first NMOS transistor M1 has a drain coupled to the source of the second NMOS transistor (not illustrated) and so on, such that the (N-1)th NMOS transistor (not illustrated) has a drain coupled to the source of the N-th NMOS transistor MN.

[0022] The conducting characteristics versus non-conducting characteristics of the NMOS stack and the PMOS stack will now be discussed in more detail. Note that the output voltage at the output node 115 has a known state in both the first clock phase and the second clock phase. This is very advantageous because the voltage bias circuit 120 can then control the gate voltage of the second transistor to the Nth transistor in the NMOS stack 110 and correspondingly control the gate voltage of the first transistor to the (N-1)th transistor in the PMOS stack 105 to provide an appropriate amount of voltage following for their gate voltages so that the transistors in either stack are protected from excessive voltage or strain when the transistors are turned on or off. For example, the transistors in the PMOS stack 105 should be non-conducting (all of its transistors are turned off) during the first clock phase so that there is no conduction from the power supply node 125 through the PMOS stack 105 to the output node 115. Note that the transistors in the PMOS stack 105 can all be considered to be indexed or numbered consecutively starting from the first transistor P1. During the first clock phase, the bias voltage circuit 120 may bias the first transistor P1 to the (N-1)th transistor in the PMOS stack 105 according to the order in the stack. For example, during the first clock phase, the drain of transistor P1 is grounded. Therefore, during the first clock phase, the bias voltage circuit 120 may charge the gate of transistor P1 to the supply voltage Vdd. Therefore, during the first clock phase, the gate-drain voltage of transistor P1 is maintained at a safe level of Vdd. In order to maintain this same safe amount of gate-drain voltage difference from the second transistor to the (N-1)th transistor in the PMOS stack 105, the bias voltage circuit 120 applies a continuously higher multiple of the supply voltage to each consecutive transistor during the first clock phase. For example, the bias voltage circuit 120 may drive a second PMOS transistor (not illustrated) using a gate voltage of 2*Vdd during the first clock phase. Although the drain voltage of this second PMOS transistor is unclear due to the non-conducting state of the PMOS stack 105, the gate-drain voltage difference of the second PMOS transistor will not exceed the safe level of Vdd. Similarly, the bias voltage circuit 120 can drive the third PMOS transistor (not illustrated) with a gate voltage of 3*Vdd during the first clock phase, and so on, so that the gate voltage of the (N-1)th PMOS transistor (not illustrated) is charged to (N-1)*Vd. The Nth PMOS transistor PN is turned off during the first clock phase because the second clock signal DP charges the gate of the transistor PN with N*Vdd during the first clock phase. Therefore, it can be seen that during the first clock phase, the gate-drain and gate-source voltage differences on each transistor in the PMOS stack 105 do not exceed the supply voltage Vdd. In addition, it can be seen that the gate of each transistor in the PMOS stack 105 is charged to the product of Vdd and the order of the transistor in the PMOS stack 105.

[0023] The NMOS stack 110 should be turned on during the first clock phase so that the output node 115 is discharged to ground. Since the first clock signal DN charges the gate of the first transistor M1 to the supply voltage Vdd, the first transistor M1 is turned on during the first clock phase. Similarly, the bias voltage circuit 120 charges the gates of the remaining second NMOS transistors to the Nth NMOS transistor MN to the supply voltage Vdd so that these transistors are also turned on during the first clock phase. Therefore, during the first clock phase, the gate-source voltage difference and the gate-drain voltage difference of each transistor in the NMOS stack 110 do not exceed the supply voltage Vdd.

[0024] In the second clock phase, the PMOS stack 105 is turned on so that the output node 115 can be charged to N*Vdd. At the beginning of the second clock phase, the second clock signal DP drops to (N-1)*Vdd, so that the Nth PMOS transistor PN is turned on. Similarly, the bias voltage circuit 120 charges the gates of the first PMOS transistor P1 to the (N-1)th transistor to (N-1)*Vdd, so that these transistors are also turned on. Therefore, during the second clock phase, the gate-source voltage difference and the gate-drain voltage difference of each transistor in the PMOS stack 105 do not exceed the supply voltage Vdd.

[0025] During the second clock phase, the transistors in the NMOS stack 110 are disconnected so that the output node 115 can still be charged to N*Vdd. In order to provide sufficient voltage following for the gate, the gate of each transistor in the NMOS stack 110 is charged to the product of its index or order within the NMOS stack minus 1 and the supply voltage Vdd. For example, the bias voltage circuit 120 charges the gate of the Nth transistor MN to (N-1)*Vdd. Similarly, the bias voltage circuit 120 charges the gate of the (N-1)th NMOS transistor (not illustrated) to (N-2)*Vdd and so on, so that the gate of the second NMOS transistor (not illustrated) is charged to Vdd. During the second clock phase, the first clock signal DN grounds the gate of the first NMOS transistor M1, so that this transistor is also disconnected. Therefore, during the second clock phase, the gate-source voltage difference and the gate-drain voltage difference of each of the transistors in the NMOS stack 110 do not exceed Vdd.

[0026] Compared to analog approaches (such as the common gate stack architecture discussed previously), the high voltage driver 100 can easily control the gate voltages of the NMOS transistors and the PMOS transistors so that an appropriate amount of voltage following is achieved at the transistor gates despite the relatively high (N*Vdd) Vpp of the output signal at the output node 115. Some example implementations of the high voltage driver will now be discussed. Figure 2100. A high voltage driver 200 is shown in which PMOS stack 105 and NMOS stack 110 each have three transistors. Therefore, power supply node 125 supports a power supply voltage of 3*Vdd. When PMOS stack 105 is turned on and NMOS stack 110 is not turned on during the second clock phase, output node 115 is therefore driven to 3*Vdd. Similarly, when NMOS stack 110 is turned on and PMOS stack 105 is not turned on during the first clock phase, output node 115 discharges. Therefore, the output signal at output node 115 will have a peak-to-peak voltage of 3*Vdd. PMOS stack 105 includes a transistor P1 having a source coupled to the drain of PMOS transistor P2. The source of transistor P2 is connected to the drain of PMOS transistor P3. Then, the source of transistor P3 is connected to power supply node 125. Therefore, transistor P3 is equivalent to transistor PN in high voltage driver 100.

[0027] The NMOS stack 110 includes a transistor M1 having a source coupled to ground and a drain coupled to a source of an NMOS transistor M2. The drain of the transistor M2 is connected to a source of an NMOS transistor M3 having a drain coupled to the output node 115. Therefore, the transistor M3 is equivalent to the transistor MN in the high voltage driver 100.

[0028] The clock signal DN drives the gate of transistor M1 and circulates between Vdd in the first clock phase and 0V in the second clock phase. The clock signal DP drives the gate of transistor P3 and circulates between 3*Vdd in the first clock phase and 2*Vdd in the second clock phase. The voltage bias circuit of high voltage driver 200 includes a 2Vdd voltage source that drives the gate of transistor P2. This gate voltage is constant regardless of whether the clock is in the first clock phase or the second clock phase. Similarly, the Vdd voltage source drives the gate of transistor M2 in both the first clock phase and the second clock phase. The voltage bias circuit of high voltage driver 200 also includes a first multiplexer 205, which selects between the 2*Vdd voltage source and the Vdd voltage source to drive the gate of transistor P1. The first multiplexer 205 is configured to select Vdd during the first clock phase and select 2*Vdd during the second clock phase. The voltage bias circuit of the high voltage driver 200 also includes a second multiplexer 215 that selects between the 2*Vdd voltage source and the Vdd voltage source to drive the gate of the transistor M3. The multiplexer 215 is similar to the multiplexer 205 in that the multiplexer 215 is configured to select Vdd during the first clock phase and select 2*Vdd during the second clock phase.

[0029] As will be further explained herein, a power amplifier may include multiple drivers, such as a high voltage driver 200. Depending on whether a given driver is active or inactive, a combined output signal will be generated that is the sum of the output signals from the active drivers. In order to provide a consistent output impedance when a given driver is inactive (not generating a combined output signal), the high voltage driver 200 includes a sleep circuit 210, which may also be labeled a sleep switch. When the high voltage driver 200 is active and thus generating a combined output signal, the sleep circuit 210 is not conducting. However, when the high voltage driver is selected to be inactive and thus not generating a combined output signal, the sleep circuit 210 is conducting to charge the output node 115 to have a constant voltage, such as Vdd.

[0030] Figure 3A 2 shows in more detail the sleep circuit 210 in which the high voltage driver 200 is in the first clock phase. For the sake of illustration clarity, Figure 3AMultiplexers 205 and 215 are not shown in FIG. As previously noted, during the first clock phase, the transistors in the PMOS stack are biased according to the product of the order of the transistors in the PMOS stack and Vdd, so that the PMOS stack is non-conductive. Since the index or order of transistor P1 is 1, its gate voltage is Vdd. Similarly, transistor P2 is the second transistor in the PMOS stack, so its gate voltage is 2*Vdd. Finally, during the first clock phase, the clock signal DP is charged to 3*Vdd, so the gate voltage of transistor P3 is also the product of the order of the transistors in the PMOS stack and Vdd. The gate-source voltage of transistor P3 is zero, so it is disconnected. Thus, the drain voltage of transistor P3 is uncertain, but since the gate voltage of transistor P2 is 2*Vdd, the drain voltage of transistor P3 cannot drop below 2*Vdd. Similarly, the drain voltage of transistor P2 is indeterminate, but since the gate voltage of transistor P1 is Vdd, the drain voltage of transistor P2 will not drop below Vdd. Therefore, during the first clock phase, transistors P1 to P3 will all be turned off, with the gate-source voltage difference and the gate-drain voltage difference not exceeding Vdd. More generally, there are N transistors in the PMOS stack, ranging from the first PMOS transistor P1 with the drain coupled to the output node 115 to the Nth transistor with the source coupled to the supply node 125. During the first clock phase, the bias voltage circuit charges the gate of transistor P1 to Vdd, the gate of transistor P2 to 2*Vdd, and so on, so that the gate of the Nth PMOS transistor is charged to N*Vdd. As such, each PMOS transistor is turned off during the first clock phase and its gate voltage has an appropriate voltage following amount to protect the PMOS transistor from being exposed to a gate-source voltage difference or a gate-drain voltage difference exceeding Vdd, thereby ensuring robustness against transistor strain or damage despite the high voltage N*Vdd at the supply node 125.

[0031] During the first clock phase, transistors M1 to M3 in the NMOS stack are all turned on, so that the output node 115 is grounded. During the first clock phase, the clock signal DN is charged to Vdd, which turns on transistor M1. The gate voltage of transistors M2 and M3 is also Vdd, so that these transistors are also turned on. Therefore, during the first clock phase, the gate-source voltage difference and the gate-drain voltage difference of transistors M1 to M3 will not exceed Vdd. More generally, there are N transistors in the NMOS stack, ranging from transistor M1 with a source coupled to ground to the Nth NMOS transistor with a drain coupled to the output node 115. During the first clock phase, the bias voltage circuit charges the gates of the second NMOS transistor to the Nth NMOS transistor to Vdd, and the DP clock signal charges the gate of the first NMOS transistor to Vdd. Therefore, during the first clock phase, the NMOS stack is turned on and discharges the output node 115 to ground.

[0032] The sleep circuit 210 may be implemented by a series coupling of an NMOS transistor M5, a PMOS transistor P4, and an NMOS transistor M4. The transistor M5 has a drain coupled to a power supply of Vdd. The source of the transistor M5 is connected to the source of the transistor P4. The drain of the transistor P4 is connected to the drain of the transistor M4, which in turn has a source coupled to the output node 115. A suitable controller (such as a voltage bias circuit ( Figure 3A The sleep circuit 210 (not shown) charges the gate of transistor M5 to Vdd, so that transistor M5. With both its gate and source charged to Vdd, the gate-source voltage of transistor M5 is therefore 0V, so that transistor M5 is turned off. Similarly, during the first clock phase, the voltage bias circuit charges the gate of transistor P4 to Vdd, so that transistor P4 is also turned off. Although transistor M4 is turned on during the first clock phase due to the voltage bias circuit charging its gate to Vdd, since transistors P4 and M5 are turned off, the sleep circuit 210 does not affect the voltage of the output node 115.

[0033] Figure 3B The gate voltage of the transistor in the high voltage driver 200 during the second clock phase is shown in FIG. Figure 3A Likewise, multiplexers 205 and 215 are not shown for clarity of illustration. Figure 3AThe gate voltages of transistors M5 and P4 in the sleep circuit 210 are discussed. Since the output voltage is now 3Vdd, the gate voltage of transistor M4 is increased to 2Vdd to protect transistor M4 from excessive voltage stress. Therefore, the sleep circuit 210 is in a non-conducting state during both the first clock phase and the second clock phase. The gate of each transistor in the PMOS stack is biased to 2*Vdd. Therefore, each transistor in the PMOS stack is turned on, so that the output node 115 is charged to 3*Vdd. Therefore, during the second clock phase, the gate-source voltage difference and the gate-drain voltage difference of each PMOS transistor do not exceed Vdd. In order to make the NMOS stack non-conducting during the second clock phase, the gate of each NMOS transistor is biased to the product of the order of the NMOS transistor in the NMOS stack minus 1 and Vdd. For example, the gate of transistor M3 is biased to 2*Vdd. Similarly, the gate of transistor M2 is biased to Vdd. Finally, the gate of transistor M1 is grounded. Therefore, during the second clock phase, the gate-source voltage difference and the gate-drain voltage difference of each NMOS transistor do not exceed Vdd.

[0034] If the high voltage driver is inactive and therefore not used to generate an output signal to drive the antenna, the sleep circuit 210 is turned on, such as Figure 3C As shown in . Since the high voltage driver is inactive, both the PMOS stack and the NMOS stack are turned off. Therefore, during the first clock phase, the gate voltage of the PMOS transistor is as shown in FIG. Figure 3A As discussed above. The gate voltage of transistor M1 is 0V, while the gates of transistors M2 and M3 are charged to Vdd. Therefore, transistor M1 is disconnected and the NMOS stack is made non-conductive. Therefore, during the sleep mode of operation, the output node 115 is floating relative to the PMOS and NMOS stacks. In order to force the sleep circuit 210 to turn on, the bias voltage circuit (or another suitable bias voltage source) charges the gate of transistor M5 to 2Vdd. Therefore, transistor M5 is fully turned on and its source is charged to Vdd. The bias voltage circuit also grounds the gate of transistor P4, so that transistor P4 is also fully turned on to charge its drain to Vdd. Finally, the bias voltage circuit charges the gate of transistor M4 to 2Vdd, so that transistor M4 is fully turned on and the output node 115 is charged to Vdd.

[0035] Figure 4105 and NMOS stack 110 each have an example high voltage driver 400 of four transistors. Therefore, the power supply node 125 supports a power supply voltage of 4*Vdd. When the PMOS stack 105 is turned on and the NMOS stack 110 is not turned on during the second clock phase, the output node 115 is therefore driven to 4*Vdd. Similarly, during the first clock phase when the NMOS stack 110 is turned on and the PMOS stack 105 is not turned on, the output node 115 discharges. Therefore, the output signal at the output node 115 will have a 4*Vdd peak-to-peak voltage.

[0036] The PMOS stack 105 includes transistors P1, P2, P3 and also includes a transistor P4. The source of transistor P4 is coupled to the power supply node 125, and the drain of transistor P4 is coupled to the source of transistor P3. The second clock source 135 drives the gate of transistor P4 using a DP clock signal, which oscillates between 4Vdd in the first clock phase and 3Vdd in the second clock phase. The bias voltage circuit includes a multiplexer 410 for controlling the gate voltage of transistor P1 and a multiplexer 405 for controlling the gate voltage of transistor P2. As previously discussed, the bias voltage circuit functions so that the gates of the transistors in the PMOS stack 105 are charged to the product of their index and Vdd during the first clock phase. Therefore, the multiplexer 410 is configured to select Vdd during the first clock phase to charge the gate of transistor P1. Similarly, the multiplexer 405 selects 2Vdd during the first clock phase to charge the gate of transistor P2. In both clock phases, the gate of transistor P3 is charged to 3 Vdd. Therefore, during the first clock phase, the transistors in PMOS stack 105 are turned off and are not exposed to excessive voltage stress.

[0037] In the second clock phase, the DP clock signal drops to 3VDD, causing transistor P4 to turn on. Similarly, multiplexers 405 and 410 also select 3VDD to charge the gates of their corresponding transistors during the second clock phase. Therefore, the PMOS stack 105 is turned on in the second clock phase, so that the output voltage Vout is charged to 4VDD without exposing the transistors in the PMOS stack 105 to excessive voltage stress.

[0038] The NMOS stack 110 includes transistors M1, M2, M3 and also includes a transistor M4, the drain of which is coupled to the output node 115 and the source is coupled to the drain of the transistor M3. The first clock source 130 drives the gate of the transistor M1 using a first clock signal DN, which oscillates between Vdd during the first clock phase and zero volts during the second clock phase. During both clock phases, the gate voltage of the transistor M2 is maintained at Vdd. The multiplexer 415 selects Vdd during the first clock phase to turn on the transistor M4. Similarly, the multiplexer 420 selects Vdd during the first clock phase to turn on the transistor M3. Therefore, the NMOS stack 110 is turned on during the first clock phase to ground the output voltage Vout without causing any excessive voltage stress on its transistors.

[0039] During the second clock phase, the DN clock signal is zero volts to turn off transistor M1. During the second clock phase, the gate voltage of each of transistors M2 to M4 in the NMOS stack 110 is charged to the product of its index minus 1 and Vdd. Therefore, the multiplexer 415 selects 3Vdd during the second clock phase to charge the gate of transistor M4. Similarly, the multiplexer 420 selects 2Vdd during the second clock phase. Therefore, during the second clock phase, the transistors in the NMOS stack 110 are all turned off without any excessive voltage strain. The sleep switch 210 functions as discussed with reference to the high voltage driver 200.

[0040] By comparing high voltage driver 200 with high voltage driver 400, it can be seen that the multiplexer that drives the gate of transistor P1 selects between the first supply voltage and the second supply voltage. For multiplexer 205, the first supply voltage is 2Vdd and the second supply voltage is Vdd. For multiplexer 410, the first supply voltage is 3Vdd and the second supply voltage is Vdd. Therefore, multiplexers 205 and 410 are examples of first multiplexers that are configured to select between the first supply voltage and the second supply voltage to drive the gate of the first PMOS transistor. With respect to driving the gate of the Nth NMOS transistor (transistor M3 of high voltage driver 200 and transistor M4 of high voltage driver 200), multiplexers 215 and 415 perform this same selection. Thus, multiplexers 215 and 415 are examples of a second multiplexer configured to select between the first supply voltage and the second supply voltage to drive the gate of the Nth NMOS transistor.

[0041] An example transmitter including multiple high voltage drivers will now be discussed. Figure 5, an example transmitter 500 including first M high voltage drivers 505 and second M high voltage drivers 510 is shown, where M is a complex positive integer. The following discussion will assume that M is 64 without loss of generality, such that lower or higher values ​​of M may be used in alternative implementations. Each high voltage driver 505 and 510 may be constructed as discussed with reference to the high voltage driver 100. In one implementation, each high voltage driver 505 and 510 is constructed as discussed with reference to the high voltage driver 200. The output node of each high voltage driver 505 is coupled to a corresponding capacitor Cp. If there are 64 high voltage drivers 505, then there will be 64 capacitors Cp. The multiple capacitors Cp form an example of a voltage summing circuit that sums the output voltages from each high voltage driver 505. Each capacitor Cp is coupled between the output node of its corresponding high voltage driver 505 and the output coil L s The input coil L of the transformer 520 p Between the Vtop_p terminals. Output coil L s The output node of each high voltage driver 510 is coupled to an antenna 525 (or multiple antennas) represented by a 50 ohm resistor. The output node of each high voltage driver 510 is coupled to a corresponding capacitor Cm. If there are 64 high voltage drivers 510, then there will be 64 capacitors Cm. The multiple capacitors Cm are an example of a voltage summing circuit that sums the output voltages from the high voltage drivers 510. Each capacitor Cm is coupled between the output node of its corresponding high voltage driver 510 and the input coil L p The capacitance of each capacitor Cm may be equal to the capacitance of each capacitor Cp.

[0042] Since the clock signals Dp and Dn (not illustrated) of each high voltage driver 505 are synchronized, they can be represented by a single clock signal Din. The decoder 515 generates Din based on the complex digital baseband signal. In response to the phase of the complex baseband signal, the decoder 515 adjusts the clock signal Din accordingly. The decoder 515 also generates a supplementary clock Din_n that is a complement (180 degrees inverted) of Din. Like the clock Din, the supplementary clock Din_n is only a representation of two synchronous clock signals that control the gates of the equivalents of transistors PN and M1 in each of the high voltage drivers 510. Due to their complementary phases, the high voltage drivers 505 and 510 drive the input coil L in a differential manner. p .

[0043] In addition to its phase, the complex baseband signal also has a magnitude. Based on this magnitude, the decoder 515 activates or cancels the appropriate number of high voltage drivers 505 and 510. For example, if the complex baseband signal has a maximum magnitude, the decoder 515 can activate the entire M high voltage drivers 505 and 510. When the complex baseband signal magnitude decreases from this maximum value, the decoder 515 can cancel the corresponding number of high voltage drivers 505 and the same number of high voltage drivers 510. This is advantageous in terms of efficiency because modern communication protocols (such as WiFi or the fifth generation cellular standard) generally have a relatively high peak-to-average power ratio. During the average power moment, the transmitter 500 can therefore save power by activating only a portion of the M high voltage drivers 505 and the same portion of the M high voltage drivers 510. But during the peak power moment, the transmitter 500 can activate all M high voltage drivers 505 and all M high voltage drivers 510.

[0044] Assume that Vdd is 1.3V and each high voltage driver 505 and 510 is constructed as discussed with reference to high voltage driver 200 (N=3). Therefore, the output node of each high voltage driver 505 can cycle between ground and 3.9V. If all 64 high voltage drivers 505 are activated, the Vtop_p terminal of the input coil Ls is charged to approximately 3.9V during the second clock phase of Din. Since the high voltage driver 510 is used to charge the opposite terminal Vtop_m of the input coil Ls, the terminal Vtop_m is charged to -3.9V during the first clock phase of Din. Therefore, this relatively high output voltage swing does not require a robust setting transformer to drive the corresponding antenna. In one specific implementation, the transformer 520 can therefore have a relatively low turns ratio of 1:1.25. This relatively low turns ratio simplifies the manufacture of the transformer 520 because it can be easily implemented in the metal layer of the integrated circuit including the transformer 500. In addition, the relatively low turns ratio of the transformer 520 reduces power losses. Thus, transmitter 500 can provide a robust peak-to-peak output voltage at the antenna it drives, yet is fully compatible with CMOS process nodes.

[0045] In certain aspects, the high voltage drivers described herein may form part of a circuit that forms a digital-to-analog (DAC) converter that is configured to output a radio frequency (RF) modulated signal (e.g., forming part of an "RF-DAC" based transmitter architecture, where ... Figure 5 The transmitter circuitry 500 described may effectively function as a combined DAC, up-conversion mixer, and power amplifier).

[0046] Now about Figure 6The flowchart of discusses a method of operation of a high voltage driver. The method includes action 600 occurring during a first clock phase of a clock signal and includes disconnecting N PMOS transistors arranged in series in a first sequence from a first PMOS transistor coupled to the output node to an Nth PMOS transistor coupled to a supply node by charging the gate of each PMOS transistor in a first sequence from a first PMOS transistor coupled to the output node to the product of a supply voltage (Vdd) and the order of the PMOS transistor in the first sequence, wherein N is an integer of 3 or greater and wherein the supply node is charged to N*Vdd. An example of a first sequence of PMOS transistors is Figure 3A A PMOS stack is formed. Each PMOS transistor has an order in this first order. For example, transistor P1 is first in this order. Transistor P2 is second. Finally, transistor P3 is third. The gate of each PMOS transistor is charged to the product of Vdd and its order. For example, the gate of transistor P1 is charged to Vdd, the gate of transistor P2 is charged to 2*Vdd, and the gate of transistor P3 is charged to 3*Vdd.

[0047] The method further includes an act 605 of grounding the output node by turning on the N NMOS transistors arranged in series in a second order from a first NMOS transistor coupled to ground to an Nth NMOS transistor coupled to the output node during the first clock phase. An example of act 605 is to ground the output node. Figure 3A The gate of each NMOS transistor in the NMOS stack is charged to Vdd.

[0048] The method also includes action 610 occurring during a second clock phase of the clock signal and including charging the output node to N*Vdd by turning on the N PMOS transistors by charging the gate of each PMOS transistor to (N-1)*Vdd. Figure 3B An example of action 610 where N is equal to 3 such that (N-1) is equal to 2 is shown in FIG. Figure 3B As shown in , the gate of each PMOS transistor in the PMOS stack is therefore charged to 2*Vdd.

[0049] Finally, the method includes act 615 of turning off the N NMOS transistors during the second phase of the clock signal by charging the gate of each NMOS transistor in the second sequence to the product of Vdd and a difference between the order of the NMOS transistor in the second sequence and 1. Figure 3BAn example of action 615 is shown with reference to an NMOS stack. For example, the order of transistor M1 in the NMOS stack is of course 1, so that the difference between this order and 1 is zero. Therefore, the gate of transistor M1 is actually discharged during the second clock phase. Similarly, the order of transistor M2 in the NMOS stack is 2, so that the difference between this order and 1 is 1 accordingly. Therefore, the gate of transistor M2 is charged to Vdd*(2-1), i.e., Vdd. In addition, the order of transistor M3 is 3, so that the difference between this order and 1 is 2 accordingly. Therefore, the gate of transistor M3 is charged to Vdd*(3-1), i.e., 2*Vdd.

[0050] The present disclosure will now be summarized in a series of clauses:

[0051] Clause 1. A voltage driver, the voltage driver comprising:

[0052] a plurality of p-type metal oxide semiconductor (PMOS) transistors, the plurality of PMOS transistors being arranged in series from a first PMOS transistor to an (N-1)th PMOS transistor, wherein N is an integer of 3 or greater, and the first PMOS transistor having a drain connected to an output node of the voltage driver;

[0053] an Nth PMOS transistor having a source coupled to a supply voltage node and having a drain coupled to the source of the (N-1)th PMOS transistor;

[0054] a first n-type metal oxide semiconductor (NMOS) transistor having a source coupled to ground;

[0055] a plurality of NMOS transistors arranged in series from a second NMOS transistor to an Nth NMOS transistor, the Nth NMOS transistor having a drain coupled to the output node of the voltage driver and the second NMOS transistor having a source coupled to the drain of the first NMOS transistor;

[0056] a first clock source configured to drive a gate of the first NMOS transistor with a first clock signal that cycles between a supply voltage (Vdd) during a first clock phase and ground during a second clock phase; and

[0057] A second clock source configured to drive the gate of the Nth PMOS transistor with a second clock signal that cycles between N*Vdd during the first clock phase and (N-1)*Vdd during the second clock phase.

[0058] Clause 2. The voltage driver of clause 1, wherein the supply voltage node is configured to be charged to N*Vdd.

[0059] Clause 3. The voltage driver of any of clauses 1 to 2, wherein N is equal to 4.

[0060] Clause 4. The voltage driver according to any one of clauses 1 to 3, further comprising:

[0061] A bias voltage circuit is configured to charge a gate of each of the plurality of PMOS transistors to (N-1)*Vdd during the second clock phase.

[0062] Item 5. The voltage driver of Item 4, wherein the bias voltage circuit is further configured to charge a gate of each of the plurality of NMOS transistors to Vdd during the first clock phase.

[0063] Item 6. A voltage driver according to Item 4, wherein the bias voltage circuit is further configured to charge the gate of the first PMOS transistor to Vdd during the first clock phase, and to charge the gate of each consecutive PMOS transistor after the first PMOS transistor among the multiple PMOS transistors to the sum of Vdd and a gate voltage of a preceding PMOS transistor among the multiple PMOS transistors during the first clock phase.

[0064] Item 7. A voltage driver according to Item 4, wherein the bias voltage circuit is further configured to charge the gate of the second NMOS transistor to Vdd during the second clock phase, and to charge the gate of each consecutive NMOS transistor after the second NMOS transistor in the multiple NMOS transistors to the sum of Vdd and the gate voltage of the previous NMOS transistor in the multiple NMOS transistors during the second clock phase.

[0065] Clause 8. The voltage driver of any one of clauses 1 to 7, wherein N is equal to 3.

[0066] Item 9. The voltage driver of Item 8, wherein the bias voltage circuit comprises a first multiplexer configured to select between Vdd and 2*Vdd to drive the gate of the first PMOS transistor during the first clock phase and during the second clock phase.

[0067] Clause 10. The voltage driver of Clause 9, wherein the bias voltage circuit further comprises a second multiplexer configured to select between Vdd and 2*Vdd to drive the gate of the Nth NMOS transistor during the first clock phase and during the second clock phase.

[0068] Clause 11. The voltage driver of clause 3, further comprising:

[0069] A sleep circuit is coupled between a supply node of Vdd and the output node, wherein the sleep circuit is configured to be non-conductive during the first clock phase and during the second clock phase.

[0070] Item 12. A voltage driver according to Item 11, wherein the first clock source is configured to ground the gate of the first NMOS transistor during a sleep mode of the voltage driver, and wherein the second clock source is configured to charge the gate of the Nth PMOS transistor to N*Vdd during the sleep mode of the voltage driver.

[0071] Clause 13. The voltage driver of Clause 12, wherein the sleep circuit is configured to turn on during the sleep mode of the voltage driver to charge the output node to Vdd.

[0072] Clause 14. The voltage driver of Clause 12, wherein the sleep circuit comprises a plurality of transistors coupled between the supply node of Vdd and the output node.

[0073] Item 15. A voltage driver according to Item 14, wherein the plurality of transistors include an (N+1)th NMOS transistor having a source coupled to the output node, an (N+1)th PMOS transistor having a drain coupled to the drain of the (N+1)th NMOS transistor, and an (N+2)th NMOS transistor having a source coupled to the source of the (N+1)th PMOS transistor and a drain coupled to the power supply node of Vdd.

[0074] Clause 16. A power amplifier, the power amplifier comprising:

[0075] a plurality of first voltage drivers, each of the first voltage drivers comprising a plurality of N PMOS transistors coupled between a power supply node and an output node and comprising a plurality of N NMOS transistors coupled between the output node and ground, wherein N is a positive integer of 3 or greater;

[0076] a decoder configured to decode a baseband signal to select whether each first voltage driver is inactive or active based on a magnitude of the baseband signal and to phase a first clock signal and a second clock signal based on a phase of the baseband signal, wherein the first clock signal is configured to cycle between ground and a supply voltage (Vdd) to drive a gate of a first NMOS transistor of a plurality of N NMOS transistors in each activated voltage driver of the voltage drivers, and the second clock signal is configured to cycle between (N-1)*Vdd and N*Vdd to drive a gate of an Nth PMOS transistor of a plurality of N PMOS transistors in each activated voltage driver of the voltage drivers; and

[0077] A voltage summing circuit is coupled to each output node and is configured to sum the output voltages at each output node.

[0078] Item 17. A power amplifier according to Item 16, wherein the power amplifier is included in an integrated circuit having a transformer, the transformer comprising a first coil and a second coil, and wherein the voltage summing circuit comprises a plurality of N first capacitors, each first capacitor having a first terminal coupled to an output node of a corresponding first voltage driver in the first voltage driver and having a second terminal coupled to the first coil.

[0079] Clause 18. The power amplifier of clause 17, wherein the second coil is coupled to at least one antenna.

[0080] Clause 19. The power amplifier of clause 18, wherein each first capacitor is coupled to a first end of the first coil, the power amplifier further comprising:

[0081] a plurality of second voltage drivers; and

[0082] A plurality of second capacitors are provided, each second capacitor being coupled between an output node of a corresponding second voltage driver of the second voltage drivers and the second end of the first coil.

[0083] Clause 20. The power amplifier of Clause 19, wherein the decoder is further configured to select whether each second voltage driver is inactive or active based on the magnitude of the baseband signal.

[0084] Clause 21. A method of driving an output node by a voltage driver, the method comprising:

[0085] during a first clock phase of a clock signal, turning off a plurality of N PMOS transistors arranged in series in a first sequence from a first PMOS transistor coupled to the output node to an Nth PMOS transistor coupled to the power supply node by charging a gate of each PMOS transistor in a first sequence from a first PMOS transistor coupled to the output node to a product of a power supply voltage (Vdd) and an order of the PMOS transistors in the first sequence, wherein N is an integer of 3 or greater and wherein the output node is charged to N*Vdd; and

[0086] The output node is grounded by turning on a plurality of N NMOS transistors arranged in series in a second sequence from a first NMOS transistor coupled to ground to an Nth NMOS transistor coupled to the output node during the first clock phase by charging a gate of each NMOS transistor in the second sequence to Vdd.

[0087] Clause 22. The method according to clause 21, further comprising:

[0088] During a second clock phase of the clock signal; turning on the plurality of N PMOS transistors by charging the gate of each PMOS transistor to (N-1)*Vdd to charge the output node to N*Vdd; and

[0089] The plurality of N NMOS transistors are turned off during the second phase of the clock signal by charging the gate of each NMOS transistor in the second sequence to a product of Vdd and a difference between an order of the NMOS transistor in the second sequence and 1.

[0090] Clause 23. The method according to clause 22, further comprising:

[0091] During the first clock phase and the second clock phase, a sleep circuit coupled between the output node and a power supply of Vdd is disconnected.

[0092] Clause 24. The method according to clause 23, further comprising:

[0093] During a sleep mode of the voltage driver, the sleep circuit is turned on to charge the output node to Vdd.

[0094] Clause 25. A voltage driver, the voltage driver comprising:

[0095] a plurality of PMOS transistors arranged in series from a first PMOS transistor to an Nth PMOS transistor, wherein the first PMOS transistor has a drain coupled to an output node and the Nth PMOS transistor has a source coupled to a power supply node, wherein N is an integer of 3 or greater;

[0096] a plurality of NMOS transistors arranged in series from a first NMOS transistor to an Nth NMOS transistor, wherein the first NMOS transistor has a source coupled to ground and the Nth NMOS transistor has a drain coupled to the output node;

[0097] a first multiplexer configured to select between a first supply voltage and a second supply voltage to drive a gate of the first PMOS transistor; and

[0098] a second multiplexer configured to select between the first supply voltage and the second supply voltage to drive a gate of the Nth NMOS transistor.

[0099] Item 26. A voltage driver according to Item 25, wherein N is equal to 3 and the first supply voltage is equal to twice the second supply voltage, and wherein a second PMOS transistor of the plurality of PMOS transistors has a gate coupled to the first supply voltage and a second NMOS transistor of the plurality of NMOS transistors has a gate coupled to the second supply voltage.

[0100] Clause 27. A voltage driver according to clause 25, wherein N is equal to 4 and the first supply voltage is equal to three times the second supply voltage, and wherein a third PMOS transistor of the plurality of PMOS transistors has a gate coupled to the first supply voltage and a second NMOS transistor of the plurality of NMOS transistors has a gate coupled to the second supply voltage.

[0101] Clause 28. The voltage driver according to any one of clauses 25 to 27, further comprising:

[0102] A first clock source is configured to drive the first NMOS crystal

[0103] the grid of the tube; and

[0104] A second clock source is configured to drive a gate of the Nth PMOS transistor.

[0105] It should be understood that many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the equipment disclosed herein without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific embodiments illustrated and described herein (because they are only some examples of the present disclosure), but should be fully equivalent to the attached claims and their functional equivalents.

Claims

1. A voltage driver, comprising: a plurality of p-type metal oxide semiconductor (PMOS) transistors, the plurality of p-type metal oxide semiconductor (PMOS) transistors being arranged in series from a first PMOS transistor to an (N-1)th PMOS transistor, wherein N is an integer of 3 or greater, and the first PMOS transistor having a drain coupled to an output node of the voltage driver; an Nth PMOS transistor having a source coupled to a supply voltage node and having a drain coupled to the source of the (N-1)th PMOS transistor; a first n-type metal oxide semiconductor (NMOS) transistor having a source coupled to ground; a plurality of NMOS transistors arranged in series from a second NMOS transistor to an Nth NMOS transistor, the Nth NMOS transistor having a drain coupled to the output node of the voltage driver and the second NMOS transistor having a source coupled to the drain of the first NMOS transistor; a first clock source configured to drive a gate of the first NMOS transistor with a first clock signal that cycles between a supply voltage (Vdd) during a first clock phase and ground during a second clock phase; and A second clock source configured to drive the gate of the Nth PMOS transistor with a second clock signal that cycles between N*Vdd during the first clock phase and (N-1)*Vdd during the second clock phase. 2 . The voltage driver of claim 1 , wherein the supply voltage node is configured to be charged to N*Vdd.

3. The voltage driver according to claim 2, wherein N is equal to 4.

4. The voltage driver according to claim 2, further comprising: A bias voltage circuit is configured to charge a gate of each of the plurality of PMOS transistors to (N-1)*Vdd during the second clock phase. 5 . The voltage driver of claim 4 , wherein the bias voltage circuit is further configured to charge a gate of each of a plurality of NMOS transistors to Vdd during the first clock phase.

6. The voltage driver of claim 4 , wherein the bias voltage circuit is further configured to charge the gate of the first PMOS transistor to Vdd during the first clock phase, and to charge the gate of each consecutive PMOS transistor after the first PMOS transistor among the plurality of PMOS transistors to a sum of Vdd and a gate voltage of a preceding PMOS transistor among the plurality of PMOS transistors during the first clock phase.

7. The voltage driver of claim 4 , wherein the bias voltage circuit is further configured to charge the gate of the second NMOS transistor to Vdd during the second clock phase, and to charge the gate of each consecutive NMOS transistor after the second NMOS transistor among the plurality of NMOS transistors to a sum of Vdd and a gate voltage of a preceding NMOS transistor among the plurality of NMOS transistors during the second clock phase. The voltage driver according to claim 4 , wherein N is equal to 3.

9. The voltage driver of claim 8, wherein the bias voltage circuit comprises a first multiplexer configured to select between Vdd and 2*Vdd to drive the gate of the first PMOS transistor during the first clock phase and during the second clock phase.

10. The voltage driver of claim 9, wherein the bias voltage circuit further comprises a second multiplexer configured to select between Vdd and 2*Vdd to drive the gate of the Nth NMOS transistor during the first clock phase and during the second clock phase.

11. The voltage driver according to claim 2, further comprising: A sleep circuit is coupled between a supply node of Vdd and the output node, wherein the sleep circuit is configured to be non-conductive during the first clock phase and during the second clock phase.

12. The voltage driver of claim 11 , wherein the first clock source is configured to ground the gate of the first NMOS transistor during a sleep mode of the voltage driver, and wherein the second clock source is configured to charge the gate of the Nth PMOS transistor to N*Vdd during the sleep mode of the voltage driver. 13 . The voltage driver of claim 12 , wherein the sleep circuit is configured to be turned on during the sleep mode of the voltage driver to charge the output node to Vdd.

14. The voltage driver of claim 12, wherein the sleep circuit comprises a plurality of transistors coupled between the supply node of Vdd and the output node.

15. The voltage driver according to claim 14, wherein the plurality of transistors include an (N+1)th NMOS transistor having a source coupled to the output node, an (N+1)th PMOS transistor having a drain coupled to the drain of the (N+1)th NMOS transistor, and an (N+2)th NMOS transistor having a source coupled to the source of the (N+1)th PMOS transistor and a drain coupled to the power supply node of Vdd.

16. A power amplifier, comprising: a plurality of first voltage drivers, each of the first voltage drivers comprising a plurality of N PMOS transistors coupled between a power supply node and an output node and comprising a plurality of N NMOS transistors coupled between the output node and ground, wherein N is a positive integer of 3 or greater; a decoder configured to decode a baseband signal to select whether each first voltage driver is inactive or active based on a magnitude of the baseband signal and to phase a first clock signal and a second clock signal based on a phase of the baseband signal, wherein the first clock signal is configured to cycle between ground and a supply voltage (Vdd) to drive a gate of a first NMOS transistor of the plurality of N NMOS transistors in each activated first voltage driver of the first voltage drivers, and the second clock signal is configured to cycle between (N-1)*Vdd and N*Vdd to drive a gate of an Nth PMOS transistor of the plurality of N PMOS transistors in each activated first voltage driver of the first voltage drivers; and A voltage summing circuit is coupled to each output node and is configured to sum the output voltages at each output node.

17. A power amplifier according to claim 16, wherein the power amplifier is included in an integrated circuit having a transformer, the transformer comprising a first coil and a second coil, and wherein the voltage summing circuit comprises a plurality of N first capacitors, each first capacitor having a first terminal coupled to an output node of a corresponding first voltage driver in the first voltage driver and having a second terminal coupled to the first coil.

18. The power amplifier of claim 17, wherein the second coil is coupled to at least one antenna.

19. The power amplifier of claim 17, wherein each first capacitor is coupled to a first end of the first coil, the power amplifier further comprising: a plurality of second voltage drivers; and A plurality of second capacitors are provided, each second capacitor being coupled between an output node of a corresponding second voltage driver of the second voltage drivers and the second end of the first coil.

20. The power amplifier of claim 19, wherein the decoder is further configured to select whether each second voltage driver is inactive or active based on the magnitude of the baseband signal.

21. A method of driving an output node by a voltage driver, the method comprising: during a first clock phase of a clock signal, turning off a plurality of N PMOS transistors arranged in series in a first sequence from a first PMOS transistor coupled to the output node to an Nth PMOS transistor coupled to a power supply node by charging a gate of each PMOS transistor in a first sequence from a first PMOS transistor coupled to the output node to a product of a power supply voltage (Vdd) and an order of the PMOS transistors in the first sequence, wherein N is an integer of 3 or greater and wherein the power supply node is charged to N*Vdd; as well as The output node is grounded by turning on a plurality of N NMOS transistors arranged in series in a second sequence from a first NMOS transistor coupled to ground to an Nth NMOS transistor coupled to the output node during the first clock phase by charging a gate of each NMOS transistor in the second sequence to Vdd.

22. The method according to claim 21, further comprising: During a second clock phase of the clock signal; turning on the plurality of N PMOS transistors by charging the gate of each PMOS transistor to (N-1)*Vdd to charge the output node to N*Vdd; as well as The plurality of N NMOS transistors are turned off during the second phase of the clock signal by charging the gate of each NMOS transistor in the second sequence to a product of Vdd and a difference between an order of the NMOS transistor in the second sequence and 1.

23. The method according to claim 22, further comprising: During the first clock phase and the second clock phase, a sleep circuit coupled between the output node and a power supply of Vdd is disconnected.

24. The method according to claim 23, further comprising: During a sleep mode of the voltage driver, the sleep circuit is turned on to charge the output node to Vdd.

25. A voltage driver, comprising: a plurality of PMOS transistors arranged in series from a first PMOS transistor to an Nth PMOS transistor, wherein the first PMOS transistor has a drain coupled to an output node and the Nth PMOS transistor has a source coupled to a power supply node, wherein N is an integer of 3 or greater; a plurality of NMOS transistors arranged in series from a first NMOS transistor to an Nth NMOS transistor, wherein the first NMOS transistor has a source coupled to ground and the Nth NMOS transistor has a drain coupled to the output node; a first multiplexer configured to select between a first supply voltage and a second supply voltage to drive a gate of the first PMOS transistor; and a second multiplexer configured to select between the first supply voltage and the second supply voltage to drive a gate of the Nth NMOS transistor.

26. The voltage driver of claim 25, wherein N is equal to 3 and the first supply voltage is equal to twice the second supply voltage, and wherein a second PMOS transistor of the plurality of PMOS transistors has a gate coupled to the first supply voltage, and a second NMOS transistor of the plurality of NMOS transistors has a gate coupled to the second supply voltage.

27. The voltage driver of claim 25, wherein N is equal to 4 and the first supply voltage is equal to three times the second supply voltage, and wherein a third PMOS transistor of the plurality of PMOS transistors has a gate coupled to the first supply voltage, and a second NMOS transistor of the plurality of NMOS transistors has a gate coupled to the second supply voltage.

28. The voltage driver according to claim 25, further comprising: a first clock source configured to drive a gate of the first NMOS transistor; and A second clock source is configured to drive a gate of the Nth PMOS transistor.

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