Capacitance information extraction method, device and equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a capacitance information extraction method, device and equipment, and the method comprises the steps: obtaining a conductor object of which the capacitance information is to be extracted, determining that the first conductor belongs to a conductor network different from that of the first conductor in the conductor object, the second conductor is connected with the first conductor in a short-circuit manner; identifying a target area of short circuit between the first conductor and the second conductor, and separating the first conductor and the second conductor based on position information of the target area, so that the first conductor and the second conductor after separation do not have a short circuit relation; and determining a capacitance filtering area between the first conductor and the second conductor after separation, and removing capacitance information in the capacitance filtering area when the capacitance information of the first conductor after separation is extracted. According to the technical scheme provided by the invention, the precision of capacitance extraction can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, device and equipment for extracting capacitance information. Background Art

[0002] In the field of integrated circuit technology, in order to meet specific design requirements, it is sometimes necessary to ignore the capacitance extracted from some conductors. Existing solutions usually filter the capacitance between different layers through process files, or treat some conductors as rectangular blocks in the device area, thereby ignoring the capacitance of these rectangular blocks. However, these technologies are often only applicable to specific scenarios. Once they are out of these specific scenarios, the accuracy of capacitance extraction will decrease. For example, for the problem of capacitance extraction of the contact part of the conductor, the traditional method will produce a large capacitance extraction error when the conductor is short-circuited.

[0003] Therefore, a more accurate method for extracting capacitance information is urgently needed. Summary of the invention

[0004] The present application provides a capacitance information extraction method, device and equipment, which can improve the extraction accuracy of capacitance information.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, an embodiment of the present application provides a method for extracting capacitance information, the method comprising: Acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; Identifying a target area where the first conductor and the second conductor are short-circuited, and separating the first conductor and the second conductor based on location information of the target area so that there is no short-circuit relationship between the separated first conductor and the second conductor; A capacitance filtering region between the separated first conductor and the second conductor is determined, and when the capacitance information of the separated first conductor is extracted, the capacitance information located in the capacitance filtering region is eliminated.

[0006] The present embodiment provides a method for extracting capacitance information, by identifying the first conductor and the second conductor in the conductor object that have a short-circuit relationship, thereby determining the area that may cause capacitance calculation errors. Subsequently, by separating the first conductor and the second conductor, the short-circuit relationship between them can be eliminated, thereby ensuring that the capacitance information extraction process can be performed normally. In the process of extracting capacitance information, by determining the capacitance filtering area and eliminating the capacitance information in the area, the additional capacitance information introduced due to the elimination of the short-circuit relationship is avoided, thereby improving the accuracy of capacitance extraction. The whole process can not only ensure that the conductor with a short-circuit relationship can extract capacitance information normally, but also reduce the error of capacitance extraction, ensure the accuracy of capacitance information, provide more accurate data for chip layout design, and optimize the chip layout design process.

[0007] In one embodiment, identifying a target area of ​​a short between the first conductor and the second conductor includes: Acquire first space coordinates corresponding to each surface of the first conductor, and acquire second space coordinates corresponding to each surface of the second conductor; An overlapping area between the first conductor and the second conductor is determined according to the first space coordinate and the second space coordinate, and a target area for short circuit between the first conductor and the second conductor is determined according to the overlapping area.

[0008] This embodiment accurately determines the geometric position and shape of the conductors by obtaining the spatial coordinates of each surface of the first conductor and the second conductor, providing accurate geometric data support for subsequent capacitance calculation. Then, the overlapping area between the first conductor and the second conductor can be determined by the first spatial coordinate and the second spatial coordinate, and the overlapping area can determine the target area of ​​the short circuit between the two conductors. By identifying the target area of ​​the short circuit, the accuracy of subsequent capacitance extraction can be ensured, the calculation error caused by the short circuit area is reduced, and the accuracy of capacitance calculation in chip layout design is improved.

[0009] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes: If the position information of the target area indicates that the target area is located on the same plane, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the target area to separate the first conductor and the second conductor.

[0010] In this embodiment, if the target area is located on the same plane, the area of ​​the specified thickness is cut along the normal direction, and the conductor can be accurately separated, thereby ensuring that the capacitance information extraction process can be performed normally. In addition, by accurately controlling the depth and position of the cut, the error introduced by the conductor cut can be minimized while ensuring that the conductors are kept sufficiently spaced, thereby improving the accuracy of the subsequent capacitance calculation.

[0011] In one embodiment, the area cut off from the first conductor and / or the second conductor matches the projection of the target area in the normal direction.

[0012] This embodiment ensures that only necessary conductors are removed by accurately matching the cut-off area, thereby avoiding capacitance errors caused by unreasonable conductor cutting. Secondly, the cut-off area is consistent with the projection of the target area, which can effectively improve the electrical isolation between the conductors and prevent short circuits or signal interference.

[0013] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes: If the position information of the target area indicates that the target area is located on the same plane, the first conductor and / or the second conductor is moved along the normal direction of the target area to separate the first conductor and the second conductor.

[0014] In this embodiment, the first conductor and the second conductor are separated by moving, which can eliminate the short-circuit relationship between the conductors and avoid cutting off the conductors themselves, thereby improving the extraction accuracy of capacitance information.

[0015] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes: If the location information of the target area indicates that the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Each of the sub-regions is traversed, and for a current sub-region, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the current sub-region to separate the first conductor and the second conductor.

[0016] This embodiment divides the target area into multiple sub-areas, each of which can be located on the same plane for independent processing, which can avoid interference between conductors in different planes and ensure the accuracy of conductor separation. Accurately cutting the specified thickness of the conductor along the normal direction in each sub-area can not only effectively control the cutting depth and shape of the conductor, but also ensure that there will be no over-cutting or under-cutting during the cutting process, thereby improving the accuracy and quality of conductor separation. In addition, precise cutting operations can increase the physical isolation between conductors and reduce the risk of short circuits, thereby ensuring the stability and safety of the circuit. This processing method of splitting sub-areas allows each sub-area to be independently optimized according to specific needs, enhancing the accuracy of capacitance calculation.

[0017] In one embodiment, separating the first conductor and the second conductor based on the position information of the target area includes: If the position information of the target area indicates that the target area is located on multiple different planes, a reference plane corresponding to the multiple different planes is determined, and the first conductor and / or the second conductor is moved along the normal direction of the reference plane to separate the first conductor and the second conductor.

[0018] This embodiment can effectively avoid the short-circuit relationship between conductors by selecting a suitable reference plane from multiple planes in the target area and adjusting the position of the conductor along the normal direction of the reference plane, thereby ensuring the normal operation of the circuit and avoiding failures or performance degradation caused by short-circuiting. This method enables the relative position of the conductor to be accurately controlled, optimizes the circuit layout without affecting other circuit components, reduces electrical interference, and improves the accuracy of capacitance calculation. At the same time, the reference plane is flexibly selected to ensure that it moves in the normal direction of the reference plane, and the conductor can be separated smoothly. This method reduces the number of conductor adjustments and reduces the risk of inaccuracy in the subsequent capacitance calculation process.

[0019] In one embodiment, determining a capacitive filtering area between the separated first conductor and the second conductor includes: If the target areas are located on the same plane, determining a first projection area of ​​the target area on the first conductor and a second projection area of ​​the target area on the second conductor along a normal direction of the target area; The first projection area and the second projection area are determined as capacitive filtering areas between the separated first conductor and the second conductor.

[0020] This embodiment projects along the normal direction in the target area to determine the projection area on the first conductor and the second conductor, and can accurately locate the capacitance contribution area between the two conductors, thereby improving the accuracy of capacitance calculation. In addition, by setting the capacitance filtering area, that is, limiting the capacitance calculation between the first projection area and the second projection area, the calculation result is ensured to be more reliable. This method can clearly define the capacitance influence area and reduce the interference of the separation operation on the capacitance calculation result.

[0021] In one embodiment, the method further comprises: If the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Traverse each of the sub-areas, and for the current sub-area, determine a third projection area of ​​the sub-area on the first conductor and a fourth projection area of ​​the sub-area on the second conductor along the normal direction of the sub-area, and determine the third projection area and the fourth projection area as a capacitive filtering area between the separated first conductor and the second conductor.

[0022] This embodiment can significantly improve the accuracy and adaptability of capacitance calculation by splitting the target area into multiple sub-areas and performing projection and capacitance calculation on each sub-area respectively. This solution can more accurately process the capacitance contribution of the target area on different planes and avoid calculation errors caused by complex geometric shapes. At the same time, the capacitance calculation of each sub-area is performed on its independent plane, thereby ensuring the accuracy of the calculation results.

[0023] In a second aspect, an embodiment of the present application provides a device for extracting capacitance information, the device comprising: A conductor object acquisition unit, configured to acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; a conductor separation unit, configured to identify a target area where the first conductor and the second conductor are short-circuited, and to separate the first conductor and the second conductor based on position information of the target area, so that there is no short-circuit relationship between the separated first conductor and the second conductor; The capacitance filtering unit is used to determine a capacitance filtering area between the separated first conductor and the second conductor, and to remove capacitance information located in the capacitance filtering area when extracting capacitance information of the separated first conductor.

[0024] In a third aspect, an embodiment of the present application provides a computer device, comprising a memory and a processor, wherein the memory is used to store a computer program, and when the computer program is executed by the processor, the method for extracting capacitance information as described above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A flow chart of a method for extracting capacitance information provided in an embodiment of the present application; Figure 2 A schematic diagram of a cutting operation provided in an embodiment of the present application; Figure 3 A schematic diagram of another excision operation provided in an embodiment of the present application; Figure 4 A schematic diagram of another excision operation provided in an embodiment of the present application; Figure 5 A schematic diagram of a reference plane provided for an embodiment of the present application; Figure 6 A block diagram of a device for extracting capacitance information provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a computer device provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a first conductor and a second conductor in an overlapping state provided in an embodiment of the present application; FIG9 (a) is a schematic diagram of separation of overlapping states by a cutting method provided in an embodiment of the present application; FIG9( b ) is a schematic diagram of separating overlapping states by moving method provided in an embodiment of the present application.

[0027] Description of Reference Numerals 1-first conductor, 2-second conductor, 3-target area, 4-resected area, 5-reference plane. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] In the actual application of capacitance calculation, it is often necessary to ignore the capacitance extracted from some conductor surfaces in order to achieve the extraction effect of certain specific characteristics. In the current capacitance calculation scheme, the capacitance filtering problem between different layers is usually described through process files. During the calculation process, the software will determine which layers need to filter the capacitance, so as to eliminate the irrelevant conductor capacitance contribution in the capacitance calculation results and achieve the purpose of capacitance filtering.

[0030] Another common capacitance filtering technique is filtering the capacitance of the device region. Since the graphical information in the software is usually represented by a Manhattan structure and the device is also presented in the form of a cuboid in the data structure, users often want to ignore the capacitance information of these device regions during the capacitance extraction process. At the same time, the capacitance of other graphics can be filtered or converted into total capacitance according to specific parameters. This capacitance filtering technology is relatively common in practical applications and can effectively meet some common design requirements.

[0031] However, existing capacitance filtering technology can often only be used for specific scenarios and may not be suitable for all situations when directly applied. A typical application scenario is the problem of capacitance extraction of the contact (touch) part between conductors. When two conductors are short-circuited together, the traditional capacitance calculation method cannot accurately extract the capacitance. At this time, the software will treat the two conductors as different networks (Net), extract their capacitance information separately, and process the short-circuited capacitance in subsequent calculations. However, this processing method may lead to large capacitance extraction errors, especially in the calculation of the capacitance of the conductor contact surface. Therefore, a more accurate method for extracting capacitance information is currently needed.

[0032] In order to solve the above technical problems, according to an embodiment of the present application, an embodiment of a method for extracting capacitance information is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] In this embodiment, a method for extracting capacitance information is provided. Figure 1 A flow chart of a method for extracting capacitance information provided by an embodiment of the present application is as follows: Figure 1 As shown, the process includes the following steps.

[0034] Step S1, obtaining a conductor object whose capacitance information is to be extracted, and determining, for a first conductor in the conductor object, a second conductor that belongs to a different conductor network from the first conductor and is in a short-circuit relationship with the first conductor.

[0035] In this embodiment, the conductor object may be a conductor for which capacitance information extraction is expected. During the design process, the conductor object may contain multiple different conductors for different reasons. For example, when the size of the conductor object is large, in order to facilitate accurate extraction of capacitance information, the conductor object will be divided into multiple conductors belonging to different conductor networks during the design process. Subsequently, the capacitance information of these multiple conductors is extracted separately, so that the overall capacitance information of the conductor object can be summarized. For another example, the conductor object itself contains multiple conductors with short-circuited relationships, and these conductors with short-circuited relationships can also be in different conductor networks. When extracting capacitance information, it is necessary to consider the short-circuited relationship between different conductors, so as to extract accurate capacitance information.

[0036] In this embodiment, any first conductor in the conductor object is used as the target conductor to be processed, and a second conductor that is short-circuited with the first conductor can be determined. It should be noted that the number of second conductors is not limited in this embodiment. For example, there may be only one second conductor or multiple second conductors that are short-circuited with the first conductor. Short-circuiting means that the two conductors are directly connected electrically and are not isolated by other components or media.

[0037] Specifically, the conductor object to be processed is obtained from the chip layout design data, and a conductor in the conductor object is selected as the processing target, and the conductor is called the first conductor. In the chip layout design, different conductors may belong to different networks (Net). The network in the chip layout design can refer to the connection relationship between various devices in the chip circuit, and these connection relationships can be described by a netlist. A netlist is a file that describes the connection relationship between circuit elements and contains the connection information between various devices in the circuit. Next, other conductors that are electrically short-circuited with the first conductor but belong to different networks can be identified, and the other conductors can be used as the above-mentioned second conductors.

[0038] Step S3, identifying a target area where the first conductor and the second conductor are short-circuited, and separating the first conductor and the second conductor based on position information of the target area, so that there is no short-circuit relationship between the separated first conductor and the second conductor.

[0039] The target area refers to the area where the first conductor and the second conductor are short-circuited, and the position information of this area is used to guide subsequent separation operations.

[0040] Specifically, identify the target area of ​​the short circuit between the first conductor and the second conductor. This target area is the place where the two conductors are in direct contact determined according to the chip layout design data, which will affect the extraction of capacitance information. Once the target area is determined, a separation operation needs to be performed based on the position information of this target area. The position information may include information such as the geometry, size, and specific position of the target area in the circuit. The separation operation refers to physically or logically separating the first conductor and the second conductor to eliminate the short circuit relationship between them. This may involve changing the layout of the conductors, such as separating the first conductor and the second conductor by moving or cutting. After separation, the first conductor and the second conductor can be regarded as independent conductors in the capacitance extraction process, so that their respective capacitances can be calculated more accurately.

[0041] Step S5, determining a capacitance filtering region between the separated first conductor and the second conductor, and removing capacitance information located in the capacitance filtering region when extracting capacitance information of the separated first conductor.

[0042] The capacitance filtering area refers to an area determined after the first conductor and the second conductor are separated, and is used to remove capacitance information in the area during the capacitance extraction process.

[0043] Specifically, after the first conductor and the second conductor are separated, it is necessary to determine the capacitance filtering area. This area generally refers to the conductor part newly introduced in the separation operation. For example, the first conductor and the second conductor originally have a short-circuit relationship on a certain surface. After the short-circuit relationship is eliminated by the separation operation, the first conductor and the second conductor will generate a new surface at the original short-circuit position. If not restricted, these new surfaces will also be extracted from the capacitance information in the subsequent process, and this part of the capacitance information belongs to the additionally introduced capacitance information. If this part of the capacitance information is included in the overall capacitance information of the conductor object, an error will be generated. Therefore, after the first conductor and the second conductor are separated, the capacitance information corresponding to the newly introduced conductor surface should be ignored. Specifically, when extracting the capacitance information of the first conductor after separation, it is necessary to eliminate the capacitance information located in the capacitance filtering area. In other words, when calculating the capacitance of the first conductor, the conductor surface newly added by being cut or moved during the separation process is not considered, thereby improving the extraction accuracy of the capacitance information.

[0044] The present embodiment provides a method for extracting capacitance information, by identifying the first conductor and the second conductor in the conductor object that are in a short-circuit relationship, thereby determining the area that may cause capacitance calculation errors. Subsequently, by separating the first conductor and the second conductor, the short-circuit relationship between them can be eliminated, thereby ensuring that the capacitance information extraction process can be performed normally. In the process of extracting capacitance information, by determining the capacitance filtering area and eliminating the capacitance information in the area, the additional capacitance information introduced due to the elimination of the short-circuit relationship is avoided, thereby improving the accuracy of capacitance extraction. The whole process can not only ensure that the conductor with a short-circuit relationship can extract capacitance information normally, but also reduce the error of capacitance extraction, ensure the accuracy of capacitance information, provide more accurate data for chip design, and optimize the chip design process.

[0045] In some embodiments, identifying a target area for a short between a first conductor and a second conductor includes: The first space coordinates corresponding to each surface of the first conductor are obtained, and the second space coordinates corresponding to each surface of the second conductor are obtained.

[0046] Among them, the first spatial coordinate refers to the position of each surface of the first conductor in the three-dimensional space, which is usually expressed by the three coordinate values ​​of X, Y, and Z. The second spatial coordinate refers to the position of each surface of the second conductor in the three-dimensional space, which is also usually expressed by the three coordinate values ​​of X, Y, and Z. For example, the position of each surface of the conductor in the three-dimensional space can be expressed by the spatial coordinates of the four vertices on the surface. In this way, each surface can correspond to its own vertex spatial coordinates, and based on the vertex spatial coordinates, the area where each surface of the conductor is located can be restored in the three-dimensional space.

[0047] An overlapping area between the first conductor and the second conductor is determined according to the first space coordinate and the second space coordinate, and a target area for short circuit between the first conductor and the second conductor is determined according to the overlapping area.

[0048] In some embodiments, a surface used to represent a conductor in the chip layout can be determined by four vertex spatial coordinates. After obtaining the first spatial coordinate and the second spatial coordinate, the surfaces of the first conductor and the surfaces of the second conductor can be restored in the three-dimensional space based on the first spatial coordinate and the second spatial coordinate. Based on the positions of the surfaces in the three-dimensional space, the actual positions of the first conductor or the second conductor defined by the surfaces in the three-dimensional space can be determined. By identifying the overlapping relationship between the actual positions of the first conductor and the second conductor in the three-dimensional space, the target area of ​​the short circuit between the first conductor and the second conductor can be determined. Specifically, the first conductor and the second conductor that are in a short circuit relationship can have at least two states during the chip layout design process: the first is a contact state, and the second is an overlapping state. Among them, the contact state may refer to that the first conductor and the second conductor only have surface contact, but the first conductor and the second conductor are not embedded in each other's conductor structure. For example Figures 2 to 5 The first conductor and the second conductor shown are both in contact. The overlapping state means that at least part of the conductor structures of the first conductor and the second conductor are embedded in each other in the spatial graph. Figure 8 In the embodiment, a part of the conductor structure of the second conductor is embedded in the first conductor, so the short-circuit relationship between the first conductor and the second conductor is not just a contact relationship between the surfaces, but a contact relationship between the surface and the material inside the conductor. According to these two different states, different methods can be used to determine the target area of ​​the short-circuit between the first conductor and the second conductor.

[0049] Specifically, for the contact state, when there is an overlapping area between any two surfaces of the first conductor and the second conductor, the overlapping area can be used as the target area for the short circuit between the first conductor and the second conductor. For the first conductor and the second conductor in an overlapping state, a portion of the conductor embedded in the first conductor can be determined on the second conductor, and then each surface of the portion of the conductor can be identified, and each surface of the identified portion of the conductor can be used as the target area for the short circuit between the first conductor and the second conductor. For example, Figure 8 In the figure, the shaded portion may be the partial conductor determined on the second conductor. The partial conductor has six surfaces. These six surfaces may be used as the target area for short-circuiting between the first conductor and the second conductor. When the surface capacitances of the first conductor and the second conductor are calculated separately, the surface capacitances of the areas where these six surfaces are located may be ignored.

[0050] This embodiment accurately determines the geometric position and shape of the conductors by obtaining the spatial coordinates of each surface of the first conductor and the second conductor, providing accurate geometric data support for subsequent capacitance calculations. Then, the overlapping area between the first conductor and the second conductor can be determined by the first spatial coordinate and the second spatial coordinate, and the target area of ​​the short circuit between the two conductors can be determined by the overlapping area. By identifying the target area of ​​the short circuit, the accuracy of subsequent capacitance extraction can be ensured, the calculation error caused by the short circuit area is reduced, and the accuracy of capacitance calculation in chip design is improved.

[0051] In some embodiments, based on the location information of the target area, separating the first conductor and the second conductor includes: If the position information of the target region indicates that the target region is located on the same plane, a region of a specified thickness is cut off from the first conductor and / or the second conductor along a normal direction of the target region.

[0052] Specifically, if the location information of the target area indicates that the target area is located on the same plane, the separation operation can be performed along the normal direction of the target area. That is, if the target area is an area on a plane, the removal operation will be performed in a direction perpendicular to the plane. The purpose of the removal operation is to remove an area of ​​a specified thickness in the first conductor and / or the second conductor. This thickness is determined according to the design requirements and the manufacturing process to ensure that there is enough spacing between the two conductors to eliminate the short circuit phenomenon. For details, please refer to Figure 2 , the one marked as Net A can be the first conductor, and the one marked as Net B can be the second conductor. From the two-dimensional graph, the surface on the right side of the first conductor is short-circuited with the surface on the left side of the second conductor. When performing area removal, a portion of the first conductor and a portion of the second conductor can be removed along the direction perpendicular to the short-circuited surface (e.g. Figure 2 ), the total thickness of the first conductor and the second conductor removed can be the above-mentioned specified thickness. Of course, in practical applications, it is also possible to remove only the area of ​​the specified thickness on the first conductor, or only the area of ​​the specified thickness on the second conductor, to achieve the purpose of eliminating the short-circuit surface. The above-mentioned specified thickness can be flexibly determined according to actual conditions. For example, in order to reduce the impact on other surfaces of the first conductor and the second conductor, the specified thickness can be set to be relatively small.

[0053] In this embodiment, if the target area is located on the same plane, the area of ​​the specified thickness is cut along the normal direction, and the conductor can be accurately separated, thereby ensuring that the capacitance information extraction process can be performed normally. In addition, by accurately controlling the depth and position of the cut, the error introduced by the conductor cut can be minimized while ensuring that the conductors are kept sufficiently spaced, thereby improving the accuracy of the subsequent capacitance calculation.

[0054] In some embodiments, the area cut off on the first conductor and / or the second conductor matches the projection of the target area in the normal direction.

[0055] The cut-off area refers to a portion removed from the first conductor and / or the second conductor, and this operation is intended to eliminate the short circuit between the conductors. The projection refers to the projection of the target area in a direction perpendicular to its plane.

[0056] Specifically, the projection of the target area in the normal direction needs to be determined. That is, the two-dimensional shape and position of the target area on the vertical plane must be found. Then, the excision operation must ensure that the area excised from the first conductor and / or the second conductor exactly matches this projection. This means that the projection of the excision area in the normal direction of the target area is consistent with the projection of the target area.

[0057] For example, see Figure 3 , Figure 3 A schematic diagram of a cutting operation provided in an embodiment of the present application. Figure 3 As shown in (a) of FIG. 1 , the position information of the target area 3 identified between the first conductor 1 and the second conductor 2 indicates that the target area 3 is located on the same plane. Figure 3 If the target area 3 of type (a) in the figure is directly cut along the normal direction of the target area 3 to remove the area of ​​specified thickness in the first conductor 1 and / or the second conductor 2, unnecessary materials may be removed, resulting in reduced electrical performance or structural integrity of the conductor. Therefore, it is necessary to cut along the projection of the target area 3 in the normal direction to ensure that only the originally short-circuited conductor is removed, and the non-short-circuited area is not removed, that is, this projection is a direct mapping of the actual short-circuited area. This operation can obtain Figure 3 In (b), the resected area 4 matches the projection of the target area 3 in the normal direction.

[0058] This embodiment ensures that only necessary conductors are removed by accurately matching the cut-off area, thereby avoiding capacitance errors caused by unreasonable conductor cutting. Secondly, the cut-off area is consistent with the projection of the target area, which can effectively improve the electrical isolation between the conductors and prevent short circuits or signal interference.

[0059] In some embodiments, the conductors in a short-circuit relationship can also be separated by moving the conductors. It should be noted that in the process of moving the conductors, the relative positions of the conductors in the chip layout design may be changed, so that the conductors after the movement are different from the conductors before the movement in layout. If this difference is too large, it is likely to affect the calculation accuracy of the capacitance of other surfaces of the conductor. In view of this, when separating the conductors in a short-circuit relationship by moving the conductors, a chip layout design with a less complex structure can be used, or a chip layout design that only requires a small distance to separate the conductors can be used.

[0060] In practical applications, before the moving conductor is used to separate the short-circuited conductors, the distance that the conductor moves in the chip layout design can be identified. Generally speaking, if the moving distance is small, the impact on the layout of the original chip layout design is relatively small, and the moving conductor method is acceptable. Specifically, a distance threshold can be set in advance. When the moving distance is less than or equal to the distance threshold, it is considered that the moving distance is relatively small, and the moving conductor method can be used to eliminate the short-circuit relationship; if the moving distance is greater than the distance threshold, it is considered that the moving distance is too large, and it is not suitable to use the moving conductor method to eliminate the short-circuit relationship.

[0061] In addition, before it is expected that the conductors with short-circuit relationships are separated by moving the conductor, it can also be determined whether the conductors after the movement have a significant impact on the capacitance calculation of other conductor surfaces. If a significant impact is caused, it is not suitable to eliminate the short-circuit relationship by moving the conductor. Specifically, the impact caused by the moving conductor can be determined by the number of other conductors forced to move in the chip layout design, and can also be determined by the total movement distance of other conductors forced to move in the chip layout design. Among them, the other conductors forced to move refer to the conductors other than the first conductor and the second conductor in the chip layout design that have a short-circuit relationship. When the first conductor and the second conductor are separated by moving, due to the layout of the original chip layout design, some other conductors have to be adaptively moved. In this case, the number of other conductors forced to move and the total distance of the other conductors forced to move can be counted. If the number obtained by counting exceeds the preset number threshold, or the total distance obtained by counting exceeds the preset total distance threshold, it is considered that it is not suitable to eliminate the short-circuit relationship by moving the conductor at this time.

[0062] In a scenario where it is appropriate to eliminate the short-circuit relationship by moving the conductor, the first conductor and the second conductor can be separated by the following embodiments.

[0063] Specifically, based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on the same plane, the first conductor and / or the second conductor is moved along the normal direction of the target area to separate the first conductor and the second conductor.

[0064] Specifically, if the location information of the target area indicates that the short circuit occurs on the same plane, it means that the first conductor and the second conductor have a contact portion on the plane. In order to solve the short circuit problem, the first conductor and / or the second conductor can be moved along the normal direction perpendicular to the plane where the target area is located. The purpose of the moving operation is to separate the originally short-circuited conductors until there is no electrical connection between them, so as to ensure that the short circuit is completely eliminated.

[0065] In this embodiment, the first conductor and the second conductor are separated by moving, which can eliminate the short-circuit relationship between the conductors and avoid cutting off the conductors themselves, thereby improving the extraction accuracy of capacitance information.

[0066] In some embodiments, based on the location information of the target area, separating the first conductor and the second conductor includes: If the location information of the target area indicates that the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Each sub-region is traversed, and for a current sub-region, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the current sub-region.

[0067] Specifically, since the target area may span multiple planes, this means that the short-circuit problem is not limited to a single plane, but is distributed at different spatial levels. In order to simplify the processing, the target area is split into multiple sub-areas, each of which is located on the same plane. This can convert complex multi-plane problems into multiple single-plane problems for easy processing. These sub-areas are then processed one by one to ensure that the short-circuit problem on each plane is solved. For each sub-area, an area of ​​specified thickness in the first conductor and / or the second conductor is cut off along the normal direction of the plane where the sub-area is located. This is to physically separate the two conductors and eliminate short circuits.

[0068] For example, see Figure 4 , Figure 4 A schematic diagram of another excision operation provided in an embodiment of the present application. Figure 4 As shown in (a) of FIG. 1 , the position information of the target area 3 identified between the first conductor 1 and the second conductor 2 indicates that the target area 3 is located on multiple different planes. Figure 4When the target area 3 of type (a) is located on multiple different planes, direct adjustment along a unified direction may not accurately handle the conductor separation requirements between different planes. Because the conductor positions and directions on different planes are different, direct processing may result in incomplete conductor separation or errors. Therefore, it is necessary to split the target area 3 into multiple sub-areas. Different sub-areas can be processed on their own planes, avoiding interference between different planes and ensuring the accuracy of adjustment. Figure 4 As shown in (b), the cut area 4 is obtained by splitting the target area 3 into multiple sub-areas corresponding to the horizontal plane and the vertical plane, and by cutting out an area of ​​specified thickness along the normal direction of each sub-area, thereby accurately controlling the thickness of each conductor separation to avoid unnecessary conductor loss and ensuring physical isolation between the conductors to avoid short circuits.

[0069] This embodiment divides the target area into multiple sub-areas, each of which can be located on the same plane for independent processing, which can avoid interference between conductors in different planes and ensure the accuracy of conductor separation. Accurately cutting the specified thickness of the conductor along the normal direction in each sub-area can not only effectively control the cutting depth and shape of the conductor, but also ensure that there will be no over-cutting or under-cutting during the cutting process, thereby improving the accuracy and quality of conductor separation. In addition, precise cutting operations can increase the physical isolation between conductors and reduce the risk of short circuits, thereby ensuring the stability and safety of the circuit. This processing method of splitting sub-areas allows each sub-area to be independently optimized according to specific needs, enhancing the accuracy of capacitance calculation.

[0070] In some embodiments, based on the location information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on multiple different planes, a reference plane is determined in the multiple different planes, and the first conductor and / or the second conductor is moved along the normal direction of the reference plane to separate the first conductor and the second conductor.

[0071] Among them, the reference plane is a reference plane used to determine the relative position between conductors. When dealing with short circuit problems, choosing a suitable reference plane can help determine how to move the conductor to eliminate the short circuit. Of course, not all planes are suitable as reference planes. A suitable reference plane should meet the following conditions: On the one hand, the normal direction of the reference plane should allow the movement of the first conductor and the second conductor to eliminate the short circuit relationship between them. On the other hand, the selection of the reference plane should minimize interference with other parts of the circuit. For example, for Figure 3In target area 3, only the bottom surface can be used as a reference plane, because only by moving the conductor along the normal direction of the bottom surface can the short circuit relationship between the two conductors be effectively eliminated. The vertical surfaces on the left and right sides cannot be shorted by moving in the normal direction, because the directions of these surfaces are not conducive to the movement and separation of the conductors.

[0072] Therefore, the reference plane is specifically defined as: moving the first conductor and / or the second conductor along the normal direction of the reference plane can eliminate the short-circuit relationship between the first conductor and the second conductor.

[0073] Specifically, when the target area spans across multiple planes, a reference plane is determined, and by moving the conductors along the normal direction of the reference plane, it can be ensured that the short circuits between the conductors are eliminated.

[0074] For example, see Figure 5 , Figure 5 A schematic diagram of a reference plane provided in an embodiment of the present application. Figure 5 As shown in (a) of FIG. 1 , the position information of the target area 3 identified between the first conductor 1 and the second conductor 2 indicates that the target area 3 is located on multiple different planes. Figure 5 The target area 3 of type (a) is located on multiple different planes. In this case, if an inappropriate reference plane (such as a vertical plane) is selected, the movement direction of the conductor may not be able to effectively avoid short circuits, so the problem cannot be solved.

[0075] In order to effectively avoid short circuit, it is necessary to select a suitable reference plane. Figure 5 As can be seen from (b) in the figure, the bottom surface is more suitable as the reference plane 5. Only by moving the conductor along the normal direction of the bottom surface can the short circuit between the two conductors be effectively avoided. On the contrary, if the side or vertical surface is selected as the reference plane 5 and the conductor is moved along its normal direction, effective movement space cannot be provided because these directions are not conducive to the effective separation of the conductors. Therefore, selecting the bottom surface as the reference plane 5 is the most appropriate solution.

[0076] This embodiment can effectively avoid the short-circuit relationship between conductors by selecting a suitable reference plane from multiple planes in the target area and adjusting the position of the conductor along the normal direction of the reference plane, thereby ensuring the normal operation of the circuit and avoiding failures or performance degradation caused by short-circuiting. This method enables the relative position of the conductor to be accurately controlled, optimizes the circuit layout without affecting other circuit components, reduces electrical interference, and improves the accuracy of capacitance calculation. At the same time, the reference plane is flexibly selected to ensure that it moves in the normal direction of the reference plane, and the conductor can be separated smoothly. This method reduces the number of conductor adjustments and reduces the risk of inaccuracy in the subsequent capacitance calculation process.

[0077] In some embodiments, determining a capacitive filtering area between the separated first conductor and the second conductor includes: If the target areas are located on the same plane, determining a first projection area of ​​the target area on the first conductor and a second projection area of ​​the target area on the second conductor along a normal direction of the target area; The first projection area and the second projection area are determined as the capacitive filtering area between the separated first conductor and the second conductor.

[0078] When the target area is located on a single plane, the first projection area here refers to the projection of the target area on the first conductor, and the second projection area refers to the projection of the target area on the second conductor.

[0079] Specifically, if the target area is located on a single plane, this means that the short-circuit problem and the subsequent separation operation all occur in the same plane. Along the normal direction of the target area, the projection area of ​​the target area on the first conductor and the second conductor is determined. Determining the first projection area and the second projection area as capacitance filtering areas means that these areas will be excluded in the subsequent capacitance calculation. Short-circuit errors and error capacitance contributions are avoided, thereby improving accuracy and reliability.

[0080] This embodiment projects along the normal direction in the target area to determine the projection area on the first conductor and the second conductor, and can accurately locate the capacitance contribution area between the two conductors, thereby improving the accuracy of capacitance calculation. In addition, by setting the capacitance filtering area, that is, limiting the capacitance calculation between the first projection area and the second projection area, the calculation result is ensured to be more reliable. This method can clearly define the capacitance influence area and reduce the interference of the separation operation on the capacitance calculation result.

[0081] In some embodiments, the method further comprises: If the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Traverse each sub-region, and for the current sub-region, determine the third projection region of the sub-region on the first conductor and the fourth projection region of the sub-region on the second conductor along the normal direction of the sub-region, and determine the third projection region and the fourth projection region as the capacitive filtering region between the separated first conductor and the second conductor.

[0082] When the target area is located on multiple planes, the third projection area here refers to the projection of the target area on the first conductor, and the fourth projection area refers to the projection of the target area on the second conductor.

[0083] Specifically, when the target area spans multiple planes, direct processing may become complicated. Therefore, splitting the target area into multiple sub-areas, each of which is located on a single plane, can simplify the problem. For each sub-area, the projection area of ​​the sub-area on the first conductor and the second conductor is determined along its normal direction. Determining the third and fourth projection areas as capacitance filtering areas means that these areas will be excluded in subsequent capacitance calculations. Short circuit errors and error capacitance contributions are avoided, thereby improving accuracy and reliability.

[0084] This embodiment can significantly improve the accuracy and adaptability of capacitance calculation by splitting the target area into multiple sub-areas and performing projection and capacitance calculation on each sub-area respectively. This solution can more accurately process the capacitance contribution of the target area on different planes and avoid calculation errors caused by complex geometric shapes. At the same time, the capacitance calculation of each sub-area is performed on its independent plane, thereby ensuring the accuracy of the calculation results.

[0085] In one embodiment, for Figure 8 In the overlapping state shown, when separating the first conductor and the second conductor, the above-mentioned cutting separation and moving separation methods can also be used. Please refer to Figure 9 (a). When the cutting separation method is adopted, the multiple surfaces of the partial conductor where the second conductor is embedded in the first conductor can be cut and separated respectively, so as to eliminate the short-circuit state between the first conductor and the second conductor. For example, the upper and lower surfaces, front and rear surfaces, and left surface of the partial conductor can be cut with a specified thickness, while the right surface can be left unprocessed because the right surface is actually located inside the second conductor, and without cutting the right surface, the short-circuit relationship between the first conductor and the second conductor has been eliminated. Subsequently, when calculating the surface capacitance of the first conductor and the second conductor, the projection areas of the above-mentioned upper and lower surfaces, front and rear surfaces, and left surfaces on the first conductor and the second conductor can be determined, and the capacitance of these projection areas can be ignored.

[0086] Please refer to FIG9 (b). When the moving separation method is adopted, the left surface of the above-mentioned partial conductor can be used as a reference plane, and then the first conductor and / or the second conductor can be moved along the normal direction of the reference plane to separate the first conductor and the second conductor. When calculating the surface capacitance of the first conductor after separation, the area where the right surface of the original partial conductor is located can be ignored; and when calculating the surface capacitance of the second conductor after separation, the area where the upper and lower surfaces, front and rear surfaces, and left surface of the original partial conductor are located can be ignored.

[0087] Accordingly, please refer to Figure 6 A block diagram of a device for extracting capacitance information provided in an embodiment of the present application, the terminal includes: The conductor object acquisition unit 101 is used to acquire the conductor object to be used for extracting capacitance information, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; The conductor separation unit 103 is used to identify a target area where the first conductor and the second conductor are short-circuited, and to separate the first conductor and the second conductor based on the position information of the target area, so that there is no short-circuit relationship between the separated first conductor and the second conductor; The capacitance filtering unit 105 is used to determine a capacitance filtering area between the separated first conductor and the second conductor, and to remove capacitance information in the capacitance filtering area when extracting capacitance information of the separated first conductor.

[0088] In some optional embodiments, the conductor separation unit 103 is specifically used to obtain the first spatial coordinates corresponding to each surface of the first conductor, and to obtain the second spatial coordinates corresponding to each surface of the second conductor; determine the overlapping coordinates between the first spatial coordinates and the second spatial coordinates, and use the area represented by the overlapping coordinates as the target area for short-circuiting between the first conductor and the second conductor.

[0089] In some optional embodiments, the conductor separation unit 103 is specifically configured to remove an area of ​​a specified thickness in the first conductor and / or the second conductor along a normal direction of the target area if the position information of the target area indicates that the target area is located on the same plane.

[0090] In some optional embodiments, the area cut off on the first conductor and / or the second conductor matches the projection of the target area in the normal direction.

[0091] In some optional embodiments, the conductor separation unit 103 is specifically configured to move the first conductor and / or the second conductor along the normal direction of the target area to separate the first conductor and the second conductor if the position information of the target area indicates that the target area is located on the same plane.

[0092] In some optional embodiments, the conductor separation unit 103 is specifically used to split the target area into multiple sub-areas if the position information of the target area indicates that the target area is located on multiple different planes, wherein any sub-area is located on the same plane; traverse each sub-area, and for the current sub-area, cut off an area of ​​specified thickness in the first conductor and / or the second conductor along the normal direction of the current sub-area.

[0093] In some optional embodiments, the conductor separation unit 103 is specifically used to determine a reference plane in the different multiple planes if the position information of the target area indicates that the target area is located on multiple different planes, and move the first conductor and / or the second conductor along the normal direction of the reference plane to separate the first conductor and the second conductor.

[0094] In some optional embodiments, the capacitive filtering unit 105 is specifically used to determine, if the target areas are located on the same plane, a first projection area of ​​the target area on the first conductor and a second projection area of ​​the target area on the second conductor along the normal direction of the target area; and determine the first projection area and the second projection area as the capacitive filtering area between the separated first conductor and the second conductor.

[0095] In some optional embodiments, the device also includes a region splitting processing unit, which is used to, if the target area is located on multiple different planes, split the target area into multiple sub-areas, wherein any sub-area is located on the same plane; traverse each sub-area, and for the current sub-area, along the normal direction of the sub-area, determine the third projection area of ​​the sub-area on the first conductor, and the fourth projection area of ​​the sub-area on the second conductor, and determine the third projection area and the fourth projection area as the capacitive filtering area between the separated first conductor and the second conductor.

[0096] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0097] In this embodiment, a capacitance information extraction device is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0098] See also Figure 7 , Figure 7 A schematic diagram of the structure of a computer device provided in an embodiment of the present application is shown in FIG. Figure 7As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0099] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0100] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0101] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0102] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0103] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0104] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0105] The methods, devices or units described in the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0106] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0107] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or equipment. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices, and apparatuses according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0111] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0112] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0113] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0114] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for extracting capacitance information, characterized in that: The method comprises: Acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; Identifying a target area where the first conductor and the second conductor are short-circuited, and separating the first conductor and the second conductor based on location information of the target area so that there is no short-circuit relationship between the separated first conductor and the second conductor; A capacitance filtering region between the separated first conductor and the second conductor is determined, and when the capacitance information of the separated first conductor is extracted, the capacitance information located in the capacitance filtering region is eliminated.

2. The method according to claim 1, characterized in that Identifying a target area of ​​a short between the first conductor and the second conductor includes: Acquire first space coordinates corresponding to each surface of the first conductor, and acquire second space coordinates corresponding to each surface of the second conductor; An overlapping area between the first conductor and the second conductor is determined according to the first space coordinate and the second space coordinate, and a target area for short circuit between the first conductor and the second conductor is determined based on the overlapping area.

3. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on the same plane, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the target area to separate the first conductor and the second conductor.

4. The method according to claim 3, characterized in that The area cut off from the first conductor and / or the second conductor matches the projection of the target area in the normal direction.

5. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on the same plane, the first conductor and / or the second conductor is moved along the normal direction of the target area to separate the first conductor and the second conductor.

6. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the location information of the target area indicates that the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Each of the sub-regions is traversed, and for a current sub-region, a region of a specified thickness in the first conductor and / or the second conductor is cut off along a normal direction of the current sub-region to separate the first conductor and the second conductor.

7. The method according to claim 1 or 2, characterized in that: Based on the position information of the target area, separating the first conductor and the second conductor includes: If the position information of the target area indicates that the target area is located on multiple different planes, a reference plane corresponding to the multiple different planes is determined, and the first conductor and / or the second conductor is moved along the normal direction of the reference plane to separate the first conductor and the second conductor.

8. The method according to claim 1, characterized in that: Determining a capacitive filtering area between the separated first conductor and the second conductor includes: If the target areas are located on the same plane, determining a first projection area of ​​the target area on the first conductor and a second projection area of ​​the target area on the second conductor along a normal direction of the target area; The first projection area and the second projection area are determined as capacitive filtering areas between the separated first conductor and the second conductor.

9. The method according to claim 8, characterized in that The method further comprises: If the target area is located on multiple different planes, split the target area into sub-areas corresponding to each plane; Traverse each of the sub-areas, and for the current sub-area, determine a third projection area of ​​the sub-area on the first conductor and a fourth projection area of ​​the sub-area on the second conductor along the normal direction of the sub-area, and determine the third projection area and the fourth projection area as a capacitive filtering area between the separated first conductor and the second conductor.

10. A device for extracting capacitance information, characterized in that: The device comprises: A conductor object acquisition unit, configured to acquire a conductor object for which capacitance information is to be extracted, and for a first conductor in the conductor object, determine a second conductor that belongs to a different conductor network than the first conductor and is in a short-circuit relationship with the first conductor; a conductor separation unit, configured to identify a target area where the first conductor and the second conductor are short-circuited, and to separate the first conductor and the second conductor based on position information of the target area, so that there is no short-circuit relationship between the separated first conductor and the second conductor; The capacitance filtering unit is used to determine a capacitance filtering area between the separated first conductor and the second conductor, and to remove capacitance information located in the capacitance filtering area when extracting capacitance information of the separated first conductor.

11. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, the method for extracting capacitance information as claimed in any one of claims 1 to 9 is implemented.

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