Positive and negative power supply detection synchronous control method and circuit
By designing a positive and negative power supply detection synchronization control circuit, it ensures that it is turned on only when both positive and negative power supply reaches the required voltage, solving the problem of the positive and negative power supply in the prior art, and realizing the stability and cost reduction of the circuit.
Patent Information
- Application Number
- CN202510024036.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-04-18
AI Technical Summary
The prior art is difficult to ensure the synchronization of positive and negative power supplies in use scenarios, resulting in noise from the circuit and increasing employment and manufacturing costs.
A positive and negative power supply detection synchronization control circuit is designed. By connecting the resistor and transistor, it ensures that the power output ports VOUT+ and VOUT- can be turned on only when both the positive power supply input port VIN+ and the negative power supply input port VIN- reach the required voltage, so as to avoid the situation of conduction alone.
It realizes the synchronization in the use scenarios of positive and negative power supply, avoids the generation of circuit noise, reduces costs, and ensures the stability of the detection circuit output.
Smart Images
Figure CN119847047A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power supply detection, and in particular to a positive and negative power supply detection synchronous control method and circuit. Background Art
[0002] The power supply detection circuit uses one indicator light for each group of power supplies. When a group of power supplies has no power, the corresponding indicator light will go out. This method has the following disadvantages: 1. It requires more components and the cost is higher; 2. Multiple indicator lights need to be installed on the panel, which takes up a large space and increases the cost. Later, a method was designed to control the power supply and power failure of the positive and negative power supplies through circuit delay, independent detection control, single-chip microcomputer, etc., so as to achieve the effect of synchronous power supply detection.
[0003] However, the use of circuit delay and independent detection control cannot ensure that the positive and negative power supplies are powered on and off at the same time. When positive and negative power supplies are used, the circuit generates noise due to the asynchrony of the positive and negative power supplies. The use of a single-chip microcomputer for control requires the design of software programming and the single-chip microcomputer, which increases labor and manufacturing costs. Summary of the invention
[0004] The purpose of the present invention is to provide a positive and negative power supply detection synchronous control method and circuit. Only when the positive power supply input port VIN+ and the negative power supply input port VIN- both reach the required voltage, the positive power supply output port VOUT+ and the positive power supply input port VIN+ and the negative power supply output port VOUT- and the negative power supply input port VIN- can be turned on, aiming to solve the problems in the prior art.
[0005] The present invention is implemented as follows: a positive and negative power supply detection synchronous control circuit includes a positive power supply, a negative power supply and a detection circuit, wherein the detection circuit is connected to both ends of the positive power supply and the negative power supply respectively, and the detection circuit includes: resistors R1 to R11, NPN transistors Q2 and Q4, PNP transistors Q3 and Q5, N-channel MOS transistor Q1, P-channel MOS transistor Q6, a positive power supply input port VIN+, a positive power supply output port VOUT+, a negative power supply input port VIN-, a negative power supply output port VOUT- and a ground port GND; The positive power input port VIN+ is connected to the resistor R1, the resistor R3 and the MOS tube Q1, the resistor R1 is connected to the transistor Q2 and the resistor R2, and one end of the resistor R2 is connected to the ground port GND; One end of the MOS transistor Q1 is connected to the positive power output port VOUT+, the other end of the MOS transistor Q1 is connected to the resistor R3 and the resistor R5, the resistor R5 is connected to the PNP transistor Q3, one end of the PNP transistor Q3 is connected to the resistor R4, the resistor R4 is connected to the NPN transistor Q2, one end of the NPN transistor Q2 is grounded, and the PNP transistor Q3 is connected to the resistor R6; The negative power input port VIN- is connected to the resistor R8, the NPN transistor Q4, the resistor R10 and the MOS transistor Q6, the resistor R8 is connected to the resistor R7 and the NPN transistor Q4, and one end of the resistor R7 is connected to the ground port GND; MOS tube Q6 is connected to the negative power output port VOUT-, the MOS tube is connected to resistor R10 and resistor R11, one end of resistor R11 is connected to PNP transistor Q5, PNP transistor Q5 is connected to resistor R9, resistor R9 is connected to NPN transistor Q4, and PNP transistor Q5 is connected to resistor R6.
[0006] Furthermore, the positive power input port VIN+ is connected to pin 2 of resistor R1, pin 2 of resistor R3 and the source (S) of MOS tube Q1, pin 1 of resistor R1 is connected to the base (B) of transistor Q2 and pin 2 of resistor R2, and pin 1 of resistor R2 is connected to the ground port GND.
[0007] Furthermore, the drain (D) of the MOS tube Q1 is connected to the positive power output port VOUT+, the gate (G) of the MOS tube Q1 is connected to pin 1 of the resistor R3 and pin 2 of the resistor R5, pin 1 of the resistor R5 is connected to the emitter (E) of the PNP transistor Q3, the base (B) of the PNP transistor Q3 is connected to pin 2 of the resistor R4, pin 1 of the resistor R4 is connected to the collector (C) of the transistor Q2, the emitter (E) of the transistor Q2 is grounded, and the collector (C) of the transistor Q3 is connected to pin 1 of the resistor R6.
[0008] Furthermore, the negative power input port VIN- is connected to the pin 1 of the resistor R8, the emitter (E) of the NPN transistor Q4, the pin 2 of the resistor R10 and the source (S) of the MOS transistor Q6, the pin 2 of the resistor R8 is connected to the pin 1 of the resistor R7 and the base (B) of the NPN transistor Q4, and the pin 2 of the resistor R7 is connected to the ground port GND; Furthermore, the drain (D) of the MOS transistor Q6 is connected to the negative power supply output port VOUT-, the gate (G) of the MOS transistor Q6 is connected to pin 1 of the resistor R10 and pin 2 of the resistor R11, pin 1 of the resistor R11 is connected to the collector (C) of the PNP transistor Q5, the base (B) of the PNP transistor Q5 is connected to pin 2 of the resistor R9, pin 1 of the resistor R9 is connected to the collector (C) of the NPN transistor Q4, and the emitter (E) of the PNP transistor Q5 is connected to pin 2 of the resistor R6.
[0009] Compared with the prior art, the positive and negative power supply detection synchronous control method and circuit provided by the present invention have the following beneficial effects: In the circuit of the present technical solution, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can only be turned on when both the positive power input port VIN+ and the negative power input port VIN- reach the required voltage. As long as one of the two input voltages does not meet the requirement, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- cannot be turned on. There is no situation where they are turned on separately, and they can be turned off at the same time when the power is off. The problem of using the positive and negative power supplies asynchronously can be solved, so that the independent detection control mode can ensure that the positive and negative power supplies are powered on and powered off at the same time, and the synchronization of the positive and negative power supplies is ensured in the scenario where the positive and negative power supplies are used, so that the output of the detection circuit is stable. 2. When the positive power input port VIN+ reaches the required voltage value, transistor Q3 can flow through I EC , because the collector (C) of transistor Q3 is connected to pin 1 of resistor R6, and pin 2 of resistor R6 is connected to the emitter (E) of transistor Q5, when the negative power input port VIN- does not reach the required value, the negative power output port VOUT- and the negative power input port VIN- are cut off, and the emitter (E) and collector (C) of transistor Q5 are cut off. Because the emitter (E) and collector (C) of transistor Q5 are cut off, resistor R6 cannot generate current, so that the emitter (E) and collector (C) of transistor Q3 are turned on but no current passes through, and transistor Q1 is also cut off, and the positive power output port VOUT+ and the positive power input port VIN+ are cut off. When the negative power input port VIN- reaches the required voltage value, transistor Q5 can generate I EB , because the collector (C) of transistor Q5 is connected to pin 2 of resistor R6, and pin 1 of resistor R6 is connected to the collector (C) of transistor Q3, when the positive power input port VIN+ does not reach the required value, the positive power output port VOUT+ and the positive power input port VIN+ are cut off and the emitter (E) and collector (C) of transistor Q3 are cut off, so that resistor R6 cannot generate current, and transistor Q5 has no I EB , the negative power output port VOUT- and the negative power input port VIN- are cut off. When the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage value, transistors Q3 and Q5 can both generate I EC current, and at the same time, the positive power output port VOUT+ is connected to the positive power input port VIN+, and the negative power output port VOUT- is connected to the negative power input port VIN-.
[0010] The positive and negative power supply detection synchronous control method is applied to the positive and negative power supply detection synchronous control circuit mentioned above, and specifically comprises the following steps: S101: The positive power input port VIN+ input voltage is divided by resistors R1 and R2. According to the resistance values of resistors R1 and R2, the voltage VR2 across resistor R2 is set. As the voltage of the positive power input port VIN+ increases, VR2 also increases. When VR2 increases above the cut-off voltage of transistor Q2, transistor Q2 will generate an I BE Current, so that the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q3 has I EB When the collector (C) and emitter (E) of transistor Q3 can flow through an I EC =βxI EB , when transistor Q3 has I EC When the resistor R3 has a voltage V R3 , when V R3 The voltage is higher than the V th When , MOS tube Q1 is turned on, so that the positive power output port VOUT+ and the positive power input port VIN+ are turned on; S102: Negative power input port VIN- input voltage, divided by resistor R8 and resistor R7, set the voltage V across resistor R8 according to the resistance value of resistor R8 and resistor R7 R8 As the negative power input port VIN- voltage increases, V R8 Increase, when V R8 When the cut-off voltage of transistor Q4 is increased, transistor Q4 will generate an I BE , the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q5 has I EB When the transistor Q5 emitter (E) and collector (C) can pass a current I EC =βxI EB , when there is a current I in transistor Q5 EC When the resistor R10 generates a voltage V R10 , when V R10 The voltage is higher than the V th When MOS tube Q6 is turned on, the negative power output port VOUT- is turned on with the negative power input port VIN-; S103: When the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage value, transistors Q3 and Q5 can both generate I EC Current, and at the same time, can make the positive power output port VOUT+ and the positive power input port VIN+ conductive and the negative power output port VOUT- and the negative power input port VIN- conductive; S104: The positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can be turned on only when the positive power input port VIN+ and the negative power input port VIN- reach the required voltage. As long as one of the two input voltages does not meet the requirement, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can not be turned on. There is no situation where one is turned on separately and they can be turned off at the same time when the power is off to ensure the synchronization of the positive and negative power supplies.
[0011] Specifically, when the positive power input port VIN+ input voltage is lower than the required value, V R2 The transistor Q2 cut-off voltage is lower than the transistor Q2 cut-off voltage, and the transistor Q2 cannot generate I BE The collector (C) and emitter (E) of transistor Q2 are cut off, and transistor Q3 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q3, making no circuit pass between resistor R3 and resistor R5, and making the voltage V on resistor R3 R3 Unable to reach the Vt of MOS tube Q1 h , transistor Q1 is cut off, so that the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
[0012] Specifically, when the negative power input port VIN- voltage is higher than the required value, V R8 Lower than the cut-off voltage of transistor Q4, transistor Q4 cannot generate I BE The collector (C) and emitter (E) of transistor Q4 are cut off, and transistor Q5 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q5, making no circuit pass between resistor R10 and resistor R11, and making the voltage V on resistor R10 R10 Unable to reach the V of MOS tube Q6 th , transistor Q3 is cut off, so that the negative power output port VOUT- and the negative power input port VIN- are cut off.
[0013] Specifically, when the positive power input port VIN+ reaches the required voltage value, transistor Q3 can flow through I EC When the negative power input port VIN- does not reach the required value, the negative power output port VOUT- and the negative power input port VIN- are cut off, and the emitter (E) and collector (C) of the transistor Q5 are cut off, so that the emitter (E) and collector (C) of the transistor Q3 are turned on but no current flows through, and the transistor Q1 is also cut off, and the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
[0014] Specifically, when the negative power input port VIN- reaches the required voltage value, transistor Q5 can generate I EB When the positive power input port VIN+ does not reach the required value, the positive power output port VOUT+ and the positive power input port VIN+ are cut off, and the emitter (E) and collector (C) of the transistor Q3 are cut off, so that the resistor R6 cannot generate current, and the transistor Q5 has no I EB , the negative power output port VOUT- and the negative power input port VIN- are cut off. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 This is a structural schematic diagram of the positive and negative power supply detection synchronous control circuit proposed by the present invention; Figure 2 It is a structural schematic diagram of the detection circuit in the positive and negative power supply detection synchronous control circuit proposed by the present invention; Figure 3 This is a schematic block diagram of the process of the positive and negative power supply detection synchronous control method proposed by the present invention. DETAILED DESCRIPTION
[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0017] The implementation of the present invention is described in detail below in conjunction with specific embodiments.
[0018] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0019] Reference Figure 1-2As shown, the positive and negative power supply detection synchronous control circuit includes a positive power supply, a negative power supply and a detection circuit. The detection circuit is connected to both ends of the positive power supply and the negative power supply respectively. The detection circuit includes: resistors R1 to R11, NPN transistors Q2 and Q4, PNP transistors Q3 and Q5, N-channel MOS transistor Q1, P-channel MOS transistor Q6, positive power supply input port VIN+, positive power supply output port VOUT+, negative power supply input port VIN-, negative power supply output port VOUT- and ground port GND; the positive power supply input port VIN+ is connected to resistor R1, resistor R3 and MOS transistor Q1, and the positive power supply input port VIN+ is connected to resistor R1, resistor R3 and MOS transistor Q1. Resistor R1 connects transistor Q2 and resistor R2, and one end of resistor R2 is connected to the ground port GND; one end of MOS tube Q1 is connected to the positive power output port VOUT+, and the other end of MOS tube Q1 is connected to resistor R3 and resistor R5, resistor R5 is connected to PNP transistor Q3, one end of PNP transistor Q3 is connected to resistor R4, resistor R4 is connected to NPN transistor Q2, one end of NPN transistor Q2 is grounded, and PNP transistor Q3 is connected to resistor R6; negative power input port VIN- is connected to resistor R8, NPN transistor Q4, resistor R10 and MOS tube Q6, resistor R8 is connected to resistor R7 and NPN transistor Q4, one end of resistor R7 is connected to ground port GND; MOS tube Q6 is connected to negative power output port VOUT-, MOS tube is connected to resistor R10 and resistor R11, one end of resistor R11 is connected to PNP transistor Q5, PNP transistor Q5 is connected to resistor R9, resistor R9 is connected to NPN transistor Q4, PNP transistor Q5 is connected to resistor R6, in the circuit of the technical solution, only when the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VIN- are connected. The positive power output port VOUT- and the negative power input port VIN- can be turned on. As long as one of the two input voltages does not meet the requirements, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- cannot be turned on. There is no situation where they are turned on separately. They can be turned off at the same time when the power is off, which can solve the problem of asynchronous use of positive and negative power supplies, so that the independent detection control method can ensure that the positive and negative power supplies are powered on and powered off at the same time, and ensure the synchronization of the positive and negative power supplies in the scenario where the positive and negative power supplies are used, so that the output of the detection circuit is stable.
[0020] In this embodiment, the positive power input port VIN+ is connected to pin 2 of the resistor R1, pin 2 of the resistor R3 and the source (S) of the MOS tube Q1, pin 1 of the resistor R1 is connected to the base (B) of the transistor Q2 and pin 2 of the resistor R2, and pin 1 of the resistor R2 is connected to the ground port GND.
[0021] In this embodiment, the drain (D) of the MOS transistor Q1 is connected to the positive power output port VOUT+, the gate (G) of the MOS transistor Q1 is connected to the 1st pin of the resistor R3 and the 2nd pin of the resistor R5, the 1st pin of the resistor R5 is connected to the emitter (E) of the PNP transistor Q3, the base (B) of the PNP transistor Q3 is connected to the 2nd pin of the resistor R4, the 1st pin of the resistor R4 is connected to the collector (C) of the transistor Q2, the emitter (E) of the transistor Q2 is grounded, and the collector (C) of the transistor Q3 is connected to the 1st pin of the resistor R6. When the positive power input port VIN+ reaches the required voltage value, the transistor Q3 can flow through I EC , because the collector (C) of transistor Q3 is connected to pin 1 of resistor R6, and pin 2 of resistor R6 is connected to the emitter (E) of transistor Q5, when the negative power input port VIN- does not reach the required value, the negative power output port VOUT- and the negative power input port VIN- are cut off, and the emitter (E) and collector (C) of transistor Q5 are cut off. Because the emitter (E) and collector (C) of transistor Q5 are cut off, resistor R6 cannot generate current, so that the emitter (E) and collector (C) of transistor Q3 are turned on but no current passes through, and transistor Q1 is also cut off, and the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
[0022] In this embodiment, the negative power input port VIN- is connected to the 1st pin of the resistor R8, the emitter (E) of the NPN transistor Q4, the 2nd pin of the resistor R10 and the source (S) of the MOS transistor Q6, the 2nd pin of the resistor R8 is connected to the 1st pin of the resistor R7 and the base (B) of the NPN transistor Q4, and the 2nd pin of the resistor R7 is connected to the ground port GND. When the negative power input port VIN- reaches the required voltage value, the transistor Q5 can generate I EB , because the collector (C) of transistor Q5 is connected to pin 2 of resistor R6, and pin 1 of resistor R6 is connected to the collector (C) of transistor Q3, when the positive power input port VIN+ does not reach the required value, the positive power output port VOUT+ and the positive power input port VIN+ are cut off and the emitter (E) and collector (C) of transistor Q3 are cut off, so that resistor R6 cannot generate current, and transistor Q5 has no I EB , the negative power output port VOUT- and the negative power input port VIN- are cut off.
[0023] In this embodiment, the drain (D) of the MOS transistor Q6 is connected to the negative power output port VOUT-, the gate (G) of the MOS transistor Q6 is connected to the 1 pin of the resistor R10 and the 2 pin of the resistor R11, the 1 pin of the resistor R11 is connected to the collector (C) of the PNP transistor Q5, the base (B) of the PNP transistor Q5 is connected to the 2 pin of the resistor R9, the 1 pin of the resistor R9 is connected to the collector (C) of the NPN transistor Q4, and the emitter (E) of the PNP transistor Q5 is connected to the 2 pin of the resistor R6. When the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage value, the transistors Q3 and Q5 can both generate I EC current, and at the same time, the positive power output port VOUT+ is connected to the positive power input port VIN+, and the negative power output port VOUT- is connected to the negative power input port VIN-.
[0024] Reference Figure 3 As shown, the positive and negative power supply detection synchronous control method is applied to the positive and negative power supply detection synchronous control circuit mentioned above, and specifically includes the following steps: S101: The positive power input port VIN+ input voltage is divided by resistors R1 and R2. According to the resistance values of resistors R1 and R2, the voltage VR2 across resistor R2 is set. As the voltage of the positive power input port VIN+ increases, VR2 also increases. When VR2 increases above the cut-off voltage of transistor Q2, transistor Q2 will generate an I BE Current, so that the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q3 has I EB When the collector (C) and emitter (E) of transistor Q3 can flow through an I EC =βxI EB , when transistor Q3 has I EC When the resistor R3 has a voltage V R3 , when V R3 The voltage is higher than the V th When , MOS tube Q1 is turned on, so that the positive power output port VOUT+ and the positive power input port VIN+ are turned on; S102: Negative power input port VIN- input voltage, divided by resistor R8 and resistor R7, set the voltage V across resistor R8 according to the resistance value of resistor R8 and resistor R7 R8 As the negative power input port VIN- voltage increases, V R8 Increase, when V R8 When the cut-off voltage of transistor Q4 is increased, transistor Q4 will generate an I BE, the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q5 has I EB When the transistor Q5 emitter (E) and collector (C) can pass a current I EC =βxI EB , when there is a current I in transistor Q5 EC When the resistor R10 generates a voltage V R10 , when V R10 The voltage is higher than the V th When MOS tube Q6 is turned on, the negative power output port VOUT- is turned on with the negative power input port VIN-; S103: When the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage value, transistors Q3 and Q5 can both generate I EC Current, and at the same time, can make the positive power output port VOUT+ and the positive power input port VIN+ conductive and the negative power output port VOUT- and the negative power input port VIN- conductive; S104: The positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can be turned on only when the positive power input port VIN+ and the negative power input port VIN- reach the required voltage. As long as one of the two input voltages does not meet the requirement, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can not be turned on. There is no situation where one is turned on separately and they can be turned off at the same time when the power is off to ensure the synchronization of the positive and negative power supplies.
[0025] In this embodiment, when the input voltage of the positive power input port VIN+ is lower than the required value, V R2 The transistor Q2 cut-off voltage is lower than the transistor Q2 cut-off voltage, and the transistor Q2 cannot generate I BE The collector (C) and emitter (E) of transistor Q2 are cut off, and transistor Q3 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q3, making no circuit pass between resistor R3 and resistor R5, and making the voltage V on resistor R3 R3 Unable to reach the Vt of MOS tube Q1 h , transistor Q1 is turned off, so that the positive power output port VOUT+ and the positive power input port VIN+ are turned off. When the voltage of the negative power input port VIN- is higher than the required value, V R8 Lower than the cut-off voltage of transistor Q4, transistor Q4 cannot generate I BEThe collector (C) and emitter (E) of transistor Q4 are cut off, and transistor Q5 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q5, making no circuit pass between resistor R10 and resistor R11, and making the voltage V on resistor R10 R10 Unable to reach the V of MOS tube Q6 th , transistor Q3 is turned off, so that the negative power output port VOUT- and the negative power input port VIN- are turned off. When the positive power input port VIN+ reaches the required voltage value, transistor Q3 can flow through I EC When the negative power input port VIN- does not reach the required value, the negative power output port VOUT- and the negative power input port VIN- are cut off, and the emitter (E) and collector (C) of the transistor Q5 are cut off, so that the emitter (E) and collector (C) of the transistor Q3 are turned on but no current flows through, and the transistor Q1 is also cut off, and the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
[0026] In this embodiment, when the negative power input port VIN- reaches the required voltage value, the transistor Q5 can generate I EB When the positive power input port VIN+ does not reach the required value, the positive power output port VOUT+ and the positive power input port VIN+ are cut off, and the emitter (E) and collector (C) of the transistor Q3 are cut off, so that the resistor R6 cannot generate current, and the transistor Q5 has no I EB , the negative power output port VOUT- and the negative power input port VIN- are cut off. Only when the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can be turned on. As long as one of the two input voltages does not meet the requirements, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can be turned on. There is no situation where they are turned on separately. They can be turned off at the same time when the power is off, which can solve the problem of using the positive and negative power supplies asynchronously, so that the independent detection control mode can ensure that the positive and negative power supplies are powered on and powered off at the same time, and ensure the synchronization of the positive and negative power supplies in the scenario where the positive and negative power supplies are used, so that the output of the detection circuit is stable; In this embodiment, the entire operation process can be controlled by a computer, with the addition of a PLC, etc., to achieve automated operation control, perform signal feedback, and implement sequential steps. These are all common knowledge of current automated control and will not be described in detail in this embodiment.
[0027] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A positive and negative power supply detection synchronous control circuit, comprising a positive power supply, a negative power supply and a detection circuit, wherein the detection circuit is connected to both ends of the positive power supply and the negative power supply, respectively, and is characterized in that: The detection circuit includes: resistors R1 to R11, NPN transistors Q2 and Q4, PNP transistors Q3 and Q5, N-channel MOS transistor Q1, P-channel MOS transistor Q6, positive power input port VIN+, positive power output port VOUT+, negative power input port VIN-, negative power output port VOUT- and ground port GND; The positive power input port VIN+ is connected to the resistor R1, the resistor R3 and the MOS tube Q1, the resistor R1 is connected to the transistor Q2 and the resistor R2, and one end of the resistor R2 is connected to the ground port GND; One end of the MOS transistor Q1 is connected to the positive power output port VOUT+, the other end of the MOS transistor Q1 is connected to the resistor R3 and the resistor R5, the resistor R5 is connected to the PNP transistor Q3, one end of the PNP transistor Q3 is connected to the resistor R4, the resistor R4 is connected to the NPN transistor Q2, one end of the NPN transistor Q2 is grounded, and the PNP transistor Q3 is connected to the resistor R6; The negative power input port VIN- is connected to the resistor R8, the NPN transistor Q4, the resistor R10 and the MOS transistor Q6, the resistor R8 is connected to the resistor R7 and the NPN transistor Q4, and one end of the resistor R7 is connected to the ground port GND; MOS tube Q6 is connected to the negative power output port VOUT-, the MOS tube is connected to resistor R10 and resistor R11, one end of resistor R11 is connected to PNP transistor Q5, PNP transistor Q5 is connected to resistor R9, resistor R9 is connected to NPN transistor Q4, and PNP transistor Q5 is connected to resistor R6.
2. The positive and negative power supply detection synchronous control circuit according to claim 1, characterized in that: The positive power input port VIN+ is connected to pin 2 of resistor R1, pin 2 of resistor R3 and the source (S) of MOS tube Q1, pin 1 of resistor R1 is connected to the base (B) of transistor Q2 and pin 2 of resistor R2, and pin 1 of resistor R2 is connected to the ground port GND.
3. The positive and negative power supply detection synchronous control circuit as claimed in claim 2, characterized in that: The drain (D) of the MOS tube Q1 is connected to the positive power supply output port VOUT+, the gate (G) of the MOS tube Q1 is connected to pin 1 of the resistor R3 and pin 2 of the resistor R5, pin 1 of the resistor R5 is connected to the emitter (E) of the PNP transistor Q3, the base (B) of the PNP transistor Q3 is connected to pin 2 of the resistor R4, pin 1 of the resistor R4 is connected to the collector (C) of the transistor Q2, the emitter (E) of the transistor Q2 is grounded, and the collector (C) of the transistor Q3 is connected to pin 1 of the resistor R6.
4. The positive and negative power supply detection synchronous control circuit as claimed in claim 3, characterized in that: The negative power input port VIN- is connected to pin 1 of resistor R8, the emitter (E) of NPN transistor Q4, pin 2 of resistor R10 and the source (S) of MOS tube Q6, pin 2 of resistor R8 is connected to pin 1 of resistor R7 and the base (B) of NPN transistor Q4, and pin 2 of resistor R7 is connected to the ground port GND.
5. The positive and negative power supply detection synchronous control circuit as claimed in claim 4, characterized in that: The drain (D) of MOS tube Q6 is connected to the negative power supply output port VOUT-, the gate (G) of MOS tube Q6 is connected to pin 1 of resistor R10 and pin 2 of resistor R11, pin 1 of resistor R11 is connected to the collector (C) of PNP transistor Q5, the base (B) of PNP transistor Q5 is connected to pin 2 of resistor R9, pin 1 of resistor R9 is connected to the collector (C) of NPN transistor Q4, and the emitter (E) of PNP transistor Q5 is connected to pin 2 of resistor R6.
6. A positive and negative power supply detection synchronous control method, characterized in that: The positive and negative power supply detection synchronous control circuit applied to any one of claims 1 to 5 specifically comprises the following steps: S101: The positive power input port VIN+ input voltage is divided by resistors R1 and R2. According to the resistance values of resistors R1 and R2, the voltage VR2 across resistor R2 is set. As the voltage of the positive power input port VIN+ increases, VR2 also increases. When VR2 increases above the cut-off voltage of transistor Q2, transistor Q2 will generate an I BE Current, so that the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q3 has I EB When the collector (C) and emitter (E) of transistor Q3 can flow through an I EC =βxI EB , when transistor Q3 has I EC When the resistor R3 has a voltage V R3 , when V R3 The voltage is higher than the V th When , MOS tube Q1 is turned on, so that the positive power output port VOUT+ and the positive power input port VIN+ are turned on; S102: Negative power input port VIN- input voltage, divided by resistor R8 and resistor R7, set the voltage V across resistor R8 according to the resistance value of resistor R8 and resistor R7 R8 As the negative power input port VIN- voltage increases, V R8 Increase, when V R8 When the cut-off voltage of transistor Q4 is increased, transistor Q4 will generate an I BE , the transistor collector (C) and emitter (E) can flow through an I CE =βxI BE , when transistor Q5 has I EB When the transistor Q5 emitter (E) and collector (C) can pass a current I EC =βxI EB , when there is a current I in transistor Q5 EC When the resistor R10 generates a voltage V R10 , when V R10 The voltage is higher than the V th When MOS tube Q6 is turned on, the negative power output port VOUT- is turned on with the negative power input port VIN-; S103: When the positive power input port VIN+ and the negative power input port VIN- both reach the required voltage value, transistors Q3 and Q5 can both generate I EC Current, and at the same time, can make the positive power output port VOUT+ and the positive power input port VIN+ conductive and the negative power output port VOUT- and the negative power input port VIN- conductive; S104: The positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can be turned on only when the positive power input port VIN+ and the negative power input port VIN- reach the required voltage. As long as one of the two input voltages does not meet the requirement, the positive power output port VOUT+ and the positive power input port VIN+ and the negative power output port VOUT- and the negative power input port VIN- can not be turned on. There is no situation where one is turned on separately and they can be turned off at the same time when the power is off to ensure the synchronization of the positive and negative power supplies.
7. The positive and negative power supply detection synchronous control method according to claim 6, characterized in that: When the positive power input port VIN+ input voltage is lower than the required value, V R2 The transistor Q2 cut-off voltage is lower than the transistor Q2 cut-off voltage, and the transistor Q2 cannot generate I BE The collector (C) and emitter (E) of transistor Q2 are cut off, and transistor Q3 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q3, making no circuit pass between resistor R3 and resistor R5, and making the voltage V on resistor R3 R3 Unable to reach the Vt of MOS tube Q1 h , transistor Q1 is cut off, so that the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
8. The positive and negative power supply detection synchronous control method according to claim 7, characterized in that: When the negative power input port VIN- voltage is higher than the required value, V R8 Lower than the cut-off voltage of transistor Q4, transistor Q4 cannot generate I BE The collector (C) and emitter (E) of transistor Q4 are cut off, and transistor Q5 is unable to generate I EB The current cuts off the emitter (E) and collector (C) of transistor Q5, making no circuit pass between resistor R10 and resistor R11, and making the voltage V on resistor R10 R10 Unable to reach the V of MOS tube Q6 th , transistor Q3 is cut off, so that the negative power output port VOUT- and the negative power input port VIN- are cut off.
9. The positive and negative power supply detection synchronous control method according to claim 8, characterized in that: When the positive power input port VIN+ reaches the required voltage value, transistor Q3 can flow through I EC When the negative power input port VIN- does not reach the required value, the negative power output port VOUT- and the negative power input port VIN- are cut off, and the emitter (E) and collector (C) of the transistor Q5 are cut off, so that the emitter (E) and collector (C) of the transistor Q3 are turned on but no current flows through, and the transistor Q1 is also cut off, and the positive power output port VOUT+ and the positive power input port VIN+ are cut off.
10. The positive and negative power supply detection synchronous control method according to claim 9, characterized in that: When the negative power input port VIN- reaches the required voltage value, transistor Q5 can generate I EB When the positive power input port VIN+ does not reach the required value, the positive power output port VOUT+ and the positive power input port VIN+ are cut off, and the emitter (E) and collector (C) of the transistor Q3 are cut off, so that the resistor R6 cannot generate current, and the transistor Q5 has no I EB , the negative power output port VOUT- and the negative power input port VIN- are cut off.