Computing system for processing command and method of operating the same

Abstract

The present application may provide a computing system with improved command processing speed. The computing system may include a host device configured to generate a command including information associated with operations to be requested, the information including a first information portion associated with a first of the operations and a second information portion associated with a second operation to be requested after the first operation, and outputting a command including the first information portion and the second information portion; and a storage device configured to store data and communicate with a host device, where the storage device is configured to receive a command from the host device, perform a first operation in response to the command, and perform a portion of a second operation based on a second information portion in the command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0138381, filed on October 17, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a semiconductor device, and more particularly, to a computing system for processing commands and a method of operating the computing system. Background Art

[0004] A storage device can be any type of computing hardware used to store or retrieve data files and objects. A storage device can operate under the control of another device, such as a host device. A storage device can include a memory device that stores data, a buffer memory that temporarily stores data, and a memory controller that controls the memory device and the buffer memory. Summary of the Invention

[0005] Various embodiments of the disclosed technology relate to a computing system capable of reducing command processing time and a method of operating the computing system.

[0006] In an embodiment of the disclosed technology, a computing system may include: a host device configured to generate a command including information associated with an operation to be requested, the information including a first information portion associated with a first operation among the operations and a second information portion associated with a second operation to be requested after the first operation, and output a command including the first information portion and the second information portion; and a storage device configured to store data and communicate with the host device, wherein the storage device is configured to receive the command from the host device, perform the first operation in response to the command, and perform a portion of the second operation based on the second information portion in the command.

[0007] In an embodiment of the disclosed technology, a method for operating a computing system may include: generating, by a host device, a first command including information associated with an operation to be requested, the information including a first information portion associated with the first operation and a second information portion associated with a second operation to be requested after the first operation; sending, by the host device, the first command to a storage device storing data; performing, by the storage device, the first operation in response to the first command; performing, by the storage device, a portion of the second operation based on the second information portion in response to the first command; sending, by the storage device, a response to the first command to the host device; generating, by the host device, a second command including the second information portion; sending, by the host device, the second command to the storage device; and performing, by the storage device, the remaining operations of the second operation except the portion in response to the second command.

[0008] In an embodiment of the disclosed technology, a computing system may include: a host device, configured to insert multiple second information portions associated with multiple second operations into a command for requesting a first operation, and output a command including the multiple second information portions; and a storage device, communicatively coupled to the host device and configured to receive the command from the host device, perform the first operation in response to the command, and perform corresponding portions of the multiple second operations based on the multiple second information portions in the command. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram illustrating a computing system based on an embodiment of the disclosed technology.

[0010] Figure 2 is a schematic diagram illustrating commands transmitted and received between a host device and a storage device according to an embodiment of the disclosed technology.

[0011] Figure 3 is a schematic diagram illustrating additional header segments according to an embodiment of the disclosed technology.

[0012] Figure 4 1 is a flowchart illustrating an example of performing a portion of a second operation to be requested after performing a first operation according to an embodiment of the disclosed technology.

[0013] Figure 5A and Figure 5B FIG. 1 is a diagram illustrating an example of performing a requested read operation after performing a first operation according to an embodiment of the disclosed technology.

[0014] Figure 6A and Figure 6B FIG. 1 is a diagram illustrating an example of performing a requested write operation after performing a first operation according to an embodiment of the disclosed technology.

[0015] Figure 7FIG. 1 is a diagram illustrating an example of providing error information to a host device according to an embodiment of the disclosed technology.

[0016] Figure 8 is a flowchart illustrating an example of performing a portion of each of a plurality of second operations to be requested after performing a first operation according to an embodiment of the disclosed technology.

[0017] Figure 9 is a flow chart illustrating a method of operating a computing system based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0018] The specific structural features or functions of certain embodiments disclosed in this patent document are examples that describe certain implementations of the disclosed technology.

[0019] The host device and storage device can communicate using data packets called protocol information units (PIUs). A PUI is a type of data packet generated according to a predefined standard. A PUI may include a basic header segment, transaction-specific fields, and an extra header segment (EHS). The host device and storage device can transmit data by including the data in the extra header segment of the PUI.

[0020] Figure 1 is a schematic diagram illustrating a computing system based on an embodiment of the disclosed technology.

[0021] Reference Figure 1 , the computing system 10 may include a storage device 100 that stores data and a host device 200 that communicates with the storage device 100 to access the data stored in the storage device. The host device 200 may include one or more processors to perform operations and write data to or receive data from the storage device 100. In some embodiments, the host device 200 may have various device configurations including: a cellular phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, an in-vehicle infotainment system, etc. In an embodiment, the computing system 10 may be an electronic system configured to process various types of information, such as: a mobile phone, a smart phone, an MP3 player, a laptop computer, a server computer, a desktop computer, a TV, a tablet PC, or an in-vehicle infotainment system.

[0022] In some embodiments, the storage device 100 may store data under the control of the host device 200 .

[0023] The memory device 100 may include a memory device 110 , a buffer memory 120 , and a memory controller 130 that controls operations of the memory device 110 and the buffer memory 120 .

[0024] The storage device 100 can be implemented as any of various storage devices, such as a solid-state drive (SSD), a multimedia card of the MMC or eMMC type, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a peripheral component interconnect (PCI) or PCI Express (PCI-Express) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick, depending on the communication method between the storage device 100 and the host device 200. In some embodiments discussed in this patent document, the memory device 110 is a UFS device.

[0025] The memory device 100 may be manufactured in any of various types of packaging. For example, the memory device 100 may be manufactured in any of the following types of packaging: package on package (POP), system-in-package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stacked package (WSP).

[0026] The memory device 110 can store data. The memory device 110 may include a plurality of memory blocks for storing data. Each memory block may include a plurality of memory cells.

[0027] In an embodiment, the memory device 110 may include multiple partitions. Each partition is a continuous area and may be a storage area that stores multiple pieces of data corresponding to continuous addresses input from the host device 200. Each of the multiple partitions may include multiple storage blocks. In an embodiment, the number of storage blocks included in each of the multiple partitions may be different from each other or the same as each other. Each partition may be a storage area corresponding to a logical address group composed of logical addresses input from the host device. Here, each logical address group may include continuous logical addresses.

[0028] In an embodiment, memory device 110 may be a non-volatile memory that retains data even if power is interrupted. In some embodiments discussed in this patent document, memory device 110 is a NAND flash memory.

[0029] In an embodiment, the memory device 110 may receive an internal command and an address from the memory controller 130. The internal command may be a command generated by the memory controller 130 to control the operation of the memory device 110 and the buffer memory 120. The memory device 110 may perform the operation indicated by the internal command on the area selected by the address. For example, the memory device 110 may perform a write operation (or program operation), a read operation, and an erase operation.

[0030] In an embodiment, the memory device 110 may store a mapping table including a mapping relationship between a logical address and a physical address provided from the host device 200. The mapping table may further include write pointer location information indicating a logical address of data to be stored in each partition. In some embodiments, a portion of the mapping table may be loaded into a memory included in the buffer memory 120 or the memory controller 130.

[0031] The buffer memory 120 may temporarily store data. For example, the buffer memory 120 may temporarily store data provided from the host device 200 or data read from the memory device 110.

[0032] In an embodiment, the buffer memory 120 may be a volatile memory that stores data only when power is supplied and loses the stored data when power is interrupted. For example, examples of the buffer memory 120 may include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0033] The memory controller 130 may control overall operations of the memory device 100 .

[0034] In an embodiment, the memory controller 130 may include a processor that executes firmware (FW), a memory that stores the firmware, a host interface that communicates with the host device 200 , a memory interface that communicates with the memory device 110 , and the like.

[0035] When power is supplied to the memory device 100, the memory controller 130 may execute firmware (FW). When the memory device 110 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host device 200, a flash translation layer (FTL) that controls communication between the host device 200 and the memory device 110, and a flash interface layer (FIL) that controls communication with the memory device 110.

[0036] In an embodiment, memory controller 130 may receive data and a logical block address (LBA) from host device 200 and may convert the logical block address (LBA) into a physical block address (PBA), which indicates the address of a memory cell included in memory device 110 and where the data is to be stored. In some embodiments discussed in this patent document, the term "logical block address" may be used to indicate a logical address. In some embodiments discussed in this patent document, the term "physical block address" may be used to indicate a physical address.

[0037] In an embodiment, the host device 200 may provide a logical address indicated by the position of a write pointer in the partition to which the corresponding logical address belongs. In one example, the logical address provided by the host device 200 may be a starting logical address of an operation corresponding to the request of the host device 200.

[0038] In an embodiment, the memory controller 130 may load a portion of the mapping table stored in the memory device 110 into the buffer memory 120 or a memory included in the memory controller 130. The memory controller 130 may convert the logical address provided from the host device 200 into a physical address mapped to the corresponding logical address based on the loaded mapping table. In addition, the memory controller 130 may update the mapping table by mapping the physical address to the logical address provided from the host device 200.

[0039] In an embodiment, the memory controller 130 may control the memory device 110 so that a write operation, a read operation, or an erase operation is performed in response to a request of the host device 200. For example, the memory controller 130 may provide the memory device 110 with an internal command, an address, and data required to perform the write operation, the read operation, or the erase operation.

[0040] The host device 200 may control the overall operation of the computing system 10. In some embodiments discussed in this patent document, the host device 200 communicates with the storage device 100 through a UFS communication method.

[0041] In an embodiment, the host device 200 may generate a command CMD corresponding to an input / output request and may transmit the generated command CMD to the memory device 100. Here, the input / output request may include a write request, a read request, or an erase request.

[0042] In an embodiment, the host device 200 may generate a command CMD including information for requesting an operation. For example, the host device 200 may generate a command CMD including a first information portion INFO1 for requesting a first operation and a second information portion INFO2 related to at least one of the second operations to be requested after requesting the first operation, or at least a portion of the second operation, and may output the generated command CMD including the first information portion INFO1 and the second information portion INFO2. In some embodiments, the host device may send a command CMD including the first information portion INFO1 for requesting the first operation and the second information portion INFO2 for requesting a portion of the second operation that is a subsequent operation of the first operation. In one example, the second information portion INFO2 related to the second operation may include a portion of the information for requesting the second operation. Here, when requesting a portion of each of multiple second operations, the command CMD may include multiple second information portions INFO2 respectively related to the multiple second operations.

[0043] In some embodiments, the first operation and the second operation can be the same type of operation or different types of operations.

[0044] In an embodiment, the memory device 100 may receive a command CMD from the host device 200 and may perform a first operation based on the first information portion INFO1 requesting the first operation in response to the command CMD. In addition, the memory device 100 may perform a portion of at least one second operation based on the second information portion INFO2 related to the at least one second operation included in the command CMD.

[0045] Figure 2 is a schematic diagram of commands sent and received between a host device and a storage device according to an embodiment of the disclosed technology.

[0046] In one embodiment, the command CMD may be a command defined in the Small Computer System Interface (SCSI) standard. In another embodiment, the command CMD may be a command defined in the UFS standard. For example, the command CMD may be composed of a protocol information unit (PIU). The PIU may include a command PIU, a response PIU, a data output PIU, a data input PIU, a prepare-transfer PIU, a mode sense PIU, a mode select PIU, a read buffer PIU, a write buffer PIU, and the like, depending on the desired operation to be performed by the host device 200 or the storage device 100.

[0047] like Figure 2As shown, the command CMD is implemented using the command PIU. In an embodiment, the host device 200 may send the command CMD through the command PIU, where the command CMD includes a first information part INFO1 for requesting a first operation and a second information part INFO2 related to a second operation.

[0048] Reference Figure 2 , the command CMD may include a basic header segment, a transaction specific field and an extra header segment (EHS).

[0049] The basic header segment may include information for enabling the host device 200 or the storage device 100 to determine whether a target and source, a function request or additional data and parameters are required; and / or whether additional data and parameters are included in the command CMD, etc.

[0050] For example, the basic header segment may include a transaction type, a flag, a logical unit number (LUN), a task tag, host device identification information, a command set type, an overall EHS length, and the like.

[0051] The transaction type may be information for defining the use of the data structure of the command CMD.

[0052] The flag may indicate the type of operation requested by the command CMD.

[0053] A LUN may represent a number for identifying a logical unit for accessing the storage device 100 by the host device 200. Here, a logical unit may represent an addressable storage area within the storage device. For example, a logical unit may represent at least one of a page, a memory block, a memory block group, a partition, a plane, or a die.

[0054] The task tag may represent information for identifying a request corresponding to the command CMD.

[0055] The command set type may indicate the type of commands included in a command descriptor block (CDB).

[0056] The overall EHS length may indicate the length of the additional header segments.

[0057] Transaction specific fields may include data transmission length, command descriptor block (CDB), etc.

[0058] The data transmission length may indicate the length of data transmitted from the host device 200 to the memory device 100 or from the memory device 100 to the host device 200 in response to the request of the command CMD. Here, the data transmission length may correspond to the length of the logical address.

[0059] A command descriptor block (CDB) may include information about various commands and addresses according to the type of the CDB. For example, the CDB may include a logical address corresponding to a command CMD.

[0060] In an embodiment, the host device 200 may include the first information part INFO1 for requesting the first operation in the basic header segment and the transaction specific field.

[0061] When the basic header segment does not have enough space to store data, the additional header segment may be used to additionally store at least a portion of the data.

[0062] In an embodiment, the host device 200 may include the second information part INFO2 related to the second operation in the additional header segment.

[0063] Although Figure 2 The host device 200 is shown to transmit a command CMD including both information for requesting the first operation and information related to the second operation via a command PIU, but the disclosed technology is not limited thereto. For example, the host device 200 may transmit a command CMD including both information for requesting the first operation and information related to the second operation via another type of PIU.

[0064] Figure 3 is a schematic diagram of additional header segments according to an embodiment of the disclosed technology.

[0065] Reference Figure 3 , the additional header segment may include a length field (Length), an EHS type field (EHSType), an EHS subtype field (EHSSubType) and an EHS data field (EHS data).

[0066] The 0th byte (0) of the additional header segment may be a length field. The length field (Length) may be a field having the total length of the additional header segment. In an embodiment, N may be "32×L-1". L may be the value stored in the length field.

[0067] The first byte of the additional header segment may correspond to the EHS Type field (EHSType). The EHS Type field (EHSType) may specify the type of the additional header segment. In an embodiment, the host device 200 may store a specific value in the EHS Type field (EHSType) indicating that the corresponding data is of a type used to request a second operation. In this case, the storage device 100 may recognize that the multiple pieces of data included in the header segment are multiple pieces of information used to request a second operation using the EHS Type field (EHSType).

[0068] The second and third bytes (2 and 3) of the additional header segment may correspond to an EHS subtype field (EHSSubType).

[0069] The fourth to N-th bytes (4 to N) of the additional header segment may correspond to an EHS data field (EHS data), and the EHS data field (EHS data) may include information related to the second operation.

[0070] In embodiments, the EHS data field (EHS data) may include flags related to the second operation, LUNs, task tags, host device identification information, data transmission length, logical addresses, various types of other CDBs, and the like. For example, the host device 200 may include a flag indicating the type of the second operation, such as a read operation or a write operation, in the EHS data field (EHS data). Furthermore, the host device 200 may include the LUN intended to be accessed for the second operation in the EHS data field (EHS data). Furthermore, the host device 200 may include a task tag identifying the request corresponding to the second operation in the EHS data field (EHS data). Furthermore, the host device 200 may include host device identification information in the EHS data field (EHS data). Furthermore, the host device 200 may include a data transmission length in the EHS data field (EHS data), indicating the length of data to be read during a read operation or the length of data to be stored during a write operation. Furthermore, the host device 200 may include a logical address in the EHS data field (EHS data), indicating the location where the second operation is to be performed.

[0071] In some embodiments, when there are multiple second operations, multiple additional header segments may be generated.

[0072] Figure 4 1 is a flowchart illustrating an example of performing a portion of a second operation to be requested after performing a first operation according to an embodiment of the disclosed technology. Figure 4 is a diagram illustrating a case where there is one subsequent operation to a first operation.

[0073] Reference Figure 4 At S41 , the host device 200 may send a first command CMD1 to the memory device 100 , the first command CMD1 including a first information portion INFO1 for requesting a first operation and a second information portion INFO2 related to a second operation.

[0074] At S42, the storage device 100 may perform the first operation and a portion of the second operation, and then send a response RESP1 to the first command CMD1 to the host device 200. The response RESP1 may be a signal indicating that the first command CMD1 has been processed and / or executed, and may be implemented using a response PIU.

[0075] At S43, the host device 200 may send a second command CMD2 to the memory device 100, the second command CMD2 including an additional second information portion INFO2' for requesting the second operation. For example, the additional second information portion INFO2' may be used to request the remaining second operations.

[0076] At S44, the memory device 100 may perform the remaining operations of the second operation except for the executed portion, and then transmit a response RESP2 to the second command CMD2 to the host device 200. In this case, since a portion of the second operation has been performed in advance in response to the first command CMD1, the time required for the memory device 100 to process or execute the second command CMD2 can be reduced.

[0077] Figure 5A and Figure 5B FIG. 1 is a diagram illustrating an example of performing a requested read operation after performing a first operation according to an embodiment of the disclosed technology. Figure 5A and Figure 5B It shows that when the second operation is a read operation Figure 4 In some embodiments, as shown in FIG. Figure 5A As shown, a portion of the second operation is performed, and as Figure 5B As shown, the remaining operations of the second operation except for this part are performed.

[0078] Reference Figure 4 and Figure 5A At S51, the host device 200 may send a first command CMD1 to the memory controller 130. The first command CMD1 includes a first information portion INFO1 for requesting a first operation and a second information portion INFO2 related to a second operation. Here, the second information portion INFO2 related to the second operation may include a logical address (LBA) corresponding to the second operation.

[0079] At S52 , after performing the first operation based on the first information portion INFO1 for requesting the first operation, the memory controller 130 may acquire a portion of the mapping table from the memory device 110 .

[0080] At S53 , the memory controller 130 may obtain, from the mapping table, a physical address (PBA) mapped to the logical address (LBA) corresponding to the second operation based on the second information portion INFO2 related to the second operation. For example, the memory controller 130 may obtain the logical address (LBA) corresponding to the second operation from the second information portion INFO2 related to the second operation. The memory controller 130 may convert the logical address (LBA) corresponding to the second operation into a physical address (PBA) based on the mapping table. Furthermore, when the second operation corresponds to a sequential read request, the memory controller 130 may identify the target partition for the second operation based on the partition identification information and may obtain the location information of the write pointer in the target partition based on the mapping table.

[0081] At S54 , the memory controller 130 may provide a physical address (PBA) together with the read command to the memory device 110 .

[0082] At S55 , the memory device 100 may read data DATA corresponding to the second operation from the memory device 110 based on the acquired physical address (PBA), and store the read data in the buffer memory 120 .

[0083] At S56 , the memory controller 130 may transmit a response RESP1 corresponding to the first command CMD1 to the host device 200 .

[0084] Reference Figure 4 and Figure 5B , at S57 , the host device 200 may transmit a second command CMD2 including an additional second information part INFO2 ′ for requesting a second operation to the memory controller 130 .

[0085] At S58 , the memory controller 130 may acquire data DATA corresponding to the second operation from the buffer memory 120 .

[0086] At S59, the memory controller 130 may transmit a response RESP2 corresponding to the second command CMD2 to the host device 200. Here, the response RESP2 may include data DATA corresponding to the second operation.

[0087] Figure 6A and Figure 6B FIG. 1 is a diagram illustrating an example of performing a requested write operation after performing a first operation according to an embodiment of the disclosed technology. Figure 6A and Figure 6B It shows that when the second operation is a write operation Figure 4 In some embodiments, as shown in Figure 6A As shown, a portion of the second operation is performed, and as Figure 6B As shown, the remaining operations of the second operation except for this part are performed.

[0088] Reference Figure 4 and Figure 6A At S61, the host device 200 may send a first command CMD1 to the memory controller 130. The first command CMD1 includes a first information portion INFO1 for requesting a first operation and a second information portion INFO2 related to a second operation. Here, the second information portion INFO2 related to the second operation may include a logical address (LBA) corresponding to the second operation.

[0089] At S62, after executing the first operation based on the first information portion INFO1 for requesting the first operation, the memory controller 130 may update the mapping table by mapping the physical address (PBA) to the logical address (LBA) corresponding to the second operation. When the second operation corresponds to a sequential write request, the memory controller 130 may identify the target partition of the second operation based on the partition identification information and may update the write pointer position information corresponding to the second operation in the mapping table.

[0090] At S63 , the memory controller 130 may transmit mapping information LBA-PBA between the logical address (LBA) and the physical address (PBA) to the memory device 110 .

[0091] At S64 , the memory controller 130 may control the buffer memory 120 to allocate a buffer area AREA in the buffer memory 120 that will temporarily store data corresponding to the second operation.

[0092] At S65 , the buffer memory 120 may allocate a buffer area AREA under the control of the memory controller 130 .

[0093] At S66 , the memory controller 130 may transmit a response RESP1 corresponding to the first command CMD1 to the host device 200 .

[0094] Reference Figure 4 and Figure 6B At S67, the host device 200 may transmit a second command CMD2 including an additional second information part INFO2' for requesting a second operation to the memory controller 130. Here, the second command may include write data DATA corresponding to the second command CMD2.

[0095] At S68 , the memory controller 130 may control the buffer memory 120 to store the write data DATA in a pre-allocated area AREA in the buffer memory 120 .

[0096] At S69 , the memory controller 130 may transmit a response RESP2 corresponding to the second command CMD2 to the host device 200 .

[0097] Figure 7 FIG. 1 is a diagram illustrating an example of providing error information to a host device according to an embodiment of the disclosed technology.

[0098] Reference Figure 4 and Figure 7 At S71 , the host device 200 may send a first command CMD1 to the memory device 100 , the first command CMD1 including a first information portion INFO1 for requesting a first operation and a second information portion INFO2 related to a second operation.

[0099] After performing a first operation based on the first information portion INFO1 for requesting the first operation, the storage device 100 may determine whether an error is expected to occur during the second operation based on the second information portion INFO2 related to the second operation. If it is determined that an error is expected to occur, the storage device 100 may transmit information about the error to the host device 200.

[0100] For example, at S72 , the storage device 100 may detect an error based on the second information part INFO2 related to the second operation.

[0101] Here, when the data is erroneous or invalid, for example, when the flag, LUN, task tag, host device identification information, data transmission length, and logical address included in the second information portion INFO2 related to the second operation are erroneous or invalid, the storage device 100 can detect the error. In addition, when a read failure occurs when performing a part of the second operation, the storage device 100 can detect the error.

[0102] At S73, the memory device 100 may transmit a response RESP1 corresponding to the first command CMD1 to the host device 200. Here, the response RESP1 may include information about the error. Thereafter, in an embodiment, the host device 200 may correct the error data included in the second information portion INFO2 related to the second operation based on the information about the error, and may transmit an additional second information portion INFO2′ including the corrected data for requesting the second operation to the memory device 100 when requesting the second operation.

[0103] Figure 8 is a flowchart illustrating an example of performing a portion of each of a plurality of second operations to be requested after performing a first operation according to an embodiment of the disclosed technology. Figure 81 is a schematic diagram illustrating a case where there are a plurality of subsequent operations of a first operation. Hereinafter, description will be made assuming that the first operation, the second operation, and the third operation are sequentially performed.

[0104] Reference Figure 8 At S81 , the host device 200 may send a first command CMD1 to the storage device 100 , the first command CMD1 including a first information portion INFO1 for requesting a first operation, a second information portion INFO2 related to a second operation, and information INFO3 related to a third operation.

[0105] At S82 , the memory device 100 may perform the first operation, a portion of the second operation, and a portion of the third operation, and then transmit a response RESP1 to the first command CMD1 to the host device 200 .

[0106] Thereafter, the host device 200 may generate a plurality of commands for requesting a plurality of subsequent operations, respectively, and may sequentially transmit the plurality of commands to the storage device 100. In addition, the storage device 100 may sequentially perform the remaining operations excluding a portion of the corresponding subsequent operations among the plurality of subsequent operations in response to the plurality of commands.

[0107] At S83, the host device 200 may send a second command CMD2 to the memory device 100, the second command CMD2 including an additional second information portion INFO2' for requesting the second operation. For example, the additional second information portion INFO2' may be used to request the remaining second operations.

[0108] At S84, the storage device 100 may perform the remaining operations of the second operation except for the portion, and then transmit a response RESP2 to the second command CMD2 to the host device 200. In this case, since a portion of the second operation has been performed in advance in response to the first command CMD1, the time required for the storage device 100 to process or execute the second command CMD2 can be reduced.

[0109] At S85 , the host device 200 may transmit a third command CMD3 to the memory device 100 , the third command CMD3 including information INFO3 ′ for requesting a third operation.

[0110] At S86, the storage device 100 may perform the remaining operations of the third operation except for the portion, and then transmit a response RESP3 to the third command CMD3 to the host device 200. In this case, since a portion of the third operation has been performed in advance in response to the first command CMD1, the time required for the storage device 100 to process the third command CMD3 can be reduced.

[0111] Figure 9 is a flow chart illustrating a method of operating a computing system based on an embodiment of the disclosed technology. Figure 9 The method shown can be used by, for example Figure 1 The computing system 10 shown executes.

[0112] Reference Figure 9 At S901, the computing system 10 may generate a first command, the first command including information for requesting a first operation and information related to a second operation to be requested after the first operation. For example, the computing system 10 may include the information related to the second operation in an additional header segment included in the first command.

[0113] At S903 , the computing system 10 may send a first command to the storage device 100 .

[0114] At S905 , the computing system 10 may perform a first operation in response to the first command.

[0115] At S907 , the computing system 10 may execute a portion of the second operation based on the information related to the second operation in response to the first command.

[0116] For example, when the second operation is a read operation, the computing system 10 may convert the logical address corresponding to the second operation into a physical address mapped to the logical address based on information related to the second operation. In addition, the computing system 10 may pre-acquire data corresponding to the second operation based on the physical address.

[0117] In an example, when the second operation is a write operation, the computing system 10 may map the physical address to a logical address corresponding to the second operation. In addition, the computing system 10 may allocate a buffer area that will temporarily store data corresponding to the second operation.

[0118] At S909 , the computing system 10 may transmit a response signal corresponding to the first command to the host device 200 .

[0119] At S911 , the computing system 10 may generate a second command including information for requesting a second operation.

[0120] At S913 , the computing system 10 may send a second command to the storage device 100 .

[0121] At S915 , the computing system 10 may perform remaining operations of the second operation except the portion in response to the second command.

[0122] In an example, when the second operation is a read operation, the computing system 10 may send the pre-fetched data to the host device 200 .

[0123] In an example, when the second operation is a write operation, the storage device 100 of the computing system 10 may receive data corresponding to the second operation from the host device 200 and store the data corresponding to the second operation in the pre-allocated buffer area. In addition, when the storage device 100 receives a flush request from the host device 200, the storage device 100 may store the data corresponding to the second operation stored in the buffer area in the storage area corresponding to the pre-mapped physical address.

[0124] In this way, the command processing speed of a computing system implemented based on some embodiments of the disclosed technology can be improved.

[0125] The embodiments and implementations disclosed above are merely examples, and thus various enhancements and modifications may be made to the disclosed embodiments and implementations and other embodiments and implementations based on what is described and illustrated in this patent document.

Claims

1. A computing system comprising: a host device, generating a command including information associated with an operation to be requested, the information including a first information portion associated with a first operation among the operations and a second information portion associated with a second operation to be requested after the first operation, and outputting a command including the first information portion and the second information portion; as well as A storage device stores data and communicates with the host device, wherein the storage device receives the command from the host device, performs the first operation in response to the command, and performs a portion of the second operation based on a second information portion in the command.

2. The computing system of claim 1, wherein The command includes a basic header segment, a transaction specific field and an extra header segment, namely, an EHS; and The host device includes the first information in the basic header segment and the transaction specific field, and includes the second information in the additional header segment.

3. The computing system of claim 1 , wherein the second information portion comprises one or more of a logical address corresponding to the second operation, a length of the logical address, a type of the second operation, identification information of a storage area to be accessed during the second operation, or identification information of the host device.

4. The computing system of claim 3, wherein the storage device comprises: a memory device storing a mapping table, the mapping table including a mapping relationship between a logical address provided from the host device and a physical address of the memory device; as well as A buffer memory temporarily stores data provided from the host device or data read from the memory device. 5 . The computing system of claim 4 , wherein in a case where the second operation is a read operation, the storage device acquires a physical address mapped to a logical address corresponding to the second operation from the mapping table based on the second information portion. 6 . The computing system according to claim 5 , wherein the storage device reads data corresponding to the second operation from the memory device based on the acquired physical address and stores the read data in the buffer memory. 7 . The computing system of claim 4 , wherein in a case where the second operation is a write operation, the storage device updates the mapping table by mapping a physical address to a logical address corresponding to the second operation. 8 . The computing system according to claim 4 , wherein in a case where the second operation is a write operation, the storage device allocates a buffer area in the buffer memory for temporarily storing data corresponding to the second operation. 9 . The computing system of claim 1 , wherein the storage device performs the first operation and a portion of the second operation and then sends a response to the command to the host device.

10. The computing system of claim 1, wherein the storage device determines whether an error is expected to occur during the second operation based on the second information portion; and sends information about the error to the host device when it is determined that the error is expected to occur.

11. A method of operating a computing system, comprising: generating, by a host device, a first command including information associated with an operation to be requested, the information including a first information portion associated with the first operation and a second information portion associated with a second operation to be requested subsequent to the first operation; The host device sends the first command to a storage device storing data; performing, by the storage device, the first operation in response to the first command; performing, by the storage device in response to the first command, a portion of the second operation based on the second information portion; The storage device sends a response to the first command to the host device; generating, by the host device, a second command including the second information portion; The host device sends the second command to the storage device; as well as The remaining operations of the second operation except the portion are performed by the storage device in response to the second command.

12. The method of claim 11, wherein generating the first command comprises: The second information portion is inserted into an extra header segment, ie, EHS, included in the first command.

13. The method of claim 11, wherein performing a portion of the second operation comprises: In response to the second operation being a read operation, converting a logical address corresponding to the second operation into a physical address mapped to the logical address based on the second information portion; as well as Data corresponding to the second operation is pre-fetched based on the physical address.

14. The method of claim 13, wherein performing the remaining operations comprises: The pre-fetched data is sent to the host device.

15. The method of claim 11, wherein performing a portion of the second operation comprises: In a case where the second operation is a write operation, in response to the second operation, mapping the physical address to a logical address corresponding to the second operation; as well as A buffer area for temporarily storing data corresponding to the second operation is allocated.

16. The method of claim 15, wherein performing the remaining operations comprises: receiving data corresponding to the second operation from the host device; storing data corresponding to the second operation in the buffer area; as well as In response to a flush request of the host device, the data corresponding to the second operation stored in the buffer area is stored in a storage area corresponding to the physical address.

17. A computing system comprising: a host device that inserts a plurality of second information parts associated with a plurality of second operations into a command for requesting the first operation, and outputs a command including the plurality of second information parts; as well as A storage device is communicatively coupled to the host device, the storage device receives the command from the host device, performs the first operation in response to the command, and performs corresponding parts of the plurality of second operations based on a plurality of second information parts in the command.

18. The computing system of claim 17, wherein the host device receives a response to the command from the storage device; generates a plurality of commands for requesting the plurality of second operations, respectively; and sequentially sends the plurality of commands to the storage device. 19 . The computing system of claim 18 , wherein the storage device sequentially performs remaining operations among the plurality of second operations except for corresponding parts of the plurality of second operations in response to the plurality of commands.

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