High-speed data interaction method and device of ink-jet printer and storage medium

Abstract

The invention discloses a high-speed data interaction method and device of an ink-jet printer and a storage medium. The method comprises the following steps that S1, a data buffer area is arranged between transmission channels of an FPGA and an MCU; s2, the MCU initializes the state of a data buffer area; s3, the MCU obtains the data blocks from the printing task queue and transmits the data blocks to a data buffer area; s4, the MCU sends a write-in completion signal to the FPGA through the control line; s5, after the FPGA receives the write-in completion signal, reading the data from the data buffer area for processing; s6, after reading is completed, the FPGA feeds back a reading completion signal to the MCU through the control line so as to prepare for next data exchange, the high-speed DRAM is introduced to serve as a data cache region, the data transmission architecture between the MCU and the FPGA is optimized, the bandwidth bottleneck problem of a traditional data bus is effectively solved, and the data exchange efficiency is improved. And the overall system response speed and the printing efficiency of the digital ink-jet printer are greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of printers, and in particular to a high-speed data interaction method, device and storage medium of an inkjet printer. Background Art

[0002] In modern digital inkjet printer systems, data exchange between microcontroller units (MCUs) and field programmable gate arrays (FPGAs) is an important part of achieving efficient printing. However, with the continuous enhancement of printer functions and the increase in printing speed, the demand for data transmission between MCUs and FPGAs is also increasing. In this process, traditional data bus architectures usually face the following problems:

[0003] Bandwidth bottleneck: The existing bus architecture often suffers from insufficient bandwidth during frequent data transmission. Since a large amount of data needs to be transmitted at high speed between the MCU and FPGA, the traditional bus bandwidth cannot meet this requirement, resulting in low data transmission rate and affecting the overall performance of the printer.

[0004] Data transmission rate mismatch: MCU and FPGA have differences in data processing capabilities and operating frequencies. When transmitting data, the traditional bus connection architecture is prone to data congestion or transmission delays due to rate mismatch, which leads to poor data flow during the printing process and affects printing efficiency.

[0005] Slow system response speed: Due to the limitations of the bus architecture, under high-load printing tasks, data transmission delays and rate mismatch problems become more serious, resulting in a decrease in the printer's system response speed, affecting user experience and production efficiency.

[0006] These technical defects have severely restricted the performance and application scope of digital inkjet printers, especially in scenarios that require high-speed, large data volume transmission, where traditional architectures can no longer meet the requirements for efficient printing. Therefore, there is an urgent need for a new data exchange architecture that can increase data transmission rates, alleviate bandwidth bottlenecks, and reduce system latency, in order to improve the overall performance and printing efficiency of digital inkjet printers. Summary of the invention

[0007] In order to solve the above-mentioned technical problems, the present invention provides a high-speed data interaction method, device and storage medium for an inkjet printer.

[0008] The technical solution of the present invention is achieved in this way:

[0009] A high-speed data interaction method for an inkjet printer is as follows:

[0010] S1, set up a data buffer between the transmission channels of FPGA and MCU;

[0011] S2, the state of the MCU initializing the data buffer;

[0012] S3, MCU obtains the data block from the print task queue and transfers the data block to the data buffer;

[0013] S4, after the transmission of step S3 is completed, the MCU sends a write completion signal to the FPGA through the control line;

[0014] S5, after receiving the write completion signal, FPGA reads data from the data buffer for processing;

[0015] S6, after the reading is completed, the FPGA feeds back a reading completion signal to the MCU through the control line to prepare for the next data exchange.

[0016] Preferably, the data buffer is specifically a high-speed DRAM, and the FPGA and MCU respectively implement data interaction with the DRAM through a plurality of control lines.

[0017] Preferably, the plurality of control lines specifically include read / write enable lines, address lines, and data lines.

[0018] Preferably, a synchronization circuit is added between the MCU and the FPGA, specifically a bistable trigger is used to build a synchronizer, a control signal from the MCU is used as an input of the synchronizer, and a clock signal of the synchronizer matches the system clock of the FPGA.

[0019] Preferably, in step S2, the MCU initializes the state of the data buffer, specifically by clearing the memory space in the data buffer.

[0020] Preferably, the data buffer further includes the following data processing steps:

[0021] L1, MCU reads DRAM status and sends data information to DRAM. After DRAM confirms that it is ready, MCU starts to send data blocks;

[0022] L2, after the MCU sends the data block, it sends the information to the DRAM to confirm the complete transmission;

[0023] L3, MCU triggers the synchronization circuit, FPGA sends a request signal to DRAM, and DRAM starts sending data to FPGA after confirming that it is ready;

[0024] The DRAM state includes a read-write state, and the read-write state is specifically to determine whether the storage unit of the DRAM can meet the current read-write demand;

[0025] In the DRAM, multiple levels of cache areas are also set up, namely, a first-level cache area, a second-level cache area and a third-level cache area. The first-level cache area and the second-level cache area are read-write areas, and the third-level cache area is a data transmission area. Data exchange between the first-level cache area and the second-level cache area is transmitted through the third-level cache area.

[0026] A device for high-speed data interaction of an inkjet printer comprises at least one processor, at least one memory and computer program instructions stored in the memory. When the computer program instructions are executed by the processor, the method for high-speed data interaction of the inkjet printer is implemented.

[0027] A storage medium stores computer program instructions, characterized in that when the computer program instructions are executed by a processor, the method for high-speed data interaction of the above-mentioned inkjet printer is implemented.

[0028] The present invention effectively solves the bandwidth bottleneck problem of the traditional data bus by introducing high-speed DRAM as a data cache area and optimizing the data transmission architecture between the MCU and the FPGA, thereby greatly improving the overall system response speed and printing efficiency of the digital inkjet printer. The control line multiplexing technology is adopted to ensure that the data exchange between the MCU and the FPGA can be carried out efficiently and synchronously, which significantly reduces the delay of data transmission, improves the continuity of the data flow and the smoothness of the printing process. Through the efficient data exchange mechanism and the improvement of real-time processing capabilities, the printer can better control the ink output and printing accuracy, thereby improving the quality of printed output and meeting high-end printing needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of a high-speed data interaction method of an inkjet printer of the present invention. DETAILED DESCRIPTION

[0030] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0031] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0032] Example 1

[0033] like Figure 1 The present invention provides a high-speed data interaction method for an inkjet printer, as follows:

[0034] S1, set up a data buffer between the transmission channels of FPGA and MCU, which serves as the key hub for data interaction between the two and improves the stability and efficiency of data transmission;

[0035] Preferably, the data buffer is specifically a high-speed DRAM, and the FPGA and MCU respectively implement data interaction with the DRAM through a plurality of control lines; a high-frequency, low-latency DRAM module is used as an intermediate cache. The capacity of DRAM should be selected according to the data processing requirements of the printer, usually between 256MB and 2GB, which can effectively alleviate the bottleneck problem that may be caused by the difference in data transmission rate between FPGA and MCU, and create a good environment for stable data transmission. Through reasonable hardware connection and circuit design, ensure that DRAM can accurately access the data transmission link between FPGA and MCU, making it the core hub for data interaction between the two, thereby significantly improving the stability and efficiency of the entire data transmission system;

[0036] S2, the state of MCU initializing the data buffer. The MCU performs initialization operations on the data buffer, and the core step is to thoroughly clean up the memory space in the data buffer. During the initialization process, the MCU first performs a comprehensive scan of the memory address of the data buffer and resets the content of each storage unit to a preset initial value, usually set to zero or a specific invalid data mark. This operation can effectively clear the historical data, random noise data, or erroneous data generated by system abnormalities that may remain in the buffer, minimizing the risk of data transmission errors;

[0037] S3, MCU obtains the data block from the print task queue, transfers the data block to the data buffer, MCU reads the DRAM status, and obtains the current working status information of DRAM through the specific communication protocol and control signal interaction with DRAM, including the occupancy of storage units, the preparation status of data writing, etc. Only after DRAM confirms that it is ready, that is, it has sufficient storage space and the internal circuit is in a stable writable state, the MCU will officially start the data block sending process. After the data block is sent, the MCU sends information to DRAM again. This information is used to clearly inform DRAM that the data has been sent completely. This confirmation information helps DRAM to perform internal data management and status updates, such as marking data storage locations, updating storage unit occupancy information, etc., to provide accurate metadata support for subsequent data reading and processing;

[0038] S4, after the transmission of step S3 is completed, the MCU sends a write completion signal to the FPGA through the control line. When the data is successfully transmitted to the data buffer, the MCU sends a write completion signal to the FPGA through the control line. This control line is an important communication line between the FPGA and the MCU, responsible for transmitting various control signals and status information. As a key trigger signal, the write completion signal can effectively coordinate the working rhythm of the FPGA and the MCU with its accurate and timely transmission, and notify the FPGA that the data buffer is ready for reading, thereby triggering the subsequent FPGA data reading operation, ensuring the continuity and efficiency of the data interaction process;

[0039] S5, after receiving the write completion signal, FPGA reads data from the data buffer for processing. After receiving the write completion signal from the MCU, FPGA starts the process of reading data from the data buffer for subsequent processing.

[0040] Before reading data, FPGA needs to send a request signal to DRAM. This request signal contains the specific address information of the data required by FPGA, data volume information, and control instructions for the read operation. After receiving the request signal from FPGA, DRAM first parses and verifies the request information to confirm the legality and validity of the request. Subsequently, DRAM checks its own working status and the readiness of the storage unit. Only after confirming that everything is ready, it starts to transmit data to FPGA according to the requirements of FPGA. In this process, data is transmitted through carefully designed data lines and interfaces to ensure high speed and stability of data.

[0041] S6, after the reading is completed, the FPGA feeds back the read completion signal to the MCU through the control line to prepare for the next data exchange. After the data reading is completed, the FPGA feeds back the read completion signal to the MCU through the control line. This feedback signal, as an important end mark of this data exchange, can promptly inform the MCU that the FPGA has successfully acquired the data and completed the related processing operations, and the data buffer can receive new data to be written again. This feedback mechanism helps to establish a stable data interaction cycle, ensuring that the data exchange between the FPGA and the MCU can be carried out continuously and efficiently.

[0042] Preferably, the plurality of control lines specifically include read-write enable lines, address lines, and data lines. The read-write enable lines are key control signal lines for data read-write operations, and their level states determine the data transmission direction and operation type. When the read-write enable lines are in a specific level combination, they can trigger the read operation or write operation of the DRAM respectively, ensuring that the data is transmitted in the correct manner at the correct time. The address line is responsible for determining the specific storage location or reading location of the data in the DRAM. By sending precise address encoding information on the address line, the MCU or FPGA can accurately locate a specific storage unit in the DRAM to achieve fixed-point read and write operations of the data. The width of the address line is closely related to the storage capacity and addressing mode of the DRAM. Reasonable design of the number of bits of the address line can optimize the efficiency and speed of data transmission while meeting the storage requirements. The data line is responsible for the transmission of actual data, and its data width determines the parallelism and data volume of each data transmission. Wider data lines can transmit more data bits in the same clock cycle, thereby significantly improving the data transmission rate. During the data transmission process, the data line needs to have good electrical characteristics and signal integrity to ensure accurate and error-free transmission of data and avoid data errors caused by signal interference or attenuation.

[0043] Preferably, a synchronization circuit is added between the MCU and the FPGA, specifically a bistable trigger is used to build a synchronizer, a control signal from the MCU is used as an input of the synchronizer, and a clock signal of the synchronizer matches the system clock of the FPGA.

[0044] Preferably, in step S2, the MCU initializes the state of the data buffer, specifically by clearing the memory space in the data buffer.

[0045] Preferably, the data buffer further includes the following data processing steps:

[0046] L1, MCU reads DRAM status and sends data information to DRAM. After DRAM confirms that it is ready, MCU starts to send data blocks;

[0047] L2, after the MCU sends the data block, it sends the information to the DRAM to confirm the complete transmission;

[0048] L3, MCU triggers the synchronization circuit, FPGA sends a request signal to DRAM, and DRAM starts sending data to FPGA after confirming that it is ready;

[0049] The DRAM state includes a read-write state, and the read-write state is specifically to determine whether the storage unit of the DRAM can meet the current read-write demand;

[0050] In the DRAM, multiple levels of cache are also set, namely, the first-level cache, the second-level cache and the third-level cache. The first-level cache and the second-level cache are read-write areas, and the third-level cache is a data transmission area. The data exchange between the first-level cache and the second-level cache is transmitted through the third-level cache. The first-level cache and the second-level cache are read-write areas and bear the main data reading and writing functions. The first-level cache usually has a small capacity but a very high access speed. Its design purpose is to quickly respond to data read and write requests from FPGA or MCU, and store the most frequently used data in the near future or the data blocks to be processed. The capacity of the second-level cache is relatively large, and the speed is slightly lower than that of the first-level cache. It is used to cache data overflowed from the first-level cache due to capacity limitations or relatively less urgent data to balance the storage and access efficiency of data. The third-level cache is a data transmission area, which is responsible for the data exchange transmission between the first-level cache and the second-level cache. When the first-level cache needs to exchange data with the second-level cache, the data is first transmitted to the third-level cache, and then forwarded to the target cache by the third-level cache. This multi-level cache structure can effectively optimize the data storage and transmission process, improve the efficiency and speed of data processing through hierarchical management and dynamic allocation of cached data, and reduce the delays and performance losses that may be caused by frequent direct access to DRAM storage units.

[0051] Preferably, in the data processing of the DRAM, the read and write tasks are classified according to their impact on the real-time and performance of the printing system. For example, data reading tasks related to the real-time control of the nozzle (such as the current position of the nozzle, the reading of the ink remaining monitoring data, etc.) can be classified as high-priority real-time tasks, because these data directly affect the continuity and quality of printing; and some read and write tasks for background printing task management or non-critical configuration data can be classified as low-priority tasks. The read and write tasks are classified according to their impact on the real-time and performance of the printing system. For example, data reading tasks related to the real-time control of the nozzle (such as the current position of the nozzle, the reading of the ink remaining monitoring data, etc.) can be classified as high-priority real-time tasks, because these data directly affect the continuity and quality of printing; and some read and write tasks for background printing task management or non-critical configuration data can be classified as low-priority tasks. When the task is in the waiting queue, the priority is recalculated regularly (for example, every 10 milliseconds) according to the above formula. When a new task is added or the task status changes (such as an increase in data volume or an increase in waiting time), the priority is also updated in time. This ensures that high-priority tasks are processed at the appropriate time, and prevents low-priority tasks from occupying resources for a long time and causing delays in high-priority tasks.

[0052] The MCU continuously monitors the status of the print task queue, including the number of tasks, task priority, and data volume information of each task. When there are multiple tasks in the task queue and the data of the subsequent tasks are ready (for example, the data received from the network has reached a certain amount or the data parsing of the locally stored data has been completed), the timing of pre-writing begins to be evaluated. For example, if there are three print tasks in the task queue, and the data of the second task has been completely received in the local cache, and the first task is in the process of transferring data to DRAM and has transferred more than 50%, then the data of the second task can be considered for pre-writing, and the priority distribution of the tasks can be analyzed. If the high-priority task is about to be completed and the data volume of the low-priority task is large, the low-priority task is pre-written at the end of the high-priority task, so that the processing can be quickly switched to the low-priority task after the high-priority task is completed, reducing the overall task switching time. For example, the high-priority text printing task is about to end, and the low-priority image printing task has a large data volume. When the last few lines of data of the text printing task are transferred, the image printing task data is pre-written to DRAM, and the resource utilization of the system is monitored in real time, including CPU utilization, data bus bandwidth utilization, and DRAM free space. When the system resource utilization is at a relatively low level, for example, the CPU utilization is less than 60%, the data bus bandwidth utilization is less than 70%, and the free space of DRAM is greater than 1.5 times the amount of data to be pre-written, the pre-write operation is triggered. This ensures that the pre-write operation does not compete for resources with other ongoing critical tasks, avoids system performance degradation, and considers the stability of data transmission. If there are no errors or delays in the current data transmission, and the system clock signal is stable and not subject to external interference, then the pre-write operation can be performed if the resource conditions are met. For example, by monitoring the error check code of the data transmission (such as the CRC check result), if the check results are correct for multiple consecutive times and the jitter of the system clock is within the allowable range, the pre-write can be started.

[0053] Preferably,

[0054] Dynamically adjust the amount of pre-written data according to the free space of DRAM. First, obtain the current free space size of DRAM, and then determine a pre-write ratio coefficient based on the system load and the urgency of subsequent tasks. For example, if the DRAM free space is 500MB, the system load is light and the subsequent tasks are of medium priority, the pre-write ratio coefficient can be set to 0.3, and the amount of pre-written data is 150MB. However, it is necessary to ensure that there is still enough space in DRAM after pre-writing for other tasks (such as FPGA data reading operations) to proceed normally. Generally, 20%-30% of free space is reserved as a buffer.

[0055] Consider the integrity of the data block. Try to pre-write in complete data blocks to avoid splitting a data block into multiple pre-write operations. For example, if the print data is organized in the form of pixel rows of images or paragraphs of text, each pre-write should ensure that it is a complete pixel row or paragraph. This can reduce the processing complexity of the FPGA when reading data later and improve data processing efficiency.

[0056] Frequency Control

[0057] Set a minimum time interval threshold, such as 10 milliseconds. There must be at least this threshold time interval between two pre-write operations. This can avoid excessive occupation of system resources and confusion in data transmission caused by too frequent pre-write operations. At the same time, adjust this threshold according to the urgency of the task and the amount of data. For urgent tasks with small amounts of data, the threshold time can be appropriately shortened, but it cannot be lower than the minimum value for the system to run stably, such as 5 milliseconds; for non-urgent tasks with large amounts of data, the threshold time can be extended to 20 milliseconds or even longer.

[0058] Frequency control is performed in combination with the data transmission rate. If the current data transmission rate is fast, it means that the system has sufficient bandwidth resources. If other conditions are met, the pre-write frequency can be appropriately increased; conversely, if the data transmission rate is slow, the pre-write frequency can be reduced to ensure the overall stability of the system. For example, when the data transmission rate is higher than 100MB / s, the pre-write frequency can be once every 8 milliseconds; when the transmission rate is lower than 50MB / s, the pre-write frequency is adjusted to once every 15 milliseconds.

[0059] Error handling and recovery

[0060] During the pre-writing process, each data block is error-checked, such as using CRC or ECC. If an error is found during the check, the pre-writing operation is stopped immediately and the data block is marked as an error state. At the same time, whether to perform data recovery operations is determined based on the type and severity of the error. For some correctable errors, such as single-bit errors that ECC can handle, you can try to continue pre-writing after correcting the error in situ; for uncorrectable errors, such as serious damage to the data block, you need to re-acquire the data of the data block, which may be downloaded from the network or re-read from local storage, and then perform the pre-writing operation again.

[0061] Establish an error recording mechanism to record error information that occurs during the pre-writing process, including the error type, the time when the error occurred, the location of the error data block, etc. Analyze these error records regularly to optimize the parameter settings and data processing flow of the pre-writing operation and improve the reliability and stability of the pre-writing operation. For example, if it is found that a certain type of task often has errors during pre-writing, it may be a data format conversion problem. Optimize the data format conversion module for this task to reduce the probability of errors.

[0062] A device for high-speed data interaction of an inkjet printer comprises at least one processor, at least one memory and computer program instructions stored in the memory. When the computer program instructions are executed by the processor, the method for high-speed data interaction of the inkjet printer is implemented.

[0063] A storage medium stores computer program instructions, characterized in that when the computer program instructions are executed by a processor, the method for high-speed data interaction of the above-mentioned inkjet printer is implemented.

[0064] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A high-speed data exchange method for an inkjet printer, characterized in that: The steps include: S1, set up a data buffer between the transmission channels of FPGA and MCU; S2, the state of the MCU initializing the data buffer; S3, MCU obtains the data block from the print task queue and transfers the data block to the data buffer; S4, after the transmission of step S3 is completed, the MCU sends a write completion signal to the FPGA through the control line; S5, after receiving the write completion signal, FPGA reads data from the data buffer for processing; S6, after the reading is completed, the FPGA feeds back a reading completion signal to the MCU through the control line to prepare for the next data exchange.

2. The high-speed data exchange method of an inkjet printer according to claim 1, characterized in that: The data buffer is specifically a high-speed DRAM, and the FPGA and MCU respectively implement data interaction with the DRAM through a plurality of control lines.

3. The high-speed data exchange method of an inkjet printer according to claim 1, characterized in that: The plurality of control lines specifically include read / write enable lines, address lines, and data lines.

4. The high-speed data exchange method of an inkjet printer according to claim 1, characterized in that: A synchronization circuit is added between the MCU and the FPGA, specifically a bistable trigger is used to build a synchronizer, and a control signal from the MCU is used as an input of the synchronizer. The clock signal of the synchronizer matches the system clock of the FPGA.

5. The high-speed data exchange method of an inkjet printer according to claim 1, characterized in that: In step S2, the MCU initializes the state of the data buffer, specifically clearing the memory space in the data buffer.

6. The high-speed data exchange method of an inkjet printer according to claim 1, characterized in that: In the data buffer, the following data processing steps are also included: L1, MCU reads DRAM status and sends data information to DRAM. After DRAM confirms that it is ready, MCU starts to send data blocks; L2, after the MCU sends the data block, it sends the information to the DRAM to confirm the complete transmission; L3, MCU triggers the synchronization circuit, FPGA sends a request signal to DRAM, and DRAM starts sending data to FPGA after confirming that it is ready; The DRAM state includes a read-write state, and the read-write state is specifically to determine whether the storage unit of the DRAM can meet the current read-write demand; In the DRAM, multiple levels of cache areas are also set up, namely, a first-level cache area, a second-level cache area and a third-level cache area. The first-level cache area and the second-level cache area are read-write areas, and the third-level cache area is a data transmission area. Data exchange between the first-level cache area and the second-level cache area is transmitted through the third-level cache area.

7. A device for high-speed data interaction of an inkjet printer, comprising at least one processor, at least one memory and computer program instructions stored in the memory, wherein when the computer program instructions are executed by the processor, the method described in any one of claims 1 to 6 is implemented.

8. A storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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