An integer-to-floating-point transfer and conversion fused instruction set processor

Abstract

The application relates to an integer-to-floating-point transmission and conversion fusion instruction set processor, which comprises an instruction emission control component for sending instruction control information; a memory execution component for generating target register write port information according to the instruction control information, generating instruction execution completion information and delivering the information to an instruction submission component; an integer execution component for decoding the instruction control information to obtain first instruction execution control information, and further reading integer source operands from an integer register file; and a floating-point execution component for decoding the first instruction execution control information to obtain second instruction execution control information, and further converting the integer source operands into floating-point numbers according to the second instruction execution control information and writing the floating-point numbers into a floating-point register file, and generating exception code information according to an exception state generated in the conversion process and delivering the exception code information to the instruction submission component. The application can improve the processing efficiency of the processor for integer-to-floating-point transmission and conversion.

Description

Technical Field

[0001] This invention relates to the field of processor design, and in particular to an instruction set processor that integrates integer-to-floating-point transfer and conversion. Background Technology

[0002] In processors, integers are typically stored in memory or integer registers, while floating-point numbers are typically stored in memory or floating-point registers. Modern processor microarchitectures usually employ separate integer and floating-point register files. Integer operations primarily manipulate the integer registers, and floating-point operations primarily manipulate the floating-point registers. To conserve the number of read / write ports for register files, a direct read / write path between the integer and floating-point register files is typically not provided; instead, other data paths are used. If a floating-point instruction requires an integer from an integer register, multiple instructions are needed. Typically, an integer-to-floating-point transfer instruction is used to transfer the integer from the integer register to the floating-point register, and then an integer-to-floating-point instruction is used to convert the integer stored in the floating-point register back to a floating-point number. This transfer and conversion method requires at least two instructions to achieve the transfer and conversion between floating-point and integer numbers. This not only wastes instruction processing resources in the processor's instruction unit and reduces instruction processing efficiency, but also significantly increases the execution latency of data transfer and conversion due to the need to read and write registers twice, which is detrimental to improving processor performance. To improve processor performance, it is necessary to explore a method to speed up the transfer and conversion of integers to floating-point numbers. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an instruction set processor that integrates integer-to-floating number transmission and conversion, which can improve the processor's processing efficiency for integer-to-floating number transmission and conversion.

[0004] The technical solution adopted by this invention to solve its technical problem is: to provide an instruction set processor that integrates integer-to-floating-point number transmission and conversion, comprising:

[0005] The instruction issuance control unit is used to send instruction control information for integer-to-floating-point conversion instructions to the corresponding execution unit;

[0006] The memory access execution unit is used to generate target register write port information based on the instruction control information, generate instruction execution completion information and pass it to the instruction submission unit;

[0007] An integer execution unit is used to decode the instruction control information to obtain first instruction execution control information, and to read integer source operands from an integer register file according to the first instruction execution control information;

[0008] The floating-point execution unit is used to decode the first instruction execution control information to obtain the second instruction execution control information, then convert the integer source operand into a floating-point number according to the second instruction execution control information, generate exception encoding information according to the exception state generated during the conversion process, write the converted floating-point number result into a floating-point register file according to the write port control information, and pass the exception encoding information to the instruction submission unit.

[0009] Furthermore, the integer execution unit includes:

[0010] A first decoder is used to decode the instruction control information to obtain the first instruction execution control information;

[0011] The integer register read control module is used to generate read port control information for the integer register file according to the first instruction execution control information, and to read the integer source operand from the integer register file according to the read port control information.

[0012] Furthermore, the floating-point execution unit includes:

[0013] The second decoder is used to decode the first instruction execution control information to obtain the second instruction execution control information;

[0014] The floating-point control status register is used to set the floating-point trap control bit, the rounding mode control bit, and the floating-point exception status bit according to the exception status during the conversion from integer to floating-point number.

[0015] An integer-to-floating-point number conversion sub-component is used to convert the integer source operand into a floating-point number according to the second instruction execution control information, the floating-point exception trap control bit and the rounding mode control bit to obtain the floating-point number result, and generate exception encoding information according to the exception state in the conversion process and pass it to the instruction submission component.

[0016] The floating-point register write control module is used to write the floating-point number result into the floating-point register file according to the write port control information.

[0017] Furthermore, the floating-point exception trap control bit is used to set the handling strategy when an exception occurs during the integer to floating-point conversion process, the rounding mode control bit is used to set the rounding mode of the result of the integer to floating-point conversion, and the floating-point exception status bit is used to record the exception status that occurs during the integer to floating-point conversion process.

[0018] Furthermore, the integer-to-floating-point transfer conversion sub-component includes:

[0019] The third decoder is used to decode the second instruction execution control information to obtain the third instruction execution control information, which includes the instruction type, the integer format to be converted, the converted floating-point format, and the result rounding mode.

[0020] A complementer is used to convert a signed negative integer to a positive number.

[0021] The selector is used to select the data generated by the complementer when the signed integer to be converted is negative; otherwise, it selects the integer to be converted with the data bit width expanded to the set bit width as the data for subsequent operations.

[0022] A zero-heading detector is used to detect the number of zero-heading data generated by the selector and determine the initial value of the exponent of the floating-point number after transmission conversion.

[0023] A shifter is used to shift the data generated by the selector to the left according to the number of leading zeros, so as to form the initial value of the mantissa of the floating-point number after transmission conversion;

[0024] The rounding module performs a rounding operation on the initial value of the mantissa generated by the shifter according to the converted floating-point format and the result rounding mode, corrects the initial value of the exponent generated by the head-zero detector, generates the converted floating-point result, and detects abnormal coding information in the conversion process.

[0025] The result selector selects to output the floating-point result or the exception encoding information based on the third instruction execution control information.

[0026] Furthermore, the anomaly encoding information includes:

[0027] Inaccurate result anomaly, used to indicate that the true values ​​of the integer to be converted and the floating-point result are not equal;

[0028] A floating-point overflow exception is used to indicate that the value of the integer to be transmitted exceeds the representation range of the converted floating-point format.

[0029] Furthermore, the integers to be transmitted and converted include 64-bit unsigned long word integers, 32-bit unsigned word integers, 16-bit unsigned half-word integers, and 64-bit signed long word integers, 32-bit signed word integers, and 16-bit signed half-word integers represented in two's complement. The integer register file includes several 64-bit integer registers, each of which stores one of the integers to be transmitted and converted as a 64-bit integer source operand. The unsigned word integers are stored in the lower 32 bits of the integer registers, with the higher 32 bits padded with zeros. The signed word integers are stored in the lower 32 bits of the integer registers, with the higher 32 bits extended by the sign bit. The unsigned half-word integers are stored in the lower 16 bits of the integer registers, with the higher 48 bits padded with zeros. The signed half-word integers are stored in the lower 16 bits of the integer registers, with the higher 48 bits extended by the sign bit.

[0030] Furthermore, the instruction control information for the integer-to-floating-point transfer conversion instruction is sent by the integer storage instruction data transmission port STD.

[0031] Furthermore, the integer-to-float transfer conversion instruction, the integer-to-float transfer instruction, and the integer storage data instruction share the same integer storage instruction data transmission port (STD) of the instruction issuance control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data lines, and address lines of the integer register file; the integer-to-float transfer conversion instruction and the integer-to-float transfer instruction share the data path from the integer execution unit to the floating-point execution unit; the integer-to-float transfer conversion instruction, the integer-to-float transfer instruction, and the floating-point load instruction share the same write port, data lines, and address lines of the floating-point register file.

[0032] Furthermore, the floating-point register file includes several 64-bit floating-point registers, each of which stores one double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers. Each of the double-precision floating-point numbers, single-precision floating-point numbers, and half-precision floating-point numbers can be used independently. The half-precision floating-point numbers include FP16 half-precision floating-point numbers and BF16 half-precision floating-point numbers.

[0033] Beneficial effects

[0034] By adopting the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0035] (1) This invention integrates the functions of the original integer to floating-point number transfer instruction and integer to floating-point number conversion instruction, without adding new data paths, integer register read ports and floating-point register write ports. Integer to floating-point number transfer conversion can be achieved with a single instruction, which expands the function of a single instruction, speeds up the execution speed of integer to floating-point number transfer and conversion in the processor, and thus improves the processor performance.

[0036] (2) The integer to floating-point number transfer conversion instruction proposed in this invention saves processor instruction processing resources, increases instruction processing efficiency, and eliminates the need for two register reads and writes, making the execution delay of the transfer conversion operation less than the sum of the execution delays of the original transfer instruction and conversion instruction, which is conducive to speeding up the execution speed and thus improving the processor's computing performance.

[0037] (3) This invention not only supports the conversion of long word integers and word integers to double-precision floating-point numbers and single-precision floating-point numbers, but also supports the conversion of word integers and half-word integers to half-precision floating-point numbers. Furthermore, it reuses the same conversion circuit for different data formats, which not only saves hardware costs, but also helps to improve the applicability of the processor in emerging fields such as artificial intelligence. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure of the integer-to-floating-point number conversion sub-component according to an embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0041] Embodiments of the present invention relate to an instruction set processor that integrates integer-to-floating-point transfer and conversion, such as... Figure 1 As shown, it includes:

[0042] The instruction unit (101) includes an internal first-level instruction cache and its access control, used to fetch instructions from the instruction cache or the next level cache or even main memory, and to decode the fetched instructions.

[0043] The instruction issue control unit (102) includes register renaming and issue control, which is used to implement the mapping of all instruction logical registers to physical registers, correlation detection and issue control, and sets up multiple issue ports for different instruction types, corresponding to different execution units;

[0044] Integer storage instruction data dispatch queue (103) is used to control and dispatch integer storage (Store) instruction data and integer to floating-point number conversion instructions. The storage (Store) instruction address and data dispatch are separated. The storage (Store) instruction address is dispatched and executed through the dispatch queue calculated by the memory access instruction address. The storage (Store) instruction data is dispatched and executed through a dedicated data dispatch queue.

[0045] The integer register file (104) is used to store integer source operands and operation results. It has multiple read ports to provide source operands for integer operations and multiple write ports to write back the register results for integer operations or integer load instructions. This component contains 32 integer registers, each with a bit width of 64 bits. Unsigned word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are padded with zeros. Signed word integers are stored in the lower 32 bits of the integer register, and the upper 32 bits are extended by the sign bit. Unsigned half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are padded with zeros. Signed half-word integers are stored in the lower 16 bits of the integer register, and the upper 48 bits are extended by the sign bit.

[0046] The integer execution unit (105) is used to receive instruction execution requests, read source operands from the integer register file (104) or receive data input from other units, perform arithmetic operations according to the instructions, obtain the execution results and write them back to the integer register file (104) or output them to other units, and pass the instruction execution completion information to the instruction submission unit (115). The instruction submission unit (115) is often called ROB (Reorder Buffer).

[0047] The first decoder (106) is used to decode the received instructions and generate control information for instruction execution;

[0048] The read integer register control module (107) is used to generate read port control information for the integer register file (104) based on the instruction execution control information, including read enable and read register number, as well as bypass selection control signals, etc.

[0049] The memory access execution unit (108) is used to process memory access instructions from the instruction issuance control unit (102), complete the memory access address calculation, access the internal first-level data cache, determine whether the data cache is hit, and if it is not hit, it needs to further generate a request to access the next level cache or main memory, and submit the instruction execution completion information to the instruction submission unit (115); for integer to floating-point transfer instructions and transfer and conversion fusion instructions, no address calculation or data cache access is required. It is only used to receive instruction execution requests, receive data input from other units or read source operands from the floating-point register file (114), perform arithmetic operations according to the instructions, obtain the execution result and write it back to the floating-point register file (114) or output it to other units, and pass the instruction execution completion information to the instruction submission unit (115); among them, instruction submission and writing back to the register file are completed by borrowing the report completion interface of the memory access instruction execution and the write port of the Load instruction to write the floating-point register file;

[0050] The floating-point execution unit (109) is used to receive instruction execution requests, receive data input from other units or read source operands from the floating-point register file (114), perform arithmetic operations according to instructions, obtain execution results and write them back to the floating-point register file (114) or output them to other units, and pass instruction execution completion information to the instruction submission unit (115).

[0051] The second decoder (110) is used to further decode the received floating-point arithmetic instructions and generate the control information required for the execution of the floating-point instructions;

[0052] The Floating-Point Control Register (111) contains information such as the floating-point exception status bit, rounding mode bit, floating-point exception trap control bit, and control bits for special data. It is also called the FPCR (Floating-Point Control Register). When converting from an integer to a floating-point number, the result needs to be rounded according to the floating-point rounding mode bit. If an exception occurs during the integer to floating-point conversion, exception code information needs to be generated, the exception status bit of the FPCR needs to be registered, and the floating-point exception trap control bit needs to be used to determine whether an arithmetic trap is generated and then processed in software.

[0053] The integer-to-floating-point conversion sub-component (112) is used to convert the integer transmitted from the integer execution unit (105) into a floating-point number output based on the instruction execution control information generated by the second decoder (110) and the status information of the floating-point control status register (111), as well as to process exception information and generate an exception code for the execution result; wherein, if the integer to be converted and the actual value of the converted floating-point number are not equal, the instruction for integer-to-floating-point conversion will result in an inaccurate result exception; if the value of the integer to be converted exceeds the representable range of the converted floating-point format, the instruction for integer-to-floating-point conversion will result in a floating-point overflow exception.

[0054] The floating-point register write control module (113) is used to select, according to the instruction control information, to write the execution result of the integer to floating-point transfer conversion instruction, the integer to floating-point transfer instruction, or the floating-point load instruction to the floating-point register file (114).

[0055] The floating-point register file (114) is used to store floating-point source operands and operation results. It has multiple read ports to provide source operands for floating-point operations and multiple write ports to write back the register results for floating-point operations or floating-point load instructions. This component contains 32 floating-point registers, each with a bit width of 64 bits. It can store one double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers. Instructions can also use only one single-precision floating-point number (lower 32 bits) or one half-precision floating-point number (lower 16 bits) at a time.

[0056] The instruction submission unit (115) is used to receive instruction completion information submitted by the integer, floating-point or memory access execution unit and complete the instruction exit according to the program sequence.

[0057] This instruction set processor supports a unified instruction set for integer-to-floating-point transfer and conversion, used to transfer integers from integer registers and convert them to floating-point numbers in floating-point registers. The source register of this instruction set is an integer register, the source operand is an integer, the destination register is a floating-point register, and the execution result is a floating-point number.

[0058] The specific instructions are shown in Table 1:

[0059] Table 1. An instruction set for the integration of integer-to-floating-point transfer and conversion.

[0060] Serial Number Command mnemonics Instruction Description Instruction format 1 CMOVLD Signed long word integer transmission converted to double-precision floating-point instructions CMOVLDRa.rl,Fb.wd 2 CMOVLS Signed long word integer transmission converted to single-precision floating-point instructions CMOVLSRa.rl,Fb.ws 3 CMOVULD Unsigned long word integer transfer converted to double-precision floating-point instructions CMOVULDRa.rl,Fb.wd 4 CMOVULS Unsigned long word integer transfer converted to single-precision floating-point instruction CMOVULSRa.rl,Fb.ws 5 CMOVWD Signed word integer transmission converted to double-precision floating-point instructions CMOVWDRa.rw,Fb.wd 6 CMOVWS Signed word integer transfer converted to single-precision floating-point instructions CMOVWSRa.rw,Fb.ws 7 CMOVUWD Unsigned word integer transfer converted to double-precision floating-point instructions CMOVUWDRa.rw,Fb.wd 8 CMOVUWS Unsigned word integer transfer converted to single-precision floating-point instructions CMOVUWSRa.rw,Fb.ws 9 CMOVWHF Signed word integer transmission converted to half-precision floating-point instructions CMOVWHFRa.rw,Fb.wh 10 CMOVUWHF Unsigned word integer transfer converted to half-precision floating-point instruction CMOVUWHFRa.rw,Fb.wh 11 CMOVHHF Signed half-word integer transfer converted to half-precision floating-point instructions CMOVHHFRa.rh,Fb.wh 12 CMOVUHHF Unsigned half-word integer transfer converted to half-precision floating-point instruction CMOVUHHFRa.rh,Fb.wh

[0061] Signed integers are represented and stored using two's complement, while unsigned integers are represented using sign-magnitude representation. The integers to be converted include unsigned long word integers, unsigned word integers, unsigned half-word integers, and signed long word integers, signed word integers, and signed half-word integers represented using two's complement. The floating-point numbers to be generated include double-precision floating-point numbers, single-precision floating-point numbers, FP16 half-precision floating-point numbers, and BF16 half-precision floating-point numbers. Double-precision floating-point numbers include 1 sign bit (S), 11 exponents (E), and 52 mantissas (F); single-precision floating-point numbers include 1 sign bit (S), 8 exponents (E), and 23 mantissas (F); FP16 half-precision floating-point numbers include 1 sign bit (S), 5 exponents (E), and 10 mantissas (F); and BF16 half-precision floating-point numbers include 1 sign bit (S), 8 exponents (E), and 7 mantissas (F).

[0062] The instruction for integer-to-floating-point transfer and conversion supports four rounding modes defined by the IEEE-754 floating-point standard: rounding to nearest, rounding to zero, rounding to positive infinity, and rounding to negative infinity. The rounding mode can be directly determined by the instruction code or dynamically controlled by the rounding mode control bit in FPCR.

[0063] Integer-to-floating-point conversion instructions are executed through the following components:

[0064] The integer storage instruction transmission port of the integer storage instruction data transmission queue (103) in the instruction issuance control unit (102) transmits an integer to floating-point number transfer conversion instruction, and the instruction control information is simultaneously sent to the memory access execution unit (108) and the integer execution unit (105);

[0065] The memory access execution unit (108) generates the execution completion information of the integer to floating-point transfer conversion instruction according to the instruction control information and passes it to the instruction submission unit (115). At the same time, it generates the target register write port control information and passes it to the floating-point execution unit (109).

[0066] The integer execution unit (105) reads the source operands from the integer register file (104) according to the instruction control information, and passes the read data and instruction control information to the floating-point execution unit (109);

[0067] The integer-to-floating-point conversion sub-component (112) in the floating-point execution unit (109) completes the integer-to-floating-point conversion and exception handling under the control of instruction control information and floating-point control status register (111), generates the converted floating-point result and exception code, and submits the exception code to the instruction submission unit (115); the floating-point register write control module (113) selects to write the execution result of the integer-to-floating-point conversion instruction, the integer-to-floating-point transfer instruction or the floating-point load instruction to the floating-point register file (114) according to the instruction control information.

[0068] Among them, the same instruction launch port of the integer-to-float transfer conversion instruction and the integer-to-float transfer instruction, and the integer storage instruction multiplexing instruction launch control unit (102), and the same instruction completion port of the multiplexing instruction submission unit (115); the same read port, data lines and address lines of the integer-to-float transfer conversion instruction and the integer-to-float transfer instruction, and the integer storage instruction multiplexing integer register file (104); the data transmission lines of the integer-to-float transfer conversion instruction and the integer-to-float transfer instruction multiplexing integer execution unit (105) to floating-point execution unit (109); the same write port, data lines and address lines of the integer-to-float transfer conversion instruction and the integer-to-float transfer instruction, and the floating-point load instruction multiplexing floating-point register file (114).

[0069] Considering that the representation ranges of signed half-word integers and signed word integers are both subsets of signed long word integers, the conversion process can extend the signed half-word integers and signed word integers to signed long word integers by the sign bit, and then reuse the conversion circuit for signed long word integers. Similarly, the representation ranges of unsigned half-word integers and unsigned word integers are both subsets of unsigned long word integers, and the conversion process can extend the unsigned half-word integers and unsigned word integers to unsigned long word integers, and then reuse the conversion circuit for unsigned long word integers. Furthermore, since the conversion of signed long word integers to floating-point numbers mainly involves only one additional step compared to the conversion of unsigned long word integers to floating-point numbers—namely, calculating the absolute value—the instructions for integer-to-floating-point conversion can reuse the same set of conversion circuits, such as... Figure 2 As shown, the integer-to-floating-point transfer conversion sub-component (112) includes:

[0070] Decoder (201) decodes instruction execution control information, determines the instruction type, the integer data format to be transmitted and converted, the data format after transmission and conversion, and the rounding mode encoding;

[0071] The complementer (202) performs the complement operation by inverting and adding 1, converting the signed negative integer to be converted into a positive number. The complementer (202) has a bit width of 64 bits.

[0072] If the signed integer to be converted is negative, select the data generated by the complementer (202); otherwise, select the integer to be converted with a data width extended to 64 bits as the data for subsequent operations.

[0073] A zero-head detector (204) detects the number of zero-heads in the data generated by the selector (203) and determines the initial exponent of the floating-point result after transmission conversion.

[0074] The shifter (205) performs a left shift operation on the data generated by the selector (203) based on the number of leading zeros generated by the leading zero detector (204) to form the initial value of the mantissa of the floating-point number after transmission conversion. The bit width of the shifter (205) is 64 bits.

[0075] The rounding module (206) performs a rounding operation on the initial value of the mantissa generated by the shifter (205) according to the data format and rounding mode encoding after transmission conversion generated by the decoder (201), corrects the initial value of the exponent generated by the head zero detector (204), detects abnormal conversion results, and generates the converted floating-point result and result abnormal information.

[0076] The result selector (207) selects the converted floating-point number or the abnormal result as the result output according to the instruction execution control information generated by the decoder (201), and outputs the corresponding abnormal code.

[0077] Referring to this embodiment, the present invention can be used with various types of processors, including general-purpose CPUs, GPUs, and dedicated processors.

Claims

1. A processor with an instruction set that integrates integer-to-floating-point number transfer and conversion, characterized in that, include: The instruction issuance control unit is used to send instruction control information for integer-to-floating-point conversion instructions to the corresponding execution unit; The memory access execution unit is used to generate target register write port control information based on the instruction control information, generate instruction execution completion information and pass it to the instruction submission unit; An integer execution unit is used to decode the instruction control information to obtain first instruction execution control information, and to read integer source operands from an integer register file according to the first instruction execution control information; The floating-point execution unit is used to decode the first instruction execution control information to obtain the second instruction execution control information, and then convert the integer source operand into a floating-point number according to the second instruction execution control information, generate exception encoding information according to the exception state generated during the conversion process, write the converted floating-point number result into a floating-point register file according to the write port control information, and pass the exception encoding information to the instruction submission unit. The integer-to-float transfer conversion instruction, the integer-to-float transfer instruction, and the integer storage data instruction share the same integer storage instruction data transmission port STD of the instruction issuance control unit, the same load instruction completion port of the instruction submission unit, and the same read port, data lines, and address lines of the integer register file; The integer-to-floating-point conversion instruction and the integer-to-floating-point transmission instruction reuse the data path from the integer execution unit to the floating-point execution unit; The integer-to-float conversion instruction and the integer-to-float load instruction share the same write port, data lines, and address lines of the floating-point register file.

2. The processor according to claim 1, characterized in that, The integer execution unit includes: A first decoder is used to decode the instruction control information to obtain the first instruction execution control information; The integer register read control module is used to generate read port control information for the integer register file according to the first instruction execution control information, and to read the integer source operand from the integer register file according to the read port control information.

3. The processor according to claim 1, characterized in that, The floating-point execution unit includes: The second decoder is used to decode the first instruction execution control information to obtain the second instruction execution control information; The floating-point control status register is used to set the floating-point trap control bit, the rounding mode control bit, and the floating-point exception status bit according to the exception status during the conversion from integer to floating-point number. An integer-to-floating-point number conversion sub-component is used to convert the integer source operand into a floating-point number according to the second instruction execution control information, the floating-point exception trap control bit and the rounding mode control bit to obtain the floating-point number result, and generate exception encoding information according to the exception state in the conversion process and pass it to the instruction submission component. The floating-point register write control module is used to write the floating-point number result into the floating-point register file according to the write port control information.

4. The processor according to claim 3, characterized in that, The floating-point exception trap control bit is used to set the handling strategy when an exception occurs during the integer to floating-point conversion process. The rounding mode control bit is used to set the rounding mode of the result of the integer to floating-point conversion. The floating-point exception status bit is used to record the exception status that occurs during the integer to floating-point conversion process.

5. The processor according to claim 3, characterized in that, The integer-to-floating-point conversion sub-component includes: The third decoder is used to decode the second instruction execution control information to obtain the third instruction execution control information, which includes the instruction type, the integer format to be converted, the converted floating-point format, and the result rounding mode. A complementer is used to convert a signed negative integer to a positive number. The selector is used to select the data generated by the complementer when the signed integer to be converted is negative; otherwise, it selects the integer to be converted with the data bit width expanded to the set bit width as the data for subsequent operations. A zero-heading detector is used to detect the number of zero-heading data generated by the selector and determine the initial value of the exponent of the floating-point number after transmission conversion. A shifter is used to shift the data generated by the selector to the left according to the number of leading zeros, so as to form the initial value of the mantissa of the floating-point number after transmission conversion; The rounding module performs a rounding operation on the initial value of the mantissa generated by the shifter according to the converted floating-point format and the result rounding mode, corrects the initial value of the exponent generated by the head-zero detector, generates the converted floating-point result, and detects abnormal coding information in the conversion process. The result selector selects to output the floating-point result or the exception encoding information based on the third instruction execution control information.

6. The processor according to claim 5, characterized in that, The anomaly encoding information includes: Inaccurate result anomaly, used to indicate that the actual values ​​of the integer to be converted and the floating-point result are not equal; A floating-point overflow exception is used to indicate that the value of the integer to be transmitted exceeds the representation range of the converted floating-point format.

7. The processor according to claim 1, characterized in that, The integers to be transmitted and converted include 64-bit unsigned long word integers, 32-bit unsigned word integers, 16-bit unsigned half-word integers, and 64-bit signed long word integers, 32-bit signed word integers, and 16-bit signed half-word integers represented in two's complement. The integer register file includes several 64-bit integer registers, each of which stores one of the integers to be transmitted and converted as a 64-bit integer source operand. The unsigned word integers are stored in the lower 32 bits of the integer registers, with the higher 32 bits padded with zeros. The signed word integers are stored in the lower 32 bits of the integer registers, with the higher 32 bits extended by the sign bit. The unsigned half-word integers are stored in the lower 16 bits of the integer registers, with the higher 48 bits padded with zeros. The signed half-word integers are stored in the lower 16 bits of the integer registers, with the higher 48 bits extended by the sign bit.

8. The processor according to claim 1, characterized in that, The instruction control information for the integer-to-floating-point conversion instruction is sent by the integer storage instruction data transmission port STD.

9. The processor according to claim 1, characterized in that, The floating-point register file includes several 64-bit floating-point registers. Each floating-point register stores one double-precision floating-point number, two single-precision floating-point numbers, or four half-precision floating-point numbers. Each double-precision floating-point number, single-precision floating-point number, and half-precision floating-point number can be used independently. The half-precision floating-point numbers include FP16 half-precision floating-point numbers and BF16 half-precision floating-point numbers.

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