Operation task processing method and device, computer equipment and storage medium

Abstract

The invention relates to an operation task processing method and device, computer equipment and a storage medium. The method comprises the steps of obtaining an operation task processing list, wherein the operation task processing list at least comprises one operation task; according to at least one operation task contained in the operation task processing list and the task processing state of the first processor, determining a target operation task which does not meet the task processing state; and in response to the target operation task executed by the first processor in the operation task processing list, sending hardware interruption to a second processor to instruct the second processor to execute the target operation task. By adopting the method, multiple operation tasks can be completed without frequent intervention of a third party.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a computing task method, device, computer equipment, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, NPU (Network Processing Unit), as an ASIC (Application-Specific Integrated Circuit) chip, provides powerful computing power support for the deployment of artificial neural networks. With the iterative development of technology, artificial intelligence models have more outstanding data processing effects in various fields. But with it comes the complexity of the model and the increase in the computing power required for the model. The quantized integer data model has gradually been unable to meet the needs of high-precision models, so some floating-point operations are retained in many models. In order to reduce the computing pressure of the NPU and enhance the overall computing power of the chip, a high-performance DSP (Digital Signal Processor) is usually integrated into the chip, which can significantly improve the overall computing power of the chip.

[0003] In order to enable the NPU in heterogeneous chips to promptly distribute part of the computing pressure to the DSP, the CPU needs to participate in the process of NPU calling the DSP to process tasks. When the NPU encounters multiple high-precision computing tasks, the CPU needs to intervene frequently, which increases the time consumption of a large number of non-computing tasks and reduces the overall computing performance. Summary of the invention

[0004] Based on this, it is necessary to provide a computing task method, device, computer equipment, and storage medium to address the above technical issues.

[0005] In a first aspect, the present disclosure provides a method for processing a computing task. The method comprises:

[0006] Obtaining a computing task processing list, wherein the computing task processing list includes at least one computing task;

[0007] Determining a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and a task processing status of the first processor;

[0008] In response to the first processor executing the target computing task in the computing task processing list, a hardware interrupt is issued to the second processor to instruct the second processor to execute the target computing task.

[0009] In one embodiment, after determining the target computing task, the method further includes:

[0010] Acquire task information of the target computing task;

[0011] Generate task description information of the target computing task based on the task information, the task description information includes a plurality of operator attributes, the operator attributes include: task type, source data address, target data address, source data type, source data dimension, target data type, target data dimension and structure size;

[0012] The task description information is serialized into a binary file, and an error detection code is added to the binary file.

[0013] In one embodiment, adding an error detection code to the binary file includes:

[0014] determining a target value of the error detection code, and adding the error detection code to the binary file based on the target value;

[0015] Alternatively, in the process of serializing the task description information including a plurality of operator attributes, a target position for serialization at a preset time is determined, and the error detection code is added at the target position.

[0016] In one embodiment, issuing a hardware interrupt to the second processor to instruct the second processor to execute the target computing task includes:

[0017] Sending a hardware interrupt to the second processor to instruct the second processor to read the binary file, deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determining that the result of deserialization is correct, executing the target computing task according to the deserialization result, obtaining a computing result, and sending the computing result to the first processor;

[0018] Receive the operation result fed back by the second processor.

[0019] In one embodiment, the method further comprises:

[0020] In response to receiving a hardware interrupt issued by the second processor, stopping processing the target computing task; the hardware interrupt issued by the second processor is issued by the second processor when the value of the error detection code is different from the value read by deserialization;

[0021] It is determined that an error occurs in the process of processing the target computing task, and error debugging is performed based on the error detection code.

[0022] In one embodiment, the task processing status includes: a task processing type and a task processing quantity; and determining, based on at least one computing task included in the computing task processing list and the task processing status of the first processor, a target computing task that does not satisfy the task processing status includes:

[0023] Determining a target computing task according to a computing task whose task type is not matched with the task processing type of at least one computing task included in the computing task processing list;

[0024] And / or, at least one computing task included in the computing task processing list is screened in sequence according to the task processing quantity, and at least one computing task remaining in the task processing list after the task processing quantity is met is determined as the target computing task.

[0025] In a second aspect, the present disclosure further provides a computing task processing method, which is applied to a second processor, and the method includes:

[0026] In response to receiving a hardware interrupt issued by the first processor, a binary file is read; wherein the binary file is generated by the first processor according to at least one computing task included in the computing task processing list and the task processing state of the first processor, and the target computing task that does not meet the task processing state is determined; and the binary file contains an error detection code;

[0027] Deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of the deserialization is correct;

[0028] The target computing task is executed according to the deserialization result to obtain a computing result, and the computing result is sent to the first processor.

[0029] In one embodiment, the method further comprises:

[0030] In response to the value of the error detection code being different from the value read by deserialization, a hardware interrupt is issued to the first processor to instruct the first processor to determine that an error occurs in the process of processing the target computing task and to perform error debugging based on the error detection code.

[0031] In a third aspect, the present disclosure further provides a computing task processing device, applied to a first processor, the device comprising:

[0032] A task acquisition module, used to acquire a computing task processing list, wherein the computing task processing list contains at least one computing task;

[0033] a task determination module, configured to determine a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and the task processing status of the first processor;

[0034] The interrupt module is used to issue a hardware interrupt to the second processor in response to the first processor executing the target computing task in the computing task processing list, so as to instruct the second processor to execute the target computing task.

[0035] In a fourth aspect, the present disclosure further provides a computing task processing device, applied to a second processor, the device comprising:

[0036] an information reading module, configured to read a binary file in response to receiving a hardware interrupt issued by the first processor; wherein the binary file is generated by the first processor according to at least one computing task included in the computing task processing list and the task processing state of the first processor, and a target computing task that does not satisfy the task processing state; and the binary file contains an error detection code;

[0037] A deserialization module, configured to deserialize the binary file, and determine that a result of the deserialization is correct in response to the value of the error detection code being the same as the value read by the deserialization;

[0038] A computing task execution module is used to execute the target computing task according to the deserialization result, obtain the computing result, and send the computing result to the first processor.

[0039] In a fifth aspect, the present disclosure further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps in any of the above method embodiments are implemented.

[0040] In a sixth aspect, the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0041] In the above embodiments, when the first processor executes the tasks in the computing task processing list, once it finds the target computing task that does not meet its own task processing status, it can transfer it to the second processor for execution. This avoids the processing capacity bottleneck problem that may occur when a single processor faces complex and diverse computing tasks. In particular, when facing a processing list containing a large number of computing tasks of different types, the advantages and idle resources of the two processors can be fully utilized to achieve parallel processing and effectively improve the overall computing efficiency. The target computing task is determined and transferred according to the task processing status of the processor, so that the system can dynamically adjust the task allocation according to the real-time busyness, performance characteristics and other factors of the processor. For example, when the load of the first processor is high and some computing tasks may be delayed in execution, such tasks are transferred to the relatively idle second processor, ensuring that the computing tasks can be processed more timely, so that the processor resources of the entire system can be more fully and reasonably utilized, and the situation of idle or overused resources can be reduced. In addition, the first processor and the second processor communicate through hardware interrupts, and the whole process does not require the intervention of a third party, so that the interaction between the first processor and the second processor can be realized. The first processor uses hardware interrupts to call the second processor, and the response speed is fast. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the specific embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 An application environment diagram of a computing task processing method in an embodiment;

[0044] Figure 2 A flowchart of a computing task processing method in one embodiment;

[0045] Figure 3 A flowchart of steps after determining a target computing task in one embodiment;

[0046] Figure 4 A flowchart of error debugging steps in an embodiment;

[0047] Figure 5 Schematic diagram of the process of step S204 in one embodiment;

[0048] Figure 6 is a flowchart of a computing task processing method in another embodiment;

[0049] Figure 7 is a structural block diagram of a computing task processing device in one embodiment;

[0050] Figure 8 is a structural block diagram of a computing task processing device in another embodiment;

[0051] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not used to limit the present disclosure.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of this article and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of this article described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0054] In this article, the term "and / or" is only a description of the association relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the related objects before and after are in an "or" relationship.

[0055] As described in the background technology, in the traditional process of NPU calling DSP, NPU needs to initiate a request to CPU, and then CPU schedules DSP to perform calculations. After the calculation is completed, CPU feeds back the result to NPU and starts NPU to perform subsequent calculation tasks. In this process, it is necessary to frequently switch between NPU, CPU and DSP, which increases the time consumption of many non-calculation tasks, reduces the linkage between NPU and DSP, and increases the complexity of calculation tasks. In addition, NPU initiates task requests to CPU through instruction bus, and then CPU calls DSP to perform calculations, which increases the pressure of bus.

[0056] The present disclosure provides a method for processing a computing task, which can be applied to Figure 1In the application environment shown. Among them, the first processor 102 can be connected to the second processor 104. The first processor 102 can obtain a computing task processing list, and the computing task processing list contains at least one computing task; the first processor 102 determines the target computing task according to at least one computing task contained in the computing task processing list and the task processing state of the first processor; in response to the first processor 102 executing the target computing task in the computing task processing list, a hardware interrupt is issued to the second processor 104 to instruct the second processor 104 to execute the target computing task.

[0057] In one embodiment, Figure 2 As shown, a computing task processing method is provided, which is applied to Figure 1 Taking the first processor 102 in the example as an example, the method includes the following steps:

[0058] S202, obtaining a computing task processing list, wherein the computing task processing list includes at least one computing task.

[0059] Among them, the calculation task processing list can be a data structure used to orderly list the tasks that need to be calculated and processed. It can be compared to a task list, except that each item in the list involves a specific work content related to a certain calculation, such as mathematical calculations, logical operations in data processing, etc. For example, in a financial data analysis system, the calculation task processing list may include tasks such as calculating the total monthly expenses of each department and calculating the annual profit growth rate; in an image recognition system, it may include tasks such as performing specific algorithm operations on image pixels to extract features. In some embodiments of the present disclosure, the specific scenario to which the calculation processing list belongs is not limited. The calculation task refers to a specific work unit that needs to perform a certain calculation operation. This calculation operation can be a very simple basic mathematical operation, such as addition, subtraction, etc., or it can be a complex logical operation (for example: single-precision floating-point calculation task, half-precision floating-point calculation task, etc.), function call, etc., which have specific meanings and processes in different application scenarios. For example, in a promotion calculation scenario of an e-commerce platform, the calculation task may be to calculate the amount that the end user actually needs to pay based on the amount of goods purchased by the user, coupon rules, etc.; in scientific computing software, the calculation task may be to solve complex differential equations, etc. Depending on the scenario, the computing tasks are also different.

[0060] Specifically, the computing task processing list may be obtained from a memory or a register.

[0061] S204: Determine a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and the task processing status of the first processor.

[0062] The task processing status may include: the type of tasks that the first processor can process and / or the number of tasks that the first processor can process.

[0063] Specifically, a computing task that does not satisfy the first processor task processing state may be determined according to all computing tasks included in the computing task processing list, and the task may be determined as a target computing task.

[0064] S206: In response to the first processor executing the target computing task in the computing task processing list, issuing a hardware interrupt to the second processor to instruct the second processor to execute the target computing task.

[0065] Hardware interrupts are signals sent by computer hardware devices (such as keyboards, mice, disk drives, timers, etc.) to notify the processor that certain events need to be processed immediately. These signals interrupt the program flow currently being executed by the processor, causing the processor to suspend the current task and execute a specific handler associated with the interrupt. This handler is called an interrupt service routine (ISR). After completing the interrupt service routine, the processor resumes the execution of the previously interrupted program.

[0066] Specifically, when the first processor executes the target computing task in the computing task processing list, since the target computing task cannot be executed by the first processor, in order to complete the target computing task, the first processor can issue a hardware interrupt to the second processor, and the target computing task is processed by the second processor.

[0067] In the above-mentioned computing task processing method, when the first processor executes the tasks in the computing task processing list, once it finds the target computing task that does not meet its own task processing status, it can transfer it to the second processor for execution. This avoids the processing capacity bottleneck problem that may occur when a single processor faces complex and diverse computing tasks. In particular, when facing a processing list containing a large number of computing tasks of different types, the respective advantages and idle resources of the two processors can be fully utilized to achieve parallel processing and effectively improve the overall computing efficiency. The target computing task is determined and transferred according to the task processing status of the processor, so that the system can dynamically adjust the task allocation according to the real-time busyness, performance characteristics and other factors of the processor. For example, when the first processor is highly loaded and some computing tasks may be delayed in execution, such tasks are transferred to the relatively idle second processor, ensuring that the computing tasks can be processed more timely, so that the processor resources of the entire system can be more fully and reasonably utilized, and the situation of idle or overused resources is reduced. In addition, the first processor and the second processor communicate through hardware interrupts, and the whole process does not require the intervention of a third party, so that the interaction between the first processor and the second processor can be realized, reducing the pressure on the bus. The first processor uses hardware interrupts to call the second processor, and the response speed is fast.

[0068] In one embodiment, Figure 3 As shown, after determining the target computing task, the method further includes:

[0069] S302: Acquire task information of the target computing task.

[0070] The task information may be information describing the computing task.

[0071] S304, generating task description information of the target computing task based on the task information, wherein the task description information includes a plurality of operator attributes, and the operator attributes include: task type, source data address, target data address, source data type, source data dimension, target data type, target data dimension and structure size.

[0072] Among them, the task description information can be a data structure that describes the operation task. For example, there is now a task of adding two inputs, and the task type is: ADD (addition) (used to specify which DSP operator to use. This attribute is more important and is required during the deserialization process to correctly parse the unique attribute information of the operator). Task types may include: SUBTRACT (subtraction), MULTIPLY (multiplication), DIVIDE (division), POOL (pooling), CONV (convolution), GEMM (matrix multiplication) and other types; Source data address: specifies the memory address where the input data is stored. Target data address specifies the memory address of the output data; Source data type: the data type of the input data. Target data type: the data type of the output data (for example, the input is float single-precision floating point, and the output is int8_t signed 8-bit integer); Source data dimension: the shape of the input data. Target data dimension: the shape of the output data (for example, the input is: 1x224x224x32 (NHWC format)). Structure size: describes the size of the space occupied by the structure object of a specific computing task (such as ADD) after serialization. This attribute is mainly used in the deserialization process. According to this attribute, a single task can be correctly parsed (when the serialized binary file contains multiple tasks (if it contains only one task), it can also be used). In addition, it should be noted that the operator attributes can also include attributes that only the target computing task has. For example, there is an attribute in SOFTMAX, axis, which is used to specify the dimension on which the operation is performed, and this attribute does not exist in ADD. Therefore, it is not a common attribute of all computing tasks (operators). It is necessary to add unique attributes for specific computing tasks.

[0073] S306, serializing the task description information into a binary file, and adding an error detection code to the binary file.

[0074] Serialization refers to the process of converting data structures or object states into a format that can be stored or transmitted. This format is usually a byte stream (binary sequence) or a text format (such as JSON, XML, etc.), and its purpose is to easily save, transfer, and restore data between different environments (such as different computer systems, different processes, or different storage media). The main function of the error detection code is to detect whether the deserialization process is the same as expected, and correctly parse the data structure that describes the target computing task. The error detection code is only used in DEBUG mode, and its function is to be used for debugging and quickly locate errors.

[0075] Specifically, the task description information may be serialized into a binary file, and an error detection code for verification may be added to the binary file.

[0076] In some exemplary embodiments, different programming languages ​​usually have corresponding serialization libraries or built-in functions. For example, in Python, you can use the pickle module (suitable for simple Python object serialization) or the json module (commonly used to convert data structures into a format that is easy to transmit and store. Although json itself is a text format, it can be further encoded as binary), etc. If it is C++ language, you can use some third-party serialization libraries such as protobuf (Protocol Buffers), etc. Take pickle as an example, using its dump function can serialize the previously constructed task description information (such as a data structure in the form of a Python dictionary) and convert it into a binary stream. According to the requirements of the selected serialization tool, the task description information object and the file object to be written are passed in (by opening a binary file and obtaining the corresponding file stream object), and the actual serialization process is performed to obtain a binary file.

[0077] In this embodiment, by serializing the task description information of the target computing task into a binary file and adding an error detection code, it can be ensured that the subsequent second processor can accurately execute the target computing task.

[0078] In one embodiment, adding an error detection code to the binary file includes:

[0079] determining a target value of the error detection code, and adding the error detection code to the binary file based on the target value;

[0080] Alternatively, in the process of serializing the task description information including a plurality of operator attributes, a target position for serialization at a preset time is determined, and the error detection code is added at the target position.

[0081] Specifically, when serializing each operator attribute (ie, in the process of generating a binary file), a fixed value (eg, 2024) is first determined and added to the binary file; the fixed value is used as an error detection code.

[0082] Alternatively, when serializing each operator attribute, the current position of writing to the binary file (for example, the position of the 1024th byte of the file currently being written) is used as an error detection code and written into the binary file. This method can greatly reduce the probability of error detection code failure.

[0083] In one embodiment, issuing a hardware interrupt to the second processor to instruct the second processor to execute the target computing task includes:

[0084] A hardware interrupt is issued to the second processor to instruct the second processor to read the binary file, deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of deserialization is correct, execute the target operation task according to the deserialization result, obtain the operation result, and send the operation result to the first processor.

[0085] Receive the operation result fed back by the second processor.

[0086] Specifically, when the first processor determines that the target computing task needs to be transferred to the second processor, a hardware interrupt signal is sent to the second processor through corresponding hardware instructions (these instructions are generally called by the underlying operating system or a specific hardware driver providing an interface), and the signal carries relevant prompt information for letting the second processor know that it is necessary to read the binary file to perform subsequent operations (for example, a specific interrupt number can be agreed to correspond to the operation of this task handover). The first processor needs to inform the second processor of key information such as the storage location of the binary file so that the second processor can accurately find and read it. This information can be transferred through a shared memory area. For example, with the support of the shared memory mechanism provided by the operating system (such as shmget, shmat and other system calls in Linux are used to create and map shared memory segments), the first processor writes the necessary information such as the path and file name of the binary file into a specific area of ​​the shared memory, and the second processor reads this information from the shared memory area to locate the binary file to be read. The second processor can also read the register of the specified first processor to obtain the binary file. The second processor is usually in a state of waiting for interrupts (by setting up the interrupt monitoring mechanism during processor initialization and operating system related configuration). After receiving the hardware interrupt signal sent by the first processor, it determines that this is a notification about reading the binary file to perform the target computing task based on the interrupt number and other identifiers, and then reads the binary file and selects a suitable deserialization method to deserialize the read binary file. Extract the error detection code information contained in the deserialized data (when adding the error detection code in the previous serialization, it is necessary to agree on its position in the data structure, such as placing it at the end or in a specific field) to determine whether the position and the corresponding error detection code value are the same to determine whether the deserialization result is correct. If correct, the second processor can execute the target computing task according to other information in the deserialization result, obtain the computing result, and send the computing result to the first processor.

[0087] In some exemplary embodiments, deserialization is the reverse process of serialization, so when the deserialization process parses the binary file, it should be consistent with the action of the serialization process. Since the error detection code is the current position of the read (write) binary file (for example, to read the input_addr attribute, the 4096th byte of the file has been read, then the 32-bit error detection code that has been written is read first. If the value in the error detection code (assuming it is 4096) is consistent with the current read position, it means that the reading is correct at this time. If it is not 4096, it means that an error has occurred.

[0088] In this embodiment, the error detection code in the deserialization process can accurately determine whether the deserialization is correct, thereby ensuring the accuracy of the calculation result.

[0089] In one embodiment, Figure 4 As shown, the method also includes:

[0090] S402, in response to receiving a hardware interrupt issued by the second processor, stop processing the target computing task; the hardware interrupt issued by the second processor is issued by the second processor when the value of the error detection code is different from the value read by deserialization.

[0091] S404, determining that an error occurs in the process of processing the target computing task, and performing error debugging based on the error detection code.

[0092] Among them, error debugging can be DEBUG.

[0093] Specifically, when an error occurs, the first processor will be informed of the error again through a hardware interrupt. At this time, the second processor will stop because it no longer has the conditions to run the target computing task. Because it is not certain whether there is a problem with the serialized binary file or the deserialization process, it is necessary to use the error detection code for DEBUG debugging.

[0094] In this embodiment, when a hardware interrupt is received from the second processor, the error detection code can be used for DEBUG debugging, so that the location where the problem occurs can be quickly located to ensure processing efficiency.

[0095] In one embodiment, the task processing status includes: task processing type and task processing quantity; Figure 5 As shown, the determining, according to at least one computing task included in the computing task processing list and the task processing status of the first processor, a target computing task that does not satisfy the task processing status includes:

[0096] S502: Determine a target computing task according to a computing task whose task type does not match the task processing type and at least one computing task included in the computing task processing list.

[0097] S504: Screen at least one computing task included in the computing task processing list in sequence according to the task processing quantity, and determine at least one computing task remaining in the task processing list after the task processing quantity is met as a target computing task.

[0098] Specifically, traverse each computing task in the computing task processing list to check whether its task type matches the task processing type of the processor. By looping through each computing task, determine whether its task type is not within the range of task processing types that the processor can handle. If it does not match, the task is determined as the target computing task. In addition, the number of computing tasks that the current first processor can still handle can also be determined. Start from the computing task processing list and check each computing task in order. At the same time, record the number of tasks that have been screened. When the task processing number limit is reached, the remaining tasks are determined as target computing tasks. The number of computing tasks can be based on the current resource status (such as a suitable value dynamically calculated from the remaining memory, processor load, etc.).

[0099] In some exemplary embodiments, for example, the number of computing tasks that the current first processor can process (task processing number) is 10, the type of computing tasks that the first processor can process is type A (task processing type), there are 15 computing tasks in the task processing list, the first six are type A, seven to ten are type B, and eleven to fifteen are type A, then the target computing task can be computing tasks of type B from seven to ten, and a computing task of type A from the fifteenth.

[0100] In this embodiment, the task processing type and task processing quantity can accurately screen out the target computing tasks while ensuring the stable operation of the first processor, which will not delay the operation efficiency of the first processor and can also find out the computing tasks that do not satisfy the first processor.

[0101] In one embodiment, Figure 6 As shown, the embodiment of the present disclosure further provides a computing task processing method, which is described by taking the method applied to the second processor 104 as an example, and the method includes:

[0102] S602, in response to receiving a hardware interrupt issued by the first processor, reading a binary file; wherein the binary file is generated by the first processor based on at least one computing task included in the computing task processing list and the task processing status of the first processor, and a target computing task that does not satisfy the task processing status; the binary file contains an error detection code.

[0103] S604, deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of the deserialization is correct.

[0104] S606: Execute the target computing task according to the deserialization result to obtain a computing result, and send the computing result to the first processor.

[0105] It should be noted that the specific implementation methods and limitations in this embodiment can be found in the above embodiments, and will not be repeated here.

[0106] In one embodiment, the method further comprises:

[0107] In response to the value of the error detection code being different from the value read by deserialization, a hardware interrupt is issued to the first processor to instruct the first processor to determine that an error occurs in the process of processing the target computing task and to perform error debugging based on the error detection code.

[0108] It should be noted that the specific implementation methods and limitations in this embodiment can be found in the above embodiments, and will not be repeated here.

[0109] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0110] Based on the same inventive concept, the embodiment of the present disclosure also provides a computing task processing device for implementing the computing task processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more computing task processing device embodiments provided below can refer to the limitations of the computing task processing method above, and will not be repeated here.

[0111] In one embodiment, Figure 7 As shown, a computing task processing device 700 is provided, which is applied to a first processor, and the device includes: a task acquisition module 702, a task determination module 704 and an interrupt module 706, wherein:

[0112] A task acquisition module 702 is used to acquire a computing task processing list, wherein the computing task processing list contains at least one computing task;

[0113] A task determination module 704, configured to determine a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and the task processing status of the first processor;

[0114] The interrupt module 706 is used to issue a hardware interrupt to the second processor in response to the first processor executing the target computing task in the computing task processing list, so as to instruct the second processor to execute the target computing task.

[0115] In one embodiment of the device, the device further comprises:

[0116] A serialization module is used to obtain task information of the target computing task; generate task description information of the target computing task based on the task information, wherein the task description information includes multiple operator attributes, and the operator attributes include: task type, source data address, target data address, source data type, source data dimension, target data type, target data dimension and structure size; serialize the task description information into a binary file, and add an error detection code to the binary file.

[0117] In one embodiment of the device, the serialization module is further used to determine a target value of the error detection code, and add the error detection code to the binary file based on the target value; or, in the process of serializing the task description information including multiple operator attributes, determine a target position for serialization at a preset time, and add the error detection code at the target position.

[0118] In one embodiment of the device, the interrupt module 706 is also used to issue a hardware interrupt to the second processor to instruct the second processor to read the binary file, deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of deserialization is correct, execute the target operation task according to the result of the deserialization, obtain the operation result, and send the operation result to the first processor; receive the operation result fed back by the second processor.

[0119] In one embodiment of the device, the device also includes: an error debugging module, used to stop processing the target computing task in response to receiving a hardware interrupt issued by the second processor; the hardware interrupt issued by the second processor is issued by the second processor when the value of the error detection code is different from the value read by deserialization; determine that an error occurs in the process of processing the target computing task, and perform error debugging based on the error detection code.

[0120] In one embodiment of the device, the task processing status includes: task processing type and task processing quantity; the task determination module 704 includes:

[0121] The first task determination module is used to determine a target computing task according to a computing task whose task type is not matched with the task processing type of at least one computing task included in the computing task processing list.

[0122] The second task determination module is used to screen at least one computing task included in the computing task processing list in sequence according to the task processing quantity, and determine at least one computing task remaining in the task processing list after satisfying the task processing quantity as a target computing task.

[0123] In one embodiment, Figure 8 As shown, the embodiment of the present disclosure further provides a computing task processing device 800, which is applied to a second processor, and the device includes:

[0124] The information reading module 802 is used to read a binary file in response to receiving a hardware interrupt issued by the first processor; wherein the binary file is generated by the first processor according to at least one computing task included in the computing task processing list and the task processing state of the first processor, and the target computing task that does not meet the task processing state is determined; and the binary file contains an error detection code;

[0125] A deserialization module 804 is used to deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of deserialization is correct;

[0126] The computing task execution module 806 is used to execute the target computing task according to the deserialization result, obtain the computing result, and send the computing result to the first processor.

[0127] In one embodiment of the device, the device also includes: an interrupt output module, which is used to issue a hardware interrupt to the first processor in response to the value of the error detection code being different from the value read by deserialization, so as to instruct the first processor to determine that an error has occurred in the process of processing the target computing task, and perform error debugging based on the error detection code.

[0128] Each module in the above-mentioned computing task processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0129] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data related to computing tasks. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a computing task processing method is implemented.

[0130] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0131] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0132] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0133] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0134] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided by the present disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided by the present disclosure may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processor involved in each embodiment provided by the present disclosure may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited thereto.

[0135] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the attached claims.

Claims

1. A computing task processing method, characterized in that: Applied to a first processor, the method comprises: Obtaining a computing task processing list, wherein the computing task processing list includes at least one computing task; Determining a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and a task processing status of the first processor; In response to the first processor executing the target computing task in the computing task processing list, a hardware interrupt is issued to the second processor to instruct the second processor to execute the target computing task.

2. The method according to claim 1, characterized in that After determining the target computing task, the method further includes: Acquire task information of the target computing task; Generate task description information of the target computing task based on the task information, the task description information includes a plurality of operator attributes, the operator attributes include: task type, source data address, target data address, source data type, source data dimension, target data type, target data dimension and structure size; The task description information is serialized into a binary file, and an error detection code is added to the binary file.

3. The method according to claim 2, characterized in that The adding an error detection code to the binary file comprises: determining a target value of the error detection code, and adding the error detection code to the binary file based on the target value; Alternatively, in the process of serializing the task description information including a plurality of operator attributes, a target position for serialization at a preset time is determined, and the error detection code is added at the target position.

4. The method according to claim 2, characterized in that: The sending of a hardware interrupt to the second processor to instruct the second processor to execute the target computing task includes: Sending a hardware interrupt to the second processor to instruct the second processor to read the binary file, deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determining that the result of deserialization is correct, executing the target computing task according to the deserialization result, obtaining a computing result, and sending the computing result to the first processor; Receive the calculation result fed back by the second processor.

5. The method according to claim 4, characterized in that The method further comprises: In response to receiving a hardware interrupt issued by the second processor, stopping processing the target computing task; the hardware interrupt issued by the second processor is issued by the second processor when the value of the error detection code is different from the value read by deserialization; It is determined that an error occurs in the process of processing the target computing task, and error debugging is performed based on the error detection code.

6. The method according to claim 1, characterized in that The task processing status includes: a task processing type and a task processing quantity; and determining, based on at least one computing task included in the computing task processing list and the task processing status of the first processor, a target computing task that does not meet the task processing status includes: Determining a target computing task according to a computing task whose task type is not matched with the task processing type of at least one computing task included in the computing task processing list; And / or, at least one computing task included in the computing task processing list is screened in sequence according to the task processing quantity, and at least one computing task remaining in the task processing list after the task processing quantity is met is determined as the target computing task.

7. A computing task processing method, characterized in that: Applied to a second processor, the method comprises: In response to receiving a hardware interrupt issued by the first processor, a binary file is read; wherein the binary file is generated by the first processor according to at least one computing task included in the computing task processing list and the task processing state of the first processor, and the target computing task that does not meet the task processing state is determined; and the binary file contains an error detection code; Deserialize the binary file, and in response to the value of the error detection code being the same as the value read by deserialization, determine that the result of the deserialization is correct; The target computing task is executed according to the deserialization result to obtain a computing result, and the computing result is sent to the first processor.

8. The method according to claim 7, characterized in that The method further comprises: In response to the value of the error detection code being different from the value read by deserialization, a hardware interrupt is issued to the first processor to instruct the first processor to determine that an error occurs in the process of processing the target computing task and to perform error debugging based on the error detection code.

9. A computing task processing device, characterized in that: Applied to a first processor, the device comprises: A task acquisition module, used to acquire a computing task processing list, wherein the computing task processing list contains at least one computing task; a task determination module, configured to determine a target computing task that does not satisfy the task processing status according to at least one computing task included in the computing task processing list and the task processing status of the first processor; The interrupt module is used to issue a hardware interrupt to the second processor in response to the first processor executing the target computing task in the computing task processing list, so as to instruct the second processor to execute the target computing task.

10. A computing task processing device, characterized in that: Applied to a second processor, the device comprises: an information reading module, configured to read a binary file in response to receiving a hardware interrupt issued by the first processor; wherein the binary file is generated by the first processor according to at least one computing task included in the computing task processing list and the task processing state of the first processor, and a target computing task that does not satisfy the task processing state; and the binary file contains an error detection code; A deserialization module, configured to deserialize the binary file, and determine that a result of the deserialization is correct in response to the value of the error detection code being the same as the value read by the deserialization; A computing task execution module is used to execute the target computing task according to the deserialization result, obtain the computing result, and send the computing result to the first processor.

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