Storage device and operating method of storage device

Abstract

A memory device and a method of operating the memory device are provided. The storage device includes: a non-volatile memory device; and a controller configured to: receive first data from the non-volatile memory device; performing first error correction decoding on the first data to obtain second data; controlling an error correction capability and an error detection capability of the second error correction decoding based on the information on the first error correction decoding; and performing second error correction decoding on the second data based on the error correction capability and the error detection capability to obtain third data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0139015 filed on October 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices, and more particularly, to a storage device that corrects errors with improved accuracy and an operating method of the storage device. Background Art

[0004] A storage device refers to a device that stores data under the control of a host device such as a computer, a smart phone, or a smart tablet. Storage devices include devices that store data on a disk, such as a hard disk drive (HDD), or devices that store data in a semiconductor memory (particularly a non-volatile memory), such as a solid-state drive (SSD) or a memory card.

[0005] Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0006] With the development of semiconductor manufacturing technology, the integration and storage capacity of storage devices continue to increase. The high integration of storage devices makes it possible to reduce manufacturing complexity. However, the high integration of storage devices leads to a reduction in the size of the storage devices and a change in the structure of the storage devices. In this case, various problems that have only existed until now are being discovered, leading to new problems that may damage or destroy the data stored in the storage devices and reduce the reliability of the storage devices. Therefore, there is a continuous need for a method and device that can improve the reliability of storage devices. Summary of the invention

[0007] One or more embodiments provide a memory device and an operating method of the memory device that improves reliability by correcting errors with improved accuracy.

[0008] According to an aspect of the embodiment, a storage device includes: a nonvolatile memory device; and a controller configured to: receive first data from the nonvolatile memory device;

[0009] Performing first error correction decoding on first data to obtain second data; controlling error correction capability and error detection capability of second error correction decoding based on information about the first error correction decoding; and performing second error correction decoding on the second data based on the error correction capability and error detection capability to obtain third data.

[0010] According to one aspect of the embodiment, a storage device includes: a non-volatile memory device; and a controller, which is configured to: receive first data from the non-volatile memory device; perform first error correction decoding on the first data to obtain second data; control a method for performing second error correction decoding based on information of the first error correction decoding; perform second error correction decoding on the second data based on the method to obtain third data; and repeatedly perform the first error correction decoding and the second error correction decoding by further performing the first error correction decoding and the second error correction decoding on the third data.

[0011] According to one aspect of an embodiment, a method for operating a storage device is provided, the storage device including a nonvolatile memory device and a controller. The method includes: performing low-density parity check (LDPC) decoding on first data transmitted from the nonvolatile memory device by the controller to obtain second data; controlling error correction capability and error detection capability of polar code consecutive erasure list (SCL) decoding based on decoding information about LDPC decoding by the controller; and performing polar code SCL decoding on the second data based on the error correction capability and the error detection capability by the controller to obtain third data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features will become more apparent from the following description of embodiments in conjunction with the accompanying drawings.

[0013] Figure 1 A storage device according to an embodiment is shown.

[0014] Figure 2 An error correction code block according to an embodiment is shown.

[0015] Figure 3 A method in which an error correction code block performs error correction decoding according to an embodiment is shown.

[0016] Figure 4 A first encoder of an encoding block according to an embodiment is shown.

[0017] Figure 5 A second encoder of an encoding block according to an embodiment is shown.

[0018] Figure 6 A factor graph describing the operating principle of the second encoder according to an embodiment is shown.

[0019] Figure 7 An example of defining a cycle in a factor graph is shown.

[0020] Figure 8 A first decoder is shown decoding a block according to an embodiment.

[0021] Fig. 9 A second decoder is shown decoding a block according to an embodiment.

[0022] Fig.10 A method in which a sequential deletion list (SCL) decoder performs SCL decoding according to an embodiment is shown.

[0023] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a diagram for describing a process in which an SCL decoder performs SCL decoding according to an embodiment.

[0024] Fig.12 The conditions under which the SCL decoder according to the embodiment increases the error detection capability or the error correction capability are shown.

[0025] Fig.13 The conditions under which the SCL decoder according to the embodiment increases the error detection capability or the error correction capability are shown.

[0026] Fig.14 A method in which an SCL decoder adjusts the use of dynamic freeze bits according to an embodiment is shown.

[0027] Fig.15 An error correction code block according to another embodiment is shown.

[0028] Fig.16 A second decoder is shown decoding a block according to an embodiment.

[0029] Fig.17 A method in which an error correction code block performs error correction decoding according to an embodiment is shown.

[0030] Fig.18 The conditions under which the SCL decoder according to the embodiment increases the error detection capability or the error correction capability are shown.

[0031] Fig.19 A method of decoding a combined decoding scheme in which decoding blocks are adjusted according to an embodiment is shown.

[0032] Fig. 20 A method of decoding a combined decoding scheme in which decoding blocks are adjusted according to an embodiment is shown. Fig.21 is a diagram of a system to which a storage device is applied according to an embodiment. DETAILED DESCRIPTION

[0033] Below, the embodiment will be described with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and repeated description thereof is omitted. It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, directly connected to or directly coupled to another element or layer, or there can be an intermediate element or layer. On the contrary, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be realized in various other forms. Each embodiment provided in the following description does not exclude being associated with one or more features of another example or another embodiment that is also provided herein or is not provided herein but consistent with the present disclosure.

[0034] Figure 1 FIG. 1 shows a storage device 100 according to an embodiment. Figure 1 , the memory device 100 may include a nonvolatile memory device 110, a memory controller 120, and an external buffer 130. The nonvolatile memory device 110 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

[0035] For example, the nonvolatile memory device 110 may include at least one of various nonvolatile memory devices such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistance memory device.

[0036] The memory controller 120 may receive various requests from an external host device for writing data to the nonvolatile memory device 110 or reading data from the nonvolatile memory device 110. The memory controller 120 may store (or buffer) user data communicated with the external host device in the external buffer 130, and may store metadata for managing the memory device 100 in the external buffer 130.

[0037] The memory controller 120 may access the nonvolatile memory device 110 through the first signal line SIGL1 and the second signal line SIGL2. For example, the memory controller 120 may transmit a command and an address to the nonvolatile memory device 110 through the first signal line SIGL1. The memory controller 120 may exchange data with the nonvolatile memory device 110 through the first signal line SIGL1.

[0038] The memory controller 120 may transmit the first control signal to the nonvolatile memory device 110 through the second signal line SIGL2. The memory controller 120 may receive the second control signal from the nonvolatile memory device 110 through the second signal line SIGL2.

[0039] In an embodiment, the memory controller 120 may be configured to control two or more nonvolatile memory devices. The memory controller 120 may provide a first signal line and a second signal line for each of the two or more nonvolatile memory devices.

[0040] As another example, the memory controller 120 may share the first signal line for two or more nonvolatile memory devices.The memory controller 120 may share some of the second signal lines for two or more nonvolatile memory devices and may provide other of the second signal lines separately.

[0041] The external buffer 130 may include a random access memory. For example, the external buffer 130 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistance random access memory.

[0042] The memory controller 120 may include a bus 121, a host interface 122, an internal buffer 123, a processor 124, a buffer controller 125 (e.g., a buffer control circuit), a memory manager 126 (e.g., a memory manager circuit), and an error correction code (ECC) block 127 (e.g., an ECC circuit).

[0043] The bus 121 may provide a communication channel between components of the memory controller 120 . The host interface 122 may receive various requests from an external host device and may parse the received requests. The host interface 122 may store the parsed requests in the internal buffer 123 .

[0044] The host interface 122 may send various responses to an external host device. The host interface 122 may exchange signals with an external host device according to a given communication protocol. The internal buffer 123 may include a random access memory. For example, the internal buffer 123 may include a static random access memory or a dynamic random access memory.

[0045] The processor 124 may execute an operating system or firmware for driving the memory controller 120. The processor 124 may read the parsed request stored in the internal buffer 123, and may generate an address and a command for controlling the nonvolatile memory device 110. The processor 124 may provide the generated command and address to the memory manager 126.

[0046] The processor 124 may store various metadata for managing the storage device 100 in the internal buffer 123. The processor 124 may access the external buffer 130 through the buffer controller 125. The processor 124 may control the buffer controller 125 and the memory manager 126 so that user data stored in the external buffer 130 is provided to the nonvolatile memory device 110.

[0047] The processor 124 may control the host interface 122 and the buffer controller 125 so that the data stored in the external buffer 130 is provided to the external host device. The processor 124 may control the buffer controller 125 and the memory manager 126 so that the data received from the nonvolatile memory device 110 is stored in the external buffer 130. The processor 124 may control the host interface 122 and the buffer controller 125 so that the data received from the external host device is stored in the external buffer 130.

[0048] The buffer controller 125 may write data into the external buffer 130 or may read data from the external buffer 130 under the control of the processor 124. The memory manager 126 may communicate with the nonvolatile memory device 110 through the first and second signal lines SIGL1 and SIGL2 under the control of the processor 124.

[0049] The memory manager 126 may access the nonvolatile memory device 110 under the control of the processor 124. For example, the memory manager 126 may access the nonvolatile memory device 110 through the first signal line SIGL1 and the second signal line SIGL2. The memory manager 126 may communicate with the nonvolatile memory device 110 based on a protocol conforming to a standard or a protocol defined by a manufacturer.

[0050] The error correction code block 127 may perform error correction encoding on data to be provided to the nonvolatile memory device 110 by using the error correction code ECC. The error correction code block 127 may perform error correction decoding on data received from the nonvolatile memory device 110 by using the error correction code ECC.

[0051] In an embodiment, the external buffer 130 and the buffer controller 125 may be omitted from the memory device 100. When the external buffer 130 and the buffer controller 125 are omitted, the functions described as being performed by the external buffer 130 and the buffer controller 125 may be performed by the internal buffer 123.

[0052] Figure 2 FIG. 2 shows an error correction code block 200 according to an embodiment. In an embodiment, the error correction code block 200 may correspond to Figure 1The error correction code block 127 of the memory controller 120 of the storage device 100 is configured.

[0053] Reference Figure 1 and Figure 2 , the error correction code block 200 may include an encoding block 210 and a decoding block 240. The encoding block 210 may perform error correction encoding on the first data DT1 to be written in the nonvolatile memory device 110. The decoding block 240 may perform error correction decoding on the fourth data DT4 read from the nonvolatile memory device 110.

[0054] The encoding block 210 may include a first encoder 220 and a second encoder 230. The first encoder 220 may perform a first error correction encoding on the first data DT1, and may generate the second data DT2. For example, the first error correction encoding may include a cyclic redundancy check (CRC) code encoding or an encoding in which a parity check (PC) code encoding and a polar code encoding are combined (or concatenated). However, the type of the first error correction encoding is not limited thereto.

[0055] The second encoder 230 may perform second error correction coding on the second data DT2 and may generate third data DT3. For example, the second error correction coding may include low density parity check (LDPC) coding. However, the type of the second error correction coding is not limited thereto.

[0056] The decoding block 240 may include a first decoder 250 and a second decoder 260. The first decoder 250 may perform first error correction decoding on the fourth data DT4 and may generate fifth data DT5. For example, the first error correction decoding may include LDPC decoding. However, the type of the first error correction decoding is not limited thereto.

[0057] The first decoder 250 may generate decoding information DI about the first error correction decoding. For example, the decoding information DI may include information about the structure of the first decoder 250 or information about the state of the first error correction decoding (e.g., the state of the result of the first error correction decoding). The first decoder 250 may transmit the decoding information DI to the second decoder 260.

[0058] The second decoder 260 may receive the decoding information DI from the first decoder 250. The second decoder 260 may adjust the manner in which the second decoder 260 performs the second error correction decoding based on the decoding information DI about the first error correction decoding. For example, the second decoder 260 may control the second error correction decoding based on the decoding information DI about the first error correction decoding.

[0059] The second decoder 260 may perform second error correction decoding on the fifth data DT5, and may generate sixth data DT6. For example, the second error correction decoding may include CRC code decoding or decoding in which PC code decoding and polar code decoding (e.g., continuous deletion list (SCL) decoding (or polar code SCL decoding)) are combined (or concatenated). However, the type of the second error correction decoding is not limited thereto.

[0060] According to an embodiment, the decoding block 240 may combine (or cascade) and perform heterogeneous error correction decoding. In this case, the decoding block 240 may control the second error correction decoding to be performed after the first error correction decoding based on the decoding information DI of the first error correction decoding previously performed. Because the decoding information DI of the first error correction decoding previously performed is applied to the second error correction decoding performed after the first error correction decoding, the accuracy of error detection or error correction of the decoding block 240 may be further improved.

[0061] Figure 3 An example of a method in which the error correction code block 200 performs error correction decoding is shown. Figure 1 , Figure 2 and Figure 3 In operation S110 , the error correction code block 200 may receive data. For example, the decoding block 240 of the error correction code block 200 may receive fourth data DT4 read from the nonvolatile memory device 110 through the bus 121 .

[0062] In operation S120, the decoding block 240 may perform first decoding based on the received data and may generate first decoded data. For example, the first decoder 250 of the decoding block 240 may perform first error correction decoding (eg, LDPC decoding) on ​​the fourth data DT4 and may generate fifth data DT5 as the first decoded data.

[0063] In operation S130, the decoding block 240 may adjust the correction detection capability based on the decoding information DI of the first decoding. For example, the first decoder 250 of the decoding block 240 may transmit the decoding information DI about the first error correction decoding to the second decoder 260. For example, when the first decoder 250 performs the first error correction decoding by LDPC decoding, the decoding information DI may indicate the LDPC decoding and the characteristics of the LDPC decoding. The second decoder 260 may determine the method for performing the second error correction decoding (e.g., SCL decoding) based on the decoding information DI. For example, the second decoder 260 may increase the error correction capability or may reduce the error detection capability, or the second decoder 260 may reduce the error correction capability or may increase the error detection capability.

[0064] In operation S140, the decoding block 240 may perform a second decoding based on the first decoded data and the adjusted error correction detection capability, and may generate the second decoded data. For example, the decoding block 240 may perform a second error correction decoding on the fifth data DT5 based on the adjusted error correction capability and the adjusted error detection capability, and may generate the sixth data DT6 as the second decoded data.

[0065] In operation S150, the decoding block 240 may output the second decoded data. For example, the second decoder 260 of the decoding block 240 may output the sixth data DT6 as error correction completed data.

[0066] As described above, the decoding block 240 may adjust the error correction capability and the error detection capability of the second decoder 260 based on the decoding information DI of the first decoder 250. In an embodiment, when the decoding information DI indicates that the reliability of the fifth data DT5 is relatively low, the decoding block 240 may increase the error correction capability of the second decoder 260 and may reduce the error detection capability of the second decoder 260. When the decoding information DI indicates that the reliability of the fifth data DT5 is relatively high, the decoding block 240 may reduce the error correction capability of the second decoder 260 and may increase the error detection capability of the second decoder 260.

[0067] Since the manner in which the second decoder 260 performs the second error correction decoding is adjusted based on the decoding information DI associated with the first decoder 250, the decoding block 240 may correct and detect errors with improved accuracy, and the reliability of the sixth data DT6 may be improved.

[0068] Figure 4 An example of the first encoder 220 of the encoding block 210 is shown. Figure 1 , Figure 2 and Figure 4 , the first encoder 220 may receive the first data DT1. The first data DT1 may include the first information bit IF1, the second information bit IF2, the third information bit IF3, the fourth information bit IF4, and the fifth information bit IF5. The first information bit IF1, the second information bit IF2, the third information bit IF3, the fourth information bit IF4, and the fifth information bit IF5 may constitute the data that the external host device intends to write into the storage device 100.

[0069] The first encoder 220 may include a precoder PE and a code graph CG. The precoder PE may receive the first data DT1. The precoder PE may generate the first intermediate data ID1 by adding the frozen bit FB, the first dynamic frozen bit DF1, and the second dynamic frozen bit DF2 to the first information bit IF1, the second information bit IF2, the third information bit IF3, the fourth information bit IF4, and the fifth information bit IF5 of the first data DT1.

[0070] For example, the first intermediate data ID1 may sequentially include frozen bits FB, first information bits IF1, second information bits IF2, first dynamic frozen bits DF1, third information bits IF3, fourth information bits IF4, second dynamic frozen bits DF2, and fifth information bits IF5.

[0071] For example, the frozen bit FB may have a fixed value. For example, the frozen bit FB may have a value of "0" or "1".

[0072] Each of the first dynamic frozen bit DF1 and the second dynamic frozen bit DF2 may have a value determined based on the value of the preceding information bit. For example, the first dynamic frozen bit DF1 may have a value that allows a fixed value (e.g., a value of "0" or "1") to be obtained when an exclusive OR (XOR) operation is performed together with the value of the first information bit IF1 and the value of the second information bit IF2. For example, the precoder PE may determine the first dynamic frozen bit DF1 by performing an XOR operation based on the first information bit IF1 and the second information bit IF2. The second dynamic frozen bit DF2 may have a value that allows a fixed value (e.g., a value of "0" or "1") to be obtained when an exclusive OR (XOR) operation is performed together with the value of the third information bit IF3 and the value of the fourth information bit IF4. For example, the precoder PE may determine the second dynamic frozen bit DF2 by performing an XOR operation based on the third information bit IF3 and the fourth information bit IF4.

[0073] The code pattern CG may apply polar code encoding to the first intermediate data ID1. The code pattern CG may include a bit line that transfers a bit of the first intermediate data ID1 to a bit of the second data DT2. The code pattern CG may include a plurality of XOR operations. Each of the plurality of XOR operations may be performed between two bit lines.

[0074] In the code graph CG, each XOR operation can be represented by a circle including an addition symbol and a line connected to the circle. The XOR operation can output a value obtained by performing an XOR operation on a bit of a bit line connected to the line and a bit of a bit line connected to the circle to the bit line connected to the circle. The calculation result of the code graph CG can be the second data DT2 including the first encoded bit EB1.

[0075] exist Figure 4 Detailed description is given in FIG. 1 , however, according to an embodiment, the number of bits of the first data DT1 , the number of bits of the first intermediate data ID1 , and the number of bits of the second data DT2 are not limited thereto.

[0076] Figure 5 An example of the second encoder 230 of the encoding block 210 is shown. Figure 1 , Figure 2 and Figure 5 , the second encoder 230 may receive the second data DT2. For example, the second data DT2 may include eight bits. The second encoder 230 may perform LDPC encoding on the second data DT2, and may generate the third data DT3 including the second coded bit EB2. For example, the second encoder 230 may generate the second coded bit EB2 of the third data DT3 by adding (one or more) parity check bits satisfying the check condition to the first coded bit EB1 of the second data DT2. For example, the third data DT3 may include nine bits. For example, the second encoder 230 may add (one or more) parity check bits to (one or more) given positions.

[0077] The number of bits of the second data DT2 and the number of bits of the third data DT3 are Figure 5 However, according to an embodiment, the number of bits of the second data DT2 and the number of bits of the third data DT3 are not limited thereto.

[0078] Figure 6 An example of a factor graph FG describing the operating principle of the second encoder 230 is shown. Figure 1 , Figure 2 , Figure 5 and Figure 6 , the factor graph FG may include a plurality of check nodes CN and a plurality of variable nodes VN. Each of the plurality of variable nodes VN may be connected to two or more check nodes CN by an edge. The number of edges connected to each variable node VN may be the degree of the variable node VN. Information about the degree of the variable node VN may be included as part of the decoding information DI.

[0079] The plurality of variable nodes VN may correspond to the second encoded bits EB2 of the third data DT3 , respectively. That is, the variable node VN may include the first encoded bits EB1 of the second data DT2 and the parity bit(s) added by the second encoder 230 .

[0080] The second encoder 230 may add (one or more) parity check bits so that the sum of the bits of the variable nodes VN connected to each check node CN is a fixed value (e.g., "0" or "1"). When the sum of the bits of the variable nodes VN connected to each check node CN is a fixed value (e.g., "0" or "1"), the check condition may be satisfied.

[0081] Figure 7 An example is shown in which a cycle CY is defined in a factor graph FG. Figure 7As shown by the solid line, a closed loop of edges starting from a variable node VN or a check node CN, passing through (one or more) any other variable nodes and (one or more) any other check nodes one by one, and reaching the variable node VN or the check node CN at the starting point can be a cycle CY. Figure 7 As shown, a cycle including 6 edges may have a length of 6 cycles (6CY). Information about the cycles of the factor graph FG may be included as part of the decoding information DI.

[0082] Figure 8 An example of a first decoder 250 of the decoding block 240 is shown. Figure 1 , Figure 2 and Figure 8 , the first decoder 250 may receive the fourth data DT4. The fourth data DT4 may include read bits RB read from the nonvolatile memory device 110. Each of the read bits RB may have a log likelihood ratio LLR. Hereinafter, the log likelihood ratio LLR may be used as a meaning similar to the term "likelihood ratio" or "likelihood", and may be used interchangeably.

[0083] The log-likelihood ratio LLR of the read bit RB may be an initial log-likelihood ratio LLR. For example, the nonvolatile memory device 110 may read the read bit RB while changing the read level. For example, the read level may be a voltage level applied to a memory cell to read data stored in the memory cell. The first decoder 250 may assign the initial log-likelihood ratio LLR to each of the read bits RB depending on whether the read bit maintains the same value or is variable according to a variable read level in a read operation.

[0084] The first decoder 250 can Figure 6 The factor graph FG of the first decoder 250 is applied to the read bit RB of the fourth data DT4. For example, based on the factor graph FG, the first decoder 250 may calculate the sum of the values ​​of the variable node VN corresponding to each check node CN. The first decoder 250 may modify the log likelihood ratio LLR of the read bit RB based on the calculated sum value. The first decoder 250 may update the value of the variable node VN based on the sum calculated at each check node CN or the value of the variable node VN transmitted to each check node CN.

[0085] The first decoder 250 may repeat the updating of the value of the variable node VN and the updating of the value of the check node CN for a given number of times. For example, the given number of times may be determined during the manufacturing process of the first decoder 250, or may be set by the external host device or the processor 124 after the manufacturing of the first decoder 250. The first decoder 250 may generate the fifth data DT5 by repeating the updating of the value of the variable node VN and the updating of the value of the check node CN for a given number of times and removing the parity bit(s) of the given position(s) added by the second encoder 230.

[0086] The fifth data DT5 may include a first decoded bit DB1. The first decoded bit DB1 of the fifth data DT5 may have a corresponding log likelihood ratio LLR.

[0087] Fig. 9 An example of the second decoder 260 of the decoding block 240 is shown. Figure 1 , Figure 2 and Fig. 9 , the second decoder 260 may receive fifth data DT5. The fifth data DT5 may include the first decoded bit DB1 and a corresponding log-likelihood ratio LLR.

[0088] The second decoder 260 may include a code pattern CG and an SCL decoder SD. The code pattern CG may apply polar code decoding to the fifth data DT5. The code pattern CG may have the same Figure 4 The code graph CG has the same structure and can be used with Figure 4 The operation is performed in the direction opposite to the direction of the code graph CG.

[0089] The result of the operation of the code graph CG may be the second intermediate data ID2. As in the first intermediate data ID1, the second intermediate data ID2 may sequentially include a frozen bit FB, a first information bit IF1, a second information bit IF2, a first dynamic frozen bit DF1, a third information bit IF3, a fourth information bit IF4, a second dynamic frozen bit DF2, and a fifth information bit IF5.

[0090] Because the frozen bit FB has a fixed value (e.g., a known bit), the frozen bit FB may not have a log-likelihood ratio LLR. Since the first information bit IF1, the second information bit IF2, the first dynamic frozen bit DF1, the third information bit IF3, the fourth information bit IF4, the second dynamic frozen bit DF2, and the fifth information bit IF5 have a changed value, the bits IF1, IF2, DF1, IF3, IF4, DF2, and IF5 may have corresponding log-likelihood ratios LLR.

[0091] The SCL decoder SD may receive the second intermediate data ID2. The SCL decoder SD may generate a given number of candidate data based on the values ​​of the first information bit IF1, the second information bit IF2, the first dynamic frozen bit DF1, the third information bit IF3, the fourth information bit IF4, the second dynamic frozen bit DF2, and the fifth information bit IF5 and the corresponding log-likelihood ratios LLR. For example, the SCL decoder SD may generate the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4.

[0092] The SCL decoder SD may select one of the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4 to output as the sixth data DT6. For example, the sixth data DT6 may be data whose error correction is completed by the decoding block 240. The sixth data DT6 may sequentially include a first information bit IF1, a second information bit IF2, a third information bit IF3, a fourth information bit IF4, and a fifth information bit IF5.

[0093] The SCL decoder SD can perform error correction and error detection. For example, the SCL decoder SD can use the first dynamic frozen bit DF1, the second dynamic frozen bit DF2, or the first dynamic frozen bit DF1 and the second dynamic frozen bit DF2 in error correction or error detection. The number of dynamic frozen bits used by the SCL decoder SD in error correction can correspond to the error correction capability. For example, an increase in the number of dynamic frozen bits used by the SCL decoder SD in error correction can result in an increase in the error correction capability. The number of dynamic frozen bits used by the SCL decoder SD in error detection can correspond to the error detection capability. For example, an increase in the number of dynamic frozen bits used by the SCL decoder SD in error detection can result in an increase in the error detection capability.

[0094] Fig.10 An example of a method in which an SCL decoder SD performs SCL decoding is shown. Figure 1 , Figure 2 , Fig. 9 and Fig.10 , in operation S210, the SCL decoder SD may perform SCL decoding while correcting an error based on the correction capability, and may generate a first set of candidate data. For example, the SCL decoder SD may sequentially select bits of the second intermediate data ID2 based on the log likelihood ratios LLR of the bits of the second intermediate data ID2. The SCL decoder SD may sequentially select bits of the second intermediate data ID2 while maintaining the first set of candidate data whose number is preset. When the first dynamic frozen bit DF1 is used for error correction, the SCL decoder SD may correct the error by excluding values ​​that do not satisfy the rule for generating the first dynamic frozen bit DF1.

[0095] In operation S220, the SCL decoder SD may perform error detection on the first set of candidate data based on the detection capability, and may generate the second set of candidate data. For example, when the second dynamic frozen bit DF2 is used for error detection, the SCL decoder SD may detect the candidate data that does not satisfy the rule for generating the second dynamic frozen bit DF2 from the first set of candidate data as an error.

[0096] In operation S230, the SCL decoder SD may select sixth data DT6 from the second group of candidate data. For example, the SCL decoder SD may select candidate data considered to have the smallest error (or no error) as the sixth data DT6.

[0097] FIG. 11A to FIG. 11D 1 is a diagram for describing a process in which the SCL decoder SD performs SCL decoding. Figure 1 , Figure 2 , Fig. 9 and Fig.11A , the SCL decoder SD may perform SCL decoding based on a graph starting from the first node N1 and extending in the form of a tree. Each node may be connected to two edges corresponding to "0" and "1", respectively. The two edges may be connected to different nodes.

[0098] The SCL decoder SD may calculate a metric at each node based on a log likelihood ratio LLR of each bit of the second intermediate data ID2. The metric may indicate the likelihood of a path from the first node N1 to each node. As the value of the metric decreases, the likelihood of the path to each node may become higher.

[0099] The SCL decoder SD may have a length of a given value. The SCL decoder SD may select and maintain a list of paths, the number of which corresponds to the given length value. For example, the SCL decoder SD may select and maintain a list of paths with a lower metric. Fig. 9 As shown, when the SCL decoder SD manages the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4, the length (or depth) of the list managed by the SCL decoder SD may be "4".

[0100] Reference Figure 1 , Figure 2 , Fig. 9 , Fig.11A and Fig. 11B, at the first node N1, the SCL decoder SD may select the value of the first information bit IF1 from the bits of the second intermediate data ID2 as the first bit with the log-likelihood ratio LLR. Because the length (or depth) of the list managed by the SCL decoder SD is "4", the SCL decoder SD may select both the path where the first information bit IF1 is "0" and the path where the first information bit IF1 is "1". The path where the first information bit IF1 is "0" may be connected to the second node N2, and the path where the first information bit IF1 is "1" may be connected to the third node N3. The SCL decoder SD may calculate the first metric M1 based on the likelihood of the path up to the second node N2 (or from the first node N1 to the second node N2), and may calculate the second metric M2 based on the likelihood of the path up to the third node N3 (or from the first node N1 to the third node N3).

[0101] At each of the second node N2 and the third node N3, the SCL decoder SD may select the value of the second information bit IF2 from the bits of the second intermediate data ID2 as the second bit having the log likelihood ratio LLR. Since the length (or depth) of the list managed by the SCL decoder SD is "4", the SCL decoder SD may select both the path where the second information bit IF2 is "0" and the path where the second information bit IF2 is "1".

[0102] At the second node N2, the path where the second information bit IF2 is "0" may be connected to the fourth node N4, and the path where the second information bit IF2 is "1" may be connected to the fifth node N5. The SCL decoder SD may calculate the third metric M3 based on the likelihood of the path up to the fourth node N4, and may calculate the fourth metric M4 based on the likelihood of the path up to the fifth node N5.

[0103] At the third node N3, the path where the second information bit IF2 is "0" may be connected to the sixth node N6, and the path where the second information bit IF2 is "1" may be connected to the seventh node N7. The SCL decoder SD may calculate the fifth metric M5 based on the likelihood of the path up to the sixth node N6, and may calculate the sixth metric M6 based on the likelihood of the path up to the seventh node N7.

[0104] Fig. 11C An example of using the first dynamic freeze bit DF1 in error detection is shown. Figure 1 , Figure 2 , Fig. 9 , Fig. 11B and Fig. 11C When the first dynamic frozen bit DF1 is used in error detection, the SCL decoder SD may use the first dynamic frozen bit DF1 in a similar manner to the information bit in the process of selecting a path.

[0105] At each of the fourth node N4, the fifth node N5, the sixth node N6, and the seventh node N7, the SCL decoder SD may select the value of the first dynamic freeze bit DF1 from the bits of the second intermediate data ID2 as the third bit having the log likelihood ratio LLR. Because the length (or depth) of the list managed by the SCL decoder SD is "4", the SCL decoder SD may select four of the eight paths extending from the fourth node N4, the fifth node N5, the sixth node N6, and the seventh node N7, and may prune the remaining four paths.

[0106] At the fourth node N4, the path where the first dynamic frozen bit DF1 is "0" can be connected to the eighth node N8, and the path where the first dynamic frozen bit DF1 is "1" can be connected to the ninth node N9. At the fifth node N5, the path where the first dynamic frozen bit DF1 is "0" can be connected to the tenth node N10, and the path where the first dynamic frozen bit DF1 is "1" can be connected to the eleventh node N11.

[0107] At the sixth node N6, the path where the first dynamic frozen bit DF1 is "0" may be connected to the twelfth node N12, and the path where the first dynamic frozen bit DF1 is "1" may be connected to the thirteenth node N13. At the seventh node N7, the path where the first dynamic frozen bit DF1 is "0" may be connected to the fourteenth node N14, and the path where the first dynamic frozen bit DF1 is "1" may be connected to the fifteenth node N15.

[0108] In an embodiment, the SCL decoder SD may select a path up to the ninth node N9 and may calculate a seventh metric M7 based on the likelihood of the path up to the ninth node N9. The SCL decoder SD may select a path up to the tenth node N10 and may calculate an eighth metric M8 based on the likelihood of the path up to the tenth node N10.

[0109] The SCL decoder SD may select a path up to the thirteenth node N13 and may calculate a ninth metric M9 based on the likelihood of the path up to the thirteenth node N13. The SCL decoder SD may select a path up to the fifteenth node N15 and may calculate a tenth metric M10 based on the likelihood of the path up to the fifteenth node N15.

[0110] In an embodiment, at the eighth node N8, the path where the third information bit IF3 is "0" may be connected to the sixteenth node N16, and the path where the third information bit IF3 is "1" may be connected to the seventeenth node N17. At the ninth node N9, the path where the third information bit IF3 is "0" may be connected to the eighteenth node N18, and the path where the third information bit IF3 is "1" may be connected to the nineteenth node N19.

[0111] At the tenth node N10, the path where the third information bit IF3 is "0" is connectable to the twentieth node N20, and the path where the third information bit IF3 is "1" is connectable to the twenty-first node N21. At the eleventh node N11, the path where the third information bit IF3 is "0" is connectable to the twenty-second node N22, and the path where the third information bit IF3 is "1" is connectable to the twenty-third node N23.

[0112] At the twelfth node N12, the path where the third information bit IF3 is "0" is connectable to the twenty-fourth node N24, and the path where the third information bit IF3 is "1" is connectable to the twenty-fifth node N25. At the thirteenth node N13, the path where the third information bit IF3 is "0" is connectable to the twenty-sixth node N26, and the path where the third information bit IF3 is "1" is connectable to the twenty-seventh node N27.

[0113] At the fourteenth node N14, the path where the third information bit IF3 is "0" is connected to the twenty-eighth node N28, and the path where the third information bit IF3 is "1" is connected to the twenty-ninth node N29. At the fifteenth node N15, the path where the third information bit IF3 is "0" is connected to the thirtieth node N30, and the path where the third information bit IF3 is "1" is connected to the thirty-first node N31.

[0114] The SCL decoder SD may collect first candidate data CD1, second candidate data CD2, third candidate data CD3, and fourth candidate data CD4 corresponding to the four paths, respectively, according to the log likelihood ratios LLR. The SCL decoder SD may verify the validity of the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4 based on the first dynamic freezing bit DF1 after finally collecting the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4.

[0115] For example, after finally collecting the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4, the SCL decoder SD may determine the candidate data that does not satisfy the rule of the first dynamic frozen bit DF1 from the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4 as error data. According to the rule of the first dynamic frozen bit DF1, the value of the first dynamic frozen bit DF1 may be defined so that the value obtained by performing an XOR operation with the value of the first information bit IF1 and the value of the second information bit IF2 is a value "0". When the dynamic frozen bit is used in error detection, invalid data in the set of candidate data finally collected may be determined as an error.

[0116] Fig.11D An example of using the first dynamic freeze bit DF1 in error correction is shown. Figure 1 , Figure 2 , Fig. 9 , Fig. 11B and Fig.11D , when the first dynamic frozen bit DF1 is used in error correction, the SCL decoder SD may select only a path satisfying the rule of the first dynamic frozen bit DF1 in the process of selecting a path.

[0117] According to the rule of the first dynamic frozen bit DF1, the value of the first dynamic frozen bit DF1 may be defined so that a value obtained by performing an XOR operation with the value of the first information bit IF1 and the value of the second information bit IF2 is a value of "0".

[0118] For example, at the fourth node N4, the SCL decoder SD may select a path where the value of the first dynamic frozen bit DF1 is "0", that is, the eighth node N8, so that the rule of the first dynamic frozen bit DF1 is satisfied. For example, the SCL decoder SD may perform an XOR operation based on the value ("0") of the first information bit IF1 and the value ("0") of the second information bit IF2, and select a path corresponding to "0". The SCL decoder SD may calculate the seventh metric M7 based on the likelihood of the path up to the eighth node N8.

[0119] At the fifth node N5, the SCL decoder SD may select a path where the value of the first dynamic frozen bit DF1 is "1", that is, the eleventh node N11, so that the rule of the first dynamic frozen bit DF1 is satisfied. For example, the SCL decoder SD may perform an XOR operation based on the value ("0") of the first information bit IF1 and the value ("1") of the second information bit IF2, and select a path corresponding to "1". The SCL decoder SD may calculate the eighth metric M8 based on the likelihood of the path up to the eleventh node N11.

[0120] At the sixth node N6, the SCL decoder SD may select a path where the value of the first dynamic frozen bit DF1 is "1", that is, the thirteenth node N13, so that the rule of the first dynamic frozen bit DF1 is satisfied. For example, the SCL decoder SD may perform an XOR operation based on the value ("1") of the first information bit IF1 and the value ("0") of the second information bit IF2, and select a path corresponding to "1". The SCL decoder SD may calculate a ninth metric M9 based on the likelihood of the path up to the thirteenth node N13.

[0121] At the seventh node N7, the SCL decoder SD may select a path where the value of the first dynamic frozen bit DF1 is "0", that is, the fourteenth node N14, so that the rule of the first dynamic frozen bit DF1 is satisfied. For example, the SCL decoder SD may perform an XOR operation based on the value ("1") of the first information bit IF1 and the value ("1") of the second information bit IF2, and select a path corresponding to "0". The SCL decoder SD may calculate the tenth metric M10 based on the likelihood of the path up to the fourteenth node N14.

[0122] As described above, the SCL decoder SD may correct errors by pruning paths that do not satisfy the rule of the first dynamic frozen bit DF1 in the process of finding paths of the first candidate data CD1 , the second candidate data CD2 , the third candidate data CD3 , and the fourth candidate data CD4 .

[0123] In an embodiment, FIG. 11A to FIG. 11D Such an example is shown in FIG. 1 , in which a diagram up to the third information bit IF3 is shown and a path up to the first dynamic freeze bit DF1 is found. FIG. 11A to FIG. 11D The described method can similarly find the paths corresponding to the remaining bits not described. Therefore, to avoid redundancy, the additional description will be omitted.

[0124] Fig.12 An example of the conditions under which the SCL decoder SD increases the error detection capability or the error correction capability is shown. Figure 1 , Figure 2 and Fig.12 In an embodiment, the decoding information DI may include structural information about the LDPC code of the first decoder 250.

[0125] In an embodiment, as the degree of the variable node increases, as the factor graph FG (refer to Figure 6 and Figure 7 ) decreases, or as the length of the cycles (e.g., the longest cycle) of the factor graph FG becomes longer, the SCL decoder SD can increase the error detection capability.

[0126] For example, as the degree of the variable node increases, as the factor graph FG (ref. Figure 6 and Figure 7 ) decreases, or as the length of the cycle (e.g., the longest cycle) of the factor graph FG becomes longer, the reliability of error correction of the first decoder 250 may become higher. As the reliability of error correction of the first decoder 250 becomes higher, the SCL decoder SD may increase the error detection capability and may reduce the error correction capability.

[0127] In an embodiment, as the degree of the variable node decreases, as the factor graph FG (refer to Figure 6 and Figure 7 ) increases, or as the length of a cycle (eg, the longest cycle) of the factor graph FG becomes shorter, the SCL decoder SD may increase the error correction capability.

[0128] For example, as the degree of the variable node decreases, as the factor graph FG (ref. Figure 6 and Figure 7 ) increases, or as the length of a cycle (e.g., the longest cycle) of the factor graph FG becomes shorter, the reliability of error correction of the first decoder 250 may become lower. As the reliability of error correction of the first decoder 250 becomes lower, the SCL decoder SD may increase the error correction capability, and may reduce the error detection capability.

[0129] Fig.13 Another example of the conditions under which the SCL decoder SD increases the error detection capability or error correction capability is shown. Figure 1 , Figure 2 and Fig.13 In an embodiment, the decoding information DI may include state information about the first error correction decoding of the first decoder 250.

[0130] In an embodiment, as the number of check nodes that do not meet the check condition decreases, as the number of iterations of LDPC decoding increases, or as the syndrome weight decreases, the SCL decoder SD can increase the error detection capability. For example, the syndrome weight can be the sum of the values ​​of the check nodes after LDPC decoding is completed.

[0131] In an embodiment, as the number of check nodes that do not satisfy the check condition decreases, as the number of iterations of LDPC decoding increases, or as the syndrome weight decreases, the reliability of error correction of the first decoder 250 may become higher. As the reliability of error correction of the first decoder 250 becomes higher, the SCL decoder SD may increase the error detection capability and may reduce the error correction capability.

[0132] In an embodiment, as the number of check nodes that do not satisfy the check condition increases, as the number of iterations of LDPC decoding decreases, or as the syndrome weight becomes larger, the SCL decoder SD may increase the error correction capability.

[0133] For example, as the number of check nodes that do not satisfy the check condition increases, as the number of iterations of LDPC decoding decreases, or as the syndrome weight becomes larger, the reliability of error correction of the first decoder 250 may become lower. As the reliability of error correction of the first decoder 250 becomes lower, the SCL decoder SD may increase the error correction capability and may reduce the error detection capability.

[0134] Fig.14An example of a method in which the SCL decoder SD adjusts the use of dynamic freeze bits is shown. Figure 1 , Figure 2 , Fig. 9 and Fig.14 In operation S310, the SCL decoder SD may determine whether to increase the error correction capability. When the error correction capability needs to be increased, in operation S320, the SCL decoder SD may use the dynamic freeze bit DF for error correction.

[0135] For example, the SCL decoder SD can use the highest position dynamic frozen bit DF among the dynamic frozen bits DF being used for error detection for error correction. When the previous position dynamic frozen bit DF is used for error correction, all candidate paths corresponding to the error can be pruned, and thus, the error can be further reduced.

[0136] When the error correction capability does not need to be increased, the SCL decoder SD may determine whether to increase the error detection capability in operation S330. When the error detection capability needs to be increased, the SCL decoder SD may use the dynamic freeze bit DF having a later position for error detection in operation S340.

[0137] For example, the SCL decoder SD can use the most recent dynamic frozen bit DF among the dynamic frozen bits DF being used for error correction for error detection. When the previous dynamic frozen bits DF are used for error correction, more candidate paths corresponding to errors can be pruned, and thus, errors can be further reduced.

[0138] When the error correction capability does not need to be increased and the error detection capability does not need to be increased, the SCL decoder SD may maintain the use of the dynamic freeze bit DF. For example, the current position of the dynamic freeze bit DF may be maintained by the SCL decoder SD.

[0139] Fig.15 FIG. 3 shows an error correction code block 300 according to another embodiment. In an embodiment, the error correction code block 300 may correspond to Figure 1 The error correction code block 127 of the memory controller 120 of the storage device 100 is configured.

[0140] Reference Figure 1 and Fig.15 , the error correction code block 300 may include an encoding block 310 and a decoding block 340. The encoding block 310 may perform error correction encoding on the first data DT1 to be written in the nonvolatile memory device 110. The decoding block 340 may perform error correction decoding on the fourth data DT4 read from the nonvolatile memory device 110.

[0141] The encoding block 310 may include a first encoder 320 and a second encoder 330. The first encoder 320 may perform a first error correction encoding on the first data DT1 and may generate the second data DT2. For example, the first error correction encoding may include polar code encoding. However, the type of the first error correction encoding is not limited thereto.

[0142] The second encoder 330 may perform second error correction coding on the second data DT2 and may generate third data DT3. For example, the second error correction coding may include LDPC coding. However, the type of the second error correction coding is not limited thereto.

[0143] The configuration and operation of the first encoder 320 and the second encoder 330 may be similar to Figure 2 The configuration and operation of the first encoder 220 and the second encoder 230 are the same. Therefore, in order to avoid redundancy, additional description will be omitted.

[0144] The decoding block 340 may include a first decoder 350, a second decoder 360, and a third encoder 370. The first decoder 350 may perform a first error correction decoding on the fourth data DT4 or the fourth intermediate data ID4, and may generate the fifth data DT5. For example, the first error correction decoding may include LDPC decoding. However, the type of the first error correction decoding is not limited thereto.

[0145] The first decoder 350 may generate decoding information DI about the first error correction decoding. For example, the decoding information DI may include information about the structure of the first decoder 350 or information about the state of the first error correction decoding (e.g., the state of the result of the first error correction decoding). The first decoder 350 may transmit the decoding information DI to the second decoder 360.

[0146] The second decoder 360 may receive the decoding information DI from the first decoder 350. The second decoder 360 may control the second error correction decoding based on the decoding information DI about the first error correction decoding.

[0147] The second decoder 360 may perform second error correction decoding on the fifth data DT5 and may generate sixth data DT6 or third intermediate data ID3. For example, the second error correction decoding may include SCL decoding. However, the type of the second error correction decoding is not limited thereto.

[0148] The third encoder 370 may perform third error correction coding on the third intermediate data ID3, and may generate fourth intermediate data ID4. For example, the third error correction coding may include LDPC coding. However, the type of the third error correction coding is not limited thereto.

[0149] According to an embodiment, the decoding block 340 may combine (or cascade) and perform heterogeneous error correction decoding. In this case, the decoding block 340 may control the second error correction decoding to be performed after the first error correction decoding based on the decoding information DI of the first error correction decoding previously performed. Because the decoding information DI of the first error correction decoding previously performed is applied to the second error correction decoding performed after the first error correction decoding, the accuracy of error detection or error correction of the decoding block 340 may be further improved.

[0150] In addition, according to an embodiment, the decoding block 340 may combine (or concatenate) heterogeneous error correction decodings, and the combined (or concatenated) decodings may be repeatedly performed. In this case, in each iteration, the decoding block 340 may control the second error correction decoding to be performed after the first error correction decoding based on the decoding information DI of the first error correction decoding previously performed. In each iteration of the combined (or concatenated) decoding, since the decoding information DI of the first error correction decoding previously performed is applied to the second error correction decoding performed after the first error correction decoding, the second error correction decoding may be performed differently for each combined (or concatenated) decoding, and the accuracy of error detection or error correction of the decoding block 340 may be further improved.

[0151] In the embodiments, reference Fig.15 An example is described in which the third encoder 370 is used to generate the fourth intermediate data ID4 from the third intermediate data ID3. However, the third encoder 370 may be omitted according to the types of encoding and decoding algorithms used by the first encoder 320 and the second decoder 360 or according to the types of encoding and decoding algorithms used by the second encoder 330 and the first decoder 350. For example, the third intermediate data ID3 generated by the second decoder 360 may be directly input to the first decoder 350.

[0152] Fig.16 An example of a second decoder 360 of the decoding block 340 is shown. Figure 1 , Fig.15 and Fig.16 , the second decoder 360 may receive fifth data DT5. The fifth data DT5 may include the first decoded bit DB1 and the corresponding log-likelihood ratio LLR.

[0153] The second decoder 360 may include a code pattern CG and an SCL decoder SD. The code pattern CG may apply polar code decoding to the fifth data DT5. The code pattern CG may have the same Figure 4 The code graph CG has the same structure and can be used with Figure 4 The operation is performed in the direction opposite to the direction of the code graph CG.

[0154] The result of the operation of the code graph CG may be the second intermediate data ID2. As in the first intermediate data ID1, the second intermediate data ID2 may sequentially include a frozen bit FB, a first information bit IF1, a second information bit IF2, a first dynamic frozen bit DF1, a third information bit IF3, a fourth information bit IF4, a second dynamic frozen bit DF2, and a fifth information bit IF5.

[0155] Because the frozen bit FB has a fixed value (e.g., a known bit), the frozen bit FB may not have a log-likelihood ratio LLR. Since the first information bit IF1, the second information bit IF2, the first dynamic frozen bit DF1, the third information bit IF3, the fourth information bit IF4, the second dynamic frozen bit DF2, and the fifth information bit IF5 have a changed value, the bits IF1, IF2, DF1, IF3, IF4, DF2, and IF5 may have corresponding log-likelihood ratios LLR.

[0156] The SCL decoder SD may receive the second intermediate data ID2. The SCL decoder SD may generate a given number of candidate data based on the values ​​of the first information bit IF1, the second information bit IF2, the first dynamic frozen bit DF1, the third information bit IF3, the fourth information bit IF4, the second dynamic frozen bit DF2, and the fifth information bit IF5 and the corresponding log-likelihood ratios LLR. For example, based on the second intermediate data ID2, the SCL decoder SD may generate the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4.

[0157] The SCL decoder SD may select one of the first candidate data CD1, the second candidate data CD2, the third candidate data CD3, and the fourth candidate data CD4. When the combined (or cascaded) decoding iterations of the first decoder 350 and the second decoder 360 are not performed a given number of times, the SCL decoder SD may output the third intermediate data ID3 as the selected candidate data. The third intermediate data ID3 may sequentially include a frozen bit FB, a first information bit IF1, a second information bit IF2, a first dynamic frozen bit DF1, a third information bit IF3, a fourth information bit IF4, a second dynamic frozen bit DF2, a fifth information bit IF5, and a corresponding log-likelihood ratio LLR.

[0158] When the iteration of the combined (or cascaded) decoding of the first decoder 350 and the second decoder 360 is performed a given number of times, the SCL decoder SD may output the sixth data DT6 as the selected candidate data. For example, the sixth data DT6 may be data whose error correction is completed by the decoding block 340. The sixth data DT6 may sequentially include the first information bit IF1, the second information bit IF2, the third information bit IF3, the fourth information bit IF4, and the fifth information bit IF5.

[0159] In addition to reference Fig.15 and Fig.16 Except for the differences between the descriptions given, the configuration and operation of the first decoder 350 and the second decoder 360 may be the same as those described with reference to Figure 2 The configuration and operation of the described first decoder 250 and the second decoder 260 are the same. Therefore, in order to avoid redundancy, additional description will be omitted.

[0160] Fig.17 An example of a method in which the error correction code block 300 performs error correction decoding is shown. Figure 1 , Fig.15 and Fig.17 In operation S410 , the error correction code block 300 may receive data. For example, the decoding block 340 of the error correction code block 300 may receive fourth data DT4 read from the nonvolatile memory device 110 through the bus 121 .

[0161] In operation S420, the decoding block 340 may perform first decoding based on the received data and may generate first decoded data. For example, the first decoder 350 of the decoding block 340 may perform first error correction decoding (eg, LDPC decoding) on ​​the fourth data DT4 and may generate fifth data DT5 as first decoded data.

[0162] In operation S430, the decoding block 340 may adjust (e.g., control) the correction detection capability based on the decoding information DI of the first decoding. For example, the first decoder 350 of the decoding block 340 may transmit the decoding information DI about the first error correction decoding to the second decoder 360. The second decoder 360 may determine a method of performing the second error correction decoding (e.g., SCL decoding) based on the decoding information DI. For example, the second decoder 360 may increase the error correction capability or may reduce the error detection capability, or the second decoder 360 may reduce the error correction capability or may increase the error detection capability.

[0163] In operation S440, the decoding block 340 may perform a second decoding based on the first decoded data and the adjusted error correction detection capability, and may generate the second decoded data. For example, the second decoder 360 of the decoding block 340 may perform a second error correction decoding on the fifth data DT5 based on the adjusted error correction capability and the adjusted error detection capability, and may generate the sixth data DT6 as the second decoded data. For example, the first decoding and the second decoding may be performed iteratively.

[0164] In operation S450, the decoding block 340 may determine whether the number of iterations reaches the first threshold TH1. For example, the decoding block 340 may determine whether the number of times the first error correction decoding of the first decoder 350 and the second error correction decoding of the second decoder 360 are combined (or concatenated) and repeated reaches the first threshold TH1.

[0165] When the number of iterations does not reach the first threshold TH1, in operation S460, the decoding block 340 may control to perform another iteration. For example, the decoding block 340 may perform encoding on the second decoded data. For example, the third encoder 370 of the decoding block 340 may perform a third error correction encoding (e.g., LDPC encoding) on ​​the second decoded data (i.e., the third intermediate data ID3).

[0166] In operation S470, the decoding block 340 may assign a log likelihood ratio LLR based on the metric of the second error correction decoding. For example, the third encoder 370 of the decoding block 340 may be an initial log likelihood ratio for each bit based on the metric for each bit of the third intermediate data ID3 calculated by the second decoder 360. Then, the decoding block 340 may start the process again from operation S420.

[0167] When the number of iterations reaches the first threshold TH1, the decoding block 340 may output second decoded data in operation S480. For example, the second decoder 360 of the decoding block 340 may output sixth data DT6 as error correction completed data.

[0168] In an embodiment, increasing the error detection capability may include increasing the number of frozen bits used in error detection. Since the increase in error detection capability results in a decrease in the number of frozen bits used in error correction, the error correction capability may be reduced.

[0169] Likewise, increasing the error correction capability may include increasing the number of frozen bits used in error correction. Since the increase in error correction capability results in a decrease in the number of frozen bits used in error detection, the error detection capability may decrease.

[0170] The decoding block 340 may reduce the number of locally distributed errors by setting the error correction capability to be greater than the error detection capability in an initial iteration of combined (or concatenated) decoding of the first error correction decoding of the first decoder 350 and the second error correction decoding of the second decoder 360. The decoding block 340 may detect errors caused by the accumulation of errors of the global log-likelihood ratio LLR by setting the error detection capability to be greater than the error correction capability after an initial iteration of combined (or concatenated) decoding of the first error correction decoding of the first decoder 350 and the second error correction decoding of the second decoder 360.

[0171] Fig.18 Another example of the conditions under which the SCL decoder SD increases the error detection capability or error correction capability is shown. Figure 1 , Figure 2 and Fig.18 In an embodiment, the decoding information DI may include state information about the first error correction decoding of the first decoder 250.

[0172] In an embodiment, as the number of check nodes that do not meet the check condition decreases, as the number of iterations of LDPC decoding increases, as the syndrome weight decreases, or as the number of iterations of combined (or cascaded) decoding increases, the SCL decoder SD can increase the error detection capability. For example, the syndrome weight can be the sum of the values ​​of the check nodes after LDPC decoding is completed.

[0173] For example, as the number of check nodes that do not satisfy the check condition decreases, as the number of iterations of LDPC decoding increases, as the syndrome weight decreases, or as the number of iterations of combined (or cascaded) decoding increases, the reliability of error correction of the first decoder 250 may become higher. As the reliability of error correction of the first decoder 250 becomes higher, the SCL decoder SD may increase the error detection capability and may reduce the error correction capability.

[0174] In an embodiment, the SCL decoder SD may increase error correction capability as the number of check nodes that do not meet the check condition increases, as the number of LDPC decoding iterations decreases, as the syndrome weight becomes larger, or as the number of combined (or cascaded) decoding iterations decreases.

[0175] For example, as the number of check nodes that do not satisfy the check condition increases, as the number of iterations of LDPC decoding decreases, as the syndrome weight becomes larger, or as the number of iterations of combined (or cascaded) decoding decreases, the reliability of error correction of the first decoder 250 may become lower. As the reliability of error correction of the first decoder 250 becomes lower, the SCL decoder SD may increase the error correction capability and may reduce the error detection capability.

[0176] In an embodiment, the structural information of the decoding information DI of the decoding block 340 may be the same as that of the reference Fig.12 The structural information of the decoding information DI described is the same. Therefore, in order to avoid redundancy, additional description will be omitted.

[0177] Fig.19 A first example of a method in which the decoding block 340 performs combined (or concatenated) decoding is shown. As described above, the metric may be calculated based on the log likelihood ratio LLR of each bit of the data. Figure 1 , Fig.15 and Fig.19In operation S510, the decoding block 340 may calculate the difference between the highest metric and the second height metric. For example, the decoding block 340 may calculate the difference between the highest metric and the second height metric among the metric of the last bit of the first candidate data CD1, the metric of the last bit of the second candidate data CD2, the metric of the last bit of the third candidate data CD3, and the metric of the last bit of the fourth candidate data CD4.

[0178] In operation S520, the decoding block 340 may determine whether the difference is greater than a second threshold value TH2. When the difference is not greater than the second threshold value TH2, the decoding block 340 may perform the next iteration of the combined (or cascaded) decoding. The SCL decoder SD may select the candidate data with the lowest metric of the last bit as the third intermediate data ID3. The SCL decoder SD may calculate an initial log-likelihood ratio LLR based on the metric of the bits of the third intermediate data ID3.

[0179] When the difference is greater than the second threshold TH2, the decoding block 340 may terminate the combined (or concatenated) decoding iterations early as the first option OPT1 in operation S530. The decoding block 340 may output the candidate data with the lowest metric of the last bit as the sixth data DT6.

[0180] When the difference is greater than the second threshold value TH2, in operation S530, as the second option OPT2, the decoding block 340 may adjust the log likelihood ratio LLR. For example, the decoding block 340 may select the candidate data with the lowest metric of the last bit as the third intermediate data ID3. The SCL decoder SD may calculate the initial log likelihood ratio LLR according to the metric of the bit of the third intermediate data ID3. The SCL decoder SD may adjust the log likelihood ratio LLR by further reducing the calculated log likelihood ratio LLR. The decoding block 340 may accelerate error correction by adjusting the log likelihood ratio LLR.

[0181] In an embodiment, each of the first option OPT1 and the second option OPT2 may be enabled or disabled by the external host device or processor 124. As another example, the first option OPT1 and the second option OPT2 may have different thresholds and may be enabled or disabled together by the external host device or processor 124.

[0182] Fig. 20 A second example of a method in which the decoding block 340 performs combined (or concatenated) decoding is shown. Figure 1 , Fig.15 and Fig. 20 In operation S610, the decoding block 340 may count the number of candidate data. For example, the decoding block 340 may count the number of valid candidate data determined to be error-free in the error detection process.

[0183] In operation S620, the decoding block 340 may determine whether the number of counts is greater than a third threshold value TH3. When the number of counts is not greater than the third threshold value TH3, the decoding block 340 may perform the next iteration of combined (or cascaded) decoding. The SCL decoder SD may select the candidate data with the lowest metric of the last bit as the third intermediate data ID3. The SCL decoder SD may calculate an initial log-likelihood ratio LLR based on the metric of the bits of the third intermediate data ID3.

[0184] When the number of counts is greater than the third threshold value TH3, in operation S630, the decoding block 340 may adjust the log likelihood ratio LLR. For example, the decoding block 340 may select the candidate data with the lowest metric of the last bit as the third intermediate data ID3. The SCL decoder SD may calculate the initial log likelihood ratio LLR according to the metric of the bit of the third intermediate data ID3. The SCL decoder SD may adjust the log likelihood ratio LLR by further reducing the calculated log likelihood ratio LLR. The decoding block 340 may accelerate error correction by adjusting the log likelihood ratio LLR.

[0185] Fig.21 is a diagram of a system 1000 to which a storage device is applied according to an embodiment. Fig.21 The system 1000 may be substantially a mobile system such as a portable communication terminal (eg, a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Fig.21 The system 1000 is not necessarily limited to a mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (eg, a navigation device).

[0186] refer to Fig.21 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0187] The main processor 1100 may control all operations of the system 1000, and more specifically, control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0188] The main processor 1100 may include at least one CPU core 1110, and may also include a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is a dedicated circuit for high-speed data operations (e.g., artificial intelligence (AI) data operations). The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 1100.

[0189] Memories 1200a and 1200b may be used as main memory devices of system 1000. Although each of memories 1200a and 1200b may include volatile memory such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memories 1200a and 1200b may also include nonvolatile memory such as flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM). Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0190] The storage devices 1300a and 1300b may be used as non-volatile memory devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers (STRG CTRL) 1310a and 1310b and NVM (non-volatile memory) 1320a and 1320b, respectively, and the NVM 1320a and 1320b are configured to store data via the control of the storage controllers 1310a and 1310b. Although the NVM 1320a and 1320b may include a flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVM 1320a and 1320b may also include other types of NVMs, such as PRAM and / or RRAM.

[0191] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and may be included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of solid-state device (SSD) or memory card, and may be detachably combined with other components of the system 1000 through an interface such as the connection interface 1480 to be described below. The storage devices 1300a and 1300b may be devices that apply a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Memory Express (NVMe), but are not limited thereto.

[0192] The image capture device 1410 may capture a still image or a moving image. The image capture device 1410 may include a camera, a video camera, and / or a webcam.

[0193] The user input device 1420 may receive various types of data input by a user of the system 1000 and may include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0194] The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the system 1000, and may convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0195] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0196] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0197] The power supply device 1470 may appropriately convert power supplied from a battery embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0198] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented using various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, MultiMediaCard (MMC) interface, eMMC interface, UFS interface, embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0199] In the embodiments, reference Figures 1 to 20 The described storage device 100 can be implemented with storage devices 1300a and 1300b. Storage devices 1300a and 1300b can perform combined (or cascaded) error correction decoding, and can change the method of performing subsequent error correction decoding based on decoding information about previous error correction decoding. In addition, storage devices 1300a and 1300b can repeatedly perform combined (or cascaded) error correction decoding, and can change the method of performing initial combined (or cascaded) decoding and the method of performing subsequent combined (or cascaded) decoding.

[0200] In the above, components are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. are used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. do not refer to any form of order or numerical meaning.

[0201] Above, the components according to the embodiments are referenced by using blocks. These blocks can be implemented with various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in hardware devices, software such as applications, or a combination of hardware devices and software. In addition, these blocks may include circuits implemented with semiconductor elements in integrated circuits, or circuits registered as intellectual property (IP). For example, an IP may include a circuit system that performs a specific function, and may have a design that includes a trade secret.

[0202] According to an embodiment, a storage device may sequentially perform first error correction decoding and second error correction decoding, and may adjust a method of performing the second error correction decoding based on decoding information about the first error correction decoding. A storage device and an operating method of the storage device are provided, which improves reliability by correcting errors with improved accuracy because information about the first error correction decoding is applied to the second error correction decoding.

[0203] While various aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a non-volatile memory device; as well as A controller configured to: receiving first data from the non-volatile memory device; performing a first error correction decoding on the first data to obtain second data; controlling an error correction capability and an error detection capability of a second error correction decoding based on information about the first error correction decoding; as well as The second error correction decoding is performed on the second data based on the error correction capability and the error detection capability to obtain third data.

2. The storage device according to claim 1, wherein: The second error correction decoding includes polar code consecutive erasure list decoding.

3. The storage device according to claim 2, wherein: The third data includes information bits, frozen bits and dynamic frozen bits, and The controller is further configured to control which of the dynamic frozen bits are used for error correction and which of the dynamic frozen bits are used for error detection.

4. The storage device according to claim 3, wherein: The controller is further configured to increase the error correction capability by controlling a dynamic frozen bit having a preceding position among the dynamic frozen bits for the error detection to be used for the error correction.

5. The storage device according to claim 1, wherein: The controller includes a low density parity check decoder configured to perform the first error correction decoding, and The information about the first error correction decoding includes structural information about the low-density parity check decoder.

6. The storage device according to claim 1, wherein: The controller includes a low density parity check decoder configured to perform the first error correction decoding, and The information about the first error correction decoding indicates a degree of each variable node in a variable node of a low density parity check code of the low density parity check decoder.

7. The storage device according to claim 1, wherein: The controller includes a low density parity check decoder configured to perform the first error correction decoding, and The information about the first error correction decoding indicates the number of cycles of the low density parity check decoder.

8. The storage device according to claim 1, wherein: The controller includes a low density parity check decoder configured to perform the first error correction decoding, and The information about the first error correction decoding indicates the length of a cycle of the low-density parity check decoder.

9. The storage device according to claim 1, wherein: The first error correction decoding comprises low density parity check decoding, and The information about the first error correction decoding includes status information about the low-density parity check decoding.

10. The storage device according to claim 1, wherein: The first error correction decoding includes low density parity check decoding performed using check nodes, and The information about the first error correction decoding indicates the number of check nodes that do not meet the check condition.

11. The storage device according to claim 1, wherein: The first error correction decoding comprises low density parity check decoding, and The information about the first error correction decoding indicates the number of iterations of the low-density parity check decoding.

12. The storage device according to claim 1, wherein: The first error correction decoding comprises low density parity check decoding, and The information about the first error correction decoding indicates a syndrome weight of the low-density parity check decoding.

13. The storage device according to claim 1, wherein: The controller is also configured to: performing error correction encoding corresponding to the first error correction decoding on the third data to obtain fourth data; and The first error correction decoding and the second error correction decoding are performed on the fourth data.

14. The storage device according to claim 13, wherein: The information about the first error correction decoding indicates the number of iterations of the first error correction decoding and the second error correction decoding performed.

15. A storage device, comprising: a non-volatile memory device; as well as A controller configured to: receiving first data from the non-volatile memory device; performing a first error correction decoding on the first data to obtain second data; controlling a method for performing a second error correction decoding based on information from the first error correction decoding; performing the second error correction decoding on the second data based on the method to obtain third data; as well as The first error correction decoding and the second error correction decoding are repeatedly performed by further performing the first error correction decoding and the second error correction decoding on the third data.

16. The storage device according to claim 15, wherein: The second error correction decoding includes polar code consecutive erasure list decoding, and The controller is further configured to terminate the repeated execution of the first error correction decoding and the second error correction decoding based on that a difference between a metric of candidate data selected from a group of candidate data obtained by decoding the polar code continuous deletion list and a metric of another candidate data in the group of candidate data is greater than a threshold.

17. The storage device according to claim 15, wherein: The first error correction decoding comprises low density parity check decoding, wherein the second error correction decoding comprises polar code continuous erasure list decoding, and The controller is further configured to adjust the likelihood of bits of the selected data to be transmitted to the low-density parity check decoding based on a difference between a metric of candidate data selected from a group of candidate data obtained by decoding the polar code consecutive deletion list and a metric of another candidate data among the group of candidate data being greater than a threshold.

18. The storage device according to claim 15, wherein: The first error correction decoding comprises low density parity check decoding, wherein the second error correction decoding comprises polar code continuous erasure list decoding, and The controller is further configured to adjust the likelihood of bits of the selected data to be transmitted to the low-density parity check decoding based on the number of valid candidate data in a set of candidate data obtained by decoding the polar code consecutive deletion list being greater than a threshold.

19. A method of operating a storage device, the storage device comprising a non-volatile memory device and a controller, the method comprising: performing, by the controller, low density parity check decoding on first data transmitted from the nonvolatile memory device to obtain second data; controlling, by the controller, an error correction capability and an error detection capability of polar code consecutive erasure list decoding based on decoding information about the low density parity check decoding; as well as The controller performs the polar code consecutive erasure list decoding on the second data based on the error correction capability and the error detection capability to obtain third data.

20. The method according to claim 19, further comprising: performing, by the controller, the low density parity check decoding on the third data; modifying, by the controller, the error correction capability and the error detection capability; as well as The polar code continuous erasure list decoding is performed by the controller.

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