Memory controller, operating method thereof and memory system

Abstract

The embodiment of the invention provides a memory controller, an operation method thereof and a memory system. The memory controller comprises: a first buffer configured to buffer a valid data table and mapping information to be updated; wherein the valid data table is used for recording a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the to-be-updated mapping information comprises at least one piece of mapping information from a logic address to a physical address; each conversion unit corresponds to one physical address; the second buffer is configured to buffer the mapping table; wherein the mapping table is used for recording multiple pieces of mapping information; the acceleration processing circuit is configured to update the mapping table based on the to-be-updated mapping information; and updating the valid data table based on the to-be-updated mapping information.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory controller and an operating method thereof, and a memory system. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. With the continuous advancement of semiconductor manufacturing technology, the feature size of semiconductor devices has continued to shrink, the integration density of memory has become higher and higher, and its performance has become more and more powerful.

[0003] Semiconductor memory devices can be controlled by memory controllers, wherein a processor in the memory controller can implement various operations on the memory device by executing software. Therefore, how to improve the working efficiency, performance and stability of memory controllers has become an urgent problem to be solved in the industry. Summary of the invention

[0004] The present disclosure provides a memory controller and an operating method thereof, and a memory system.

[0005] In a first aspect, the present disclosure provides a memory controller, the memory controller comprising:

[0006] A first buffer, wherein the first buffer is configured to cache a valid data table and mapping information to be updated; wherein the valid data table is used to record a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the mapping information to be updated includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address;

[0007] A second buffer, wherein the second buffer is configured to cache a mapping table; wherein the mapping table is used to record a plurality of mapping information;

[0008] An acceleration processing circuit is coupled to the first buffer and the second buffer respectively, and the acceleration processing circuit is configured as follows:

[0009] Update the mapping table based on the mapping information to be updated;

[0010] The valid data table is updated based on the mapping information to be updated.

[0011] In some embodiments, the accelerated processing circuit includes a register; the register is configured to store an invalid physical address;

[0012] The acceleration processing circuit is specifically configured as follows:

[0013] The valid data table is updated based on the mapping information to be updated and the invalid physical address.

[0014] In some embodiments, the acceleration processing circuit is specifically configured as follows:

[0015] In response to the physical address in the mapping information to be updated being the same as the invalid physical address, reducing the valid conversion unit count of the corresponding storage block;

[0016] or,

[0017] In response to the physical address in the to-be-updated mapping information being different from the invalid physical address, the valid conversion unit count of the corresponding storage block is increased.

[0018] In some embodiments, the acceleration processing circuit is further configured to:

[0019] Determining an upper limit value and a lower limit value of the effective conversion unit count;

[0020] In response to the valid conversion unit count being equal to the upper limit value, stopping increasing the valid conversion unit count;

[0021] and / or,

[0022] In response to the valid conversion unit count being equal to the lower limit value, decreasing the valid conversion unit count is stopped.

[0023] In some embodiments, the acceleration processing circuit is further configured to:

[0024] The upper limit value is determined according to the number of the conversion units in the storage block.

[0025] In some embodiments, the accelerated processing circuit includes a list access assist circuit, and the register includes a zero register.

[0026] In some embodiments, the memory controller further comprises:

[0027] A processor is coupled to the first buffer, and the processor is configured to generate the mapping information to be updated based on the received logical address, and cache the mapping information to be updated in the first buffer.

[0028] In some embodiments, the processor is further configured to: send an update command to the accelerated processing circuit;

[0029] The acceleration processing circuit is specifically configured as follows:

[0030] In response to the update command, acquiring the mapping information to be updated from the first buffer;

[0031] The valid data table is automatically updated based on the mapping information to be updated.

[0032] In some embodiments, the processor includes a storage protection circuit; the storage protection circuit is configured to:

[0033] The processor is prohibited from updating the valid data table.

[0034] In some embodiments, the processor is further configured to:

[0035] Responding to a trim command from a host, acquiring the valid data table from the first buffer;

[0036] Based on the valid data table, a storage block in the memory device that needs to be garbage collected is determined.

[0037] In a second aspect, the present disclosure provides an operating method of a memory controller, the memory controller comprising a first cache, a second cache, and an acceleration processing circuit respectively coupled to the first cache and the second cache; the operating method comprising:

[0038] The first buffer caches a valid data table and mapping information to be updated; wherein the valid data table is used to record a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the mapping information to be updated includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address;

[0039] The second buffer caches a mapping table; wherein the mapping table is used to record a plurality of mapping information;

[0040] The acceleration processing circuit updates the mapping table based on the mapping information to be updated, and updates the valid data table based on the mapping information to be updated.

[0041] In some embodiments, the accelerated processing circuit includes a register configured to store an invalid physical address;

[0042] The acceleration processing circuit updates the valid data table based on the mapping information to be updated, including:

[0043] The acceleration processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address.

[0044] In some embodiments, the acceleration processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address, including:

[0045] In response to the physical address in the mapping information to be updated being the same as the invalid physical address, the acceleration processing circuit reduces the valid conversion unit count of the corresponding storage block;

[0046] or,

[0047] In response to the physical address in the mapping information to be updated being different from the invalid physical address, the accelerated processing circuit increases the valid conversion unit count of the corresponding storage block.

[0048] In some embodiments, the operating method further includes:

[0049] The accelerated processing circuit determines the upper limit and the lower limit of the effective conversion unit count;

[0050] In response to the valid conversion unit count being equal to the upper limit value, the acceleration processing circuit stops increasing the valid conversion unit count;

[0051] and / or,

[0052] In response to the valid conversion unit count being equal to the lower limit value, the speed-up processing circuit stops decreasing the valid conversion unit count.

[0053] In some embodiments, the accelerated processing circuit determines the upper limit value of the valid conversion unit count, including:

[0054] The acceleration processing circuit determines the upper limit value according to the number of the conversion units in the storage block.

[0055] In some embodiments, the memory controller further includes a processor; the processor is coupled to the first buffer; and the operation method further includes:

[0056] The processor generates the mapping information to be updated based on the received logical address, and caches the mapping information to be updated in the first cache.

[0057] In some embodiments, the operating method further includes:

[0058] The processor sends an update command to the acceleration processing circuit;

[0059] The acceleration processing circuit acquires the mapping information to be updated from the first buffer in response to the update command;

[0060] The acceleration processing circuit updates the valid data table based on the mapping information to be updated, including:

[0061] The acceleration processing circuit automatically updates the valid data table based on the mapping information to be updated.

[0062] In some embodiments, the processor includes a storage protection circuit; and the operating method further includes:

[0063] The storage protection circuit prohibits the processor from updating the valid data table.

[0064] In some embodiments, the operating method further includes:

[0065] The processor obtains the valid data table from the first buffer in response to a trim command from the host;

[0066] The processor determines a storage block in a memory device that needs to be garbage collected based on the valid data table.

[0067] In a third aspect, the present disclosure provides a memory system, comprising:

[0068] a memory device, the memory device comprising a plurality of memory blocks;

[0069] The memory controller described in any of the above embodiments is configured to control the memory device and update a valid data table; wherein the valid data table is used to record multiple valid conversion unit counts; and the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block.

[0070] In the disclosed embodiment, the memory controller includes an accelerated processing circuit, which is configured to update the mapping table based on the mapping information to be updated, and to update the valid data table based on the mapping information to be updated. In this way, on the one hand, updating the valid data table through the accelerated processing circuit can reduce the resource usage of the processor and improve the working efficiency and performance of the memory controller; on the other hand, the processor does not need to update the valid data table by executing software, thereby reducing the impact of software errors on the stability of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 A schematic diagram of a system with a memory provided in an embodiment of the present disclosure;

[0072] Figure 2a A schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0073] Figure 2b A schematic diagram of a solid state drive (SSD) provided in an embodiment of the present disclosure;

[0074] Figure 3 A schematic diagram of a memory system provided in an embodiment of the present disclosure;

[0075] Figure 4 A schematic diagram of a mapping table and a valid data table provided in an embodiment of the present disclosure;

[0076] Figure 5 A schematic diagram of a memory controller provided by an embodiment of the present disclosure;

[0077] Figure 6 A schematic diagram of another memory controller provided by an embodiment of the present disclosure;

[0078] Figure 7 A flowchart of a method for operating a memory controller provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0080] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0081] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0082] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0083] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0084] Figure 1 A schematic diagram of a system 100 with memory according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0085] like Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0086] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive or embedded Multi Media Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0087] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and write (also known as programming) operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host 108 through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0088] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0089] In an embodiment of the present disclosure, each of the memory chips (Die) may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), tri-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices may include one or more memory cell arrays, such as an SLC array, an MLC array, a TLC array, a QLC array, or any combination of such memory cell arrays.

[0090] Figure 3A memory system 300 is provided in an embodiment of the present disclosure, and the memory system 300 includes a memory controller 310 and one or more memory devices 320 coupled to the memory controller 310. The memory controller 310 includes at least an accelerated processing circuit 311, a processor 312, a first cache 313, and a second cache 314, and the memory device 320 includes a plurality of storage blocks.

[0091] The processor 312 may control the overall operation of the memory controller 310 to perform operations such as reading, writing and erasing on the memory device 320. Exemplarily, the processor 312 may be configured to run various firmware or software in the memory controller 310. The processor 312 may include a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 312 may also include a general-purpose processor or any conventional processor.

[0092] In the memory controller 310, a flash translation layer (FTL) can be used to maintain mapping information from logical addresses to physical addresses. The logical address constitutes the storage space of the memory device 320 perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the memory device 320. In some embodiments, the address mapping can also be implemented using an intermediate address form, for example, mapping the logical address to an intermediate address, and then further mapping the intermediate address to a physical address, where the intermediate address can include one or more levels of intermediate addresses. The flash translation layer can also be used to perform maintenance operations such as wear leveling (Wear Leveling) and garbage collection (Garbage Collection, GC).

[0093] In some embodiments, the flash translation layer can be implemented as software and / or firmware. The processor 312 can perform the various maintenance operations described above by driving the flash translation layer. In other embodiments, the flash translation layer can be implemented by various hardware automation circuits configured to perform the maintenance operations described above. In other words, the flash translation layer can be implemented as hardware, and the maintenance operations described above can be performed by hardware.

[0094] The second buffer 314 may be configured as a cache mapping table L2P_tab, and the second buffer 314 includes but is not limited to a double data rate (DDR) synchronous dynamic random access memory. Figure 4 As shown, the mapping table L2P_tab may include multiple entries, each of which records mapping information from a logical address (Ltu) to a physical address (Fla), and a storage block number corresponding to the physical address. It should be noted that the mapping table L2P_tab cached by the second buffer 314 is a part of the L2P mapping table of the entire memory device 320, and the other part of the L2P mapping table is stored in the memory device 320.

[0095] The first buffer 313 may be configured to cache the valid data table VTC_tab and the mapping information to be updated L2P_temp. The first buffer 313 includes but is not limited to a tightly coupled memory (TCM), etc. The first buffer 313 may realize high-speed interaction with the processor 312. Here, the mapping information to be updated L2P_temp may be generated by the processor 312 based on the logical address received from the external host, and cached by the processor 312 into the first buffer 313. In some embodiments, the mapping information to be updated L2P_temp may also be generated internally by the memory controller 310 in operations such as garbage collection.

[0096] like Figure 4 As shown, the valid data table VTC_tab may include multiple entries, each entry records a storage block number and its corresponding valid conversion unit count (Valid Transmission Unit Count, VTC), and each valid conversion unit count indicates the number of conversion units storing valid data in a corresponding storage block. It should be noted that a storage block may include multiple conversion units, and each conversion unit corresponds to a physical address. The capacity size of the conversion unit and the physical location in the memory device 320 are not overly limited here. Exemplarily, the conversion unit can be a physical unit smaller than a storage page (Page) (the conversion unit can also be a storage page). Among them, the conversion unit with valid data recorded is called a valid conversion unit, and the conversion unit with invalid data recorded is called an invalid conversion unit. The invalid data in the invalid conversion unit can be cleared when the memory controller 310 performs a garbage collection operation. In some embodiments, the memory controller 310 can also set one or more specific conversion units in the storage block as invalid conversion units according to actual work requirements.

[0097] The valid conversion unit count can reflect the number of valid conversion units in the storage block. Therefore, the occupied storage space of the memory device 320 can be obtained according to the valid data table VTC_tab, and the size of the remaining storage space can be further inferred. The valid data table VTC_tab can also be used to indicate which storage blocks need to be garbage collected.

[0098] It should be noted that Figure 4 The contents and values ​​in the valid data table VTC_tab and the mapping table L2P_tab are shown only as examples for easy understanding and do not limit the present application in any way.

[0099] The acceleration processing circuit 311 may be configured to update the mapping table L2P_tab in the second buffer 314 based on the mapping information to be updated L2P_temp. Here, the acceleration processing circuit 311 includes but is not limited to a direct memory access (DMA) circuit and a table access assist (TAA) circuit. The acceleration processing circuit 311 may increase the speed at which the processor 312 updates the mapping information to be updated L2P_temp to the mapping table L2P_tab in the second buffer 314, thereby improving the performance of the memory system 300.

[0100] It is understandable that when the memory device 320 is written, erased, garbage collected, etc., the data stored in the conversion unit in the storage block will change, thereby causing the mapping information of the logical address to the physical address corresponding to each conversion unit to change, and the valid conversion unit count corresponding to each storage block will also change. Therefore, it is necessary to update the valid data table VTC_tab in the first buffer 313 and the mapping table L2P_tab in the second buffer 314 in real time. In other words, the update of the mapping table L2P_tab is interrelated with the update of the valid data table VTC_tab.

[0101] In this way, the processor 312 can access the first buffer 313 at a faster speed to cache the mapping information L2P_temp to be updated in the first buffer 313. Then, the processor 312 can send an update command to the acceleration processing circuit 311, and the acceleration processing circuit 311 responds to the update command and obtains the mapping information L2P_temp to be updated from the first buffer 313. Finally, the acceleration processing circuit 311 updates the mapping table L2P_tab in the second buffer 314 based on the mapping information L2P_temp to be updated. It can be understood that the processor 312 can improve the working efficiency of the memory controller 310 by updating the mapping table L2P_tab through the first buffer 313 and the acceleration processing circuit 311.

[0102] The processor 312 can also actively update the valid data table VTC_tab in the first buffer 313 by executing corresponding software while (or after) caching the mapping information L2P_temp to be updated to the first buffer 313. However, the processor 312 needs to occupy more hardware resources in the process of updating the mapping information L2P_temp to be updated in a continuous and large range to the mapping table L2P_tab. At this time, a more complex software design is required to balance the hardware resources used by the processor 312 to update the mapping table L2P_tab and the hardware resources used to update the valid data table VTC_tab. And the processor 312 participates in the update of the mapping table L2P_tab and the valid data table VTC_tab throughout the process, resulting in low working efficiency of the memory controller 310. In addition, since the processor 312 updates the valid data table VTC_tab by executing software, it is easy to cause errors in the update of the valid data table due to software errors, thereby affecting the stability of the memory controller 310.

[0103] like Figure 5 As shown, the present disclosure provides a memory controller 410, the memory controller 410 includes: a first buffer 413, the first buffer 413 is configured to cache a valid data table VTC_tab and mapping information to be updated L2P_temp; wherein the valid data table VTC_tab is used to record multiple valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the mapping information to be updated L2P_temp includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address; a second buffer 414, the second buffer 414 is configured to cache a mapping table L2P_tab; wherein the mapping table L2P_tab is used to record multiple mapping information; an acceleration processing circuit 411, coupled to the first buffer 413 and the second buffer 414 respectively, the acceleration processing circuit 411 is configured to: update the mapping table L2P_tab based on the mapping information to be updated L2P_temp; update the valid data table VTC_tab based on the mapping information to be updated L2P_temp.

[0104] In the embodiment of the present disclosure, the first buffer 413 may be configured to cache the valid data table VTC_tab and the mapping information to be updated L2P_temp, and the first buffer 413 includes but is not limited to a tightly coupled memory, etc. The second buffer 414 may be configured to cache the mapping table L2P_tab, and the second buffer 414 includes but is not limited to a double rate synchronous dynamic random access memory.

[0105] refer to Figure 4, the mapping table L2P_tab may include multiple entries, each entry records a mapping information of a logical address to a physical address, and a storage block number corresponding to the physical address. The valid data table VTC_tab may include multiple entries, each entry records a storage block number and a valid conversion unit count corresponding to it, and each valid conversion unit count indicates the number of conversion units storing valid data in a corresponding storage block. It should be noted that a storage block may include multiple conversion units, each of which corresponds to a physical address. The capacity size of the conversion unit and the physical position in the memory device are not overly limited here. Exemplarily, the conversion unit may be a physical unit smaller than a storage page (the conversion unit may also be a storage page). Among them, the conversion unit with valid data recorded is called a valid conversion unit, and the conversion unit with invalid data recorded is called an invalid conversion unit. The invalid data in the invalid conversion unit can be cleared when the memory controller 410 performs a garbage collection operation. In some embodiments, the memory controller 410 can also set one or more specific conversion units in the storage block as invalid conversion units according to actual work requirements.

[0106] The valid conversion unit count can reflect the number of valid conversion units in the storage block. Therefore, the occupied storage space of the memory device and the size of the remaining storage space can be further inferred according to the valid data table VTC_tab. The valid data table VTC_tab can also be used to indicate which storage blocks need to be garbage collected.

[0107] The acceleration processing circuit 411 is coupled to the first buffer 413 and the second buffer 414 respectively. The acceleration processing circuit 411 can be configured to update the mapping table L2P_tab in the second buffer 414 based on the mapping information L2P_temp to be updated, and update the valid data table VTC_tab in the first buffer 413 based on the mapping information L2P_temp to be updated. Here, the acceleration processing circuit 411 includes but is not limited to a list access auxiliary circuit, and the list access auxiliary circuit has the function of quickly accessing and quickly updating various lists in the buffer and memory. In other words, the acceleration processing circuit 411 can update the valid data table VTC_tab according to the mapping information L2P_temp to be updated, so the memory controller 410 does not need to update the valid data table VTC_tab in the first buffer 413 through the processor, nor does it need to execute any software or firmware program. Exemplarily, the acceleration processing circuit 411 may include an arbiter circuit, a comparator circuit, a register, etc., so as to perform self-increment and self-decrement on the valid conversion unit count corresponding to each storage block in the valid data table VTC_tab according to one or more L2P mapping information in the mapping information L2P_temp to be updated.

[0108] In this way, on the one hand, updating the valid data table VTC_tab by accelerating the processing circuit 411 can reduce the processor's resource usage and improve the working efficiency and performance of the memory controller 410; on the other hand, there is no need for the processor to update the valid data table VTC_tab by executing software, thereby reducing the impact of software errors on the stability of the memory controller 410 and simplifying the software design.

[0109] In some embodiments, Figure 6 As shown, the acceleration processing circuit 411 includes a register 415; the register 415 is configured to store an invalid physical address Invalid_Fla; the acceleration processing circuit 411 is specifically configured to: update the valid data table VTC_tab based on the mapping information to be updated L2P_temp and the invalid physical address Invalid_Fla.

[0110] In some embodiments, the accelerated processing circuit 411 includes a list access auxiliary circuit, and the register 415 includes a zero register.

[0111] In the disclosed embodiment, the acceleration processing circuit 411 may include a register 415, and the register 415 may store an invalid physical address Invalid_Fla. Here, the invalid physical address Invalid_Fla may be determined by the flash translation layer and / or the processor. Exemplarily, the invalid physical address Invalid_Fla may correspond to a specific conversion unit in the storage block, such as a conversion unit that is not used to store data, or a conversion unit with abnormal function.

[0112] In this way, the acceleration processing circuit 411 can match one or more physical addresses in the mapping information to be updated L2P_temp with the invalid physical address Invalid_Fla in the register 415, so as to realize the self-increment and self-decrement of the valid conversion unit count of the corresponding storage block in the valid data table VTC_tab. It is worth noting that the register 415 may include a combination of one register or multiple registers, and one or more invalid physical addresses Invalid_Fla may be stored in the register 415. In the case where the register 415 stores multiple invalid physical addresses Invalid_Fla, the acceleration processing circuit 411 can match the physical addresses in the mapping information to be updated L2P_temp with all the invalid physical addresses Invalid_Fla in the register 415 one by one, and perform self-increment and self-decrement on the valid conversion unit count of the corresponding storage block.

[0113] In some embodiments, the acceleration processing circuit 411 is specifically configured to: in response to the physical address in the mapping information to be updated L2P_temp being the same as the invalid physical address Invalid_Fla, reduce the valid conversion unit count of the corresponding storage block; or, in response to the physical address in the mapping information to be updated L2P_temp being different from the invalid physical address Invalid_Fla, increase the valid conversion unit count of the corresponding storage block.

[0114] In the disclosed embodiment, the acceleration processing circuit 411 can match the physical address in the mapping information to be updated L2P_temp with the invalid physical address Invalid_Fla in the register 415 through an arbiter circuit, a comparator circuit, etc. In the case where a physical address in the mapping information to be updated L2P_temp is the same as the invalid physical address Invalid_Fla, it means that the data written by the conversion unit corresponding to the physical address is invalid data, that is, the conversion unit is an invalid conversion unit, and the acceleration processing circuit 411 can determine the storage block number corresponding to the physical address, thereby reducing the valid conversion unit count corresponding to the storage block in the valid data table VTC_tab. In the case where a physical address in the mapping information to be updated L2P_temp is different from the invalid physical address Invalid_Fla, it means that the data written by the conversion unit corresponding to the physical address is valid data, that is, the conversion unit is a valid conversion unit, and the acceleration processing circuit 411 can determine the storage block number corresponding to the physical address, thereby increasing the valid conversion unit count corresponding to the storage block in the valid data table VTC_tab.

[0115] In some embodiments, the accelerated processing circuit 411 is further configured to: determine an upper limit value and a lower limit value of the valid conversion unit count; in response to the valid conversion unit count being equal to the upper limit value, stop increasing the valid conversion unit count; and / or, in response to the valid conversion unit count being equal to the lower limit value, stop decreasing the valid conversion unit count.

[0116] In the disclosed embodiment, the accelerated processing circuit 411 can also determine the upper and lower limits of the valid conversion unit counts corresponding to each storage block in the memory device, thereby preventing errors caused by overflow of the valid conversion unit counts recorded in the valid data table VTC_tab during the self-increment and self-decrement processes.

[0117] It is understandable that if the processor 412 is used to update the valid data table VTC_tab through software, the processor 412 is not restricted in updating the valid data table VTC_tab, which may easily lead to errors in the valid conversion unit count due to software errors, such as the valid conversion unit count being less than zero, thereby affecting the stability of the memory controller 410.

[0118] Specifically, the acceleration processing circuit 411 can stop increasing the effective conversion unit count in response to the effective conversion unit count being equal to the upper limit value, that is, the effective conversion unit count will not be greater than the upper limit value; the acceleration processing circuit 411 can also stop decreasing the effective conversion unit count in response to the effective conversion unit count being equal to the lower limit value, that is, the effective conversion unit count will not be less than the lower limit value. In this way, the self-increment and self-decrement operations of the effective conversion unit count by the acceleration processing circuit 411 will not generate overflow errors, thus realizing overflow protection at the hardware level and improving the stability of the memory controller 410.

[0119] In some embodiments, when the valid conversion unit count is equal to the upper limit value, and a physical address in the mapping information to be updated L2P_temp is different from the invalid physical address Invalid_Fla, the acceleration processing circuit 411 will not continue to increase the valid conversion unit count, but send a first error prompt signal to the processor 412, where the first error prompt signal indicates that the valid conversion unit count may overflow the upper limit value; when the valid conversion unit count is equal to the lower limit value, and a physical address in the mapping information to be updated L2P_temp is the same as the invalid physical address Invalid_Fla, the acceleration processing circuit 411 will not continue to reduce the valid conversion unit count, but send a second error prompt signal to the processor 412, where the second error prompt signal indicates that the valid conversion unit count may overflow the lower limit value. In this way, the processor 412 can diagnose the memory controller 410 and the memory device according to the first error prompt signal and / or the second error prompt signal to eliminate potential errors, thereby improving the self-diagnosis capability of the memory system for errors.

[0120] In some embodiments, the acceleration processing circuit 411 is further configured to: determine the upper limit value according to the number of the conversion units in the storage block.

[0121] In the disclosed embodiment, the acceleration processing circuit 411 may set the total number of conversion units in the storage block to an upper limit value, that is, when all conversion units in the storage block are valid conversion units, the valid conversion unit count corresponding to the storage block reaches the upper limit value.

[0122] In some embodiments, Figure 6As shown, the memory controller 410 further includes: a processor 412 coupled to the first buffer 413 , the processor 412 being configured to generate the mapping information to be updated L2P_temp based on the received logical address, and cache the mapping information to be updated L2P_temp in the first buffer 413 .

[0123] In the disclosed embodiment, the memory controller 410 further includes a processor 412, and the processor 412 is coupled to the first buffer 413. The processor 412 can generate the mapping information to be updated L2P_temp based on the logical address received from the external host. It can be understood that receiving the logical address from the external host here means that the host needs to store the data in the memory device, so the processor 412 needs to generate the mapping information of the logical address corresponding to the new data to the physical address, that is, the mapping information to be updated L2P_temp. Exemplarily, the processor 412 can generate the mapping information to be updated L2P_temp based on the received logical address through the flash conversion layer.

[0124] In addition, the processor 412 can control the overall operation of the memory controller 410 to perform operations such as reading, writing and erasing on the memory device. Exemplarily, the processor 412 can be configured to run various firmware or software in the memory controller 410. The processor 412 can include a central processing unit, a microprocessor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The processor 412 can also include a general-purpose processor or any conventional processor.

[0125] In some embodiments, the processor 412 is further configured to: send an update command to the acceleration processing circuit 411; the acceleration processing circuit 411 is specifically configured to: in response to the update command, obtain the mapping information to be updated L2P_temp from the first cache 413; and automatically update the valid data table VTC_tab based on the mapping information to be updated L2P_temp.

[0126] In the disclosed embodiment, the processor 412 can access the first buffer 413 at a faster speed to cache the mapping information L2P_temp to be updated in the first buffer 413. Then, the processor 412 can send an update command to the acceleration processing circuit 411, and the acceleration processing circuit 411 obtains the mapping information L2P_temp to be updated from the first buffer 413 in response to the update command. The acceleration processing circuit 411 can automatically update the valid data table VTC_tab in the first buffer 413 based on the mapping information L2P_temp to be updated, wherein the process of automatically updating the valid data table VTC_tab can refer to the above-mentioned embodiment in which the acceleration processing circuit 411 matches the invalid physical address Invalid_Fla to realize self-increment and self-decrement, which will not be repeated here. In this way, updating the valid data table VTC_tab by the acceleration processing circuit 411 can reduce the processor's resource usage and improve the working efficiency and performance of the memory controller 410.

[0127] In some embodiments, the processor 412 includes a storage protection circuit 416; the storage protection circuit 416 is configured to: prohibit the processor 412 from updating the valid data table VTC_tab.

[0128] In the disclosed embodiment, the processor 412 may further include a storage protection circuit 416, where the storage protection circuit 416 includes but is not limited to a memory protection unit (MPU) and other logic circuits. In this way, the storage protection circuit 416 may prohibit the processor 412 from performing a write operation on a specific segment in the first buffer 413, that is, prohibit the processor 412 from updating the valid data table VTC_tab, thereby preventing the processor 412 from erroneously operating the valid data table VTC_tab, so as to improve the stability of the memory controller 410. It is understandable that the processor 412 can only read the valid data table VTC_tab in the first buffer 413, but cannot write to the valid data table VTC_tab.

[0129] In some embodiments, since the access speed of the acceleration processing circuit 411 to the first buffer 413 is much faster than that to the second buffer 414 , the valid data table VTC_tab can be quickly updated while waiting for the second buffer 414 to be accessed to improve the working efficiency of the memory controller 410 .

[0130] In some embodiments, the processor 412 is further configured to: obtain the valid data table VTC_tab from the first buffer 413 in response to a trim command from the host; and determine storage blocks in the memory device that require garbage collection based on the valid data table VTC_tab.

[0131] In the disclosed embodiment, the processor 412 may obtain the valid data table VTC_tab from the first buffer 413 in response to a trim command (TRIM) from the host, and determine a storage block requiring garbage collection according to multiple valid conversion unit counts in the valid data table VTC_tab.

[0132] The valid conversion unit count can reflect the number of valid conversion units in the storage block. Therefore, according to the valid data table VTC_tab, the storage space occupied by the memory device can be obtained and the size of the remaining storage space can be further inferred. The valid data table VTC_tab can also be used to indicate which storage blocks need to be garbage collected. Exemplarily, the larger the valid conversion unit count in the valid data table VTC_tab, the more conversion units storing valid data in the corresponding storage block; the smaller the valid conversion unit count in the valid data table VTC_tab, the fewer conversion units storing valid data in the corresponding storage block, that is, the more conversion units storing invalid data, so the garbage collection operation can be performed on the storage block with a smaller valid conversion unit count. Here, the storage block that needs to be garbage collected can be determined by setting a threshold value. For example, when the valid conversion unit count is less than the threshold value, the corresponding storage block is garbage collected.

[0133] like Figure 7 As shown, the present disclosure provides an operating method of a memory controller, wherein the memory controller includes a first cache, a second cache, and an acceleration processing circuit respectively coupled to the first cache and the second cache; the operating method includes the following steps:

[0134] Step S10, the first buffer caches a valid data table; wherein the valid data table is used to record a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the second buffer caches a mapping table; wherein the mapping table is used to record a plurality of mapping information;

[0135] Step S20: the first buffer caches the mapping information to be updated; wherein the mapping information to be updated includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address;

[0136] Step S30: The acceleration processing circuit updates the mapping table based on the mapping information to be updated, and updates the valid data table based on the mapping information to be updated.

[0137] It should be understood that Figure 7 The steps shown in the operations are not exclusive, and other steps may be performed before, after, or between any steps in the operations shown.

[0138] In some embodiments, the accelerated processing circuit includes a register, which is configured to store an invalid physical address; the accelerated processing circuit updates the valid data table based on the mapping information to be updated, including: the accelerated processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address.

[0139] In some embodiments, the acceleration processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address, including: in response to the physical address in the mapping information to be updated being the same as the invalid physical address, the acceleration processing circuit reduces the valid conversion unit count of the corresponding storage block; or, in response to the physical address in the mapping information to be updated being different from the invalid physical address, the acceleration processing circuit increases the valid conversion unit count of the corresponding storage block.

[0140] In some embodiments, the operating method also includes: the accelerated processing circuit determines the upper limit value and the lower limit value of the valid conversion unit count; the accelerated processing circuit stops increasing the valid conversion unit count in response to the valid conversion unit count being equal to the upper limit value; and / or the accelerated processing circuit stops decreasing the valid conversion unit count in response to the valid conversion unit count being equal to the lower limit value.

[0141] In some embodiments, the accelerated processing circuit determines the upper limit value of the valid conversion unit count, including: the accelerated processing circuit determines the upper limit value according to the number of the conversion units in the storage block.

[0142] In some embodiments, the memory controller also includes a processor; the processor is coupled to the first cache; the operating method also includes: the acceleration processing circuit generates the mapping information to be updated based on the received logical address, and caches the mapping information to be updated in the first cache.

[0143] In some embodiments, the operating method also includes: the processor sends an update command to the acceleration processing circuit; the acceleration processing circuit obtains the mapping information to be updated from the first cache in response to the update command; the acceleration processing circuit updates the valid data table based on the mapping information to be updated, including: the acceleration processing circuit automatically updates the valid data table based on the mapping information to be updated.

[0144] In some embodiments, the processor includes a storage protection circuit; the operating method further includes: the storage protection circuit prohibiting the processor from updating the valid data table.

[0145] In some embodiments, the operating method further includes: the processor obtaining the valid data table from the first buffer in response to a trim command from the host; and the processor determining a storage block in the memory device that requires garbage collection based on the valid data table.

[0146] The present disclosure provides a memory system, comprising: a memory device, the memory device comprising multiple storage blocks; a memory controller as described in any of the above embodiments, the memory controller being configured to control the memory device and update a valid data table; wherein the valid data table is used to record multiple valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block.

[0147] In the disclosed embodiment, by accelerating the processing circuit to update the valid data table, the processor's resource usage can be reduced to improve the working efficiency and performance of the memory system; in addition, the processor does not need to update the valid data table by executing software, thereby reducing the impact of software errors on the stability of the memory system and simplifying software design. In some embodiments, the memory controller can also determine the storage blocks in the memory device that need to be garbage collected based on the valid data table.

[0148] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0149] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory controller, characterized in that: The memory controller comprises: A first buffer, wherein the first buffer is configured to cache a valid data table and mapping information to be updated; wherein the valid data table is used to record a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the mapping information to be updated includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address; A second buffer, wherein the second buffer is configured to cache a mapping table; wherein the mapping table is used to record a plurality of mapping information; An acceleration processing circuit is coupled to the first buffer and the second buffer respectively, and the acceleration processing circuit is configured as follows: Update the mapping table based on the mapping information to be updated; The valid data table is updated based on the mapping information to be updated.

2. The memory controller according to claim 1, wherein: The accelerated processing circuit includes a register; the register is configured to store an invalid physical address; The acceleration processing circuit is specifically configured as follows: The valid data table is updated based on the mapping information to be updated and the invalid physical address.

3. The memory controller according to claim 2, wherein: The acceleration processing circuit is specifically configured as follows: In response to the physical address in the mapping information to be updated being the same as the invalid physical address, reducing the valid conversion unit count of the corresponding storage block; or, In response to the physical address in the to-be-updated mapping information being different from the invalid physical address, the valid conversion unit count of the corresponding storage block is increased.

4. The memory controller according to claim 3, wherein: The acceleration processing circuit is further configured to: Determining an upper limit value and a lower limit value of the effective conversion unit count; In response to the valid conversion unit count being equal to the upper limit value, stopping increasing the valid conversion unit count; and / or, In response to the valid conversion unit count being equal to the lower limit value, decreasing the valid conversion unit count is stopped.

5. The memory controller according to claim 4, characterized in that: The accelerated processing circuit is further configured to: The upper limit value is determined according to the number of the conversion units in the storage block.

6. The memory controller according to claim 2, wherein: The accelerated processing circuit includes a list access assist circuit, and the register includes a zero register.

7. The memory controller according to claim 1, wherein: The memory controller further includes: A processor is coupled to the first buffer, and the processor is configured to generate the mapping information to be updated based on the received logical address, and cache the mapping information to be updated in the first buffer.

8. The memory controller according to claim 7, wherein: The processor is further configured to: send an update command to the acceleration processing circuit; The acceleration processing circuit is specifically configured as follows: In response to the update command, acquiring the mapping information to be updated from the first buffer; The valid data table is automatically updated based on the mapping information to be updated.

9. The memory controller according to claim 7, wherein: The processor includes a storage protection circuit; the storage protection circuit is configured to: The processor is prohibited from updating the valid data table.

10. The memory controller according to claim 7, wherein: The processor is further configured to: Responding to a trim command from a host, acquiring the valid data table from the first buffer; Based on the valid data table, a storage block in the memory device that needs to be garbage collected is determined.

11. A method for operating a memory controller, characterized in that: The memory controller includes a first buffer, a second buffer, and an acceleration processing circuit respectively coupled to the first buffer and the second buffer; the operation method includes: The first buffer caches a valid data table and mapping information to be updated; wherein the valid data table is used to record a plurality of valid conversion unit counts; the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block; the mapping information to be updated includes at least one mapping information from a logical address to a physical address; each of the conversion units corresponds to one physical address; The second buffer caches a mapping table; wherein the mapping table is used to record a plurality of mapping information; The acceleration processing circuit updates the mapping table based on the mapping information to be updated, and updates the valid data table based on the mapping information to be updated.

12. The operating method according to claim 11, characterized in that: The accelerated processing circuit includes a register configured to store an invalid physical address; The acceleration processing circuit updates the valid data table based on the mapping information to be updated, including: The acceleration processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address.

13. The operating method according to claim 12, characterized in that: The acceleration processing circuit updates the valid data table based on the mapping information to be updated and the invalid physical address, including: In response to the physical address in the mapping information to be updated being the same as the invalid physical address, the acceleration processing circuit reduces the valid conversion unit count of the corresponding storage block; or, In response to the physical address in the mapping information to be updated being different from the invalid physical address, the accelerated processing circuit increases the valid conversion unit count of the corresponding storage block.

14. The operating method according to claim 13, characterized in that: The operation method further includes: The accelerated processing circuit determines the upper limit and the lower limit of the effective conversion unit count; In response to the valid conversion unit count being equal to the upper limit value, the acceleration processing circuit stops increasing the valid conversion unit count; and / or, In response to the valid conversion unit count being equal to the lower limit value, the speed-up processing circuit stops decreasing the valid conversion unit count.

15. The operating method according to claim 14, characterized in that: The acceleration processing circuit determines the upper limit value of the valid conversion unit count, including: The acceleration processing circuit determines the upper limit value according to the number of the conversion units in the storage block.

16. The operating method according to claim 11, characterized in that: The memory controller further includes a processor; the processor is coupled to the first buffer; The operation method further includes: The processor generates the mapping information to be updated based on the received logical address, and caches the mapping information to be updated in the first cache.

17. The operating method according to claim 16, characterized in that: The operation method further includes: The processor sends an update command to the acceleration processing circuit; The acceleration processing circuit acquires the mapping information to be updated from the first buffer in response to the update command; The acceleration processing circuit updates the valid data table based on the mapping information to be updated, including: The acceleration processing circuit automatically updates the valid data table based on the mapping information to be updated.

18. The operating method according to claim 16, characterized in that: The processor includes a storage protection circuit; the operating method also includes: The storage protection circuit prohibits the processor from updating the valid data table.

19. The operating method according to claim 16, characterized in that: The operation method also includes: The processor obtains the valid data table from the first buffer in response to a trim command from the host; The processor determines a storage block in a memory device that needs to be garbage collected based on the valid data table.

20. A memory system, characterized in that: include: a memory device, the memory device comprising a plurality of memory blocks; The memory controller according to any one of claims 1 to 10, wherein the memory controller is configured to control the memory device and update a valid data table; wherein the valid data table is used to record a plurality of valid conversion unit counts; and the valid conversion unit count indicates the number of conversion units storing valid data in the corresponding storage block.

Images