High-speed communication method and device for ATE and MCU
By introducing clock and data bus pins in the communication between ATE and MCU, and controlling data stream transmission according to the data direction signal, the problem of slow communication rate in the prior art is solved, and efficient chip testing is achieved.
Patent Information
- Application Number
- CN202411721579.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-18
AI Technical Summary
The existing ATE and MCU communication methods have slow communication rates, resulting in low chip testing efficiency.
By introducing a clock pin and a data bus pin between the ATE and the MCU, and controlling the data streaming on the data bus according to the data direction signals transmitted on the clock pin, each clock transmits 8-bit or 16-bit high-speed communication is achieved.
The communication rate between ATE and MCU is improved to 8 times or 16 times that of the prior art, thereby significantly improving the testing efficiency of MCU chips.
Smart Images
Figure CN119847955A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip performance testing, and in particular to a high-speed communication method and device between ATE and MCU. Background Art
[0002] ATE machine is a device used to perform comprehensive performance tests on MCU chips. During the test, the ATE machine needs to communicate with the MCU for a large amount of data. The existing communication methods between ATE machines and MCUs include SPI, I2C, UART, etc. During communication, each clock can only transmit 1 bit, so the communication rate is slow and the test efficiency is low. Summary of the invention
[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a high-speed communication method between ATE and MCU, which can achieve 8 bits or 16 bits per clock transmission during the test and communication process between ATE and MCU chips, so that the communication rate reaches 8 times or 16 times the communication rate of the prior art, thereby greatly improving the test efficiency of the MCU chip.
[0004] The present invention also provides a high-speed communication device between ATE and MCU, which is applied to the high-speed communication method between ATE and MCU.
[0005] The present invention also provides an electronic device for implementing the above-mentioned high-speed communication method between ATE and MCU.
[0006] The present invention also provides a computer-readable storage medium for implementing the above-mentioned high-speed communication method between ATE and MCU.
[0007] According to a first aspect of the present invention, a high-speed communication method between an ATE and an MCU is provided. The ATE comprises: a first clock pin and a first data bus pin; the MCU comprises: a second clock pin and a second data bus pin; wherein the first clock pin is electrically connected to the second clock pin, and the first data bus pin is electrically connected to the second data bus pin via a data bus; the high-speed communication method between the ATE and the MCU comprises:
[0008] When the ATE sends the first bus data to the MCU, the ATE controls the first clock pin to send a first data direction signal to the second clock pin;
[0009] The ATE controls the first data bus pin to send the first bus data to the second data bus pin through the data bus according to the first data direction signal;
[0010] When the MCU sends the second bus data to the ATE, the ATE controls the first clock pin to send a second data direction signal to the second clock pin;
[0011] The MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal.
[0012] According to some embodiments of the present invention, the first clock pin includes: an ATE_A1 pin; the second clock pin includes: an MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin; when the ATE sends the first bus data to the MCU, the ATE controls the first clock pin to send a first data direction signal to the second clock pin, including:
[0013] When the ATE sends the first bus data to the MCU, the ATE controls the ATE_A1 pin to send a first data direction signal to the MCU_A1 pin.
[0014] According to some embodiments of the present invention, the first clock pin further includes: an ATE_A2 pin; the second clock pin further includes: an MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin; when the MCU sends second bus data to the ATE, the ATE controls the first clock pin to send a second data direction signal to the second clock pin, including:
[0015] When the MCU sends the second bus data to the ATE, the ATE controls the ATE_A2 pin to send a second data direction signal to the MCU_A2 pin.
[0016] According to some embodiments of the present invention, the ATE controls the first data bus pin to send data to the second data bus pin through the data bus according to the first data direction signal, including:
[0017] When the ATE runs to the falling edge of the first data direction signal, the ATE controls the first data bus pin to set the first bus data to the data bus;
[0018] When the MCU detects a rising edge of the first data direction signal, the MCU controls the second data bus pin to collect the first bus data on the data bus.
[0019] According to some embodiments of the present invention, the MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal, including:
[0020] When the MCU detects a falling edge of the second data direction signal, the MCU controls the second data bus pin to set the second bus data to the data bus;
[0021] When the ATE runs to the rising edge of the second data direction signal, the ATE controls the first data bus pin to collect the second bus data on the data bus.
[0022] According to some embodiments of the present invention, the first clock pin includes: an ATE_A1 pin; the second clock pin includes: an MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin;
[0023] The ATE controls the first data bus pin to send data to the second data bus pin through the data bus according to the first data direction signal, including:
[0024] When the ATE runs to the falling edge of the first data direction signal through the ATE_A1 pin, the ATE controls the first data bus pin to set the first bus data to the data bus;
[0025] When the MCU detects a rising edge of the first data direction signal through the MCU_A1 pin, the MCU controls the second data bus pin to collect the first bus data on the data bus.
[0026] According to some embodiments of the present invention, the first clock pin further includes: an ATE_A2 pin; the second clock pin further includes: an MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin;
[0027] The MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal, including:
[0028] When the MCU detects a falling edge of the second data direction signal through the MCU_A2 pin, the MCU controls the second data bus pin to set the second bus data to the data bus;
[0029] When the ATE reaches the rising edge of the second data direction signal through the ATE_A2 pin, the ATE controls the first data bus pin to collect the second bus data on the data bus.
[0030] According to a second aspect of the present invention, a high-speed communication device between an ATE and an MCU includes an ATE and an MCU; the ATE includes: a first clock pin and a first data bus pin; the MCU includes: a second clock pin and a second data bus pin;
[0031] Among them, the first clock pin is electrically connected to the second clock pin, the first data bus pin is electrically connected to the second data bus pin through a data bus, and the high-speed communication device between ATE and MCU is used to implement the steps of the high-speed communication method between ATE and MCU as in any of the above embodiments.
[0032] An electronic device according to an embodiment of a third aspect of the present invention includes:
[0033] one or more processors;
[0034] Memory;
[0035] One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the high-speed communication method between ATE and MCU as described in any one of the above embodiments are implemented.
[0036] According to the computer-readable storage medium of the fourth aspect of the present invention, a computer program is stored thereon, and when the computer program is executed by a processor, the steps of the high-speed communication method between ATE and MCU as described in any one of the above embodiments are implemented.
[0037] The high-speed communication method between ATE and MCU according to the embodiment of the present invention has at least the following beneficial effects: by connecting the clock pin of ATE with the clock pin of MCU, connecting the data bus pin of ATE with the data bus pin of MCU through the data bus, and controlling the data stream transmission on the data bus according to the clock edge of the data direction signal transmitted on the two clock pins, so that in the communication interaction process between ATE and MCU, a certain time is reserved for the establishment of bus data, ensuring that the data sent by either ATE or MCU can be received by the other party under the confirmed timing, so that the method has higher communication reliability; further, because the method takes the data establishment process into consideration, the communication between ATC and MCU can be operated at a higher communication rate, thereby improving the efficiency of chip testing and reducing testing costs.
[0038] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0040] Figure 1 A schematic diagram of a high-speed communication method between ATE and MCU according to an embodiment of the present invention;
[0041] Figure 2 for Figure 1 The signal timing diagram of the first data direction signal, the second data direction signal and the bus data of the high-speed communication method between ATE and MCU is shown;
[0042] Figure 3 FIG. 4 is a schematic diagram of electrical connection between a high-speed communication device of ATE and MCU according to an embodiment of the present invention. DETAILED DESCRIPTION
[0043] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0044] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention (invention).
[0045] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0046] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.
[0047] Reference Figure 1 and Figure 3 The present invention proposes a high-speed communication method between ATE and MCU, wherein the ATE includes: first clock pins ATE_A1 to ATE_A2, and first data bus pins ATE_D0 to ATE_D7; the MCU includes: second clock pins MCU_A1 to MCU_A2, and second data bus pins MCU_D0 to MCU_D7; wherein the first clock pins ATE_A1 to ATE_A2 are electrically connected to the second clock pins MCU_A1 to MCU_A2, and the first data bus pins ATE_D0 to ATE_D7 are electrically connected to the second data bus pins MCU_D0 to MCU_D7 through a data bus; the high-speed communication method between ATE and MCU includes:
[0048] S100: When ATE sends the first bus data D0-D7 to MCU, ATE controls the first clock pins ATE_A1 to ATE_A2 to send the first data direction signal A1 to the second clock pins MCU_A1 to MCU_A2;
[0049] S200: ATE controls the first data bus pins ATE_D0 to ATE_D7 to send the first bus data D0-D7 to the second data bus pins MCU_D0 to MCU_D7 through the data bus according to the first data direction signal A1;
[0050] S300: When the MCU sends the second bus data D0-D7 to the ATE, the ATE controls the first clock pins ATE_A1 to ATE_A2 to send the second data direction signal A2 to the second clock pins MCU_A1 to MCU_A2;
[0051] S400: The MCU controls the second data bus pins MCU_D0 to MCU_D7 to send the second bus data D0-D7 to the first data bus pins ATE_D0 to ATE_D7 through the data bus according to the second data direction signal A2.
[0052] Specifically, in this embodiment, refer to Figure 3, the first clock pins include two: pin ATE_A1 and pin ATE_A2, the second clock pins include two: pin MCU_A1 and pin MCU_A2, wherein pin ATE_A1 is electrically connected to pin MCU_A1, and pin ATE_A2 is electrically connected to pin MCU_A2. The number of first data bus pins of ATE and the second data bus pins of MCU are equal and they are electrically connected one by one. In this embodiment, there are 8 pairs of data bus pins, namely ATE_D0 to ATE_D7 and MCU_D0 to MCU_D7. In other embodiments, 16 pairs of data bus pins can also be set, such as ATE_D0 to ATE_D15 and MCU_D0 to MCU_D15. Specifically, step S100 is as follows: when the first bus data D0-D7 needs to be sent from ATE to MCU, ATE controls the first clock pin ATE_A1 to send the first data direction signal A1 to the second clock pin MCU_A1. The first data direction signal A1 is a data control signal for controlling the transmission of bus data from ATE to MCU. Specifically, step S200 is as follows: when the second bus data D0-D7 needs to be sent from MCU to ATE, ATE controls the first clock pin ATE_A2 to send the first data direction signal A1 to the second clock pin MCU_A2. The second data direction signal A2 is a data control signal for controlling the transmission of bus data from MCU to ATE. During the period when the ATE_A1 pin sends the first data direction signal A1, ATE outputs bus data and MCU collects bus data; during the period when the ATE_A2 pin sends the second data direction signal A2, MCU outputs bus data and ATE collects bus data. Figure 2 The timing shown in Figure 2In the figure, letters a to p represent moments, waveform A1 is the timing diagram of the first data direction signal A1, numbers 1 to 8 represent 8 bytes transmitted on the bus, wherein each byte from byte 1 to byte 8 has 8 bits; waveform A2 is the timing diagram of the second data direction signal A2; D0-D7 represent the bus data stream transmitted on the bus, namely the first bus data and the second bus data, more specifically, byte 1 to byte 4 are taken as a frame of data, recorded as the first bus data stream; byte 5 to byte 8 are taken as a frame of data, recorded as the second bus data stream; each frame of bus data includes: a command byte, an address byte and a data byte, wherein byte 1 is the command byte of the first bus data, byte 2 is the address byte of the first bus data, byte 3 and byte 4 are the data bytes of the first bus data, wherein byte 5 is the command byte of the second bus data, byte 6 is the address byte of the second bus data, byte 7 and byte 8 are the data bytes of the second bus data. When ATE runs to the falling edge of the first data direction signal A1, that is, time a, time c, time e and time g, ATE sets the first bus data (byte 1 to byte 4) to the data bus; when MCU captures the rising edge of the first data direction signal A1, that is, time b, time d, time f and time h, MCU collects the first bus data (byte 1 to byte 4) on the data bus. When MCU captures the falling edge of the second data direction signal A2, that is, time i, time k, time m and time o, MCU sets the second bus data (byte 5 to byte 8) to the data bus; when ATE runs to the rising edge of the second data direction signal A2, that is, time j, time l, time n and time p, ATE collects the second bus data (byte 5 to byte 8) on the data bus. Thus, the data interaction between ATE and MCU during the test process is completed, and the data flow transmission on the data bus is controlled according to the clock edge of the data direction signal transmitted on the two clock pins, so that in the communication interaction process between ATE and MCU, a certain time is reserved for the establishment of bus data, ensuring that the data sent by either ATE or MCU can be received by the other party under the confirmed timing, so this method has high communication reliability; further, since this method takes the data establishment process into consideration, the communication between ATC and MCU can be operated at a higher communication rate, thereby improving the efficiency of chip testing and reducing testing costs.
[0053] Reference Figure 3, further, in some embodiments of the present invention, the first clock pin includes: ATE_A1 pin; the second clock pin includes: MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin; when the ATE sends the first bus data D0-D7 to the MCU, the ATE controls the first clock pins ATE_A1 to ATE_A2 to send the first data direction signal A1 to the second clock pins MCU_A1 to MCU_A2, including:
[0054] When ATE sends the first bus data D0 - D7 to MCU, ATE controls the ATE_A1 pin to send the first data direction signal A1 to the MCU_A1 pin.
[0055] Reference Figure 3 , further, in some embodiments of the present invention, the first clock pin further includes: an ATE_A2 pin; the second clock pin further includes: an MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin; when the MCU sends the second bus data D0-D7 to the ATE, the ATE controls the first clock pins ATE_A1 to ATE_A2 to send the second data direction signal A2 to the second clock pins MCU_A1 to MCU_A2, including:
[0056] When the MCU sends the second bus data D0-D7 to the ATE, the ATE controls the ATE_A2 pin to send the second data direction signal A2 to the MCU_A2 pin.
[0057] Reference Figure 1 Further, in some embodiments of the present invention, ATE controls the first data bus pins ATE_D0 to ATE_D7 to send data to the second data bus pins MCU_D0 to MCU_D7 through the data bus according to the first data direction signal A1, including:
[0058] When ATE runs to the falling edge of the first data direction signal A1, ATE controls the first data bus pins ATE_D0 to ATE_D7 to set the first bus data D0-D7 to the data bus;
[0059] When the MCU detects the rising edge of the first data direction signal A1, the MCU controls the second data bus pins MCU_D0 to MCU_D7 to collect the first bus data D0-D7 on the data bus.
[0060] Specifically, in this embodiment, when ATE runs to the falling edge of the first data direction signal A1, that is, time a, time c, time e and time g, ATE sets the first bus data (byte 1 to byte 4) to the data bus; when MCU captures the rising edge of the first data direction signal A1, that is, time b, time d, time f and time h, MCU collects the first bus data (byte 1 to byte 4) on the data bus.
[0061] Reference Figure 1 Further, in some embodiments of the present invention, the MCU controls the second data bus pins MCU_D0 to MCU_D7 to send the second bus data D0-D7 to the first data bus pins ATE_D0 to ATE_D7 through the data bus according to the second data direction signal A2, including:
[0062] When the MCU detects the falling edge of the second data direction signal A2, the MCU controls the second data bus pins MCU_D0 to MCU_D7 to set the second bus data D0-D7 to the data bus;
[0063] When ATE reaches the rising edge of the second data direction signal A2, ATE controls the first data bus pins ATE_D0 to ATE_D7 to collect the second bus data D0-D7 on the data bus.
[0064] Specifically, in this embodiment, when the MCU captures the falling edge of the second data direction signal A2, that is, at time i, time k, time m and time o, the MCU sets the second bus data (byte 5 to byte 8) to the data bus; when the ATE captures the rising edge of the second data direction signal A2, that is, at time j, time l, time n and time p, the MCU collects the second bus data (byte 5 to byte 8) on the data bus.
[0065] Reference Figure 1 and Figure 3 , further, in some embodiments of the present invention, the first clock pins ATE_A1 to ATE_A2 include: ATE_A1 pin; the second clock pins MCU_A1 to MCU_A2 include: MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin;
[0066] The ATE controls the first data bus pins ATE_D0 to ATE_D7 to send data to the second data bus pins MCU_D0 to MCU_D7 through the data bus according to the first data direction signal A1, including:
[0067] When ATE runs to the falling edge of the first data direction signal A1 through the ATE_A1 pin, ATE controls the first data bus pins ATE_D0 to ATE_D7 to set the first bus data D0-D7 to the data bus;
[0068] When the MCU detects a rising edge of the first data direction signal A1 through the MCU_A1 pin, the MCU controls the second data bus pins MCU_D0 to MCU_D7 to collect the first bus data D0 - D7 on the data bus.
[0069] Reference Figure 1 and Figure 3 , further, in some embodiments of the present invention, the first clock pins ATE_A1 to ATE_A2 further include: ATE_A2 pin; the second clock pins MCU_A1 to MCU_A2 further include: MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin;
[0070] The MCU controls the second data bus pins MCU_D0 to MCU_D7 to send the second bus data D0-D7 to the first data bus pins ATE_D0 to ATE_D7 through the data bus according to the second data direction signal A2, including:
[0071] When the MCU detects the falling edge of the second data direction signal A2 through the MCU_A2 pin, the MCU controls the second data bus pins MCU_D0 to MCU_D7 to set the second bus data D0-D7 to the data bus;
[0072] When ATE reaches the rising edge of the second data direction signal A2 through the ATE_A2 pin, ATE controls the first data bus pins ATE_D0 to ATE_D7 to collect the second bus data D0 - D7 on the data bus.
[0073] Reference Figure 3 According to the second aspect of the present invention, a high-speed communication device between ATE and MCU includes ATE and MCU; ATE includes: first clock pins ATE_A1 to ATE_A2, first data bus pins ATE_D0 to ATE_D7; MCU includes: second clock pins MCU_A1 to MCU_A2, second data bus pins MCU_D0 to MCU_D7;
[0074] Among them, the first clock pins ATE_A1 to ATE_A2 are electrically connected to the second clock pins MCU_A1 to MCU_A2, the first data bus pins ATE_D0 to ATE_D7 are electrically connected to the second data bus pins MCU_D0 to MCU_D7 through the data bus, and the high-speed communication device between ATE and MCU is used to implement the steps of the high-speed communication method between ATE and MCU as in any of the above embodiments.
[0075] The present invention also provides an electronic device, comprising:
[0076] one or more processors;
[0077] Memory;
[0078] One or more programs, wherein the one or more programs are stored in a memory and configured to be executed by one or more processors, and when the programs are executed by the processors, the steps of the high-speed communication method between ATE and MCU as claimed in any one of claims 1 to 7 are implemented.
[0079] The present invention also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for testing the internal parasitic parameters of a chip as described above are implemented.
[0080] It will be appreciated by those skilled in the art that all or part of the steps for implementing the above-mentioned embodiments can be accomplished by hardware, or by a program to instruct the relevant hardware to accomplish, and the program can be stored in a computer-readable storage medium. In the context of the present invention, the computer-readable medium can be considered to be tangible and non-temporary. Non-limiting examples of non-temporary tangible computer-readable media include non-volatile memory circuits (e.g., flash memory circuits, erasable programmable read-only memory circuits, or mask read-only memory circuits), volatile memory circuits (e.g., static random access memory circuits or dynamic random access memory circuits), magnetic storage media (e.g., analog or digital tapes or hard disk drives), and optical storage media (e.g., CDs, DVDs, or Blu-ray discs), etc. The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
[0081] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present invention. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.
Claims
1. A high-speed communication method between ATE and MCU, characterized in that: The ATE includes: a first clock pin and a first data bus pin; the MCU includes: a second clock pin and a second data bus pin; wherein the first clock pin is electrically connected to the second clock pin, and the first data bus pin is electrically connected to the second data bus pin via a data bus; the high-speed communication method between the ATE and the MCU includes: When the ATE sends the first bus data to the MCU, the ATE controls the first clock pin to send a first data direction signal to the second clock pin; The ATE controls the first data bus pin to send the first bus data to the second data bus pin through the data bus according to the first data direction signal; When the MCU sends the second bus data to the ATE, the ATE controls the first clock pin to send a second data direction signal to the second clock pin; The MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal.
2. The high-speed communication method between ATE and MCU according to claim 1, characterized in that: The first clock pin includes: an ATE_A1 pin; the second clock pin includes: an MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin; when the ATE sends the first bus data to the MCU, the ATE controls the first clock pin to send a first data direction signal to the second clock pin, including: When the ATE sends the first bus data to the MCU, the ATE controls the ATE_A1 pin to send a first data direction signal to the MCU_A1 pin.
3. The high-speed communication method between ATE and MCU according to claim 1, characterized in that: The first clock pin further includes: an ATE_A2 pin; the second clock pin further includes: an MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin; when the MCU sends the second bus data to the ATE, the ATE controls the first clock pin to send a second data direction signal to the second clock pin, including: When the MCU sends the second bus data to the ATE, the ATE controls the ATE_A2 pin to send a second data direction signal to the MCU_A2 pin.
4. The high-speed communication method between ATE and MCU according to claim 1, characterized in that: The ATE controls the first data bus pin to send data to the second data bus pin through the data bus according to the first data direction signal, including: When the ATE runs to the falling edge of the first data direction signal, the ATE controls the first data bus pin to set the first bus data to the data bus; When the MCU detects a rising edge of the first data direction signal, the MCU controls the second data bus pin to collect the first bus data on the data bus.
5. The high-speed communication method between ATE and MCU according to claim 1, characterized in that: The MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal, including: When the MCU detects a falling edge of the second data direction signal, the MCU controls the second data bus pin to set the second bus data to the data bus; When the ATE runs to the rising edge of the second data direction signal, the ATE controls the first data bus pin to collect the second bus data on the data bus.
6. The high-speed communication method between ATE and MCU according to claim 4, characterized in that: The first clock pin includes: an ATE_A1 pin; the second clock pin includes: an MCU_A1 pin; wherein the ATE_A1 pin is electrically connected to the MCU_A1 pin; The ATE controls the first data bus pin to send data to the second data bus pin through the data bus according to the first data direction signal, including: When the ATE runs to the falling edge of the first data direction signal through the ATE_A1 pin, the ATE controls the first data bus pin to set the first bus data to the data bus; When the MCU detects a rising edge of the first data direction signal through the MCU_A1 pin, the MCU controls the second data bus pin to collect the first bus data on the data bus.
7. The high-speed communication method between ATE and MCU according to claim 5, characterized in that: The first clock pin further includes: an ATE_A2 pin; the second clock pin further includes: an MCU_A2 pin; wherein the ATE_A2 pin is electrically connected to the MCU_A2 pin; The MCU controls the second data bus pin to send the second bus data to the first data bus pin through the data bus according to the second data direction signal, including: When the MCU detects a falling edge of the second data direction signal through the MCU_A2 pin, the MCU controls the second data bus pin to set the second bus data to the data bus; When the ATE reaches the rising edge of the second data direction signal through the ATE_A2 pin, the ATE controls the first data bus pin to collect the second bus data on the data bus.
8. A high-speed communication device between ATE and MCU, characterized in that: It includes ATE and MCU; the ATE includes: a first clock pin and a first data bus pin; the MCU includes: a second clock pin and a second data bus pin; Among them, the first clock pin is electrically connected to the second clock pin, the first data bus pin is electrically connected to the second data bus pin through a data bus, and the high-speed communication device between ATE and MCU is used to implement the steps of the high-speed communication method between ATE and MCU as described in any one of claims 1-7.
9. An electronic device, characterized in that: include: one or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the high-speed communication method between ATE and MCU as described in any one of claims 1-7 are implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the high-speed communication method between ATE and MCU as described in any one of claims 1 to 7 are implemented.