Method, system and device for establishing connection path between master device and slave device

Abstract

The invention discloses a method, a system and a device for establishing a connection path between master equipment and slave equipment. The method comprises the following steps: receiving a connection request; in response to the connection request, determining a target slave device according to the connection demand parameter; according to a slave device selection module, a target data bus and a target clock bus corresponding to a target slave device are determined, the slave device selection module comprises a plurality of slave devices arranged according to a predetermined form, and the slave devices meeting a first preset condition correspond to the same data bus; the slave devices meeting the second preset condition correspond to the same clock bus; and establishing a connection path between the master device and the target slave device according to the target data bus and the target clock bus. According to the method and the device, the technical problems that in the related technology, when the master device is connected with any one of the multiple slave devices, the multiple slave devices are correspondingly provided with different data buses and clock buses, the number of lines of the whole system is large, and the connection speed is low are solved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a method, system and device for establishing a connection path between a master device and a slave device. Background Art

[0002] In the related art, the I2C one-to-many interface expansion circuit is usually a gate type, using a large number of analog switches and logic devices to expand from one channel to multiple channels. At the same time, a group of channels are selected to communicate with the slave device Slaver and the master device Master. Each channel of this solution also has the problems of address conflict and excessive bus load. The overhead of the gate and the protection time gap during the gate switching will further increase the load of the I2C bus. The use of multiple interface expansion chips and a large number of analog switches in the same project will also bring great pressure on material costs and PCB layout routing. In order to ensure signal quality, the existing solution uses unidirectional gated logic devices to transmit the SCL signal unidirectionally, which cannot meet the Slave side SCL signal's demand for clock extension.

[0003] There are other programmable logic implementation solutions, but compared to this solution, other solutions require the design of the IIC Master core and related conversion logic inside the programmable logic, and require address resolution and data conversion for the IIC slave device that the CPU wants to access, which makes program design complicated and requires the use of large-capacity programmable logic chips. The cost is too high, the code workload is large, and the access speed is slow and the latency is high.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present invention provide a method, system and apparatus for establishing a connection path between a master device and a slave device, so as to at least solve the technical problem in the related art that when a master device is connected to any one of a plurality of slave devices, the plurality of slave devices are provided with different data buses and clock buses, the entire system has many lines and a slow connection speed.

[0006] According to one aspect of an embodiment of the present invention, a method for establishing a connection path between a master device and a slave device is provided, wherein a connection request is received, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; in response to the connection request, a target slave device is determined based on the connection requirement parameter; based on a slave device selection module, a target data bus and a target clock bus corresponding to the target slave device are determined, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; based on the target data bus and the target clock bus, a connection path is established between the master device and the target slave device.

[0007] Optionally, in response to the connection request, determining the target slave device according to the connection requirement parameters includes: in response to the connection request, obtaining slave device status information corresponding to the slave device selection module; determining the target slave device according to the slave device status information and the connection requirement parameters.

[0008] Optionally, after establishing a connection path between the master device and the target slave device based on the target data bus and the target clock bus, it also includes: detecting a signal state of the target device, wherein the target device includes: a master device, a target slave device; when the signal state of the target device changes, determining a changed device whose signal state has changed, and an update signal corresponding to the changed device; transmitting the update signal to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update signal, wherein the device to be changed is a device whose signal state has not changed.

[0009] Optionally, when the signal state of the target device changes, determining the changed device whose signal state has changed, and an update signal corresponding to the changed device, includes: determining a predetermined delay time when the signal state of the target device changes; after the predetermined delay time, determining a secondary result of whether the signal state has changed; when the secondary result is a signal state change, determining the changed device whose signal state has changed, and an update signal corresponding to the changed device.

[0010] Optionally, based on the slave device selection module, determining the target data bus and the target clock bus corresponding to the target slave device includes: when the slave device selection module includes multiple slave device selection modules, determining the target module corresponding to the target slave device from the multiple slave device selection modules; in the target module, determining the target data bus and the target clock bus corresponding to the target slave device.

[0011] Optionally, in response to the connection request, determining a target slave device according to the connection requirement parameters includes: determining a target interface from a plurality of candidate interfaces according to the connection requirement parameters; and determining the target slave device through the target interface.

[0012] According to one aspect of an embodiment of the present invention, there is provided a system for establishing a connection path between a master device and a slave device, comprising a master device, a plurality of slave devices, and a target chip, wherein a slave device selection module is provided in the target chip, the target chip receives a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; in response to the connection request, a target slave device is determined based on the connection requirement parameter, wherein the slave device selection module includes the target slave device; based on the slave device selection module, a target data bus and a target clock bus corresponding to the target slave device are determined, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, slave devices that meet a first preset condition have the same data bus corresponding to them, and slave devices that meet a second preset condition have the same clock bus corresponding to them; based on the target data bus and the target clock bus, a connection path between the master device and the target slave device is established.

[0013] Optionally, a transparent transmission logic module is also provided in the target chip, wherein the transparent transmission logic module is used to detect the signal state of the target device after establishing a connection path between the master device and the target slave device, wherein the target device includes: a master device, a target slave device; when the signal state of the target device changes, determine the changed device whose signal state has changed, and an update signal corresponding to the changed device; transmit the update signal to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update signal, wherein the device to be changed is a device whose signal state has not changed.

[0014] Optionally, an auxiliary selection interface module is further provided in the target chip, wherein the auxiliary selection interface module is used to determine a target interface from a plurality of candidate interfaces according to the connection requirement parameters; and establish a connection between the master device and the slave device selection module through the target interface.

[0015] According to one aspect of an embodiment of the present invention, there is provided a device for establishing a connection path between a master device and a slave device, comprising a receiving module for receiving a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; a first determining module for determining a target slave device in response to the connection request and according to the connection requirement parameter; a second determining module for determining a target data bus and a target clock bus corresponding to the target slave device according to a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; and an establishing module for establishing a connection path between the master device and the target slave device according to the target data bus and the target clock bus.

[0016] According to one aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the above-mentioned methods for establishing a connection path between a master device and a slave device.

[0017] According to one aspect of an embodiment of the present invention, there is provided an electronic device, comprising: a memory storing an executable program; and a processor for running the program, wherein when the program is run, the method for establishing a connection path between a master device and a slave device described in any one of the above is executed.

[0018] According to one aspect of an embodiment of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned methods for establishing a connection path between a master device and a slave device are implemented.

[0019] In an embodiment of the present invention, a connection request is received, wherein the connection request is used to establish a connection path between a master device and a slave device, and the connection request carries a connection requirement parameter; in response to the connection request, a target slave device is determined according to the connection requirement parameter; according to a slave device selection module, a target data bus and a target clock bus corresponding to the target slave device are determined, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and the slave devices that meet the first preset condition correspond to the same data bus, and the slave devices that meet the second preset condition correspond to the same clock bus; according to the target data bus and the target clock bus, a connection path between the master device and the target slave device is established. In an embodiment of the present invention, by setting a slave device selection module, the slave devices that meet the first preset condition correspond to the same data bus, and the slave devices that meet the second preset condition correspond to the same clock bus, thereby reducing the number of system lines, reducing the connection load, and achieving the effect of improving the connection speed, thereby solving the technical problem that, when the master device is connected to any one of the plurality of slave devices, the plurality of slave devices are correspondingly provided with different data buses and clock buses, the entire system has many lines, and there is a slow connection speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 is a flow chart of a method for establishing a connection path between a master device and a slave device according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a one-to-many device switching system provided by an optional implementation manner of the present invention;

[0023] Figure 3 is a schematic diagram of slave device selection logic provided by an optional implementation manner of the present invention;

[0024] Figure 4 is a schematic diagram of a state machine provided by an optional embodiment of the present invention;

[0025] Figure 5 4 is a structural block diagram of an apparatus for establishing a connection path between a master device and a slave device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0029] I2C (Inter-Integrated Circuit): is a two-wire serial bus used to connect microcontrollers and various peripheral devices such as EEPROM, A / D converter, DAC, I / O devices, etc. In Chinese, I2C is often referred to as "Inter-Integrated Circuit Bus" or "Inter-Integrated Circuit Bus".

[0030] PCB: Printed Circuit Board, sometimes also called "printed circuit board". It is the main platform for mounting and connecting electronic components and circuits in electronic devices. PCB forms circuit paths by printing copper foil traces on an insulating substrate, connecting various electronic components (such as resistors, capacitors, transistors, integrated circuits, etc.) according to a predetermined circuit design, thereby realizing the functions of electronic devices. Printed circuit boards not only provide mechanical support for electronic components, but also make electrical connections between components simple and reliable through preset traces and pads. They are an indispensable component of modern electronic devices.

[0031] SCL: In the I2C bus protocol, it is the abbreviation of "Serial Clock Line". It is one of the two main signal lines in the I2C bus and is used to synchronize data transmission. In I2C communication, the clock pulse on the SCL line is generated by the master device (Master) to control the speed of data transmission and reception, ensuring that data can be transmitted correctly between the master and slave devices. The rising and falling edges of the SCL signal are used to control the data sampling and state transition on the SDA (serial data line), thereby realizing serial communication.

[0032] SDA: In the I2C bus protocol, it is the abbreviation of "Serial Data Line". It is the signal line responsible for data transmission in the I2C bus. The sending and receiving of data are carried out through the SDA line under the synchronization of SCL (serial clock line). The data on the SDA line remains stable during the high level of the clock and can be changed during the low level of the clock. The master device (Master) and the slave device (Slave) can perform bidirectional data exchange through the SDA line to realize the reading and writing operations of information.

[0033] ACK response signal: The ACK response signal (confirmation response signal) indicates that the receiver has successfully received the data from the sender and gives a confirmation response, where ACK is the abbreviation of "Acknowledgement".

[0034] According to an embodiment of the present invention, a method embodiment for establishing a connection path between a master device and a slave device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0035] Figure 1 is a flow chart of a method for establishing a connection path between a master device and a slave device according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0036] The executor of the embodiment of the present invention can be a programmable logic chip (complex programmable logic device CPLD / field programmable gate array FPGA) chip or a processor microcontroller unit MCU, or a terminal or server that can process programmable logic, so as to set a slave device selection module, so that the slave devices that meet the first preset condition have the same data bus, and the slave devices that meet the second preset condition have the same clock bus, thereby reducing the number of system lines and reducing the connection load, thereby achieving the effect of improving the connection speed, and further solving the problem in the related art that when the master device is connected to any one of the multiple slave devices, the multiple slave devices are correspondingly set with different data buses and clock buses, the entire system has more lines, and there is a technical problem of slow connection speed.

[0037] It should be noted that the above-mentioned terminal can be of various types, for example, it can be a mobile terminal with certain computing capabilities, or it can be a fixed computer device with recognition capabilities, etc. The above-mentioned server can also be of various types, for example, it can be a local server or a virtual cloud server. The server can be a single computer device or a computer cluster in which multiple computer devices are integrated according to computing capabilities.

[0038] The steps involved in the embodiment of the present invention are introduced below:

[0039] Step S102, receiving a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter;

[0040] In step S102 involved in the embodiment of the present invention, a connection request for establishing a connection path between a master device and a slave device is received.

[0041] Among them, a connection request is involved, where the connection request is a command or signal sent by the master device to connect with a slave device that can meet its needs, and the connection request includes request information for establishing a specific connection. The connection request can be sent by the master device.

[0042] Among them, connection requirement parameters are involved. These parameters are carried in the connection request and are used to specify specific information of the slave device with which the master device wants to establish a connection. This can include the address, type, operation to be performed (read or write), data transmission rate, etc. of the slave device, so as to correctly parse and select the slave device that can meet the requirements and establish the corresponding connection.

[0043] This involves a connection path between the master device and the slave device, that is, a data transmission channel is created to enable the master device to communicate with the target slave device.

[0044] In this step, when the master device communicates with one of the multiple slave devices, it sends a connection request, which contains specific parameters of the target slave device, such as the address and the required operation type, so that a slave device that meets the requirements can be selected.

[0045] Step S104, in response to the connection request, determining the target slave device according to the connection requirement parameters;

[0046] In step S104 involved in the embodiment of the present invention, in response to the connection request, a target slave device is determined according to the connection requirement parameters.

[0047] Among them, a target slave device is involved. After receiving a connection request, the programmable logic device parses the connection requirement parameters therein and determines the specific slave device that the master device wants to communicate with based on these parameters.

[0048] In this step, the target slave device is determined so as to realize the connection between the master device and the target slave device.

[0049] Step S106, determining a target data bus and a target clock bus corresponding to a target slave device according to a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus;

[0050] In step S106 involved in the embodiment of the present invention, a target data bus and a target clock bus corresponding to the target slave device are determined according to the slave device selection module.

[0051] Among them, a slave device selection module is involved, which arranges multiple slave devices in a predetermined form so that slave devices that meet the first preset condition share the same data bus (SDA), and slave devices that meet the second preset condition share the same clock bus (SCL).

[0052] The predetermined form may be a matrix form, that is, a plurality of slave devices are arranged into a matrix in the form of rows and columns.

[0053] When the predetermined form is a matrix form, the first preset condition may be a condition of the same row in the matrix, and the second preset condition may be a condition of the same column in the matrix. That is, in this case, the slave devices in the same row can share the same data bus (SDA), and the slave devices in the same column can share the same clock bus (SCL).

[0054] The first preset condition and the second preset condition can be adaptively set according to actual applications and scenarios, and can be a structure or layout different from the above examples. It is sufficient that multiple slave devices correspond to the same data bus and multiple slave devices meet the same clock bus.

[0055] This setting can significantly reduce the number of buses required, improve resource utilization, and solve the address conflict problem. In addition, by connecting slave devices to different buses, a large number of slave devices connected to the same bus can be dispersed to solve the problem of abnormal access caused by excessive bus load.

[0056] It should be noted that, when the slave devices in the same row are arranged in a matrix form and share the same data bus, and the slave devices in the same column share the same clock bus, the mount utilization can be maximized.

[0057] In addition, since the executor of the embodiment of the present invention can be a programmable logic chip, the programmable logic chip realizes the selection of the slave device through the algorithm corresponding to the transparent logic module, that is, the corresponding slave device is selected from the slave device selection module by means of a software algorithm, without using a large number of analog switches and logic devices, thereby reducing the cost of parts and supply risk.

[0058] Moreover, since a slave device selection module is provided, the number of slave devices connected to each bus and the actual load capacitance can be flexibly adjusted according to the bus load, and the size and number of modules can be flexibly adjusted, which is also more flexible.

[0059] That is, the embodiment of the present invention sets a slave device selection module, so that slave devices that meet the first preset condition have the same data bus, and slave devices that meet the second preset condition have the same clock bus. This reduces the number of system lines and reduces the connection load, thereby achieving the effect of improving the connection speed. This further solves the problem in the related art that when a master device is connected to any one of a plurality of slave devices, the plurality of slave devices are correspondingly provided with different data buses and clock buses, the entire system has a large number of lines, and there is a technical problem of slow connection speed.

[0060] In this step, the target data bus and the target clock bus are also involved. The target data bus and the target clock bus refer to the data line and the clock line used for communication with a specific slave device determined by the slave device selection module when establishing a communication connection between the master device and the slave device.

[0061] The target data bus is a signal line used to exchange data with the target slave device. In the I2C protocol, the data bus is used to send and receive data, and the sending and receiving of data are performed in synchronization with the clock signal. When the programmable logic device determines the target slave device, it will ensure that the target data bus is connected to the master device and the target slave device to allow data transmission.

[0062] The target clock bus is a signal line used to control the rhythm of data transmission on the target data bus. In the I2C protocol, the clock bus is controlled by the master device and is used to synchronize the start and end of data transmission and the sampling of data bits. After determining the target clock bus, the programmable logic device will ensure that the target clock bus correctly transmits the clock signal between the master device and the target slave device to ensure the synchronization and correctness of data transmission.

[0063] Step S108, establishing a connection path between the master device and the target slave device according to the target data bus and the target clock bus.

[0064] In step S108 of this embodiment, a connection path between the master device and the target slave device is established based on the target data bus and the target clock bus.

[0065] By determining and enabling the target data bus and the target clock bus, the master device can accurately and efficiently establish a communication connection with the target slave device without affecting other slave devices, reducing the bus load and improving the reliability and speed of data transmission. This mechanism is particularly beneficial for communication systems that need to handle multiple slave devices because it avoids address conflicts, simplifies communication management, and can flexibly adapt to different slave device loads.

[0066] Once the connection path is established, that is, the signal lines are correctly configured and the status is set, the master device can exchange data with the target slave device through the I2C bus using the SDA and SCL signal lines, such as data read and write operations.

[0067] It should be noted that after completing the data exchange, the master device will send an end signal. After receiving this signal, the programmable logic device will release the signal line of the target slave device and put it into an idle state, allowing other slave devices to use the same signal line or wait for the next connection request from the master device.

[0068] In steps S102-S108 involved in the present application, a connection request is received, wherein the connection request is used to establish a connection path between a master device and a slave device, and the connection request carries a connection requirement parameter; in response to the connection request, a target slave device is determined according to the connection requirement parameter; according to a slave device selection module, a target data bus and a target clock bus corresponding to the target slave device are determined, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and the slave devices that meet the first preset condition correspond to the same data bus, and the slave devices that meet the second preset condition correspond to the same clock bus; according to the target data bus and the target clock bus, a connection path between the master device and the target slave device is established. In the embodiment of the present invention, by setting a slave device selection module, the slave devices that meet the first preset condition correspond to the same data bus, and the slave devices that meet the second preset condition correspond to the same clock bus, thereby reducing the number of system lines, reducing the connection load, and achieving the effect of improving the connection speed, thereby solving the technical problem that, when the master device is connected to any one of the plurality of slave devices, the plurality of slave devices are correspondingly provided with different data buses and clock buses, the entire system has many lines, and there is a slow connection speed.

[0069] As an optional embodiment, in response to a connection request, determining a target slave device based on connection requirement parameters includes: in response to the connection request, obtaining slave device status information corresponding to a slave device selection module; determining the target slave device based on the slave device status information and the connection requirement parameters.

[0070] In this embodiment, specific steps of determining a target slave device are described.

[0071] The slave device status information refers to the current operating status and configuration information of the slave device, such as whether the slave device is online, ready to communicate, busy, etc. In this optional embodiment, it may also include whether the slave device is currently used by other master devices, and its position information in the slave device selection module.

[0072] In the steps involved in this embodiment, when the master device wants to establish communication with the slave device through a connection request, the programmable logic device in the system will first obtain the current status information of all slave devices in the slave device selection module to ensure the availability of the slave device and avoid communicating with devices that are busy, faulty or not ready.

[0073] The PLD then analyzes the connection request parameters provided by the master device in the request, including the address of the target device and the specific communication requirements. Based on the slave device status information and the connection request parameters, the PLD can determine a suitable target slave device that can meet the communication requirements.

[0074] By checking the slave device status information, the system can avoid establishing connections with invalid or faulty slave devices, thereby improving the stability and reliability of communication. In addition, in this way, the process of determining the target slave device ensures that only one slave device communicates with the master device at the same time, avoiding communication conflicts caused by multiple slave devices responding at the same time. This device selection mechanism based on status information and demand parameters enables the system to dynamically adapt to different communication needs.

[0075] It should be noted that in more complex communication systems, the acquisition and analysis of slave device status information and connection requirement parameters can be further refined and optimized. For example, the status information may include the real-time load of the slave device, the communication quality, and possible priority settings. The connection requirement parameters may need to consider the urgency of the communication, the size and type of data, and the communication history between the master device and other slave devices. Through more comprehensive analysis, the system can intelligently select the best slave device and dynamically adjust the communication parameters to optimize communication efficiency and overall system performance.

[0076] As an optional embodiment, after establishing a connection path between a master device and a target slave device based on a target data bus and a target clock bus, it also includes: detecting a signal state of the target device, wherein the target device includes: a master device and a target slave device; when the signal state of the target device changes, determining a changed device whose signal state has changed, and an update signal corresponding to the changed device; transmitting the update signal to the device to be changed, so that the signal corresponding to the device to be changed is changed to an update signal, wherein the device to be changed is a device whose signal state has not changed.

[0077] In this embodiment, the process of performing signal synchronization between the master device and the target slave device after establishing a connection path between the master device and the target slave device is described.

[0078] Among them, the signal state of the target device is involved, and the signal state is a signal state indicating the change of the data bus and the clock bus state, such as a level signal state, a modulation signal state, a current signal state, etc.

[0079] That is, the above-mentioned signal can be a level signal, and the level signal refers to the voltage state of the signal representing a high level (logic 1) or a low level (logic 0) in the circuit. That is, the system needs to monitor the signal level of the communication line (data bus SDA and clock bus SCL) between the master device and the target slave device in real time, so as to obtain the corresponding signal state in order to achieve signal synchronization.

[0080] The above signal can also be a current signal, and the current change on the signal line can reflect the change of the signal state. For example, in some communication systems, the level state can be indicated by changing the current direction or current size on the data line when sending data, and the receiving end determines the data bit by detecting the current change.

[0081] The above signals may also be modulated signals. In wireless communication, the SDA and SCL signals may be modulated onto a carrier signal, and the signal states of the data bus and the clock bus may be indicated by changes in the amplitude, frequency or phase of the carrier signal.

[0082] Among them, the signal state change is involved. During the communication process, the signal state will change with the change of data transmission and communication state. This change may be caused by the master device or the slave device. For example, when the data bit is transmitted, the signal level changes from high to low, or from low to high when the signal is a level signal. At this time, the signal synchronization processing is required. If the signal is not synchronized, the phase difference of the clock signal may cause the data sampling point to deviate, destroy the timing control, and thus affect the accuracy of data transmission. In addition, in a multi-slave device communication system, if multiple slave devices operate on the data bus at the same time (such as pulling down the data line), and the master device fails to recognize it in time, it may cause signal conflicts, resulting in data transmission errors or communication failures. Signal synchronization helps reduce the risk of such conflicts and ensures that the status of the data bus and the clock bus are clear and consistent at any time.

[0083] Among them, it involves changed devices and devices to be changed. The changed devices refer to devices that cause signal status changes, and the devices to be changed refer to devices that need to update their own signals according to the signal status of the changed devices.

[0084] Among them, an update signal is involved. The update signal is a signal used to update the signal of the device to be changed after processing (such as filtering) based on the signal change generated by the changed device.

[0085] In this embodiment, after the connection path between the master device and the target slave device is established, the system will detect the signal status of the communication line (SDA and SCL) between the target devices in real time. When a signal change is detected, the programmable logic device will immediately identify whether the signal state change is caused by the master device or the slave device, and determine the type of signal change (data signal SDA or clock signal SCL). The programmable logic device will adjust and send an update signal to the other device whose signal state has not changed according to the signal generated by the changed device, ensuring that the signals of both parties are synchronized, thereby avoiding data errors or timing problems that may occur during the communication process.

[0086] By detecting and synchronizing signals in real time, signal distortion and data transmission errors can be effectively avoided. Especially in high-speed communication and long-distance transmission, signal synchronization and signal consistency are crucial to ensure data integrity and communication stability. Accurate synchronization of signals reduces waiting time during communication and improves the efficiency of data transmission. This enables the system to operate at higher data rates, meeting the needs of modern communication systems for high-speed communication.

[0087] It should be noted that the steps involved in this embodiment can be processed by the transparent transmission logic module in the programmable logic chip. The operations involved in the transparent transmission logic module do not involve cache information. Therefore, there is no need to set up cache memory in the programmable logic chip, and the logic resources occupied are small.

[0088] It should also be noted that the detection and synchronization of signal status can be further optimized, for example, by using more advanced signal processing techniques to improve signal quality, such as equalization and pre-emphasis technology to compensate for signal attenuation and distortion on the transmission line. In addition, the system can also adapt to different communication environments by dynamically adjusting the signal threshold, such as increasing the threshold in an environment with weak signal strength to enhance the sensitivity of signal detection.

[0089] As an optional embodiment, when the signal state of the target device changes, determining the changed device whose signal state has changed, and the update signal corresponding to the changed device, includes: when the signal state of the target device changes, determining a predetermined delay time; after the predetermined delay time, determining a secondary result of whether the signal state has changed; when the secondary result is a signal state change, determining the changed device whose signal state has changed, and the update signal corresponding to the changed device.

[0090] In this embodiment, a process of setting a predetermined delay time to determine an update signal is described.

[0091] Among them, a predetermined delay time is involved. After detecting a change in the signal state, the system will set a short time delay, which is called the predetermined delay time. The purpose is to eliminate misjudgments that may be caused by noise or instantaneous fluctuations. For example, rapid signal fluctuations may only be due to line interference, not a real state change. That is, the delay time corresponding to the jitter filtering mechanism is set to ensure whether the signal changes through the jitter filtering mechanism, to ensure stability and accuracy during transmission, and to avoid misoperation caused by noise or rapid signal changes.

[0092] Among them, a secondary result is involved. After the predetermined delay time ends, the system will check the signal state of the signal line again to confirm whether the change in the signal is persistent. If the state of the signal line remains in the changed state, then the secondary result is that the signal state has indeed changed.

[0093] In the steps involved in this embodiment, during the I2C communication process, when a change in the signal state of the target device is detected, a predetermined delay time is set. During this delay time, the system determines whether the change in the signal is stable or just a momentary noise or fluctuation. If the signal state of the signal line remains in the changed state at the end of the predetermined delay time, the system confirms the actual change in the signal and identifies whether it is the master device or the slave device that caused the change. Subsequently, the system generates an update signal, which is adjusted according to the signal state of the changed device, and then transmits it to the device at the other end whose signal state has not changed.

[0094] For example, if the master device pulls the SDA signal line low and the slave device has not yet responded to this change, the system will generate an update signal and send it to the slave device to ensure that the slave device can respond correctly, thereby maintaining communication synchronization and correct data transmission.

[0095] By introducing a predetermined delay time, the system can filter out instantaneous signal fluctuations, avoiding misoperation and data errors caused by noise or line interference. The secondary result confirmation ensures the persistence of signal changes, improves the stability during the communication process, and avoids communication interruptions or errors that may be caused by rapid and asynchronous changes in signals. The transmission of the update signal ensures signal synchronization between the communicating parties, improves the accuracy and efficiency of data transmission, and reduces data loss or errors caused by signal asynchrony.

[0096] It should be noted that the setting of the predetermined delay time can be dynamically adjusted and optimized according to the noise level of the communication environment and the length of the line to achieve the best filtering effect and the minimum communication delay. For example, in a high-noise environment, the predetermined delay time can be appropriately increased to more accurately identify the real signal change, while in a low-noise environment, the delay time can be reduced to speed up communication. The system can also automatically adjust the predetermined delay time so that it can adapt to the optimal value under different communication conditions. At the same time, it can be combined with other signal processing technologies, such as signal shaping and decoupling circuits, to further improve signal quality and communication efficiency.

[0097] As an optional embodiment, a target data bus and a target clock bus corresponding to a target slave device are determined based on a slave device selection module, including: when there are multiple slave device selection modules, determining a target module corresponding to the target slave device from the multiple slave device selection modules; and determining a target data bus and a target clock bus corresponding to the target slave device in the target module.

[0098] In this embodiment, the steps of determining the target data bus and the target clock bus corresponding to the target slave device when the slave device selection module also includes multiple ones are described.

[0099] The steps of this embodiment illustrate that the slave device selection module also includes multiple modules, that is, the master device can be connected to multiple data buses and clock buses, and the multiple buses can be connected to multiple slave devices, thus solving the number bottleneck problem of the original analog strobe access.

[0100] In a communication system with multiple slave device selection modules, when the master device wants to communicate with a specific target slave device, it will first determine the module containing the slave device from the multiple slave device selection modules. Because when there are multiple modules in the system, the modules can be connected to the programmable logic chip in different ways, and the modules can be independent. Each module may be connected to different types of slave devices or subsets of slave devices to be able to connect more slave devices. Therefore, it is necessary to determine the required target module. Once the target module is determined, the programmable logic device will further search for the specific location of the target slave device in the module to determine its corresponding target data bus (SDA) and target clock bus (SCL). Since each slave device has a clear assignment in the module, this process ensures that the data and clock signals can be accurately and efficiently transmitted to the target slave device without interfering with the communication of slave devices in other modules.

[0101] As an optional embodiment, in response to the connection request, determining the target slave device according to the connection requirement parameters includes: determining the target interface from multiple candidate interfaces according to the connection requirement parameters; and determining the target slave device through the target interface.

[0102] In this embodiment, a process of determining a target slave device through an interface is described.

[0103] Among them, the interface to be selected is involved. In a multi-slave device communication system, the master device may communicate with the slave device through different interfaces. The interface to be selected here refers to the possible communication channel between the master device and the slave device. Each interface can connect one or more slave devices.

[0104] Among them, the target interface is involved. Based on the connection requirement parameters, the system selects the best or most suitable interface for this communication. The determination of the target interface takes into account factors such as the availability of the device, the load of the interface, and the communication efficiency.

[0105] In the steps involved in this embodiment, when the master device sends a connection request, the control module in the system will filter out the target interface from multiple possible interfaces to be selected based on the connection requirement parameters carried in the request. The selection process may involve querying the slave device status, evaluating the interface load, and matching the communication requirements. For example, if the connection requirement parameters require high-speed data transmission, the system will select an interface with a lower load and a higher transmission rate as the target interface. After determining the target interface, the system further determines the target slave device from the list of slave devices connected to the interface according to the connection requirement parameters. This process may involve checking the current status of the slave device (such as whether it is online, whether it is ready to communicate), the current communication load (to avoid selecting a device that is already in a busy state), and the matching degree of the slave device with the connection requirement parameters. Through the determination of the target interface, the system can avoid the waste of resources and ensure that the interface that best suits the current communication requirements is used for communication, thereby improving data transmission efficiency and communication speed.

[0106] It should be noted that the system can also achieve dynamic load balancing, that is, intelligently distribute communication requests among multiple interfaces and slave devices to avoid overloading any single interface or slave device and maintain the communication performance and stability of the entire system. For example, if it is detected that the load of an interface or slave device is close to the upper limit, the system can automatically reroute new communication requests to the interface or slave device with lower load to ensure smooth and efficient data transmission. Furthermore, the system can also support multi-path communication, that is, establish communication with the target slave device through multiple target interfaces at the same time to improve the bandwidth and fault tolerance of data transmission. In some cases, such as large data transmission volume or high-availability communication, the system can split the data packet and send it through multiple target interfaces at the same time to achieve parallel communication and improve data throughput; at the same time, if a target interface or slave device fails, the system can immediately switch to other available interfaces or slave devices to ensure the continuity of communication and the integrity of data.

[0107] Based on the above embodiments and optional embodiments, an optional implementation is provided, which is described in detail below.

[0108] In the related art, for network communication electronic devices such as switches and routers, there is usually a requirement for the CPU to access multiple Slaver peripherals through the MasterI2C interface. However, as the scale of hardware design expands, the technical problems that may be encountered mainly include:

[0109] 1) The I2C Master may encounter a situation where multiple Slaver peripherals have the same address. The I2C addresses of these peripherals are fixed at the factory and the read and write addresses can no longer be flexibly allocated, resulting in address conflicts when they are connected to the same I2C bus, or one I2C Master port can only connect to one slave device of the same type.

[0110] 2) In the I2C protocol, at the same time, the Master selects a Slaver for communication; when the number of Slavers on the same I2C bus increases, the I2C bus load will continue to increase, the signal quality will continue to deteriorate and become distorted, leading to various I2C transmission errors; in order to solve the problem of too many Slavers and too heavy load, it is necessary to introduce an interface expansion circuit.

[0111] The I2C one-to-many interface expansion circuit in the related technology is usually a gate type, using a large number of analog switches and logic devices to expand from one channel to multiple channels. At the same time, a group of channels Slaver and Master are selected for communication. Each channel of this solution also has the problems of address conflict and excessive bus load. The overhead of gate and the protection time gap during gate switching will further increase the load of the I2C bus. Using multiple interface expansion chips and a large number of analog switches in the same project will also bring great pressure on material cost and PCB layout routing. In order to ensure signal quality, the existing solution uses unidirectional gated logic devices to transmit the SCL signal unidirectionally, which cannot meet the clock extension requirements of the Slave side SCL signal.

[0112] Other programmable logic implementation solutions in the related technology require the design of the IICMaster core and related conversion logic inside the programmable logic, and require address resolution and data conversion for the IIC slave device that the CPU wants to access, which leads to complex program design and the need to use large-capacity programmable logic chips, which is too costly, has a large code workload, and has slow access speeds and high latency.

[0113] Based on this, an optional implementation of the present invention provides a programmable logic implementation solution for I2C one-to-many device switching, the core of which is a programmable logic device (CPLD / FPGA) chip or an MCU, to enable an I2C MASTER to access and manage multiple slave devices with the same address through a programmable logic (CPLD / FPGA) or an MCU, and to solve the problem of too many slaves and excessive bus load by flexibly using the IO pins of the programmable logic device (CPLD / FPGA) or the MCU.

[0114] The solution includes systems and methods:

[0115] The system includes: a master device, a slave device, and a programmable logic chip. The programmable logic chip includes an auxiliary selection interface module, a downlink slave device selection matrix module, a transparent transmission logic module, and an uplink interface unit module.

[0116] (I) I2C one-to-many device switching system:

[0117] Figure 2 is a schematic diagram of a one-to-many device switching system provided by an optional embodiment of the present invention, such as Figure 2 As shown, the system is introduced:

[0118] (1) The CPU is the original single Master (same as the master device mentioned above). It is the initiator and leader of all I2C communications. When it is connected to multiple slave devices with the same address, it will encounter address access conflicts and bus load bottlenecks.

[0119] (2) Uplink interface unit module, including SDA upstream interface unit and SCL upstream interface unit, used for signal transmission interface between CPU and programmable logic (CPLD / FPGA) or MCU.

[0120] (3) Auxiliary selection interface module, the CPU is used to specify the interface (same as the target interface) of a specific SLAVER slave device (same as the target slave device) and can use interfaces such as the serial peripheral interface SPI, the universal asynchronous receiver / transmitter UART, the general purpose input / output interface GPIO, and the integrated circuit interconnect I2C. In theory, the main I2C interface of the CPU can also be reused.

[0121] (4) Downlink slave device selection matrix module, including SDA slave device selection module and SCL slave device selection module, receives and parses slave device selection information of auxiliary selection interface, selects specific SDA and SCL channels, and thus selects the specified SLAVER slave device. Only the selected SLAVER slave device can respond to I2C bus and communicate. After selection, the SLAVER slave device can transmit signals with programmable logic (CPLD / FPGA) or MCU; Figure 3 is a schematic diagram of slave device selection logic provided by an optional implementation mode of the present invention, such as Figure 3 As shown, select from the device.

[0122] That is, in order to solve the problem of too many and too heavy loads on I2C mounted slave devices, this I2C one-to-many device switching programmable logic circuit introduces an IC slave device matrix design. The programmable logic circuit leads to multiple SDA and SCL pin signals, and multiple I2C slave devices are mounted under each signal, which are cross-formed into one or more I2C slave device selection matrices. This not only solves the problem of slave device address conflicts, but also reduces the I2C bus load. The number of mounted devices can also be adjusted according to the actual load of the slave device, saving the IO resources of the programmable logic.

[0123] (5) The transparent transmission logic module, including the SDA transparent transmission logic module and the SCL transparent transmission logic module, realizes the transparent transmission of the SDA and SCL signal levels between the CPUMASTER and the SLAVER slave device, thereby ensuring that the CPU accesses a specified SLAVER slave device. Its main working mode is as follows:

[0124] a) Before accessing a slave device, the CPU MASTER needs to select a valid slave device through the auxiliary selection interface. If the selected slave device is an invalid empty device, the transparent transmission logic will not respond to any action of the CPU.

[0125] b) After selecting a valid device, the transparent transmission logic operates with a clock synchronization circuit, constantly detecting the signal levels of the CPUMASTER and SLAVER slave devices. If it detects that the signal level on one side is pulled low, it transmits this signal to the same signal on the other side after filtering. For example, if it detects that the SDA level of the MASTER is pulled low, it pulls down the SDA signal selected by the slave device after filtering.

[0126] c) This transparent transmission logic will distinguish and remember which side of the I2C bus was pulled low first, and will perform a jitter filtering action when this side returns to a high level. After the jitter filtering is correct, the other side will be restored to a high level state; that is, the transparent transmission logic involved in the optional implementation mode of the present invention adds a jitter filtering action when realizing the high and low conversion of the signal level, and restores the potential state after the jitter filtering is correct, thereby ensuring the accuracy of the signal potential.

[0127] d) Figure 4 is a schematic diagram of a state machine provided in an optional embodiment of the present invention, such as Figure 4 As shown in the figure below, the state machine shows the state machine design of the transparent transmission logic. The small pluggable transceiver SFP0 slave device is selected by default, which involves the control of ABCD4 three-state output gate circuits to realize the above transparent transmission logic.

[0128] e) The SDA and SCL signals of I2C are quickly and transparently transmitted between the transparent transmission logic CPU and the selected slave device. The address and data information related to I2C is not cached or analyzed in the programmable logic (CPLD / FPGA) or MCU. Therefore, the programmable logic (CPLD / FPGA) or MCU does not need to set up cache memory, and low-capacity and cost programmable logic (CPLD / FPGA) or MCU can be used to implement this circuit design.

[0129] f) In order to prevent interlocking, this transparent transmission logic strictly controls the output timing and state, and can only change the state of one side after filtering the state of the other side, and ensure that the bus on both sides cannot be controlled to be pulled down at the same time to cause deadlock. In order to prevent interlocking, this transparent transmission logic strictly controls the output timing and state, and can only change the state of one side according to the state of the other side, and ensure that the bus on both sides cannot be controlled to be pulled down at the same time to cause deadlock.

[0130] (II) I2C one-to-many device switching method:

[0131] The following is an introduction to the specific execution steps of the method in combination with the system:

[0132] (1) Connection process:

[0133] S1, receiving a connection request, wherein the connection request is used to establish a connection path between a master device and a slave device, and the connection request carries a connection requirement parameter;

[0134] S2, in response to the connection request, determining a target interface from a plurality of candidate interfaces;

[0135] That is, in this implementation, an I2C is used for the main interactive communication between the CPU and the programmable logic (CPLD / FPGA) or MCU. In order to cooperate with the selection of a specific slave device, the CPU needs to use an auxiliary interface such as SPI, UART, GPIO, I2C, etc. to perform the slave device selection action;

[0136] S3, obtaining slave device status information corresponding to the slave device selection matrix through the target interface;

[0137] S4, determining the target slave device according to the slave device status information and the connection requirement parameters;

[0138] S5, determining a target data bus and a target clock bus corresponding to the target slave device according to a slave device selection matrix, wherein the slave device selection matrix includes a plurality of slave devices arranged in a matrix form, and slave devices in the same row correspond to the same data bus, and slave devices in the same column correspond to the same clock bus;

[0139] Optionally, in the case where the slave device selection matrix includes multiple slave devices, a target matrix corresponding to the target slave device is determined from the multiple slave device selection matrices.

[0140] That is, a large number of analog switches and logic devices are used to expand from one channel to multiple channels. At the same time, a group of channels are selected for communication between the slave and the master. Each channel of this solution also has the problem of address conflict and bus overload.

[0141] S6, establishing a connection path between the master device and the target slave device based on the target data bus and the target clock bus.

[0142] That is, the programmable logic (CPLD / FPGA) or MCU connects to multiple I2C slave devices with the same address. After the CPU selects a specific I2C slave device through the auxiliary interface setting, the CPU's I2C MASTER can directly access the selected slave device. The SDA and SCL of the I2C MASTER will be quickly transmitted to the slave device side through the programmable logic (CPLD / FPGA) or MCU, and the ACK response signal and clock extension signal of the slave device can also be quickly transmitted back to the CPU MASTER to meet the CPU's read and write access to the selected slave device through the I2C MASTER.

[0143] (2) Interaction process:

[0144] S1, detecting the level signal state of the target device, wherein the target device includes: a master device and a target slave device;

[0145] S2, determining a predetermined delay time when the level signal state of the target device changes;

[0146] S3, after a predetermined delay time, determining a secondary result of whether the state of the level signal changes;

[0147] S4, when the secondary result is that the level signal state changes, determining a changed device whose level signal state changes, and an updated level signal corresponding to the changed device;

[0148] S5, transmitting the update level signal to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update level signal, wherein the device to be changed is a device whose level signal state has not changed.

[0149] It should be noted that the main body executing the above steps can be a transparent transmission logic module. When transmitting and interacting signals, the signal sent by the master device can quickly pass through the transparent transmission logic module, through the target data bus and the target clock bus, and be transparently transmitted to the slave device side. The signal fed back by the slave device can also be quickly transmitted back to the master device to meet the master device's read and write access requirements for the selected slave device.

[0150] After selecting a target slave device from multiple slave devices, during signal interaction, the transparent transmission logic module operates with a clock synchronization circuit, constantly detecting the signal levels of the master device and the slave device. If it detects that the signal level on one side is pulled low, it transmits this signal to the same signal on the other side. For example, if it detects that the A signal of the master device is pulled low, it pulls down the A signal selected by the slave device. This enables information interaction between the master device and the slave device.

[0151] Through the above optional implementation, at least the following beneficial effects can be achieved:

[0152] 1) The master device can be connected to multiple data buses and clock buses, and multiple buses can be connected to multiple slave devices, solving the number bottleneck of the original analog strobe access.

[0153] 2) Connect slave devices to different buses to disperse the large number of slave devices connected to the same bus and solve access anomalies caused by excessive bus load.

[0154] 3) The programmable logic chip includes a transparent transmission logic module. The operations involved in the transparent transmission logic module do not involve cache information. Therefore, there is no need to set up cache memory in the programmable logic chip, and the logic resources occupied are small.

[0155] 4) The programmable logic chip does not participate in the address parsing and conversion work, and there is no need to design an additional main device module in the programmable logic chip. This circuit design can be implemented using a low-capacity and cost programmable logic chip.

[0156] 5) Using an algorithm (specifically, using an algorithm corresponding to a transparent logic module) to select a corresponding slave device from a downstream slave device selection matrix, without using a large number of analog switches and logic devices, thereby reducing component costs and supply risks.

[0157] 6) In the downstream slave device selection matrix module, a large amount of bus resources for programming logic can be saved through the matrix logic design of the slave device's data bus and clock bus.

[0158] 7) In the downstream slave device selection matrix module, the number of slave devices connected to each bus and the actual load capacitance can be flexibly adjusted according to the bus load, and the size and number of the matrix can be flexibly adjusted.

[0159] 8) This solution has a high theoretical bandwidth and is not affected by the clock bus clock frequency, and can adapt to various access rates.

[0160] According to an embodiment of the present invention, a system for implementing the above-mentioned method for establishing a connection path between a master device and a slave device is also provided. The system includes: a master device, multiple slave devices, and a target chip. The system is described in detail below.

[0161] A master device, multiple slave devices, and a target chip, wherein a slave device selection module is provided in the target chip, the target chip receives a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; in response to the connection request, a target slave device is determined based on the connection requirement parameter, wherein the slave device selection module includes the target slave device; based on the slave device selection module, a target data bus and a target clock bus corresponding to the target slave device are determined, wherein the slave device selection module includes multiple slave devices arranged in a predetermined form, slave devices that meet a first preset condition have the same data bus, and slave devices that meet a second preset condition have the same clock bus; based on the target data bus and the target clock bus, a connection path is established between the master device and the target slave device.

[0162] Optionally, a transparent transmission logic module is also provided in the target chip, wherein the transparent transmission logic module is used to detect the signal state of the target device after establishing a connection path between the master device and the target slave device, wherein the target device includes: a master device, a target slave device; when the signal state of the target device changes, determine the changed device whose signal state has changed, and an update signal corresponding to the changed device; transmit the update signal to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update signal, wherein the device to be changed is a device whose signal state has not changed.

[0163] Optionally, an auxiliary selection interface module is further provided in the target chip, wherein the auxiliary selection interface module is used to determine a target interface from a plurality of candidate interfaces according to connection requirement parameters; and establish a connection between the master device and the slave device selection module through the target interface.

[0164] It should be noted here that the above system can be used to implement steps S102 to S108 in the method for establishing a connection path between a master device and a slave device. The instances and application scenarios implemented by the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments.

[0165] According to an embodiment of the present invention, there is also provided a device for implementing the above method for establishing a connection path between a master device and a slave device. Figure 5 is a structural block diagram of an apparatus for establishing a connection path between a master device and a slave device according to an embodiment of the present invention. Figure 5 As shown, the device includes: a receiving module 502, a first determining module 504, a second determining module 506 and an establishing module 508. The device is described in detail below:

[0166] A receiving module 502 is used to receive a connection request, wherein the connection request is used to establish a connection path between a master device and a slave device, and the connection request carries a connection requirement parameter; a first determining module 504 is connected to the above-mentioned receiving module 502, and is used to respond to the connection request and determine a target slave device based on the connection requirement parameter; a second determining module 506 is connected to the above-mentioned first determining module 504, and is used to determine a target data bus and a target clock bus corresponding to the target slave device based on a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; an establishing module 508 is connected to the above-mentioned second determining module 506, and is used to establish a connection path between the master device and the target slave device based on the target data bus and the target clock bus.

[0167] The above modules correspond one-to-one to steps S102 to S108, and the instances and application scenarios implemented by multiple modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments.

[0168] An embodiment of the present invention can provide an electronic device, which includes a memory and a processor. The processor can call the information and application stored in the memory through a transmission device to perform the following steps: receiving a connection request, wherein the connection request is used to establish a connection path between a master device and a slave device, and the connection request carries a connection requirement parameter; in response to the connection request, determining a target slave device according to the connection requirement parameter; determining a target data bus and a target clock bus corresponding to the target slave device according to a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; establishing a connection path between the master device and the target slave device according to the target data bus and the target clock bus.

[0169] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a non-volatile storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0170] The embodiment of the present invention further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method for establishing a connection path between a master device and a slave device provided in the embodiment.

[0171] An embodiment of the present invention further provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method for establishing a connection path between a master device and a slave device in each embodiment of the present application.

[0172] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0173] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0174] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0175] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0176] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0177] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0178] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for establishing a connection path between a master device and a slave device, characterized in that: include: receiving a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; In response to the connection request, determining a target slave device according to the connection requirement parameters; Determine a target data bus and a target clock bus corresponding to the target slave device according to a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; A connection path between the master device and the target slave device is established based on the target data bus and the target clock bus.

2. The method according to claim 1, characterized in that In response to the connection request, determining a target slave device according to the connection requirement parameter includes: In response to the connection request, slave device status information corresponding to the slave device selection module is acquired; and the target slave device is determined according to the slave device status information and the connection requirement parameter.

3. The method according to claim 1, characterized in that After establishing a connection path between the master device and the target slave device according to the target data bus and the target clock bus, the method further includes: Detecting a signal state of a target device, wherein the target device includes: a master device and a target slave device; In case that the signal state of the target device changes, determining a changed device whose signal state has changed, and an update signal corresponding to the changed device; The update signal is transmitted to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update signal, wherein the device to be changed is a device whose signal state has not changed.

4. The method according to claim 3, characterized in that In the case where the signal state of the target device changes, determining a changed device whose signal state has changed, and an update signal corresponding to the changed device, comprises: determining a predetermined delay time in case a signal state of the target device changes; After the predetermined delay time, determining a secondary result of whether the signal state changes; When the secondary result is a signal state change, a changed device whose signal state has changed and an update signal corresponding to the changed device are determined.

5. The method according to claim 1, characterized in that Determining a target data bus and a target clock bus corresponding to the target slave device according to the slave device selection module includes: In the case that there are multiple slave device selection modules, determining a target module corresponding to the target slave device from the multiple slave device selection modules; In the target module, a target data bus and a target clock bus corresponding to the target slave device are determined.

6. The method according to any one of claims 1 to 5, characterized in that In response to the connection request, determining a target slave device according to the connection requirement parameter includes: Determining a target interface from a plurality of candidate interfaces according to the connection requirement parameters; The target slave device is determined through the target interface.

7. A system for establishing a connection path between a master device and a slave device, characterized in that: include: A master device, a plurality of slave devices, and a target chip, wherein the target chip is provided with a slave device selection module, The target chip receives a connection request, wherein the connection request is used to establish a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; In response to the connection request, determining a target slave device according to the connection requirement parameter, wherein the slave device selection module includes the target slave device; Determine a target data bus and a target clock bus corresponding to the target slave device according to a slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and slave devices that meet a first preset condition correspond to the same data bus, and slave devices that meet a second preset condition correspond to the same clock bus; A connection path between the master device and the target slave device is established based on the target data bus and the target clock bus.

8. The system according to claim 7, characterized in that The target chip is also provided with a transparent transmission logic module, wherein the transparent transmission logic module is used to establish a connection path between the master device and the target slave device. Detecting a signal state of a target device, wherein the target device includes: a master device and a target slave device; In case that the signal state of the target device changes, determining a changed device whose signal state has changed, and an update signal corresponding to the changed device; The update signal is transmitted to the device to be changed, so that the signal corresponding to the device to be changed is changed to the update signal, wherein the device to be changed is a device whose signal state has not changed.

9. The system according to claim 7, characterized in that The target chip is also provided with an auxiliary selection interface module, wherein the auxiliary selection interface module is used to Determining a target interface from a plurality of candidate interfaces according to the connection requirement parameters; A connection is established between the master device and the slave device selection module through the target interface.

10. A device for establishing a connection path between a master device and a slave device, characterized in that: include: A receiving module, used for receiving a connection request, wherein the connection request is used for establishing a connection path between the master device and the slave device, and the connection request carries a connection requirement parameter; A first determination module, configured to determine a target slave device in response to the connection request and according to the connection requirement parameter; A second determination module is used to determine a target data bus and a target clock bus corresponding to the target slave device according to the slave device selection module, wherein the slave device selection module includes a plurality of slave devices arranged in a predetermined form, and the slave devices that meet the first preset condition correspond to the same data bus, and the slave devices that meet the second preset condition correspond to the same clock bus; An establishing module is used to establish a connection path between the master device and the target slave device according to the target data bus and the target clock bus.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the computer-readable storage medium is located is controlled to execute the method for establishing a connection path between a master device and a slave device as described in any one of claims 1 to 6.

12. An electronic device, characterized in that: include: A memory storing an executable program; A processor is used to run the program, wherein the program, when running, executes the method for establishing a connection path between a master device and a slave device as described in any one of claims 1 to 6.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for establishing a connection path between a master device and a slave device as described in any one of claims 1 to 6 are implemented.

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