Single-wire communication control method, control device and computer program product

Abstract

The invention provides a single-wire communication control method, a control device and a computer program product, and the method comprises the steps: an initiating step: a first controller initiates communication; in the output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length; a reading step: adjusting the first pin of the first controller to be an input port and starting timing, and reading the pin level of the first pin according to a fixed time until the timing duration reaches a third set duration; and a storage step: receiving the current bit data under the condition that the pin levels read within the third set duration are the same, storing the current bit data in the communication data array in sequence, and repeating the initiating step, the output step, the reading step and the storage step in sequence at least once until the communication data with the set length is read. The problem of chip resource waste caused by the fact that a communication chip needs multi-line resources due to the fact that multi-line communication is carried out in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of line communication technology, and in particular to a single-line communication control method, a control device, a computer-readable storage medium and a computer program product. Background Art

[0002] In the field of microcontrollers, standard serial communication protocols such as I2C and SPI are usually used when two microcontrollers communicate with each other. However, due to various factors, these two protocols have certain limitations in practical applications: First, the I2C protocol is a half-duplex communication protocol that only transmits data on two lines, one is the data line SDA and the other is the clock line SCL. This half-duplex mode limits the data transmission speed and cannot meet the requirements of high-speed transmission. At the same time, due to the complex timing of the I2C protocol, strict timing control is required, which has high requirements on the hardware resources of the microcontroller and is not easy to implement; secondly, although the SPI protocol is a full-duplex communication protocol with four lines SCLK, MISO, MOSI, and SS. However, in practical applications, due to the limitation of hardware resources, when communicating between multiple SPI devices, the SPI interface can only be reused on multiple devices or the master-slave mode can be used. This will increase the complexity of hardware design and reduce the flexibility of communication. Currently, the communication methods on circuit boards are often IIC, SPI, UART, etc. When there are multiple communications, the chip is required to have multiple communication resources, resulting in a waste of development and selection time and an increase in procurement costs. Summary of the invention

[0003] The main purpose of the present application is to provide a single-line communication control method, a control device, a computer-readable storage medium and a computer program product, so as to at least solve the problem in the prior art of using multiple lines for communication, which causes the communication chip to require multiple line resources, resulting in chip resource waste.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a single-wire communication control method is provided, including: an initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port; an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a low level to high level detection, the falling edge detection is a high level to low level detection, the first controller Communicate with the second controller; a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time; a storage step, when the pin levels read within the third set duration are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into a communication data array, and repeating the initiating step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0005] Optionally, before the first controller initiates communication, the method further includes: initializing the first pin of the first controller as an output port and outputting the second voltage signal, and initializing a timer of the first controller.

[0006] Optionally, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, including: the first controller outputs the first voltage signal, and at the same time the first controller controls the timer to perform timing to obtain a first timing duration; when the first timing duration reaches the first set duration, the timer of the first controller is initialized, the first controller adjusts the output to the second voltage signal, and at the same time the first controller controls the timer to perform timing until the second set duration is reached.

[0007] Optionally, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers rising edge detection or falling edge detection, including: when the first voltage signal is a low level and the second voltage signal is a high level, triggering the second controller to perform the rising edge detection, the low level is 0, and the high level is 1; when the first voltage signal is the high level and the second voltage signal is the low level, triggering the second controller to perform the falling edge detection.

[0008] Optionally, the first pin of the first controller is connected to the second pin of the second controller through a single-line communication connection, a first resistor is connected between the single line, and a second resistor is connected between the third pin of the second controller and the target side line of the single line, the target side line is the line between the second pin and the first resistor, the second controller includes a second pin and a third pin, the second pin is an I / O port, and the third pin is an external interrupt port, receiving the current bit data sent by the second controller, including: initializing the second pin and the third pin; judging whether the third pin of the second controller recognizes the rising edge or the falling edge of the target node, the target node is the access node between the second resistor and the target side line; when the third pin recognizes the rising edge or the falling edge, switching the second pin of the second controller to an output port, so that the first controller receives the current bit data sent by the output port.

[0009] Optionally, before determining whether the third pin of the second controller recognizes a rising edge or a falling edge, the method includes: determining a target duration condition, the target duration condition being a duration condition that the target duration is less than the sum of the second set duration and the third set duration, the target duration being the time interval from when the third pin recognizes the rising edge or the falling edge to when the second pin outputs the current bit data.

[0010] Optionally, the second controller includes a second pin and a third pin, the second pin is an I / O port, and the third pin is an external input port, receiving the current bit data sent by the second controller, and also includes: initializing the second pin and the third pin; judging whether the third pin of the second controller recognizes the level change of the target node; when the level changes from a low level to a high level or the level changes from a high level to a low level, switching the second pin of the second controller to an output port, so that the first controller receives the current bit data sent by the output port.

[0011] According to another aspect of the present application, a single-line communication control device is provided, the device comprising: an initiating unit, for executing an initiating step, a first controller initiating communication, the first controller comprising a first pin, the first pin being an I / O port; an output unit, for executing an output step, the first controller sequentially outputting a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, the falling edge detection is a detection of a high level turning into a low level, the first controller and the The second controller is communicatively connected; a reading unit is used to execute a reading step, adjust the first pin of the first controller to an input port and start timing, read the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time; a storage unit is used to execute a storage step, receive the current bit data sent by the second controller when the pin levels read within the third set duration are the same, store the current bit data in order into a communication data array, and repeat the initiating step, the output step, the reading step and the storage step in sequence at least once until the communication data of the set length is read.

[0012] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the methods described.

[0013] According to another aspect of the present application, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, any one of the methods described above is implemented.

[0014] Applying the technical solution of the present application, in a control method for single-wire communication, first, in an initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port; then, in an outputting step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers rising edge detection or falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level to a high level, and the falling edge detection is a detection of a high level to a low level, and the first controller and the second controller device communication connection; then, a reading step, adjusting the above-mentioned first pin of the above-mentioned first controller to an input port and starting timing, reading the pin level of the above-mentioned first pin at a fixed time until the timing duration reaches a third set duration, and the above-mentioned third set duration is a multiple of the above-mentioned fixed time; finally, a storage step, when the above-mentioned pin levels read within the above-mentioned third set duration are the same, receiving the current bit data sent by the second controller, and storing the above-mentioned current bit data in sequence into the communication data array, and repeating the above-mentioned initiation step, the above-mentioned output step, the above-mentioned reading step and the above-mentioned storage step at least once in sequence until the communication data of the set length is read. In order to realize communication on one line, the present application sets two controller MCUs (i.e., the first controller and the second controller mentioned above) on one line. The communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal of a first set time, and then outputs a second voltage signal of a second set time. The main purpose is to give the second controller an interrupt, so the time lengths of the first set time and the second set time can meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller is converted into an input port, and a timer is used to generate T1 time. If the same level is detected multiple times in succession, it is considered that the correct bit data is read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading is completed. Single-line communication is realized through the above steps, thereby reducing the waste of chip resources. The present application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which causes the communication chip to require multiple line resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A hardware structure block diagram of a mobile terminal for executing a control method for single-line communication provided in an embodiment of the present application is shown;

[0016] Figure 2 A schematic flow chart of a single-line communication control method provided according to an embodiment of the present application is shown;

[0017] Figure 3 A circuit diagram of a single-line communication provided according to an embodiment of the present application is shown;

[0018] Figure 4 A schematic diagram of a single-line communication protocol provided according to an embodiment of the present application is shown;

[0019] Figure 5 A communication flow diagram of a first controller provided according to an embodiment of the present application is shown;

[0020] Figure 6 A communication flow diagram of a second controller provided according to an embodiment of the present application is shown;

[0021] Figure 7 A structural block diagram of a single-line communication control device provided according to an embodiment of the present application is shown.

[0022] The above drawings include the following reference numerals:

[0023] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0024] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] As introduced in the background technology, in the prior art, the communication methods on circuit boards are often IIC, SPI, UART, etc. When there are multi-channel communications, the chip is required to have multi-channel communication resources, resulting in a waste of development and selection time and an increase in procurement costs. In order to solve the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, the embodiments of the present application provide a single-line communication control method, a control device, a computer-readable storage medium and a computer program product.

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0029] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 1 is a hardware structure block diagram of a mobile terminal for executing a control method for single-line communication according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0030] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the control method of single-line communication in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. The transmission device 106 is used to receive or send data via a network. The above-mentioned specific examples of the network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] In this embodiment, a single-line communication control method running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0032] Figure 2 FIG. 1 is a flow chart of a control method for single-line communication according to an embodiment of the present application. Figure 2 As shown, the method comprises the following steps:

[0033] Step S201, an initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port.

[0034] Specifically, Figure 3 To illustrate a circuit diagram provided by an embodiment of the present application, a single circuit includes a first controller ( Figure 3 MCU1 in the second controller ( Figure 3MCU2 in the figure), the first pin of the first controller MCU1 is represented by P3, the first controller and the second controller are respectively located at the two ends of the single line, and single-line communication is performed through the first controller and the second controller. The communication is initiated by MCU1, and a fixed time, such as reading a packet of data at an interval of 500ms, is assumed that there are 40 bits in a packet of data, and the time for reading 40 bits of data must be less than the interval of 500ms.

[0035] Step S202, output step, the above-mentioned first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the above-mentioned second controller triggers a rising edge detection or a falling edge detection, the above-mentioned first voltage signal and the above-mentioned second voltage signal are opposite level signals, the above-mentioned rising edge detection is a detection of a low level to a high level, and the above-mentioned falling edge detection is a detection of a high level to a low level, and the above-mentioned first controller is communicatively connected with the above-mentioned second controller.

[0036] Specifically, the P3 port of the first controller MCU1 first outputs 0 of the TL time (the first set duration), and then outputs 1 of the TH time (the second set duration). The main purpose is to give MCU2 a rising edge, so the time lengths of TL and TH can meet the rising edge detection of MCU2, and there is no rigid time requirement. Or the P3 port of the first controller MCU1 first outputs 1 of the TL time (the first set duration), and then outputs 0 of the TH time (the second set duration). The main purpose is to give MCU2 a falling edge. Similarly, the time lengths of TL and TH can meet the falling edge detection of MCU2. Figure 4 As shown in the protocol diagram, the solid line indicates that the P3 pin of the first controller MCU1 outputs 0 or 1, TL indicates the time length of output 0, and TH indicates the time length of output 1. The dotted line indicates that the P3 port of the MCU is an input port, and TZ indicates the time length set as an input port. Tbit indicates the time length of the P2 port (second pin) of the second controller MCU2 outputting data.

[0037] Step S203, a reading step, adjusts the first pin of the first controller to an input port and starts timing, reads the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time.

[0038] Specifically, after TH time (the above second set time), the P3 port of the first controller MCU1 is converted into an input port, and a timer generates T1 time (ie the above fixed time), and reads the pin level of the first pin at the fixed time within the third set time.

[0039] Step S204, a storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0040] Specifically, if the same level is detected 3 or 5 times in a row, it is considered that the correct bit data is read, and then the read bit data is stored in the array. Therefore, the TZ time (i.e. the third set duration) is required to be greater than 3*T1 or 5*T1. It is recommended to take 7*T1 to ensure that the data can be read completely 3 or 5 times. Repeat the above initiation step, the above output step, the above reading step and the above storage step 39 times (because it was previously assumed that a packet of data is 40 bits, the specific number of times is determined according to the number of bits in each packet of data) to complete the transmission and reading of 40 bits of data. The correctness and completeness of the data can be guaranteed by the second controller MCU2 sending out the 40 data in sequence.

[0041] In this embodiment, first, in an initiating step, the first controller initiates communication, and the first controller includes a first pin, and the first pin is an I / O port; then, in an outputting step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a detection of a low level to a high level, and the falling edge detection is a detection of a high level to a low level, and the first controller is connected to the second controller for communication; after that , a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time; finally, a storage step, when the pin levels read within the third set duration are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiating step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read. In order to realize communication on one line, the present application sets two controller MCUs (i.e., the first controller and the second controller mentioned above) on one line. The communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal of a first set time, and then outputs a second voltage signal of a second set time. The main purpose is to give the second controller an interrupt, so the time lengths of the first set time and the second set time can meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller is converted into an input port, and a timer is used to generate T1 time. If the same level is detected multiple times in succession, it is considered that the correct bit data is read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading is completed. Single-line communication is realized through the above steps, thereby reducing the waste of chip resources. The present application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which causes the communication chip to require multiple line resources.

[0042] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the single-wire communication control method of the present application will be described in detail below in conjunction with specific embodiments.

[0043] In order to establish a stable communication environment and improve the reliability of data reading, in an optional implementation manner, before the above step S201, the method further includes:

[0044] Step S301 , initializing the first pin of the first controller as an output port and outputting the second voltage signal, and initializing a timer of the first controller.

[0045] In the above embodiment, if Figure 5 As shown, the first pin of the first controller MCU1 is initialized, P3 is an output port, and the output can be 0 or 1. The present invention takes output 1 as an example for explanation. The timer of MCU1 is initialized, and the timing of time T is set (the first set time, the second set time, and the third set time of the present invention are all timed with T as the minimum unit). In the configuration code of the first controller MCU1, the P3 pin is set to output mode. This usually involves writing to the port configuration register of the MCU to ensure that the bit related to the P3 pin in the register is set to the output state. Select a suitable second voltage signal, which is achieved by outputting a high level (1) or a low level (0) to the P3 pin, ensuring that the P3 pin is in the correct state before starting communication, so that the level can be accurately switched in subsequent steps. Configure a timer to interrupt periodically, and the interrupt interval is set to T1 time (for example, 200 microseconds). Once the above initialization is completed, the second controller is in a state ready to send data, and the first controller enters the receiving mode. Through initialization, the system can establish a stable communication environment to ensure the accurate transmission and reception of subsequent data. It also provides the necessary hardware preparation for the timing control of communication, thereby improving communication efficiency and the reliability of data transmission.

[0046] In order to ensure that the second controller successfully completes the interrupt detection, in an optional implementation manner, the above step S202 includes:

[0047] Step S2021, the first controller outputs the first voltage signal, and the first controller controls the timer to start timing, to obtain a first timing duration;

[0048] Step S2022, when the first timing duration reaches the first set duration, the timer of the first controller is initialized, the first controller adjusts the output to the second voltage signal, and the first controller controls the timer to count until the second set duration is reached.

[0049] In the above embodiment, if Figure 5As shown, taking the first voltage signal as 0 and the second voltage signal as 1 as an example, the P3 pin of MCU1 outputs 0; the timer is used to measure the first set time; it is determined whether the first set time is reached, if it is reached, the P3 pin of MCU1 outputs 1, otherwise it continues to measure; the timer is used to measure the second set time; it is determined whether the second set time is reached, if it is reached, the P3 pin of MCU1 becomes an input port, otherwise it continues to measure. The P3 port of MCU1 first outputs 0 of the TL time, and then outputs 1 of the TH time. The main purpose of this is to give MCU2 a rising edge, so the time length of TL and TH can meet the rising edge detection of MCU2, and there is no rigid time length requirement.

[0050] In order to ensure that the transmitted data bits can be correctly identified by the receiving end, in an optional implementation manner, the above step S202 includes:

[0051] Step S2023, when the first voltage signal is at a low level and the second voltage signal is at a high level, triggering the second controller to perform the rising edge detection, the low level is 0, and the high level is 1;

[0052] Step S2024, when the first voltage signal is at the high level and the second voltage signal is at the low level, triggering the second controller to perform the falling edge detection.

[0053] In the above embodiment, the third pin P1 interrupt of the second controller can be set to trigger the falling edge. Therefore, the first pin P3 of the first controller needs to be changed to output 1 first and then output 0. By quickly switching the P3 pin level of MCU1 in single-line communication, the P1 pin external interrupt of MCU2 can be triggered, thereby starting the interrupt service program. The level of the P3 port jumps from 1 to 0, and then from 0 to 1, which can be recognized by the P1 pin of MCU2 as a rising edge, triggering an interrupt; the level of the P3 port jumps from 1 to 0, and then from 0 back to 1, which can be recognized as a falling edge, also triggering an interrupt. By controlling the rising and falling edges of the signal, it is ensured that the transmission of the data bit can be correctly recognized by the receiving end. The rising edge is usually used to indicate the beginning of the data bit, and the falling edge may be used for the end of the data bit or the beginning of the next data bit, depending on the specific communication protocol. By utilizing the interrupt mechanism, real-time signal detection and response can be achieved, thereby improving communication efficiency. When the signal changes, MCU2 can immediately enter interrupt processing without having to poll the signal status in the main program, which reduces communication delays and increases data transmission rates.

[0054] It should be noted that if Figure 3 As shown, the interrupt is to determine Figure 3The A point in the program will enter the interrupt only when there is a rising edge. The rising edge of point A is determined by the output level change of port P3 of MCU1, so here we can ensure that point A can accurately identify the rising edge. What we need to worry about is whether there will be an abnormal rising edge at the level of point A when port P3 is an input port. When P3 is an input port, the level of point A is determined by the output level of port P2 of MCU2. P2 outputs a stable level at this time, so we only need to consider whether the level change at the moment when P3 changes from output to input port will produce an abnormal rising edge. If P2 outputs 1 and port P3 changes from output to input, the level of point A changes from 1 to 1, and there is no rising edge; if P2 outputs 0 and port P3 changes from output to input, the level of point A changes from 1 to 0, and there is no rising edge. From the above analysis, it can be seen that program processing will not cause the interrupt to be triggered incorrectly.

[0055] In order to improve the efficiency of data transmission, in an optional implementation manner, the above step S204 includes:

[0056] Step S2041, initializing the second pin and the third pin;

[0057] Step S2042, determining whether the third pin of the second controller recognizes a rising edge or a falling edge of a target node, where the target node is a connection node between the second resistor and the target-side line;

[0058] Step S2043: When the third pin identifies the rising edge or the falling edge, the second pin of the second controller is switched to an output port, so that the first controller receives the current bit data sent by the output port.

[0059] In the above embodiment, if Figure 3 As shown, the first pin P3 of the first controller MCU1 is connected to the second pin P2 of the second controller MCU2 via a single line communication, a first resistor R1 is connected between the single lines, a second resistor R2 is connected between the third pin P1 of the second controller MCU2 and the target side line of the single line, the target side line is the line between the second pin and the first resistor, and the second controller includes the second pin P2 and the third pin P1. Figure 6 As shown, initialize the pins of MCU2. P1 is the interrupt port, detecting the rising edge (0→1). P2 is not required and can be either an input or output port. Figure 5Take the input port as an example. Determine whether the P1 pin of MCU2 recognizes the rising edge (0→1). If so, the second pin P2 of the second controller MCU2 is switched to the output port; otherwise, continue to judge. Output the current bit data through the second pin P2 of MCU2; so that the first controller receives the current bit data sent by the output port. Through the external interrupt mechanism, real-time detection of signal changes is achieved. When the level change of point A (target node) is recognized by the P1 pin, the interrupt service program can be entered immediately to determine whether it is a valid data bit start signal. This improves the real-time and efficiency of communication, and can respond to signal changes quickly to avoid data bit loss. Once the valid signal change is recognized, the P2 pin of MCU2 will be set to output mode and output the corresponding level according to the state of the current bit data. This enables MCU1 to receive data from MCU2 and complete the data bit transmission process. By accurately controlling signal changes and using external interrupts to respond quickly, the efficiency of data transmission is improved, and stable communication performance can be maintained even when the network load is high.

[0060] It should also be noted that the duration Tbit of MCU2 outputting data includes the TL and TH time of MCU1, so it is required that no matter whether the P2 port of MCU2 outputs 0 or 1, it cannot affect the influence of MCU1 outputting 0 and 1 on the level of point A. For example, R1=10K and R2=1K are selected. In this invention, the low level recognition range of MCU is 0~Vcc*0.2, and the high level is Vcc*0.8~Vcc. As shown in Table 1, no matter what the level of Vcc (Volt Current Condenser, power supply voltage) is, it meets the use requirements.

[0061] Table 1

[0062]

[0063]

[0064] In order to ensure that the first controller reads data accurately, in an optional implementation manner, before the above step S2042, the method further includes:

[0065] Step S401, determine the target duration condition, the target duration condition is that the target duration is less than the sum of the second set duration and the third set duration, and the target duration is the time interval from the third pin identifying the rising edge or the falling edge to the second pin outputting the current bit data.

[0066] In the above embodiment, if Figure 3As shown, the P1 port of the second controller MCU2 is an external interrupt port. When a rising edge is detected, an interrupt is entered, and then the P2 port outputs the current bit of data 0 or 1. The duration of the process from the detection of the interrupt by P1 of MCU2 to the output of data by P2 depends on the program processing and main frequency of MCU2. The processing of P2 output is placed in the interrupt in the program, and the whole process can be completed within the us level. It should be noted that the time t from the recognition of the rising edge to the level of the output of P2 by the P1 pin of MCU1, that is, the above-mentioned target duration, needs to meet the target setting duration t<the second setting duration + the third setting duration, to ensure that P3 does not read the level when P2 is still outputting the previous bit value or in the input state, resulting in data errors.

[0067] In order to save I / O port resources of the second controller MCU2, in an optional implementation manner, the above step S204 includes:

[0068] Step S2044, initializing the second pin and the third pin;

[0069] Step S2045, determining whether the third pin of the second controller recognizes a level change of the target node;

[0070] Step S2046, when the level changes from low level to high level or when the level changes from high level to low level, the second pin of the second controller is switched to an output port, so that the first controller receives the current bit data sent by the output port.

[0071] In the above embodiment, the above second controller includes a first pin P2 and a second pin P1, the above first pin P1 is an I / O port, and the second pin P1 may not use an interrupt IO port, and may use the input port to read the level to identify the level change, and then process the second pin P2 port. At this time, the second controller MCU2 uses an external input port instead of a rising edge to identify the external level change, which is more friendly to the IO port resources of the second controller MCU2, because the external interrupt port of the MCU is limited, but an additional timer is still required to generate time to read the external level. In order to ensure the stability of the level reading, filtering processing of reading the same level for n consecutive times is required, and the time t will be relatively long (the target duration t in step S401 is less than the second set duration + the third set duration t).

[0072] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0073] The present application embodiment also provides a control device for single-line communication. It should be noted that the control device for single-line communication of the present application embodiment can be used to execute the control method for single-line communication provided by the present application embodiment. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions thereof will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0074] The following is an introduction to the single-line communication control device provided in an embodiment of the present application.

[0075] Figure 7 is a structural block diagram of a single-line communication control device according to an embodiment of the present application. Figure 7 As shown, the device comprises:

[0076] The initiating unit 10 is used to execute the initiating step, wherein the first controller initiates communication, and the first controller includes a first pin, and the first pin is an I / O port.

[0077] Specifically, Figure 3 To illustrate a circuit diagram provided by an embodiment of the present application, a single circuit includes a first controller ( Figure 3 MCU1 in the second controller ( Figure 3 MCU2 in the figure), the first pin of the first controller MCU1 is represented by P3, the first controller and the second controller are respectively located at the two ends of the single line, and single-line communication is performed through the first controller and the second controller. The communication is initiated by MCU1, and a fixed time, such as reading a packet of data at an interval of 500ms, is assumed that there are 40 bits in a packet of data, and the time for reading 40 bits of data must be less than the interval of 500ms.

[0078] The output unit 20 is used to execute the output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a detection of a low level to a high level, and the falling edge detection is a detection of a high level to a low level, and the first controller is communicatively connected with the second controller.

[0079] Specifically, the P3 port of the first controller MCU1 first outputs 0 of the TL time (the first set duration), and then outputs 1 of the TH time (the second set duration). The main purpose is to give MCU2 a rising edge, so the time lengths of TL and TH can meet the rising edge detection of MCU2, and there is no rigid time requirement. Or the P3 port of the first controller MCU1 first outputs 1 of the TL time (the first set duration), and then outputs 0 of the TH time (the second set duration). The main purpose is to give MCU2 a falling edge. Similarly, the time lengths of TL and TH can meet the falling edge detection of MCU2. Figure 4 As shown in the protocol diagram, the solid line indicates that the P3 pin of the first controller MCU1 outputs 0 or 1, TL indicates the time length of output 0, and TH indicates the time length of output 1. The dotted line indicates that the P3 port of the MCU is an input port, and TZ indicates the time length set as an input port. Tbit indicates the time length of the P2 port (second pin) of the second controller MCU2 outputting data.

[0080] The reading unit 30 is used to execute the reading step, adjust the above-mentioned first pin of the above-mentioned first controller to an input port and start timing, read the pin level of the above-mentioned first pin at a fixed time until the timing duration reaches a third set duration, and the above-mentioned third set duration is a multiple of the above-mentioned fixed time.

[0081] Specifically, after TH time (the above second set time), the P3 port of the first controller MCU1 is converted into an input port, and a timer generates T1 time (ie the above fixed time), and reads the pin level of the first pin at the fixed time within the third set time.

[0082] The storage unit 40 is used to execute the storage step, and when the pin levels read within the third set time are the same, receive the current bit data sent by the second controller, store the current bit data in the communication data array in sequence, and repeat the initiation step, the output step, the reading step and the storage step at least once until the communication data of the set length is read.

[0083] Specifically, if the same level is detected 3 or 5 times in a row, it is considered that the correct bit data is read, and then the read bit data is stored in the array. Therefore, the TZ time (i.e. the third set duration) is required to be greater than 3*T1 or 5*T1. It is recommended to take 7*T1 to ensure that the data can be read completely 3 or 5 times. Repeat the above initiation step, the above output step, the above reading step and the above storage step 39 times (because it was previously assumed that a packet of data is 40 bits, the specific number of times is determined according to the number of bits in each packet of data) to complete the transmission and reading of 40 bits of data. The correctness and completeness of the data can be guaranteed by the second controller MCU2 sending out the 40 data in sequence.

[0084] In this embodiment, an initiating unit is used to execute an initiating step, and a first controller initiates communication. The first controller includes a first pin, and the first pin is an I / O port; an output unit is used to execute an output step, and the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, and the first voltage signal and the second voltage signal are mutually opposite level signals, and the rising edge detection is a detection of a low level to a high level, and the falling edge detection is a detection of a high level to a low level, and the first controller is communicatively connected with the second controller; reading A unit is used to execute a reading step, adjust the first pin of the first controller to an input port and start timing, read the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time; a storage unit is used to execute a storage step, receive the current bit data sent by the second controller when the pin levels read within the third set duration are the same, store the current bit data in order into the communication data array, and repeat the initiating step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read. In order to realize communication on one line, the present application sets two controller MCUs (i.e., the above-mentioned first controller and the second controller) on one line. The communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal of a first set time, and then outputs a second voltage signal of a second set time. The main purpose is to give the second controller an interrupt, so the time length of the first set time and the second set time can meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller is converted into an input port, and a timer is used to generate T1 time. If the same level is detected for multiple consecutive times, it is considered that the correct bit data is read, and the current bit data is stored in the communication data array. Repeat the above steps until the data reading and transmission are completed. Single-line communication is realized through the above steps, thereby reducing the waste of chip resources. The present application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which causes the communication chip to require multiple line resources.

[0085] In order to establish a stable communication environment and improve the reliability of data reading, in an optional implementation manner, the device further includes:

[0086] The initialization unit is used to initialize the first pin of the first controller as an output port and output the second voltage signal, and initialize the timer of the first controller before the first controller initiates communication.

[0087] In the above embodiment, if Figure 5As shown, the first pin of the first controller MCU1 is initialized, P3 is an output port, and the output can be 0 or 1. The present invention takes output 1 as an example for explanation. The timer of MCU1 is initialized, and the timing of time T is set (the first set time, the second set time, and the third set time of the present invention are all timed with T as the minimum unit). In the configuration code of the first controller MCU1, the P3 pin is set to output mode. This usually involves writing to the port configuration register of the MCU to ensure that the bit related to the P3 pin in the register is set to the output state. Select a suitable second voltage signal, which is achieved by outputting a high level (1) or a low level (0) to the P3 pin, ensuring that the P3 pin is in the correct state before starting communication, so that the level can be accurately switched in subsequent steps. Configure a timer to interrupt periodically, and the interrupt interval is set to T1 time (for example, 200 microseconds). Once the above initialization is completed, the second controller is in a state ready to send data, and the first controller enters the receiving mode. Through initialization, the system can establish a stable communication environment to ensure the accurate transmission and reception of subsequent data. It also provides the necessary hardware preparation for the timing control of communication, thereby improving communication efficiency and the reliability of data transmission.

[0088] In order to ensure that the second controller successfully completes the interrupt detection, in an optional implementation manner, the output unit in the above step includes:

[0089] A first output module, used for the first controller to output the first voltage signal, and the first controller controls the timer to perform timing to obtain a first timing duration;

[0090] The second output module is used to initialize the timer of the first controller when the first timing duration reaches the first set duration, and the first controller adjusts the output to the second voltage signal. At the same time, the first controller controls the timer to perform timing until the second set duration is reached.

[0091] In the above embodiment, if Figure 5 As shown, taking the first voltage signal as 0 and the second voltage signal as 1 as an example, the P3 pin of MCU1 outputs 0; the timer is used to measure the first set time; it is determined whether the first set time is reached, if it is reached, the P3 pin of MCU1 outputs 1, otherwise it continues to measure; the timer is used to measure the second set time; it is determined whether the second set time is reached, if it is reached, the P3 pin of MCU1 becomes an input port, otherwise it continues to measure. The P3 port of MCU1 first outputs 0 of the TL time, and then outputs 1 of the TH time. The main purpose of this is to give MCU2 a rising edge, so the time length of TL and TH can meet the rising edge detection of MCU2, and there is no rigid time length requirement.

[0092] In order to ensure that the transmitted data bits can be correctly recognized by the receiving end, in an optional implementation manner, the output unit further includes:

[0093] A first trigger module, used for triggering the second controller to perform the rising edge detection when the first voltage signal is at a low level and the second voltage signal is at a high level, the low level being 0 and the high level being 1;

[0094] The second trigger module is used to trigger the second controller to perform the falling edge detection when the first voltage signal is at the high level and the second voltage signal is at the low level.

[0095] In the above embodiment, the third pin P1 interrupt of the second controller can be set to trigger the falling edge. Therefore, the first pin P3 of the first controller needs to be changed to output 1 first and then output 0. By quickly switching the P3 pin level of MCU1 in single-line communication, the P1 pin external interrupt of MCU2 can be triggered, thereby starting the interrupt service program. The level of the P3 port jumps from 1 to 0, and then from 0 to 1, which can be recognized by the P1 pin of MCU2 as a rising edge, triggering an interrupt; the level of the P3 port jumps from 1 to 0, and then from 0 back to 1, which can be recognized as a falling edge, also triggering an interrupt. By controlling the rising and falling edges of the signal, it is ensured that the transmission of the data bit can be correctly recognized by the receiving end. The rising edge is usually used to indicate the beginning of the data bit, and the falling edge may be used for the end of the data bit or the beginning of the next data bit, depending on the specific communication protocol. By utilizing the interrupt mechanism, real-time signal detection and response can be achieved, thereby improving communication efficiency. When the signal changes, MCU2 can immediately enter interrupt processing without having to poll the signal status in the main program, which reduces communication delays and increases data transmission rates.

[0096] It should be noted that if Figure 3 As shown, the interrupt is to determine Figure 3 The A point in the program will enter the interrupt only when there is a rising edge. The rising edge of point A is determined by the output level change of port P3 of MCU1, so here we can ensure that point A can accurately identify the rising edge. What we need to worry about is whether there will be an abnormal rising edge at the level of point A when port P3 is an input port. When P3 is an input port, the level of point A is determined by the output level of port P2 of MCU2. P2 outputs a stable level at this time, so we only need to consider whether the level change at the moment when P3 changes from output to input port will produce an abnormal rising edge. If P2 outputs 1 and port P3 changes from output to input, the level of point A changes from 1 to 1, and there is no rising edge; if P2 outputs 0 and port P3 changes from output to input, the level of point A changes from 1 to 0, and there is no rising edge. From the above analysis, it can be seen that program processing will not cause the interrupt to be triggered incorrectly.

[0097] In order to improve the efficiency of data transmission, in an optional implementation manner, the storage unit includes:

[0098] A first initialization module, used for initializing the second pin and the third pin;

[0099] A first judgment module is used to judge whether the third pin of the second controller recognizes a rising edge or a falling edge of a target node, where the target node is a connection node between the second resistor and the target-side line;

[0100] The first switching module is used to switch the second pin of the second controller to an output port when the third pin recognizes the rising edge or the falling edge, so that the first controller receives the current bit data sent by the output port.

[0101] In the above embodiment, if Figure 3 As shown, the first pin P3 of the first controller MCU1 is connected to the second pin P2 of the second controller MCU2 via a single line communication, a first resistor R1 is connected between the single lines, a second resistor R2 is connected between the third pin P1 of the second controller MCU2 and the target side line of the single line, the target side line is the line between the second pin and the first resistor, and the second controller includes the second pin P2 and the third pin P1. Figure 6 As shown, initialize the pins of MCU2. P1 is the interrupt port, detecting the rising edge (0→1). P2 is not required and can be either an input or output port. Figure 5 Take the input port as an example. Determine whether the P1 pin of MCU2 recognizes the rising edge (0→1). If so, the second pin P2 of the second controller MCU2 is switched to the output port; otherwise, continue to judge. Output the current bit data through the second pin P2 of MCU2; so that the first controller receives the current bit data sent by the output port. Through the external interrupt mechanism, real-time detection of signal changes is achieved. When the level change of point A (target node) is recognized by the P1 pin, the interrupt service program can be entered immediately to determine whether it is a valid data bit start signal. This improves the real-time and efficiency of communication, and can respond to signal changes quickly to avoid data bit loss. Once the valid signal change is recognized, the P2 pin of MCU2 will be set to output mode and output the corresponding level according to the state of the current bit data. This enables MCU1 to receive data from MCU2 and complete the data bit transmission process. By accurately controlling signal changes and using external interrupts to respond quickly, the efficiency of data transmission is improved, and stable communication performance can be maintained even when the network load is high.

[0102] It should also be noted that the duration Tbit of MCU2 outputting data includes the TL and TH time of MCU1, so it is required that no matter whether the P2 port of MCU2 outputs 0 or 1, it cannot affect the influence of MCU1 outputting 0 and 1 on the level of point A. For example, R1=10K and R2=1K are selected. In this invention, the low level recognition range of MCU is 0~Vcc*0.2, and the high level is Vcc*0.8~Vcc. As shown in Table 1, no matter what the level of Vcc (Volt Current Condenser, power supply voltage) is, it meets the use requirements.

[0103] Table 1

[0104]

[0105]

[0106] In order to ensure that the first controller reads data accurately, in an optional implementation manner, the device further includes:

[0107] A determination unit is used to determine a target duration condition before judging whether the third pin of the second controller recognizes a rising edge or a falling edge, wherein the target duration condition is a duration condition that the target duration is less than the sum of the second set duration and the third set duration, and the target duration is the time interval from when the third pin recognizes the rising edge or the falling edge to when the second pin outputs the current bit data.

[0108] In the above embodiment, if Figure 3 As shown, the P1 port of the second controller MCU2 is an external interrupt port. When a rising edge is detected, an interrupt is entered, and then the P2 port outputs the current bit of data 0 or 1. The duration of the process from the detection of the interrupt by P1 of MCU2 to the output of data by P2 depends on the program processing and main frequency of MCU2. The processing of P2 output is placed in the interrupt in the program, and the whole process can be completed within the us level. It should be noted that the time t from the recognition of the rising edge to the level of the output of P2 by the P1 pin of MCU1, that is, the above-mentioned target duration, needs to meet the target setting duration t<the second setting duration + the third setting duration, to ensure that P3 does not read the level when P2 is still outputting the previous bit value or in the input state, resulting in data errors.

[0109] In order to save I / O port resources of the second controller MCU2, in an optional implementation manner, the storage unit includes:

[0110] A second initialization module, used to initialize the second pin and the third pin;

[0111] A second determination module, used for determining whether the third pin of the second controller recognizes a level change of the target node;

[0112] The second switching module is used to switch the second pin of the second controller to an output port when the above-mentioned level changes from a low level to a high level or when the above-mentioned level changes from the above-mentioned high level to a low level, so that the above-mentioned first controller receives the current bit data sent by the above-mentioned output port.

[0113] In the above embodiment, the above second controller includes a first pin P2 and a second pin P1, the above first pin P1 is an I / O port, and the second pin P1 may not use an interrupt IO port, and may use the input port to read the level to identify the level change, and then process the second pin P2 port. At this time, the second controller MCU2 uses an external input port instead of a rising edge to identify the external level change, which is more friendly to the IO port resources of the second controller MCU2, because the external interrupt port of the MCU is limited, but an additional timer is still required to generate time to read the external level. In order to ensure the stability of the level reading, it is necessary to have a filtering process of reading the same level n times in a row, and the time t will be relatively long.

[0114] The above-mentioned single-line communication control device includes a processor and a memory. The above-mentioned initiating unit, output unit and reading unit are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions. The above-mentioned modules are all located in the same processor; or, the above-mentioned modules are located in different processors in any combination.

[0115] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be set, and the problem of chip resource waste caused by the communication chip requiring multiple line resources due to the use of multiple lines for communication in the prior art can be solved by adjusting the kernel parameters.

[0116] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0117] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the single-wire communication control method.

[0118] Specifically, the control method of single-line communication includes:

[0119] Step S201, initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port;

[0120] Step S202, an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller;

[0121] Step S203, a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time;

[0122] Step S204, a storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0123] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the single-wire communication control method is executed when the program is running.

[0124] Specifically, the control method of single-line communication includes:

[0125] Step S201, initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port;

[0126] Step S202, an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller;

[0127] Step S203, a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time;

[0128] Step S204, a storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0129] An embodiment of the present invention provides a single-line communication control system, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, at least the following steps are implemented:

[0130] Step S201, initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port;

[0131] Step S202, an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller;

[0132] Step S203, a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time;

[0133] Step S204, a storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0134] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0135] Step S201, initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port;

[0136] Step S202, an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller;

[0137] Step S203, a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time;

[0138] Step S204, a storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

[0139] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0140] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0141] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0142] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0144] In a typical configuration, a computing device includes one or more processors (CPU), input / output pins, network pins, and memory.

[0145] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0146] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0148] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0149] 1) The control method of single-wire communication of the present application comprises an initiating step, wherein the first controller initiates communication, wherein the first controller comprises a first pin, and wherein the first pin is an I / O port; and an outputting step, wherein the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, wherein the first voltage signal and the second voltage signal are mutually opposite level signals, wherein the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller communicates with the second controller. connection; a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time; a storage step, when the pin levels read within the third set duration are the same, receiving the current bit data sent by the second controller, and storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read. In order to realize communication on one line, the present application sets two controller MCUs (i.e., the above-mentioned first controller and the second controller) on one line. The communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal of a first set time, and then outputs a second voltage signal of a second set time. The main purpose is to give the second controller an interrupt, so the time length of the first set time and the second set time can meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller is converted into an input port, and a timer is used to generate T1 time. If the same level is detected for multiple consecutive times, it is considered that the correct bit data is read, and the current bit data is stored in the communication data array. Repeat the above steps until the data reading and transmission are completed. Single-line communication is realized through the above steps, thereby reducing the waste of chip resources. The present application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which causes the communication chip to require multiple line resources.

[0150] 2) The single-line communication control device of the present application, the initiating unit, is used to execute the initiating step, the first controller initiates the communication, the first controller includes a first pin, the first pin is an I / O port; the output unit is used to execute the output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers a rising edge detection or a falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a low level to high level detection, the falling edge detection is a high level to low level detection, the first controller communicates with the second controller connection; a reading unit, used to execute a reading step, adjust the above-mentioned first pin of the above-mentioned first controller to an input port and start timing, read the pin level of the above-mentioned first pin at a fixed time until the timing duration reaches a third set duration, and the above-mentioned third set duration is a multiple of the above-mentioned fixed time; a storage unit, used to execute a storage step, when the above-mentioned pin levels read within the above-mentioned third set duration are the same, receive the current bit data sent by the second controller, store the above-mentioned current bit data in order into the communication data array, and repeat the above-mentioned initiation step, the above-mentioned output step, the above-mentioned reading step and the above-mentioned storage step at least once in sequence until the communication data of the set length is read. In order to realize communication on one line, the present application sets two controller MCUs (i.e., the above-mentioned first controller and the second controller) on one line. The communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal of a first set time, and then outputs a second voltage signal of a second set time. The main purpose is to give the second controller an interrupt, so the time length of the first set time and the second set time can meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller is converted into an input port, and a timer is used to generate T1 time. If the same level is detected for multiple consecutive times, it is considered that the correct bit data is read, and the current bit data is stored in the communication data array. Repeat the above steps until the data reading and transmission are completed. Single-line communication is realized through the above steps, thereby reducing the waste of chip resources. The present application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which causes the communication chip to require multiple line resources.

[0151] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A single-line communication control method, characterized in that: include: Initiating step, a first controller initiates communication, the first controller includes a first pin, and the first pin is an I / O port; an output step, wherein the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers rising edge detection or falling edge detection, the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller; a reading step, adjusting the first pin of the first controller to an input port and starting timing, reading the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, wherein the third set duration is a multiple of the fixed time; A storage step, when the pin levels read within the third set time are the same, receiving the current bit data sent by the second controller, storing the current bit data in order into the communication data array, and repeating the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

2. The method according to claim 1, characterized in that Before the first controller initiates communication, the method further includes: Initialize the first pin of the first controller to be an output port and output the second voltage signal, and initialize a timer of the first controller.

3. The method according to claim 1, characterized in that: The first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, including: The first controller outputs the first voltage signal, and at the same time the first controller controls a timer to perform timing to obtain a first timing duration; When the first timing duration reaches the first set duration, the timer of the first controller is initialized, the first controller adjusts the output to the second voltage signal, and the first controller controls the timer to count until the second set duration is reached.

4. The method according to claim 1, characterized in that: The first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that the second controller triggers rising edge detection or falling edge detection, including: When the first voltage signal is at a low level and the second voltage signal is at a high level, triggering the second controller to perform the rising edge detection, the low level is 0, and the high level is 1; When the first voltage signal is at the high level and the second voltage signal is at the low level, the second controller is triggered to perform the falling edge detection.

5. The method according to claim 1, characterized in that The first pin of the first controller is connected to the second pin of the second controller through a single line communication, a first resistor is connected between the single lines, a second resistor is connected between the third pin of the second controller and a target side line of the single line, the target side line is a line between the second pin and the first resistor, the second controller includes a second pin and a third pin, the second pin is an I / O port, the third pin is an external interrupt port, and receiving current bit data sent by the second controller includes: Initializing the second pin and the third pin; Determine whether the third pin of the second controller recognizes a rising edge or a falling edge of a target node, where the target node is a connection node between the second resistor and the target-side line; When the third pin identifies the rising edge or the falling edge, the second pin of the second controller is switched to an output port, so that the first controller receives the current bit data sent by the output port.

6. The method according to claim 5, characterized in that Before determining whether the third pin of the second controller recognizes a rising edge or a falling edge, the method includes: Determine a target duration condition, wherein the target duration condition is a duration condition that the target duration is less than the sum of the second set duration and the third set duration, and the target duration is the time interval from the third pin identifying the rising edge or the falling edge to the second pin outputting the current bit data.

7. The method according to claim 5, characterized in that The second controller includes a second pin and a third pin, the second pin is an I / O port, the third pin is an external input port, and receives current bit data sent by the second controller, and further includes: Initializing the second pin and the third pin; Determining whether the third pin of the second controller recognizes a level change of the target node; When the level changes from low level to high level or changes from high level to low level, the second pin of the second controller is switched to an output port, so that the first controller receives the current bit data sent by the output port.

8. A single-line communication control device, characterized in that: The device comprises: An initiating unit, configured to execute an initiating step, wherein a first controller initiates communication, wherein the first controller comprises a first pin, and the first pin is an I / O port; an output unit, configured to execute an output step, wherein the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers a rising edge detection or a falling edge detection, wherein the first voltage signal and the second voltage signal are mutually opposite level signals, the rising edge detection is a detection of a low level turning into a high level, and the falling edge detection is a detection of a high level turning into a low level, and the first controller is communicatively connected with the second controller; a reading unit, configured to execute a reading step, adjust the first pin of the first controller to an input port and start timing, and read the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, wherein the third set duration is a multiple of the fixed time; A storage unit is used to execute a storage step, and when the pin levels read within the third set time period are the same, receives the current bit data sent by the second controller, stores the current bit data in order into a communication data array, and repeats the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 7.

10. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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