Data updating method based on serial number shared memory

Abstract

The invention discloses a data updating method based on a serial number shared memory. The method is applied to a scene that a multi-core digital signal processor shares a memory for data processing. The shared memory comprises a first data packet and a second data packet; when the read-write shared memory is in a waiting state, the multi-core digital signal processor carries out in-packet data updating on the first data packet, and the in-packet data updating comprises the following steps: defining an updating serial number for a core which carries out rewriting operation on the data of the first data packet, defining a historical serial number for a core which only reads the data of the first data packet, judging whether the data of the first data packet is updated or not and whether the data needs to be read again or not by comparing the updated serial number with the value of the historical serial number, and adding overtime protection while updating the data in the second data packet. The read-write frequency of the same data in the shared memory by multiple cores is reduced, and then the number of times of waiting caused by high-frequency read-write of the shared memory data is reduced.

Description

Technical Field

[0001] The invention belongs to the field of DSP chip shared memory data transmission in a ground-to-air missile weapon system, and in particular relates to a data updating method based on a serial number shared memory. Background Art

[0002] The main control programs of surface-to-air missile weapon systems mostly run in digital signal processors (DSPs). Due to the increasing application requirements of weapon systems, the wider application backgrounds, and the increasingly complex communication data, it has become a trend to distribute different functions in surface-to-air missile weapon systems in different cores of multi-core processors for independent operation. Among them, TMS320C66xDSP is widely used based on its powerful multi-core processing capabilities and rich memory architecture.

[0003] When using multi-core to control and perform mathematical calculations on the surface-to-air missile weapon system, data interaction between different computing cores is inevitable. Data interaction based on shared memory is undoubtedly a better choice. When operating shared memory read and write, TMS320C66xDSP provides measures to determine whether the waiting state is "CACHE_WAIT" (i.e., cache waiting time) and rewrite the value of "L1D InvalidateWordCountRegister (hereinafter referred to as L1DIWC register)" to ensure the correctness and consistency of shared memory data. Specifically, when the "L1DIWC register" does not meet the conditions, the shared memory read and write operations will enter a loop wait, and the read and write operations will only be performed when the "L1DIWC register" conditions are met. In addition, in order to improve the efficiency of asynchronous data reading between multi-cores, a special status word is usually defined to identify whether the data is updated data, and it is rewritten to identify whether the current data is the latest unused data.

[0004] The commonly used method is that the data updater sets the update status word to "updated" when updating the shared memory data, and the data user reads the data and sets the update status to "not updated" when judging that the data is in the "updated" state. However, in actual projects, when faced with the high frequency of multi-core data interaction, multiple cores frequently read and write shared memory (including rewriting the update status word), which will cause read and write competition of the L1DIWC register. Frequent competition of the L1DIWC register will cause the data to be in a protected state for a long time, resulting in the data being unable to be read, which will inevitably increase the waiting time of other cores to read and write the L1DIWC register, and in severe cases, will cause the program to stagnate.

[0005] Other existing technologies, such as the patent document with publication number CN101794271B, specifically disclose a method for implementing multi-core memory consistency, including: the second-level cache of the first processor group receives a control signal of the first processor group reading the first data; if the first data is currently maintained by the second processor group, the first data is read in the first-level cache of the second processor group through the fast consistency interface of the first-level cache of the second processor group, wherein the second-level cache of the first processor group is connected to the fast consistency interface of the first-level cache of the second processor group; the read first data is provided to the first processor group for processing through the second-level cache of the first processor group. However, this technical solution solves the problem of memory consistency between clusters of the ARM Cortex-A9 architecture.

[0006] In summary, the prior art has not solved the technical problem that frequent reading and writing of shared memory by multiple cores in a multi-core digital signal processor (DSP) of a surface-to-air missile weapon system will cause read and write competition of the L1DIWC register. Frequent competition for the L1DIWC register will cause the data to be in a protected state for a long time, thereby causing the data to be unable to be read, and increasing the waiting time for other cores to read and write the L1DIWC register. In severe cases, it will cause the program to stagnate. Summary of the invention

[0007] To solve the above technical problems, the present application provides a data update method based on serial number shared memory, which is applied to the scenario of multi-core digital signal processor shared memory for data processing;

[0008] The shared memory includes a first data packet and a second data packet; when the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the data in the first data packet is updated;

[0009] The data update in the package includes:

[0010] Define a core that rewrites the data of the first data packet as core 0, and define a core that only reads the data of the first data packet as core 1;

[0011] A separate update sequence number is defined for the core 0. After the core 0 updates data, the value of the update sequence number is automatically increased and written into the first data packet. A historical sequence number is defined for the core 1. The value of the historical sequence number of the core 1 is the historical value of the update sequence number of the core 0.

[0012] When the core 1 reads the data of the first data packet, it first reads the value of the updated sequence number written by the core 0 to the first data packet, and compares it with the value of the historical sequence number to determine whether the data of the first data packet is updated and whether it needs to be read again.

[0013] Furthermore, when the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the multi-core digital signal processor also updates the data in the second data packet, and the data in the packet update includes:

[0014] When performing data update on the second data packet, the core 0 is defined as a core that performs read and write operations on the data of the second data packet, and the core 1 is defined as a core that reads and writes the data of the second data packet.

[0015] Furthermore, when the second data packet updates the data in the packet, the data update in the packet also includes adding timeout protection to avoid program stagnation when multiple cores read and write shared memory.

[0016] Further, the specific method for determining whether the data of the first data packet is updated is:

[0017] When the comparison values ​​are the same, it means that the data of the first data packet has not been updated, and there is no need to read the data of the first data packet again;

[0018] When the comparison values ​​are different, it means that the data of the first data packet has been updated and the data of the first data packet needs to be read again.

[0019] Furthermore, after the core 0 updates the data, the value of the update sequence number is automatically increased by 1.

[0020] Furthermore, the timeout protection specifically includes the following contents:

[0021] Get the current system time T0, set the starting address and data length of the access data block, and determine whether the read and write status meets the conditions;

[0022] If the conditions are met, read and write the data;

[0023] If the conditions are not met, enter the loop waiting mode. Perform the following operations during the loop waiting mode:

[0024] Set a threshold for the timeout protection time, obtain the current time T1, and determine whether T1-T0 is greater than the threshold;

[0025] If the conditions for reading and writing data are still not met when T1-T0>threshold, the loop waiting is forced to jump out and the current read and write operation is abandoned to avoid program jams.

[0026] Further, after completing the re-reading of the data of the first data packet, the updated sequence number will be assigned to the historical sequence number to form a new historical sequence number.

[0027] Furthermore, after the data of the first data packet is rewritten and updated, other cores only perform a read operation through the shared memory without making any changes.

[0028] Furthermore, after the data of the second data packet is rewritten and updated, other cores perform a read operation through the shared memory, and write the new value back to the shared memory after the data calculation is completed.

[0029] The beneficial effects of the present invention are as follows: by setting an update sequence number for a core that rewrites a data packet in shared data, defining a historical sequence number for a core that only reads a specific data packet, and comparing whether the value of the update sequence number is equal to the value of the historical sequence number, it is determined whether the data in the shared memory is updated and whether it needs to be read again, thereby reducing the frequency of multiple cores reading and writing the same data in the shared memory, thereby reducing the number of "waiting" situations caused by high-frequency reading and writing of shared memory data, using different methods for data update and transmission for different types of shared memory data, and reducing the frequency of multiple cores reading and writing the same data packet at the same time; for data that needs to be read and written by multiple cores, timeout protection measures are further taken to avoid the value of the L1DIWC register from not meeting the conditions for a long time, resulting in data "locking", thereby causing the program to be unable to continue running due to "dead waiting", thereby improving the stability of program operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a flow chart of a data updating method based on a serial number shared memory provided according to an embodiment of the present invention;

[0031] Figure 2 It is a timeout protection flow chart provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0033] The embodiment of the present invention provides a data update method based on serial number shared memory. For shared data that only needs to be rewritten by a single core, a method for determining whether the serial number is updated is used for interaction to avoid rewriting of shared memory by multiple cores. For data packets that require multiple cores to read and write shared memory data, the reading and writing method further uses a method with added timeout protection measures for interaction to improve program robustness and solve the problem of generating read and write competition of L1DIWC registers when facing the characteristics of high frequency of multi-core data interaction, which increases the waiting time for other cores to read and write L1DIWC registers. The specific implementation method of the present invention is described in detail below in conjunction with the drawings of the specification.

[0034] An embodiment of the present invention provides a data update method based on serial number shared memory, which is applied to a scenario where a multi-core digital signal processor shares memory to process data;

[0035] The shared memory includes a first data packet and a second data packet; when the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the data in the first data packet is updated;

[0036] As attached Figure 1 As shown, the data update in the package includes:

[0037] Step S100, defining a core that rewrites the data of the first data packet as core 0, and defining a core that only reads the data of the first data packet as core 1;

[0038] Step S200, defining a separate update sequence number for the core 0, after the core 0 updates the data, the value of the update sequence number is automatically increased and written into the first data packet, defining a historical sequence number for the core 1, the value of the historical sequence number of the core 1 is the historical value of the update sequence number of the core 0; the update sequence number and the historical sequence number can be defined as 8 bits, 16 bits, or 32 bits according to the data update frequency;

[0039] Step S300, including steps S310-S340;

[0040] Step S310, when the core 1 reads the data of the first data packet;

[0041] Step S320, the core 1 first reads the value of the update sequence number written by the core 0 into the first data packet;

[0042] Step S330, the core 1 compares the read value of the update sequence number with the value of the historical sequence number;

[0043] Step S340, determining whether the data in the first data packet is updated and needs to be read again.

[0044] The data in the first data packet only requires a single core to perform frequent write operations, such as the first data packet: ReadOnlyData; the data in the second data packet requires multiple cores to perform frequent write operations repeatedly, such as ReadWriteData.

[0045] The data of the first data packet and the data of the second data packet are classified by the data in the shared memory according to the demand characteristics of the data used in the current application scenario, and are calculated and assigned according to the algorithm and control logic used in the current application scenario, and then put into the first data packet and the second data packet for unified management.

[0046] The first data packet and the second data packet are data structures or arrays.

[0047] In this embodiment, when the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the multi-core digital signal processor also updates the data in the second data packet, and the data in the packet update includes:

[0048] When performing data update on the second data packet, the core 0 is defined as a core that performs read and write operations on the data of the second data packet, and the core 1 is defined as a core that reads and writes the data of the second data packet.

[0049] In this embodiment, when the second data packet updates the data in the packet, the data update in the packet also includes adding timeout protection to avoid program stagnation when multiple cores read and write shared memory. The timeout protection is performed simultaneously with the data update in the packet.

[0050] The original underlying function reads and writes shared memory data in the following way: first, set the starting address and data length of the access data packet; then determine whether it is in the cache wait state. If it is in the cache wait state, it means that the operation on the data is not completed, and enter a loop waiting until the relevant operation is completed. If it is not in the cache wait state, the data can be accessed and operated.

[0051] Due to the high frequency of multi-core data interaction, the read and write competition of the L1DIWC register will occur, which will increase the waiting time of other cores to read and write the L1DIWC register. In the case of circular waiting, in order to avoid the program being in a circular waiting state for a long time, after determining the starting address and data length of the access data packet, a method of reading and writing shared memory data with timeout protection is added. The flowchart is shown in the attached figure. Figure 2 shown.

[0052] In this embodiment, the timeout protection specifically includes the following contents:

[0053] Get the current system time T0, set the starting address and data length of the access data block, and determine whether the read and write status meets the conditions;

[0054] If the conditions are met, read and write the data;

[0055] If the conditions are not met, enter the loop waiting mode. Perform the following operations during the loop waiting mode:

[0056] Set a threshold for the timeout protection time, obtain the current time T1, and determine whether T1-T0 is greater than the threshold;

[0057] If the conditions for reading and writing data are still not met when T1-T0>threshold, the loop waiting is forced to jump out and the current read and write operation is abandoned to avoid program jams.

[0058] The threshold of the timeout protection time is the specific time of the timeout protection, and its value is set according to the actual application scenario.

[0059] In this embodiment, in step S340, the specific method of determining whether the data of the first data packet is updated is:

[0060] When the comparison values ​​are the same, it means that the data of the first data packet has not been updated, and there is no need to read the data of the first data packet again, and the data reading operation of the core 1 on the first data packet ends;

[0061] When the comparison values ​​are different, it means that the data of the first data packet has been updated, and the data of the first data packet needs to be read again to complete the data reading operation of the core 1 on the first data packet.

[0062] In this embodiment, after the core 0 updates the data, the value of the update sequence number is automatically increased by 1.

[0063] In this embodiment, after completing step S340 to read the data of the first data packet again, the updated sequence number will be assigned to the historical sequence number to form a new historical sequence number.

[0064] In this embodiment, after the data of the first data packet is rewritten and updated, other cores only perform a read operation through the shared memory without making any changes.

[0065] In this embodiment, after the data of the second data packet is rewritten and updated, other cores perform a read operation through a shared memory, and write the new value back to the shared memory after the data calculation is completed.

[0066] The data update method adopted in this embodiment determines whether the data is the latest data and whether the data needs to be re-read by comparing the values ​​of the update sequence numbers and the values ​​of the historical sequence numbers of cores 0 and 1 to see if they are equal, thereby avoiding the operation of core 1 writing to the shared memory due to rewriting the update status word. The advantage of this embodiment is that the shared memory data is only rewritten by a single core, thereby avoiding the frequency of multiple cores rewriting shared memory data to compete for the use of the L1DIWC register, reducing the frequency of multiple cores reading and writing the same data in the shared memory, and thereby reducing the number of waiting situations caused by high-frequency reading and writing of shared memory data.

[0067] The above disclosure is only a specific embodiment of the present invention, but the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A data updating method based on serial number shared memory, characterized in that: Applicable to scenarios where multi-core digital signal processors share memory for data processing; The shared memory includes a first data packet and a second data packet; when the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the data in the first data packet is updated; The data update in the package includes: Define a core that rewrites the data of the first data packet as core 0, and define a core that only reads the data of the first data packet as core 1; A separate update sequence number is defined for the core 0. After the core 0 updates data, the value of the update sequence number is automatically increased and written into the first data packet. A historical sequence number is defined for the core 1. The value of the historical sequence number of the core 1 is the historical value of the update sequence number of the core 0. When the core 1 reads the data of the first data packet, it first reads the value of the updated sequence number written by the core 0 to the first data packet, and compares it with the value of the historical sequence number to determine whether the data of the first data packet is updated and whether it needs to be read again.

2. The data updating method based on serial number shared memory according to claim 1, characterized in that: When the multi-core digital signal processor is in a waiting state when reading and writing the shared memory, the multi-core digital signal processor also updates the data in the second data packet, and the data in the packet update includes: When performing data update on the second data packet, the core 0 is defined as a core that performs read and write operations on the data of the second data packet, and the core 1 is defined as a core that reads and writes the data of the second data packet.

3. The data updating method based on serial number shared memory as claimed in claim 2, characterized in that: When the second data packet updates the data in the packet, the data update in the packet also includes adding timeout protection to avoid program stagnation when multiple cores read and write shared memory.

4. The data updating method based on serial number shared memory according to claim 1, characterized in that: The specific method for determining whether the data of the first data packet is updated is: When the comparison values ​​are the same, it means that the data of the first data packet has not been updated, and there is no need to read the data of the first data packet again; When the comparison values ​​are different, it means that the data of the first data packet has been updated and the data of the first data packet needs to be read again.

5. The data updating method based on serial number shared memory according to claim 1, characterized in that: After the core 0 updates the data, the value of the update sequence number is automatically increased by 1.

6. The data updating method based on serial number shared memory as claimed in claim 3, characterized in that: The timeout protection specifically includes the following contents: Get the current system time T0, set the starting address and data length of the access data block, and determine whether the read and write status meets the conditions; If the conditions are met, read and write the data; If the conditions are not met, enter the loop waiting mode. Perform the following operations during the loop waiting mode: Set a threshold for the timeout protection time, obtain the current time T1, and determine whether T1-T0 is greater than the threshold; If the conditions for reading and writing data are still not met when T1-T0>threshold, the loop waiting is forced to jump out and the current read and write operation is abandoned to avoid program jams.

7. The data updating method based on serial number shared memory as claimed in claim 4, characterized in that: After completing the re-reading of the data of the first data packet, the updated sequence number will be assigned to the historical sequence number to form a new historical sequence number.

8. The data updating method based on serial number shared memory as claimed in claim 1, characterized in that: After the data of the first data packet is rewritten and updated, other cores only perform a read operation through the shared memory without making any changes.

9. The data updating method based on serial number shared memory as claimed in claim 1, characterized in that: After the data of the second data packet is rewritten and updated, other cores perform a read operation through the shared memory, and write the new value back to the shared memory after the data calculation is completed.

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