Multi-master multi-slave interconnection backplane bus of power control protection device, power control protection device and system

Abstract

The invention relates to a multi-master multi-slave interconnection backplane bus of a power control protection device, the power control protection device and a system. The multi-master multi-slave interconnection backboard bus is used for mounting a plurality of master board cards and a plurality of slave board cards; and a physical layer of the multi-master multi-slave interconnection backplane bus adopts an M-LVDS (Meter-Low Voltage Differential Signaling) level standard. By adopting the multi-master multi-slave interconnection backboard bus of the electric power control protection device, data interaction of each processor module in the electric power control protection device can be flexibly and efficiently realized.

Description

Technical Field

[0001] The present application relates to the technical field of power control and protection, and in particular to a multi-master and multi-slave interconnected backplane bus of a power control and protection device, a power control and protection device, and a power control and protection system. Background Art

[0002] The control and protection device is the core component of the power system control and protection system. The control and protection device consists of a processor module, an IO module, a communication module, and a special function module. In complex scenarios, multiple processor modules are required to operate in parallel. The backplane bus is the basis for realizing data interaction between modules in the control and protection device.

[0003] At present, the backplane buses used in control and protection devices include CAN bus, VME bus, PCIe bus, etc. Among the existing backplane bus technologies, CAN bus can realize the interconnection of multiple main processor modules and the flexible expansion of IO devices. CAN bus is simple but the CAN bus transmission rate is low; VME bus is suitable for multi-processor parallel computing and flexible expansion of each module, but it adopts 64 or 32-bit parallel bus mode, and the parallel bus connection is complicated; PCIe bus has a high rate and adopts a one-to-one serial bus mode. The connection is simple, but it is a point-to-point communication form and cannot realize the multi-main processor mode. With the increase in the amount of access data, the increase in the amount of calculation, and the increase in the number of board types, the existing backplane bus technology cannot take into account the effects of flexible configuration, high-speed data transmission, and simple hardware at the same time.

[0004] Therefore, there is a problem in the conventional technology that the backplane bus cannot flexibly and efficiently realize the data interaction among the modules in the control protection device. Summary of the invention

[0005] Based on this, it is necessary to provide a multi-master and multi-slave interconnected backplane bus, a power control protection device and a power control protection system for the power control protection device, which can flexibly and efficiently realize data interaction among the modules in the control protection device.

[0006] A multi-master and multi-slave interconnected backplane bus of an electric power control protection device, wherein the multi-master and multi-slave interconnected backplane bus is used to mount multiple main board cards and multiple slave board cards; the physical layer of the multi-master and multi-slave interconnected backplane bus adopts the M-LVDS level standard.

[0007] In one of the embodiments, the application layer of the multi-master and multi-slave interconnected backplane bus adopts a custom frame protocol; the frame format of the custom frame protocol includes a start bit, priority, slot number, destination address, frame type, frame length, data area and check code in sequence.

[0008] In one of the embodiments, the link layer of the multi-master and multi-slave interconnection backplane bus adopts 8b / 10b encoding.

[0009] In one of the embodiments, the physical layer of the multi-master and multi-slave interconnected backplane bus adopts an asynchronous serial communication mode.

[0010] In one of the embodiments, a plurality of access points are arranged on the multi-master and multi-slave interconnected backplane bus; the plurality of access points are used to connect the main board and the slave board to the multi-master and multi-slave interconnected backplane bus.

[0011] In one of the embodiments, the bus rate of the multi-master and multi-slave interconnected backplane bus is at least 200 Mbps.

[0012] A power control and protection device, comprising at least one main board card and at least N slave boards, wherein the main board card comprises a controller, and each of the slave boards is connected to the controller using a multi-master and multi-slave interconnected backplane bus as described above; wherein N is greater than or equal to 2.

[0013] In one embodiment, the power control and protection device further includes a central processing unit, and the at least one mainboard card is electrically connected to the central processing unit.

[0014] In one of the embodiments, each slave card is connected to the at least one main board card through a main board card data input signal line and a main board card data output signal line in the multi-master and multi-slave interconnection backplane bus; wherein the main board card data input signal line is represented as MOSI, and the main board card data output signal line is represented as MISO.

[0015] A power control and protection system includes: the power control and protection device as described above.

[0016] The multi-master and multi-slave interconnected backplane bus of the above-mentioned power control and protection device, the power control and protection device and the power control and protection system adopt a multi-master and multi-slave backplane bus structure, which reduces the number of backplane wirings, can use a pair of buses to mount all boards, and adopt the M-LVDS level standard in multi-point communication. M-LVDS can use a smaller voltage swing, which can increase the transmission speed and meet the longer transmission distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1A schematic diagram of a multi-master and multi-slave interconnected backplane bus of a power control and protection device in one embodiment;

[0019] Figure 2 A schematic diagram of a frame format of a custom frame protocol in one embodiment;

[0020] Figure 3 is a schematic diagram of a power control protection device in one embodiment;

[0021] Figure 4 A schematic diagram of a power control and protection system in one embodiment.

[0022] The reference numerals and their meanings are as follows:

[0023] 102, main board; 104, slave board; 106, multi-master and multi-slave interconnected backplane bus; 108, central processing unit; 310, power control protection device. DETAILED DESCRIPTION

[0024] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0026] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0027] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0028] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0029] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0030] In the existing backplane bus technology, the CAN (Controller Area Network) bus can realize the interconnection of multiple main processor modules and the flexible expansion of IO devices, but the CAN bus has a low transmission rate; the VME (Versa Module Eurocard) bus is suitable for multi-processor parallel computing and flexible expansion of each module, but the parallel bus connection is complicated; the PCIE (peripheral component interconnect express) bus has a high rate and simple connection, but it is a point-to-point communication form and cannot realize the multi-master processor mode. In order to solve the shortcomings of the existing backplane bus technology, the embodiment of the present application provides a multi-master and multi-slave interconnected backplane bus of a power control and protection device, which utilizes the characteristics of the M-LVDS topology structure and adopts M-LVDS in multi-point communication. M-LVDS adopts a smaller voltage swing, has a higher transmission speed and a longer transmission distance; adopts a custom frame format, can achieve multi-master and multi-slave flexible configuration, mount all boards on a pair of transmission buses, and realize multi-processor module parallel computing and flexible expansion of each module.

[0031] In an exemplary embodiment, Figure 1 As shown, a multi-master and multi-slave interconnected backplane bus of a power control protection device is provided, and the multi-master and multi-slave interconnected backplane bus is used to mount multiple main board cards and multiple slave board cards; the physical layer of the multi-master and multi-slave interconnected backplane bus adopts the M-LVDS level standard.

[0032] The device of the main board card has the control right over the multi-master and multi-slave interconnected backplane bus, and the device of the slave board card responds to the bus command sent from the device of the main board card.

[0033] Among them, M-LVDS (Multipoint low Voltage Differential Signaling) is multi-point low voltage differential signaling. The M-LVDS standard specifies the electrical characteristics of line drivers and receivers for general data transmission through multi-point buses. In practical applications, it is based on the topology of multi-master and multi-slave interconnected backplane buses, and it is determined that the M-LVDS level standard needs to be adopted, which can solve the noise resistance and integrity of signal transmission across boards and improve bandwidth.

[0034] The multi-master and multi-slave interconnected backplane bus of the above-mentioned power control and protection device adopts a multi-master and multi-slave backplane bus structure, which reduces the number of backplane wirings, can use a pair of buses to mount all boards, and adopts the M-LVDS level standard in multi-point communication. M-LVDS can use a smaller voltage swing, which can increase the transmission speed and meet the longer transmission distance.

[0035] In an exemplary embodiment, the application layer of the multi-master and multi-slave interconnected backplane bus adopts a custom frame protocol; the frame format of the custom frame protocol includes the start bit, priority, slot number, destination address, frame type, frame length, data area and check code in sequence.

[0036] The priority may refer to the priority of a board on the bus. When multiple boards initiate bus requests at the same time, it is necessary to determine to which board a bus response signal needs to be sent according to the priority of the board.

[0037] Figure 2 The frame format corresponding to the custom frame protocol is shown. The custom frame protocol can be set according to the actual application scenario. The traditional serial communication method is only based on a simple address mode, and is not based on the information of the custom frame protocol of this application for addressing. Only simple addressing operations can be performed. This application adopts a custom frame protocol, which can improve data transmission efficiency compared with the traditional technology based on a simple address mode.

[0038] In this embodiment, by adopting a pre-set custom frame format, including a start bit, priority, slot number, destination address, frame type, frame length, data area and check code, and setting information such as frame type and priority, a flexible configuration of multiple masters and multiple slaves can be achieved, and all boards can be mounted on a pair of transmission buses to realize parallel computing of multiple processor modules and flexible expansion of each processor module, thereby improving data transmission efficiency.

[0039] In an exemplary embodiment, the link layer of the multi-master and multi-slave interconnection backplane bus adopts 8b / 10b encoding.

[0040] Among them, 8b / 10b encoding is an encoding method used in high-speed serial communication. It divides 8-bit data into 5-bit and 3-bit parts, performs 5B / 6B and 3B / 4B encoding respectively, and finally encodes it into 10-bit bytes. This encoding maintains a balance between 0 and 1 to ensure reliable data transmission.

[0041] In this embodiment, DC level balance is achieved by using 8b / 10b encoding at the link layer of the multi-master and multi-slave interconnected backplane bus.

[0042] In an exemplary embodiment, the physical layer of the multi-master and multi-slave interconnection backplane bus adopts an asynchronous serial communication method.

[0043] The asynchronous serial communication mode transmits data in units of characters, and the interval between characters transmitted by the sender is not fixed. This communication mode has the characteristic of irregular data segment transmission, which allows the communicating parties to send data at different time intervals.

[0044] In practical applications, the multi-master and multi-slave interconnected backplane bus adopts asynchronous serial communication. Compared with the traditional VME bus, it is changed from a 64 or 32-bit parallel bus to an asynchronous serial bus, which reduces the number of backplane bus wiring and increases the speed from 48Mbps to 200Mbps.

[0045] In this embodiment, by adopting an asynchronous serial communication method at the physical layer of a multi-master and multi-slave interconnected backplane bus, compared with a traditional backplane bus, the number of backplane bus wiring is reduced and the data transmission rate is improved.

[0046] In an exemplary embodiment, a plurality of access points are provided on the multi-master and multi-slave interconnection backplane bus; the plurality of access points are used to connect the main board and the slave board to the multi-master and multi-slave interconnection backplane bus.

[0047] Among them, the access point corresponds to the slot SLOT, and each slot can be inserted with a board card.

[0048] In an exemplary embodiment, the bus rate of the multi-master and multi-slave interconnected backplane bus reaches at least 200 Mbps.

[0049] In actual applications, any motherboard card is used to determine whether the current conditions meet the conditions for initiating the target operation through the chassis common monitoring signal, and initiate the target operation when any motherboard card determines that the current conditions meet the conditions for initiating the target operation. Among them, the chassis common monitoring signal can refer to the chassis common CS signal. In a specific implementation, on the basis of the application layer using a custom frame protocol, in conjunction with the chassis common CS signal, multi-master application operations can be achieved. Specifically, the CS signal is pulled high or low to represent that there is data on the bus. The devices of other motherboard cards that want to initiate the operation monitor the CS signal, and initiate the operation when the conditions for initiating the operation are met. The transmission rate in the chassis can reach 200Mbps.

[0050] In this embodiment, on the basis of adopting a custom frame protocol at the application layer, in conjunction with a chassis common monitoring signal, multi-master application operation can be implemented to improve the transmission efficiency within the chassis.

[0051] In an exemplary embodiment, Figure 3 As shown, a power control protection device is provided, including at least one main board card and at least N slave boards, the main board card includes a controller, and each slave board is connected to the controller using the multi-master and multi-slave interconnected backplane bus as mentioned above; wherein N is greater than or equal to 2.

[0052] The multi-master and multi-slave interconnected backplane bus is used to mount multiple main board cards and multiple slave board cards, and the physical layer of the multi-master and multi-slave interconnected backplane bus adopts the M-LVDS level standard.

[0053] Among them, the application layer of the multi-master and multi-slave interconnected backplane bus adopts a custom frame protocol, and the frame format of the custom frame protocol includes a start bit, a priority, a slot number, a destination address, a frame type, a frame length, a data area and a check code in sequence.

[0054] Among them, the link layer of the multi-master and multi-slave interconnection backplane bus adopts 8b / 10b encoding.

[0055] Among them, the physical layer of the multi-master and multi-slave interconnected backplane bus adopts an asynchronous serial communication method.

[0056] Among them, a plurality of access points are arranged on the multi-master and multi-slave interconnection backplane bus, and the plurality of access points are used to connect the main board and the slave board to the multi-master and multi-slave interconnection backplane bus, specifically, Figure 3 As shown, the access point may correspond to the slot SLOT0 and the slots SLOT1, SLOT2, SLOT3, ..., SLOTn.

[0057] The bus rate of the multi-master and multi-slave interconnection backplane bus is at least 200Mbps.

[0058] The above-mentioned power control and protection device adopts a multi-master and multi-slave interconnected backplane bus to connect at least one main board card and at least N slave boards, reducing the number of backplane wirings, and can use a pair of buses to mount all boards. The M-LVDS level standard is adopted in multi-point communication. M-LVDS can use a smaller voltage swing, which can increase the transmission speed and meet the longer transmission distance. It also adopts a custom frame format and can realize multi-master and multi-slave flexible configuration. All boards of the power control and protection device are mounted on a pair of transmission buses, realizing parallel calculation of multiple processor modules of the power control and protection device and flexible expansion of each processor module, further improving the data transmission efficiency of the power control and protection device.

[0059] In an exemplary embodiment, the power control and protection device further includes a central processing unit, and at least one mainboard card is electrically connected to the central processing unit.

[0060] Among them, the central processing unit can refer to Figure 3 The CPU is connected to the motherboard card, and the motherboard card is connected to the CPU by inserting it into the slot SLOT0.

[0061] In an exemplary embodiment, each slave card is connected to at least one main board card by a main board card data input signal line and a main board card data output signal line in a multi-master and multi-slave interconnection backplane bus; wherein the main board card data input signal line is represented as MOSI, and the main board card data output signal line is represented as MISO.

[0062] like Figure 3 As shown, the main board card data input signal line of the power control protection device is the MISO signal line, and the main board card data output signal line of the power control protection device is the MOSI signal line, wherein MISO_P and MISO_N correspond to the differential signal pair of the MISO signal line, and MOSI_P and MOSI_N correspond to the differential signal pair of the MOSI signal line. Figure 3 CLK indicates the clock source from the board, CS indicates the monitoring signal, and SLOT indicates the slot.

[0063] In an exemplary embodiment, Figure 4 As shown, a power control protection system is provided, the power control protection system includes Figure 3 The power control protection device shown in the figure comprises at least one main board card and at least N slave boards, wherein the main board card comprises a controller, and each of the slave boards is connected to the controller using the multi-master and multi-slave interconnection backplane bus as described above; wherein N is greater than or equal to 2.

[0064] Wherein, the power control and protection device of the power control and protection system further includes a central processing unit, and the at least one mainboard card is electrically connected to the central processing unit.

[0065] Among them, each slave board in the power control and protection device of the power control and protection system is connected to the at least one main board through the main board card data input signal line and the main board card data output signal line in the multi-master and multi-slave interconnection backplane bus, and the main board card data input signal line is represented as MOSI, and the main board card data output signal line is represented as MISO.

[0066] The multi-master and multi-slave interconnected backplane bus is used to mount multiple main board cards and multiple slave board cards, and the physical layer of the multi-master and multi-slave interconnected backplane bus adopts the M-LVDS level standard.

[0067] Among them, the application layer of the multi-master and multi-slave interconnected backplane bus adopts a custom frame protocol, and the frame format of the custom frame protocol includes a start bit, a priority, a slot number, a destination address, a frame type, a frame length, a data area and a check code in sequence.

[0068] Among them, the link layer of the multi-master and multi-slave interconnection backplane bus adopts 8b / 10b encoding.

[0069] Among them, the physical layer of the multi-master and multi-slave interconnected backplane bus adopts an asynchronous serial communication method.

[0070] Among them, a plurality of access points are arranged on the multi-master and multi-slave interconnection backplane bus, and the plurality of access points are used to connect the main board and the slave board to the multi-master and multi-slave interconnection backplane bus, specifically, Figure 3 As shown, the access point may correspond to the slot SLOT0 and the slots SLOT1, SLOT2, SLOT3, ..., SLOTn.

[0071] The bus rate of the multi-master and multi-slave interconnection backplane bus is at least 200Mbps.

[0072] The above-mentioned power control and protection system adopts a power control and protection device, in which a multi-master and multi-slave interconnected backplane bus connects at least one main board card and at least N slave boards, reducing the number of backplane wirings, and can use a pair of buses to mount all boards. In addition, the M-LVDS level standard is adopted in multi-point communication. M-LVDS can use a smaller voltage swing, which can increase the transmission speed and meet the longer transmission distance. It also adopts a custom frame format, which can realize multi-master and multi-slave flexible configuration, and mount all boards of the power control and protection device on a pair of transmission buses, realizing parallel calculation of multiple processor modules of the power control and protection device and flexible expansion of each processor module, further improving the data transmission efficiency of the power control and protection system.

[0073] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0074] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A multi-master and multi-slave interconnected backplane bus of a power control and protection device, characterized in that: The multi-master and multi-slave interconnected backplane bus is used to mount multiple main board cards and multiple slave board cards; The physical layer of the multi-master and multi-slave interconnection backplane bus adopts the M-LVDS level standard.

2. The multi-master and multi-slave interconnected backplane bus according to claim 1, characterized in that: The application layer of the multi-master and multi-slave interconnected backplane bus adopts a custom frame protocol; the frame format of the custom frame protocol includes a start bit, priority, slot number, destination address, frame type, frame length, data area and check code in sequence.

3. The multi-master and multi-slave interconnected backplane bus according to claim 1, characterized in that: The link layer of the multi-master and multi-slave interconnection backplane bus adopts 8b / 10b encoding.

4. The multi-master and multi-slave interconnected backplane bus according to claim 1, characterized in that: The physical layer of the multi-master and multi-slave interconnection backplane bus adopts an asynchronous serial communication mode.

5. The multi-master and multi-slave interconnected backplane bus according to claim 1, characterized in that: The multi-master and multi-slave interconnection backplane bus is provided with a plurality of access points; the plurality of access points are used to connect the main board and the slave board to the multi-master and multi-slave interconnection backplane bus.

6. The multi-master and multi-slave interconnected backplane bus according to claim 1, characterized in that: The bus rate of the multi-master and multi-slave interconnected backplane bus is at least 200 Mbps.

7. A power control and protection device, characterized in that: The power control and protection device includes at least one main board card and at least N slave boards, the main board card includes a controller, and each of the slave boards is connected to the controller using a multi-master and multi-slave interconnected backplane bus as described in claims 1 to 6; wherein N is greater than or equal to 2.

8. The power control and protection device according to claim 7, characterized in that: The power control and protection device further comprises a central processing unit, and the at least one mainboard card is electrically connected to the central processing unit.

9. The power control and protection device according to claim 7, characterized in that: Each slave card is connected to at least one main board card via a main board card data input signal line and a main board card data output signal line in the multi-master and multi-slave interconnected backplane bus; wherein the main board card data input signal line is represented as MOSI, and the main board card data output signal line is represented as MISO.

10. A power control and protection system, characterized in that: include: A power control and protection device as claimed in any one of claims 7 to 9.

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