Layout method for reconfigurable in-memory computing accelerators for multiple core particles

Abstract

The embodiment of the invention provides a layout method for a reconfigurable in-memory computing accelerator for multiple core particles. The layout method comprises the steps that accelerator parameters related to layout and application parameters of an application program are obtained; according to the accelerator parameters and the application parameters, operators in the application program are converted into functions supported by the accelerator, and all the functions needed by the application program and the number of the functions are obtained; simulating to independently configure each function on a single core particle of the accelerator to obtain an initial layout; a preset optimization mode is executed for multiple times to iteratively optimize the layout, a layout result is obtained, coarse-grained optimization operation is executed, the coarse-grained optimization operation comprises the steps that iterative optimization is conducted on the input layout through a simulated annealing algorithm, a disturbance mode during optimization is random exchange of functions configured on two core particles, and the optimization result is obtained; the optimization function is the total data transmission overhead among the core particles calculated based on the layout; and executing function integration operation: trying to perform function integration on the layout optimized by the coarseness optimization operation based on the accelerator parameters.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, in particular to the field of in-memory computing, and more particularly to a layout method for a reconfigurable in-memory computing accelerator for multiple cores. Background Art

[0002] In-memory computing is considered an effective way to alleviate the memory wall problem. In-memory computing accelerators use non-volatile or volatile memory arrays to complete in-memory in-situ multiplication and addition calculations, thereby accelerating matrix-vector multiplication.

[0003] In current research, a reconfigurable in-memory computing accelerator (also called a reconfigurable in-memory computing accelerator) has been proposed. Using an FPGA-like reconfiguration method, with the assistance of supporting multi-function peripheral circuits, the current reconfigurable in-memory computing accelerator can be configured to complete the acceleration of different functions, thereby achieving acceleration in different application scenarios.

[0004] When the tasks corresponding to the application need to be accelerated, the functions need to be arranged and reconfigured on the reconfigurable in-memory computing accelerator. However, the current reconfigurable in-memory computing accelerators often consider configuring all functions for the application in a single chip first, unless the resources of a single chip are not enough to meet the needs of the tasks corresponding to the application, and then arrange the functions in other chips.

[0005] With the development of deep neural network technology, the scale of models tends to increase gradually, and the resources required by related applications are getting larger and larger. The resources of a single chip (or core particle) are difficult to meet their computing needs. When the application has a large amount of tasks, if the method of performing fine-grained functional layout one by one in a single chip is adopted, the layout process will be computationally redundant, thus affecting the layout speed.

[0006] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0007] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide a layout method for a reconfigurable in-memory computing accelerator for multiple chips.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, a layout method for a reconfigurable in-memory computing accelerator is provided, the accelerator comprising a plurality of core particles, each core particle being configurable to a plurality of functions, the method comprising: obtaining accelerator parameters and application parameters of an application program related to the layout; converting operators in the application program into functions supported by the accelerator according to the accelerator parameters and the application parameters, and obtaining the functions and their quantities required by the application program; simulating the independent configuration of each function onto a single core particle of the accelerator according to the functions and their quantities required by the application program, and obtaining an initial layout; performing a preset optimization method multiple times based on the initial layout to iteratively optimize the layout, and obtaining a layout result, the preset optimization method comprising: performing a coarse-grained optimization operation, comprising: iteratively optimizing the input layout using a simulated annealing algorithm, wherein the perturbation method during the optimization is to randomly exchange the functions configured on two of the core particles, and the optimization function is the total data transmission overhead between the core particles calculated based on the layout; performing a function integration operation, comprising: attempting to perform function integration on the layout optimized by the coarse-grained optimization operation based on the accelerator parameters, so as to merge the functions configured on one core particle into another core particle with remaining resources. This solution can at least achieve the following beneficial technical effects: compared with the existing solution of directly performing fine-grained layout on a single chip, the method of the present invention can first quickly complete the accelerator function layout with a coarser granularity and reduce the total amount of data transmission between chiplets; then, function integration is performed to integrate as many functions as possible onto chiplets with surplus resources to reduce resource waste; thereby, the layout process can be better accelerated.

[0010] Optionally, a coarse-grained optimization operation is performed, including: randomly exchanging the functions configured on the two core particles in the current layout; if the data transmission overhead corresponding to the exchanged layout is smaller, the exchanged layout is used as the latest layout, otherwise, the exchanged layout is accepted as the latest layout based on the probability calculated in the simulated annealing algorithm based on the current temperature; after each layout update, it is determined whether the cooling condition is met, and if so, the next coarse-grained optimization operation is performed after cooling in the preset manner of the simulated annealing algorithm, otherwise the next coarse-grained optimization operation is performed or jumped to the function integration operation according to the preset requirements. This technical solution can at least achieve the following beneficial technical effects: by performing coarse-grained optimization operations through the simulated annealing algorithm, a layout method that reduces data transmission overhead can be found more quickly in the early stage.

[0011] Optionally, the preset requirement includes: judging whether the current cumulative number of iterations reaches a preset number threshold, if so, jumping to the function integration operation and resetting the cumulative number of iterations to an initial value, otherwise performing the next coarse-grained optimization operation. The technical solution can at least achieve the following beneficial technical effects: the present invention performs a certain number of layout iterative optimizations and then performs a function integration operation, which can reduce resource waste.

[0012] Optionally, when performing a function integration operation, a simulated annealing algorithm is used to update the layout, wherein the perturbation method during the function integration operation is to merge the functions configured on one core particle into another core particle with remaining resources, and the optimization function is the total data transmission overhead between the core particles calculated based on the layout. This technical solution can at least achieve the following beneficial technical effects: This solution also uses a simulated annealing algorithm when performing function integration, which can reduce the possibility of poor layouts being accepted and better obtain the global optimal solution.

[0013] Optionally, the initial layout is obtained by: determining the initial number of core particles N according to the functions and their quantities required by the application; simulating the initial configuration of all functions required by the application on the N core particles to obtain the initial layout, wherein the core particles of the initial layout are connected in a grid structure. This solution can at least achieve the following beneficial technical effects: In this solution, the connection between the core particles of the initial layout is a grid structure, which can better estimate the total amount of data transmission between the core particles, reduce the search space, and reduce the difficulty of layout.

[0014] Optionally, the accelerator parameters include the storage resource capacity parameters and performance parameters of each core particle, and the application parameters include the performance requirements of the operator; when performing the function integration operation, the remaining resources of each core particle are determined according to the storage resource capacity parameters of each core particle and the deployed functions, and based on the performance parameters of the core particles, the functions deployed on a core particle are randomly merged to another core particle that can meet the performance requirements and resource requirements of its corresponding operator. This technical solution can at least achieve the following beneficial technical effects: This solution considers the matching of resource requirements and performance requirements at the same time when merging, so that the final layout can better meet the requirements of each operator and improve the performance of accelerating the application.

[0015] According to a second aspect of the present invention, there is provided a reconfigurable in-memory computing accelerator, comprising a plurality of core particles, the accelerator being configured to: obtain an application to be accelerated, and obtain a layout result corresponding to the application according to the method of the first aspect; and reconstruct the structure of the accelerator using the layout result, so as to process the tasks of the application to be accelerated based on the reconstructed structure.

[0016] According to a third aspect of the present invention, there is provided a computer program product, comprising a computer program / instruction, which implements the steps of the method described in the first aspect when executed by a processor.

[0017] According to a fourth aspect of the present invention, there is provided an electronic device comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method described in the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of the module structure of a core particle in an accelerator according to an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a flow chart of a layout method for a reconfigurable in-memory computing accelerator according to an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of a layout result after layout is performed according to the method of an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] As mentioned in the background technology section, when the application has a large amount of tasks, if a fine-grained functional layout is performed one by one in a single chip, it will lead to computational redundancy in the layout process, thereby affecting the layout speed. In this regard, the method of the present invention can first quickly complete the accelerator function layout with a coarser granularity and reduce the total amount of data transmission between core particles; then, the function integration is performed to integrate some functions into core particles with surplus resources as much as possible to reduce resource waste; thereby, the layout process can be better accelerated.

[0024] The method of the present invention is used for a reconfigurable in-memory computing accelerator and is used for functionally arranging reconfigurable components in the accelerator according to application requirements.

[0025] To facilitate understanding, the structure of the reconfigurable in-memory computing accelerator is first schematically illustrated.

[0026] According to one embodiment of the present invention, the reconfigurable in-memory computing accelerator includes a plurality of core particles, each of which can be configured to support multiple functions. Figure 1 The core particle includes one or more reconfigurable storage and computing arrays and peripheral circuit modules of the same size.

[0027] The devices used in the reconfigurable storage and computing array can be volatile memory devices, such as static random access memory (SRAM), etc., or non-volatile memory devices, such as resistive random access memory (ReRAM), etc. Schematically, the reconfigurable storage and computing array in each chip can be reconfigured and support multiple functions with the assistance of peripheral circuit modules.

[0028] The peripheral circuit module includes data input driver, register, digital-to-analog converter DAC (Digital-to-analog converter, referred to as DAC), sample and hold circuit (Sample and hold, referred to as S&H), analog-to-digital converter ADC (Analog-to-digital converter, referred to as ADC), shift accumulation circuit and other digital modules or their combination. The peripheral circuit module is shared by multiple reconfigurable storage and computing arrays and assists the reconfigurable storage and computing arrays to complete the above functions. Among them, the data input driver is used to input data into the in-memory computing array; the register is used to cache input and output data; the DAC is used to convert the digital signal of the input data into an analog signal for input into the in-memory computing array; the sample and hold circuit is used to hold the analog signal output result of the in-memory computing array to wait for ADC conversion; the ADC is used to convert the analog output signal of the in-memory computing array into a digital signal; the ADC can be a shared ADC, which can be shared between multiple in-memory computing arrays, or shared between multiple columns of an in-memory computing array; the shift accumulation circuit is used to shift and accumulate the intermediate results of the digital signal after array calculation conversion. Other digital modules are used to meet the user's needs to implement other functions in the digital domain, such as: sensitive amplifier ( Figure 1 (not shown) is used to convert and read the output signal of the in-memory computing array.

[0029] According to one embodiment of the present invention, see Figure 2 , a layout method for a reconfigurable in-memory computing accelerator is provided, the method comprising: S1, S2, S3, S4. In order to better understand the present invention, each step is described in detail below in conjunction with a specific embodiment.

[0030] Step S1: Acquire accelerator parameters related to the layout and application parameters of the application program.

[0031] According to one embodiment of the present invention, the accelerator parameters include the function types supported by each core particle, the operator-function mapping table, and the storage and computing resource parameters within a single core particle. The operator-function mapping table contains the correspondence between each supported operator and the corresponding function. The in-memory computing array of each core particle can be configured to support multiple functions. Optionally, the multiple functions may include multiplication and addition calculations, content search and logical operations or combinations thereof. It should be understood that these functions are only for illustration, and the functions supported by the core particles may be defined by the manufacturer of the accelerator and may change with technological development or user needs. For example, the multiple functions may include storage functions, matrix-vector multiplication, Boolean logic, vector addition, vector subtraction, vector division and data search functions or combinations thereof. The storage and computing resource parameters include: the number of storage and computing arrays, the size of the storage and computing arrays, the precision of the device used and / or the maximum performance supported by the peripheral circuit module. The application parameters include the types of operators contained in the application and the amount of data for each operator. The array size, the number of arrays, the type of device used by the array, the device precision and the maximum performance supported by the peripheral circuit module can be freely specified according to actual conditions.

[0032] Step S2: According to the accelerator parameters and the application parameters, the operators in the application are converted into functions supported by the accelerator to obtain the functions and their quantities required by the application.

[0033] According to an embodiment of the present invention, the operator type is determined according to the application parameters, the operator-function mapping table pre-set in the accelerator parameters is queried, and each operator is converted into a function supported by the accelerator. For example: assuming that there are 20 operators (operators 1-20) and their corresponding functions (functions one to twenty) in the operator-function mapping table, and the application contains 3 operators, namely operator 1 (11), operator 2 (4), and operator 3 (4), then after conversion, the application needs function one (11), function two (4), and function three (4).

[0034] Step S3: According to the functions and their quantity required by the application, simulate configuring each function independently onto a single core of the accelerator to obtain an initial layout.

[0035] According to one embodiment of the present invention, the number of each function is added together to obtain the sum of the numbers (assuming it is N). Then the N functions can be configured on the N core particles of the accelerator, and the initial connection between the N core particles is constructed to obtain the initial layout. In order to simplify the layout, the N core particles are interconnected in a grid manner. For example, a 2D Mesh grid method is used as an example, in which each core particle is connected to the adjacent core particles horizontally and vertically, and data is transmitted between the core particles through the grid connection. Of course, a 3D Mesh grid method or other connection methods can also be used.

[0036] Step S4: Based on the initial layout, perform a preset optimization method multiple times to iteratively optimize the layout to obtain a layout result, wherein the preset optimization method includes: performing a coarse-grained optimization operation, which includes: using a simulated annealing algorithm to iteratively optimize the input layout, wherein the perturbation method during the optimization is to randomly exchange the functions configured on two of the core particles, and the optimization function is the total data transmission overhead between the core particles calculated based on the layout; performing a function integration operation, which includes: attempting to perform function integration on the layout optimized by the coarse-grained optimization operation based on accelerator parameters, so as to merge the functions configured on one core particle into another core particle with remaining resources.

[0037] According to an optional embodiment of the present invention, in step S4, the layout is optimized according to the following preset optimization method:

[0038] 1. S41, executing a coarse-grained optimization operation, which includes: randomly exchanging the functions configured on two core particles in the current layout; if the data transmission overhead corresponding to the exchanged layout is smaller, the exchanged layout is used as the latest layout, otherwise, the exchanged layout is accepted as the latest layout based on the probability calculated in the simulated annealing algorithm based on the current temperature; after each layout update, it is determined whether the cooling condition is met, if so, the next coarse-grained optimization operation is performed after cooling in a preset manner of the simulated annealing algorithm, otherwise, the next coarse-grained optimization operation is performed according to the preset requirements or the function integration operation is jumped to, wherein the preset requirements include: determining whether the current cumulative number of iterations reaches a preset number threshold, if so, jumping to the function integration operation and resetting the cumulative number of iterations to the initial value, otherwise, the next coarse-grained optimization operation is performed;

[0039] S42, performing a function integration operation, which includes: attempting to perform function integration on the layout optimized by the coarse-grained optimization operation based on the accelerator parameters, so as to merge the functions configured on one chiplet into another chiplet with remaining resources, and returning to S41 until a termination condition is reached.

[0040] Optionally, in step S41, for example, the total number of iterations (for example, A times) of the processing degree optimization operation and the number of jumps to the function integration operation (for example, Z times) are set in each cycle. A total of A coarse-grained optimization operations are performed in one cycle, and then the temperature is lowered for the iteration of the next cycle. In this embodiment, the function integration operation may not use the simulated annealing algorithm. For example, only after each Z coarse-grained optimization operation is performed, it will jump to the execution of the function integration operation, and then return to the coarse-grained optimization operation.

[0041] Optionally, when performing the function integration operation, a pair of core particles that can be functionally integrated can be randomly selected, and the function on one core particle can be integrated into the other core particle. Alternatively, according to the principle of proximity, the nearest neighbor core particle pair that can be integrated is prioritized; if there are multiple pairs of nearest neighbor core particles that can be integrated with the same distance, a pair of core particles is selected from them in coding order or randomly for integration. For example: prioritize whether the one-hop neighbor of each core particle can be integrated into the current core particle. If so, record the core particle pair formed by the relevant core particles; if not, check whether the two-hop neighbor of each core particle can be integrated into the current core particle..., and so on. Since the data transmission overhead between core particles under the current layout is relatively good after the coarse-grained optimization operation, the priority integration of the nearest neighbor core particle pairs that can be integrated can minimize the impact of function integration on the original layout and data transmission relationship, so as to complete the layout process faster and better.

[0042] When integrating functions, it is necessary to consider whether the storage space size of the core particle meets the needs of the integrated functions (i.e., whether the resource requirements are met). The storage space size of the core particle can be obtained by multiplying the number of arrays, size, and memory precision. The data volume of the operator is recorded in the application parameters. Therefore, before integrating functions, it is necessary to meet the requirement that the sum of the data volume of the operators corresponding to the integrated functions is less than or equal to the storage space size of the core particle.

[0043] In addition, when integrating functions based on accelerator parameters, in addition to considering whether the storage space size of the core particles meets the needs of the integrated functions, it is also necessary to consider whether the performance requirements of the operators can be met. That is, before the functional integration, for a pair of core particles, if the storage space size meets the conditions, it is also necessary to consider whether the highest performance supported by a single core particle can support the performance requirements of the operators corresponding to all the merged functions. If so, it indicates that the pair of core particles can be functionally integrated; otherwise, the pair of core particles cannot be functionally integrated.

[0044] According to another optional embodiment of the present invention, in step S4, the layout is optimized according to the following preset optimization method: before executing the preset number of function integration operations, the coarse-grained optimization operation and the function integration operation are performed alternately; after executing the preset number of function integration operations, the function integration operation is performed using the simulated annealing algorithm, wherein the perturbation method during the function integration operation is to merge the functions configured on one core particle into another core particle with remaining resources, and the optimization function is the total data transmission overhead between each core particle calculated based on the layout. In this embodiment, a function integration operation is performed once after each coarse-grained optimization operation is performed in the early stage, and a simulated annealing algorithm is also introduced in the function integration operation after the preset number of function integration operations are performed, which can facilitate the integration of some functions into a certain core particle more quickly in the early stage, and reduce the number of function integration operations after most of the functions are integrated in the later stage, so as to focus more on optimizing the layout and improve the structural performance corresponding to the final layout.

[0045] According to an example of the present invention, assume that an application contains three functions, namely function 1 (11), function 2 (4) and function 3 (4), and the grid structure is a 2D mesh. After layout, a schematic layout is obtained as shown below: Figure 3 As shown, each rectangle represents a core particle, and the lines between rectangles represent the connection relationship. Different core particles are connected in a grid topology, and the network-on-interposer can be used to transmit data between each other. The data to be transmitted are the intermediate results of neural network reasoning calculations and the intermediate results of other functions. Data is read from the register of one core particle and transmitted to the register of another core particle via the network to carry out the next step of calculation.

[0046] In general, when the inventors conducted research on the layout of reconfigurable in-memory computing accelerators, they found that the poor scalability and redundant layout process in the prior art were caused by only considering fine-grained functional layout within a single chip. After research, the inventors found that this defect can be solved by using a multi-chip integrated functional layout method. First, a simulated annealing algorithm is used to layout functions from a coarser granularity, a single chip is configured as a single function, and then fine-grained functional layout (functional integration) is performed within the chip according to demand, thereby achieving the expansion of the reconfigurable accelerator and accelerating the layout process.

[0047] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0048] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0049] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but are not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0050] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A layout method for a reconfigurable in-memory computing accelerator, the accelerator comprising a plurality of core particles, each core particle being configurable to have a plurality of functions, the method comprising: Get the accelerator parameters related to the layout and the application parameters of the application; According to the accelerator parameters and application parameters, the operators in the application are converted into functions supported by the accelerator to obtain the functions and their quantities required by the application. According to the functions and their quantity required by the application, simulate configuring each function independently on a single core of the accelerator to obtain an initial layout; Based on the initial layout, the preset optimization method is executed multiple times to iteratively optimize the layout to obtain the layout result. The preset optimization methods include: Performing coarse-grained optimization operations, including: iteratively optimizing the input layout using a simulated annealing algorithm, the perturbation method during optimization is to randomly exchange the functions configured on two of the core particles, and the optimization function is the total data transmission overhead between the core particles calculated based on the layout; The function integration operation is performed, which includes: attempting to perform function integration on the layout optimized by the coarse-grained optimization operation based on the accelerator parameters, so as to merge the functions configured on one chiplet into another chiplet with remaining resources.

2. The method according to claim 1, characterized in that Performs coarse-grained optimization operations, including: Randomly swap the functions configured on two core particles in the current layout; If the data transmission overhead corresponding to the swapped layout is smaller, the swapped layout is used as the latest layout; otherwise, the swapped layout is accepted as the latest layout based on the probability calculated in the simulated annealing algorithm based on the current temperature; After each layout update, it is determined whether the cooling condition is met. If so, the next coarse-grained optimization operation is performed after cooling according to the preset method of the simulated annealing algorithm. Otherwise, the next coarse-grained optimization operation is performed or the function integration operation is jumped to according to the preset requirements.

3. The method according to claim 2, characterized in that The preset requirements include: Determine whether the current cumulative number of iterations reaches the preset number threshold. If so, jump to the function integration operation and reset the cumulative number of iterations to the initial value. Otherwise, perform the next coarse-grained optimization operation.

4. The method according to claim 3, characterized in that When performing the function integration operation, the simulated annealing algorithm is used to update the layout. The perturbation method during the function integration operation is to merge the functions configured on one core particle into another core particle with remaining resources. The optimization function is the total data transmission overhead between each core particle calculated based on the layout.

5. The method according to any one of claims 1 to 4, characterized in that: The initial layout is obtained by: Determine the initial number of core particles N based on the functions and their quantity required by the application; The simulation initializes all functions required for configuring the application on N core particles to obtain an initial layout, wherein the core particles in the initial layout are connected in a grid structure.

6. The method according to any one of claims 1 to 4, characterized in that: Accelerator parameters include storage resource capacity parameters and performance parameters of each core particle, and application parameters include the performance requirements of operators; When executing the function integration operation, the remaining resources of each core particle are determined according to the storage resource capacity parameters of each core particle and the deployed functions, and based on the performance parameters of the core particles, the functions deployed on one core particle are randomly merged to another core particle that can meet the performance requirements and resource requirements of its corresponding operator.

7. A reconfigurable in-memory computing accelerator, comprising a plurality of core particles, characterized in that: The accelerator is configured as: Obtaining an application to be accelerated, and obtaining a layout result corresponding to the application according to a method of any one of claims 1 to 6; The structure of the accelerator is reconstructed using the layout result, so as to process the tasks of the application program to be accelerated based on the reconstructed structure.

8. A computer program product, comprising a computer program / instruction, which implements the steps of the method according to any one of claims 1 to 6 when executed by a processor.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 6.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-6 by executing the executable instructions.

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