A macro-based multi-mode circuit design method, device, and medium

Abstract

The application discloses a kind of based on macro multi-mode circuit design method, equipment and medium, belong to electronic design automation EDA design technical field, including, set working mode and configure the relationship between mode and macro;RTL code is carried out syntax lexical analysis, module, signal, parameter, macro in code are abstracted and converted into class, data structure, the relationship between modules is constructed, new data relationship model is formed, and each object is marked macro;Copy between mode, dispersion, merging operation is carried out;New data relationship model is generated after operation, and new RTL code is constructed according to order;Check circuit connectivity;According to the latest data model, output contains the RTL code of multiple modes.The design method of the application supports the multi-mode circuit design based on macro, mode includes the combination of multiple macros, copy, dispersion, merging operation can be carried out between mode, connectivity can be checked based on the circuit between mode, improve the efficiency and quality of chip design.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) design, and more particularly to a macro-based multi-mode circuit design method, device, and medium. Background Technology

[0002] The final product of a chip design is predetermined, including ASIC (Application-Specific Integrated Circuit) chips, FPGA (Programmable Array of Programmable Array) chips, and DUT (Device Under Test) chips. Currently, most chip design companies use FPGA prototyping to verify whether the design meets expectations. Both FPGA and ASIC front-end code are developed based on Verilog, so theoretically, ASIC code can run on the FPGA platform; this method is widely used. Therefore, design companies typically have ASIC engineers and FPGA engineers, each developing different circuits. Complex chips may be developed by teams of hundreds of people. Managing two sets of code increases collaboration costs and reduces design efficiency. Furthermore, achieving code reusability across different chip designs is difficult, and there is no good way to check whether a chip design meets connectivity requirements. In practical scenarios, only a portion of the code from ASIC and FPGA circuits can be reused. Currently, managing multiple sets of code manually is the primary method, resulting in low design efficiency and high management costs. Therefore, to address the shortcomings of existing technologies, there is an urgent need to provide a method for implementing multi-mode circuit design. Summary of the Invention

[0003] This invention aims to provide a macro-based multi-mode circuit design method to coordinate the design of circuits such as ASICs and FPGAs, thereby improving design efficiency and quality.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows:

[0005] A macro-based multi-mode circuit design method includes: Step S1, setting the working mode of a chip project and configuring the relationship between the working mode and macros, wherein a single working mode includes a combination of one or more macros, and the working mode includes a common mode, an ASIC mode, and an FPGA mode; Step S2, performing syntax and lexical analysis on the corresponding RTL code in the working mode, abstracting the modules, signals, parameters, and macros in the RTL code into classes and data structures in the high-level language C++, and abstracting the operations of creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters. To establish methods for operating and processing classes and data structures, and to build relationships between modules, a data relationship model is formed, and each object is marked with a macro; Step S3: Based on the data relationship model, copy, scatter, and merge operations are performed between the working modes; Step S4: The scatter and copy operations in Step S3 are repeatedly performed until the circuit design is completed, and a new data relationship model is generated after the operation; Step S5: Based on the new data relationship model, the circuit connectivity of all working modes is checked to ensure it is correct; Step S6: After the circuit connectivity check is passed, RTL code containing multiple working modes is output according to the new data relationship model, and the syntax of the output RTL code is checked to ensure it conforms to the syntax.

[0006] In a preferred embodiment of the present invention, the circuit in the common mode is visible and operable in both the ASIC mode and the FPGA mode, while the circuits in the ASIC mode and the FPGA mode are not visible to each other.

[0007] In a preferred embodiment of the present invention, circuits in ASIC mode and FPGA mode can be copied to each other, and circuits in the common mode can be distributed to designated ASIC mode and FPGA mode. After distribution, the circuits are marked with macros corresponding to the mode. Identical circuits in ASIC mode and FPGA mode can be merged into the common mode.

[0008] In a preferred embodiment of the present invention, the working mode further includes a DUT mode. The circuits in the ASIC mode, FPGA mode, and DUT mode can be copied to each other. The circuits in the common mode can be distributed to the specified ASIC mode, FPGA mode, and DUT mode. After distribution, the circuits are marked with the macros corresponding to the mode. The same circuits in the ASIC mode, FPGA mode, and DUT mode can be merged into the common mode.

[0009] In a preferred embodiment of the present invention, the circuit in step S3 can be abstracted into instances, ports, parameters, macros, connections, lines, and parameters that instantiate specific classes and data structures. The copy, scatter, and merge operations are abstracted into operations and processing on classes and data structures.

[0010] In a preferred embodiment of the present invention, the step of checking circuit connectivity in step S5 includes: step S51, collecting scattered objects, the objects including instances and ports; step S52, collecting the connection relationships of the objects; step S53, dispersing the collected objects and their connection relationships to a specified working mode; step S54, collecting the connection relationships of the scattered objects in the specified mode; and step S55, comparing the connection relationships before and after dispersion.

[0011] In a preferred embodiment of the present invention, the macro-based multi-mode circuit design method is encapsulated as graphical operation and command-line operation.

[0012] An electronic design EDA tool includes the macro-based multi-mode circuit design method described above.

[0013] An EDA device includes a memory and a processor; wherein the memory is used to store executable instructions that can run on the processor; and the processor is used to execute the macro-based multi-mode circuit design method as described above when running the executable instructions.

[0014] A computer storage medium storing a computer program that, when executed by a chip circuit layout device, implements the macro-based multi-mode circuit design method as described above, or when executed by an EDA device, implements the macro-based multi-mode circuit design method as described above.

[0015] Beneficial effects: The present invention provides a macro-based multi-mode circuit design method, device and medium that supports macro-based multi-mode circuit design. The mode includes a combination of one or more macros. The modes can be copied, scattered and merged. Circuit connectivity between modes can be checked. It supports Verilog code based on macro wrapping, which greatly improves the efficiency and quality of chip design.

[0016] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the steps of the multi-mode circuit design method of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the steps involved in a connectivity check.

[0019] Figure 3 This is an example of performing distributed operations on instances after encapsulating the multi-mode circuit design method of the present invention into a graphical operation flow. Detailed Implementation

[0020] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] To address the aforementioned problems in chip design, this invention provides a macro-based multi-mode circuit design method. Figure 1 This is a schematic diagram illustrating the steps of the multi-mode circuit design method of the present invention. After the chip designer determines the macro branch scheme of the project, the core steps of the main circuit design process are as follows:

[0022] Step S1: Set the operating mode of the chip project and configure the relationship between the operating mode and macros. A single operating mode includes a combination of one or more macros. The operating modes include common mode, ASIC mode, FPGA mode, and DUT mode. Circuits in the common mode are visible and operable in other modes (i.e., ASIC mode, FPGA mode, and DUT mode); circuits in other modes are mutually exclusive and invisible to each other.

[0023] Step S2 involves performing syntax and lexical analysis on the corresponding RTL code in the described working mode, abstracting modules, signals, parameters, macros, etc., in the RTL code into classes and data structures in the high-level language C++. Operations such as creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters are abstracted into operations and processing methods on the above classes and data structures. Relationships between modules are constructed to form a data relationship model, and each object is marked with a macro. Objects include signals, parameters, macros, parameter instantiation, wires, and connections.

[0024] In step S2, the modules in the RTL code generally include module name, signal, parameter, macro, instance, connection, and wire, which are shown below before conversion:

[0025]

[0026]

[0027] The objects in the module are abstracted and converted into classes and data structures in the high-level language C++. Specifically, an example is shown below:

[0028] object After conversion Module Name m_name:string parameter m_params:List<Parameter*> Signal m_ports:List<Ports*> Example m_instances:List<Instance*> Connection m_connections:List<Connection*> Wire m_wires:List<Wire*> Macro m_macros:List<Macro*>

[0029] Operations on a specific object can be abstracted into operations and processing methods on classes and data structures. Taking an "instance" as an example, the following is a case study:

[0030] operate After conversion Create a new instance addInstance(string,Module*,string):Instances* Modify Example modifyInstance(string,Module*,string):Instances* Delete instance delInstance(string,Module*,string):Instances*

[0031] Step S3: Based on the data relationship model, perform copying, distributing, and merging operations between the operating modes. Specifically, certain circuits in ASIC mode, FPGA mode, and DUT mode can be copied to each other, and certain circuits in the common mode can be distributed to specified ASIC mode, FPGA mode, and DUT mode. After distribution, the circuits are marked with the macros corresponding to the operating mode. Alternatively, identical circuits in ASIC mode, FPGA mode, and DUT mode can be merged into the common mode. That is, if a circuit exists in all the operating modes, this circuit belongs to the common mode and does not need to be wrapped by macros.

[0032] Step S4: Repeat the scattering and copying operations in step S3 until the circuit design is completed. After the operation, a new data relationship model is generated.

[0033] Step S5: Based on the new data relationship model, check whether the circuit connectivity of all operating modes is correct.

[0034] Step S6: After the circuit connectivity check passes, output RTL code containing multiple working modes based on the latest data relationship model, and check whether the output RTL code syntax is grammatically correct.

[0035] In the above steps, the circuit in step S3 can be abstracted into specific classes and data structures such as instances, ports, parameters, macros, connections, lines, and parameter instantiation. Operations such as copying, scattering, and merging are also abstracted into operations and processing on classes and data structures.

[0036] Step S5 is to check the circuit connectivity. Figure 2 This is a schematic diagram illustrating the steps involved in a connectivity check. (For example...) Figure 2 As shown, the steps for connectivity checking are as follows:

[0037] Step S51: Collect scattered objects, including instances and ports.

[0038] Step S52: Collect the connection relationships of objects.

[0039] Step S53: Distribute the collected objects and their connections to the specified working mode.

[0040] Step S54: Collect the connection relationships of the scattered objects in the specified pattern.

[0041] Step S55: Compare the connection relationships before and after dispersion.

[0042] In step S55, if the connection relationship before and after the dispersion is the same, the circuit connectivity is checked; if the connection relationship is different, the dispersion fails.

[0043] In practical applications, the multi-mode circuit design method of this invention can be encapsulated into graphical and command-line operations to facilitate collaborative work among designers. Figure 3 This is an example of performing distributed operations on instances after encapsulating the multi-mode circuit design method of the present invention into a graphical operation flow.

[0044] The following code is an example of distributing and copying instances after encapsulating the multi-mode circuit design method of the present invention into a command-line operation process.

[0045] scatter-o test.U_APB_Bridge_0,test.U_AHB_Master_0-M ASIC,FPGA

[0046] copy-o test.U_APB_Bridge_0,test.U_AHB_Master_0-M ASIC,FPGA

[0047] Based on this method, engineers only need to specify the instance to be adjusted and the corresponding mode. Without directly modifying the relevant design files, they can quickly obtain the relevant design code, intuitively display the effects before and after adjustment, check the circuit connectivity, and output the corresponding scatter report.

[0048] The multi-mode circuit design method of the present invention can be used in EDA tools, making the circuit design process in chips more convenient.

[0049] Similarly, the method of the present invention can also be used in an EDA device, which includes a memory and a processor. The memory stores executable instructions that can run on the processor. The processor, when running the executable instructions, executes the multi-mode circuit design method of the present invention.

[0050] Furthermore, the method of the invention can also be used in a computer storage medium storing a computer program that, when executed by an EDA device for chip circuitry, implements the multi-mode circuit design method of the invention. Alternatively, when executed by an EDA device, it implements the multi-mode circuit design method of the invention.

[0051] In summary, the present invention provides a macro-based multi-mode circuit design method, device, and medium that supports macro-based multi-mode circuit design. The mode includes a combination of one or more macros, and the modes can be copied, scattered, and merged. Furthermore, circuit connectivity checks can be performed between modes, and macro-wrapped Verilog code can be supported.

[0052] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A macro-based multi-mode circuit design method, characterized in that, include, Step S1: Set the working mode of the chip project and configure the relationship between the working mode and macros. A single working mode includes a combination of one or more macros. The working modes include common mode, ASIC mode, and FPGA mode. Step S2: Perform syntax and lexical analysis on the corresponding RTL code in the working mode, abstract the modules, signals, parameters, and macros in the RTL code into classes and data structures in the high-level language C++, and abstract the operations of creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters into operations and processing methods on classes and data structures, and build the relationship between modules to form a data relationship model, and mark each object with macros; Step S3: Based on the data relationship model, perform copying, dispersing, and merging operations between the working modes; Step S4: Repeat the scattering and copying operations in step S3 until the circuit design is completed, and generate a new data relationship model after the operation. Step S5: Based on the new data relationship model, check whether the circuit connectivity of all working modes is correct; Step S6: After the circuit connectivity check passes, output RTL code containing multiple working modes according to the new data relationship model, and check whether the output RTL code syntax is grammatically correct.

2. The macro-based multi-mode circuit design method as described in claim 1, characterized in that, Circuits in the common mode are visible and operable in both ASIC and FPGA modes, but circuits in ASIC and FPGA modes are not visible to each other.

3. The macro-based multi-mode circuit design method as described in claim 1, characterized in that, Circuits in ASIC mode and FPGA mode can be copied to each other. Circuits in common mode can be distributed to specified ASIC mode and FPGA mode. After distribution, the circuits are marked with the macro corresponding to the mode. Identical circuits in ASIC and FPGA modes can be merged into a common mode.

4. The macro-based multi-mode circuit design method as described in claim 1, characterized in that, The operating modes also include DUT mode, ASIC mode, FPGA mode, and circuits in DUT mode can be copied to each other. Circuits in common mode can be distributed to specified ASIC mode, FPGA mode, and DUT mode. After distribution, the circuits are marked with the macros corresponding to the mode. Identical circuits in ASIC mode, FPGA mode, and DUT mode can be merged into a common mode.

5. The macro-based multi-mode circuit design method as described in claim 1, characterized in that, The circuit in step S3 can be abstracted into instances, ports, parameters, macros, connections, lines, and parameters. The copy, scatter, and merge operations are abstracted into operations and processing on classes and data structures.

6. The macro-based multi-mode circuit design method as described in claim 1, characterized in that, The step of checking circuit connectivity in step S5 includes... Step S51: Collect scattered objects, including instances and ports; Step S52: Collect the connection relationships of the objects; Step S53: Distribute the collected objects and their connections to the specified working mode; Step S54: Collect the connection relationships of the scattered objects in the specified pattern; Step S55: Compare the connection relationships before and after dispersion.

7. A macro-based multi-mode circuit design method as described in any one of claims 1-6, characterized in that, The macro-based multi-mode circuit design method is encapsulated into graphical and command-line operations.

8. An electronic design EDA tool, characterized in that, Includes the macro-based multi-mode circuit design method as described in any one of claims 1-7.

9. An EDA device, characterized in that, The EDA device includes a memory and a processor; wherein... The memory is used to store executable instructions that can run on the processor; The processor is configured to execute the macro-based multi-mode circuit design method as described in any one of claims 1-7 when running the executable instructions.

10. A computer storage medium, characterized in that, The computer storage medium stores a computer program, which, when executed by a chip circuit placement device, implements the macro-based multi-mode circuit design method as described in any one of claims 1-7. Alternatively, when executed by an EDA device, it can implement the macro-based multi-mode circuit design method as described in any one of claims 1-7.

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