Signal transmission module, integrated circuit, electronic device and vehicle

Abstract

The invention discloses a signal transmission module, an integrated circuit, an electronic device and a vehicle, the signal transmission module comprises a multi-stage signal transmission unit and a control unit, the input end of the multi-stage signal transmission unit is correspondingly connected with a plurality of signal output sources, the output end of the multi-stage signal transmission unit is connected with a signal destination, and the signal destination is connected with the integrated circuit. A conversion unit for converting output signals of the plurality of signal output sources into input signals corresponding to the number of signal destinations, the number of signal output sources being greater than the number of signal destinations; and the control unit is connected with the multi-stage signal transmission unit and is used for controlling the signal transmission state of the multi-stage signal transmission unit according to the configuration information. According to the module and the circuit, the number of lines in the signal transmission process is effectively reduced, the wiring complexity is reduced, and the design and manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a signal transmission module and an integrated circuit, an electronic device and a vehicle. Background Art

[0002] In existing integrated circuit designs, with the increasing complexity of integrated circuits within the chip and the increase in functional modules, it is easy for the number of signal output sources to be greater than the number of signal destinations. The existing solution is to set a first-level transmission device between the signal output source and the signal destination, and the transmission device is located on the signal output port side. Since the signal output source and the signal destination belong to two different IP (Intellectual Property) modules, there is a relatively long distance in space. Therefore, the wiring connection from the signal output source to the signal destination requires a longer routing, a larger number of wirings, and high wiring complexity, which increases the cost of design and manufacturing. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a signal transmission module, which effectively reduces the number of lines in the signal transmission process, reduces the complexity of wiring, and reduces the cost of design and manufacturing.

[0004] A second object of the present invention is to provide an integrated circuit.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] A fourth object of the present invention is to provide a vehicle.

[0007] In order to achieve the above-mentioned purpose, the signal transmission module of the embodiment of the first aspect of the present invention includes: a multi-level signal transmission unit, the input end of the multi-level signal transmission unit is correspondingly connected to a plurality of signal output sources, the output end of the multi-level signal transmission unit is connected to a signal destination, and is used to convert the output signals of the plurality of signal output sources into input signals corresponding to the number of the signal destinations, wherein the number of the signal output sources is greater than the number of the signal destinations; a control unit, the control unit is respectively connected to the multi-level signal transmission unit, and is used to control the signal transmission state of the multi-level signal transmission unit according to configuration information.

[0008] According to the signal transmission module of the embodiment of the present invention, a multi-level signal transmission unit is set between the signal output source and the signal destination. The output signals of the multiple signal output sources are converted into input signals corresponding to the number of signal destinations through the multi-level signal transmission unit, which solves the signal transmission problem when the number of signal output sources is greater than the number of signal destinations. The multi-level signal transmission unit divides the signal transmission path into multiple stages. The signal transmission unit in each stage can convert multiple signals into fewer output signals, thereby achieving the effect of gradually reducing the number of output signals, thereby effectively reducing the number of lines required in the signal transmission process, reducing the complexity of wiring, and reducing the cost of design and manufacturing.

[0009] In some embodiments, the multi-stage signal transmission unit includes at least one AND-OR logic circuit; the input end of each of the AND-OR logic circuits is respectively connected to the plurality of signal output sources, and the output end of each of the AND-OR logic circuits is correspondingly connected to the signal destination.

[0010] In some embodiments, the multi-stage signal transmission unit includes a plurality of the AND-OR logic circuits; the number of the plurality of the AND-OR logic circuits is less than or equal to the number of the signal destinations.

[0011] In some embodiments, each of the AND-OR logic circuits includes: at least one AND gate circuit group, each of the AND gate circuit group includes multiple AND gate circuits, the first input end of each of the AND gate circuits is connected to the corresponding signal output source, the second input end of each of the AND gate circuits is connected to the control unit, and the output end of each of the AND gate circuits is used to output the output signal of the connected signal output source when the second input end of the AND gate circuit receives an output enable signal.

[0012] In some embodiments, each of the AND-OR logic circuits includes a plurality of the AND gate circuit groups, and the plurality of the AND gate circuit groups are connected in parallel.

[0013] In some embodiments, each of the AND-OR logic circuits further includes: an OR gate circuit, wherein the input end of the OR gate circuit is respectively connected to the output ends of the plurality of AND gate circuit groups, and the output end of the OR gate circuit is correspondingly connected to the signal destination, for outputting a corresponding signal to the connected signal destination when any of the AND gate circuit groups has an output.

[0014] In some embodiments, the multi-stage signal transmission unit includes a multi-stage multiplexer; the input end of each stage of the multiplexer in the multi-stage multiplexer is connected to the output end of the multiplexer of the previous stage, wherein the input end of the first stage of the multiplexer in the multi-stage multiplexer is respectively connected to the plurality of signal output sources, and the output end of the last stage of the multiplexer in the multi-stage multiplexer is connected to the signal destination.

[0015] In some embodiments, the first-stage multiplexer is disposed close to the signal output source.

[0016] In some embodiments, the multi-stage signal transmission unit includes: at least one multiplexer group, each of the multiplexer groups includes a plurality of first-stage multiplexers, an input end of each of the first-stage multiplexers is connected to a corresponding signal output source among the plurality of signal output sources, a channel selection end of each of the first-stage multiplexers is connected to the control unit, and is used to output an output signal of the corresponding signal output source according to a first channel selection signal; at least one second-stage multiplexer, an input end of each of the second-stage multiplexers is connected to an output end of a corresponding first-stage multiplexer in each of the multiplexer groups, an output end of each of the second-stage multiplexers is connected to the signal destination, and a channel selection end of each of the second-stage multiplexers is connected to the control unit, and is used to output a signal according to a second channel selection signal.

[0017] In some embodiments, the multi-stage signal transmission unit includes M multiplexer groups; each of the multiplexer groups includes N first-stage multiplexers; wherein M≥2 and N≥2.

[0018] In some embodiments, the multi-stage signal transmission unit includes N second-stage multiplexers; the input end of each second-stage multiplexer is respectively connected to the output end of the i-th first-stage multiplexer in each multiplexer group, where 1≤i≤N.

[0019] In some embodiments, the multi-level signal transmission unit also includes: a third-level multiplexer, the input end of the third-level multiplexer is respectively connected to the output ends of multiple second-level multiplexers, the output end of the third-level multiplexer is connected to the signal destination, and the channel selection end of the third-level multiplexer is connected to the control unit for outputting a signal according to a third channel selection signal.

[0020] In some embodiments, the control unit includes: a register, which is connected to the channel selection terminal of the first-stage multiplexer and is used to output the first channel selection signal to the channel selection terminal of the first-stage multiplexer according to configuration information.

[0021] In some embodiments, the first-stage multiplexer is a four-to-one multiplexer; and the first channel selection signal is any one of the values ​​assigned to the four bit fields of the register.

[0022] In some embodiments, the first-stage multiplexer is a four-to-one multiplexer; and the first channel selection signal is any one of the values ​​assigned to the two bit fields of the register.

[0023] In order to achieve the above-mentioned purpose, the integrated circuit of the second aspect of the embodiment of the present invention includes: multiple signal output sources and signal destinations; the signal transmission module described in the above embodiment, and the signal transmission module is respectively connected to the multiple signal output sources and the signal destinations.

[0024] According to the integrated circuit of the embodiment of the present invention, by connecting the signal transmission module to multiple signal output sources and signal destinations respectively, the output signals of multiple signal output sources can be effectively converted into input signals of the corresponding number of signal destinations, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations. At the same time, the design effectively reduces the number of lines in the integrated circuit, reduces the complexity of wiring, and reduces the cost of design and manufacturing.

[0025] In some embodiments, the signal destination includes at least one of a signal input source and a signal transmission port.

[0026] In order to achieve the above object, an electronic device according to an embodiment of the third aspect of the present invention includes at least one integrated circuit as described in the above embodiment.

[0027] The electronic device according to the embodiment of the present invention can effectively convert the output signals of multiple signal output sources into input signals of the corresponding number of signal destinations by adopting the integrated circuit described in the above embodiment, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations, and effectively reducing the number of lines in the signal transmission process, reducing the complexity of wiring, thereby improving the stability and reliability of the electronic device.

[0028] In order to achieve the above-mentioned object, a vehicle according to a fourth embodiment of the present invention includes the electronic device described in the above embodiment.

[0029] The vehicle according to the embodiment of the present invention, by adopting the electronic device described in the above embodiment, can effectively convert the output signals of multiple signal output sources into input signals of the corresponding number of signal destinations, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations, and at the same time effectively reducing the number of lines in the signal transmission process, reducing the complexity of wiring, thereby improving the overall performance of the vehicle.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 is a block diagram of a signal transmission module according to an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of selecting outputs of a plurality of AND-OR logic circuits according to an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of a 2-stage multiplexer output according to an embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of a 3-stage multiplexer output according to an embodiment of the present invention;

[0036] Figure 5 is a block diagram of an integrated circuit according to an embodiment of the present invention;

[0037] Figure 6 is a block diagram of an electronic device according to an embodiment of the present invention;

[0038] Figure 7 is a block diagram of a vehicle according to one embodiment of the present invention.

[0039] Reference numerals:

[0040] Vehicle 100;

[0041] Electronic device 110;

[0042] Integrated Circuits 111;

[0043] Signal output source 1; signal destination 2; signal transmission module 3;

[0044] Multi-level signal transmission unit 30; control unit 40;

[0045] AND-OR logic circuit 31; multiplexer group 32; second-stage multiplexer 33; third-stage multiplexer 34; register 41;

[0046] AND gate circuit group 310; OR gate circuit 311; first stage multiplexer 321;

[0047] AND gate circuit 3101. DETAILED DESCRIPTION

[0048] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0049] Reference below Figure 1 A signal transmission module according to an embodiment of the present invention is described.

[0050] Figure 1 is a block diagram of a signal transmission module according to an embodiment of the present invention, such as Figure 1 As shown, the signal transmission module 3 includes: a multi-stage signal transmission unit 30 and a control unit 40 .

[0051] In some embodiments, the multi-level signal transmission unit 30 may include a series of logic circuits or multiple multiplexers or other multi-level signal transmission devices, such as AND gates, OR gates, selectors, etc., for signal conversion and selection, which can be designed in combination according to specific needs.

[0052] In some embodiments, the input end of the multi-level signal transmission unit 30 is connected to a plurality of signal output sources, which means that the input port of the multi-level signal transmission unit 30 receives output signals from a plurality of signal output sources, and each input port corresponds to a signal output source. These signal output sources may be signals provided by different sensors, external devices, or other IP modules in the chip. Furthermore, the signals provided by these signal output sources may be digital signals or analog signals.

[0053] In some embodiments, the output end of the multi-level signal transmission unit 30 is connected to the signal destination. The design of the multi-level signal transmission unit 30 can effectively convert the output signals of multiple signal output sources into the number of input signals corresponding to the signal destination. Its internal principle is realized by having an internal logic gate circuit. Specifically, each multi-level signal transmission unit 30 can contain multiple logic gates, such as AND gates (AND), OR gates (OR), etc. These logic gates can operate according to the preset logic rules according to the logic state (high level or low level) of the input signal and generate corresponding output signals.

[0054] By combining multiple logic gates to form a multi-level signal transmission unit 30, complex signal conversion and matching logic can be implemented. For example, the AND logic of the signal can be implemented through the AND gate, and the OR logic of the signal can be implemented through the OR gate, so that the output signals of multiple signal sources can be converted into input signals of the corresponding destination according to preset rules. This combination of logic gates can be flexibly adjusted according to the configuration information to achieve different signal routing and conversion.

[0055] Therefore, the logic gate circuit inside the multi-level signal transmission unit 30 is the key to converting the output signals of multiple signal output sources into the input signals of the corresponding number of signal destinations. This design can convert and match according to the preset logic rules, thereby improving the utilization rate and flexibility of the signal.

[0056] In some embodiments, the number of signal output sources is greater than the number of signal destinations, which means that there are more signal sources (such as different modules, sensors, etc.) generating signals in the system, but the number of target ports (such as other modules, output interfaces, etc.) is limited. For example, if there are 8 output signal sources but only 3 signal destinations, the multi-stage signal transmission unit 30 can convert the output signals of the 8 signal output sources into the input signals required by the 4 signal destinations according to a preset rule.

[0057] In some embodiments, the control unit 40 may be a module or component for controlling and managing the multi-level signal transmission unit 30. It may be a circuit, or a configuration register or other control device. The control unit 40 is connected to the multi-level signal transmission unit 30, respectively, and is used to control the signal transmission state of the multi-level signal transmission unit 30 according to the configuration information.

[0058] The configuration information may be parameters and rules for guiding the operation of the multi-level signal transmission unit 30. Such information includes, but is not limited to, priority rules (which signal sources are transmitted first), logic rules (how to perform signal conversion), enable signals (which signal output sources are activated), etc. The signal transmission state may refer to the working state or working mode of the multi-level signal transmission unit 30, that is, the control unit 40 may control different working states of the multi-level signal transmission unit 30 according to different configuration information to achieve different signal transmission requirements.

[0059] In some embodiments, the design of the multi-stage signal transmission unit 30 can effectively reduce the number of lines required in the signal transmission process and reduce the complexity of wiring. The underlying principle is that the multi-stage signal transmission unit 30 can divide the signal transmission path into multiple stages, and the signal transmission unit in each stage can convert multiple signals into fewer output signals. The number of lines required in the signal transmission process can be reduced through the level-by-level conversion. Therefore, the overall signal transmission path becomes simpler and clearer, reducing the complexity of wiring.

[0060] According to the signal transmission module 3 of the embodiment of the present invention, by connecting the multi-level signal transmission unit 30 to multiple signal output sources and signal destinations respectively, the multi-level signal transmission unit 30 can effectively convert the output signals of multiple signal output sources into input signals of the corresponding number of signal destinations. The internal principle is that the multi-level signal transmission unit 30 has a circuit composed of multiple logic gates inside, and the circuit can select and convert signals according to the preset logic rules based on the configuration information provided by the control unit 40, so as to obtain the input signal required by the signal destination. This design solves the signal transmission problem when the number of signal output sources is greater than the number of signal destinations. At the same time, the multi-level signal transmission unit 30 divides the signal transmission path into multiple stages, and the signal transmission unit of each stage can convert multiple signals into fewer output signals, thereby achieving the effect of reducing the number of output signals step by step. This design can effectively reduce the number of lines required in the signal transmission process, reduce the complexity of wiring, and reduce the cost of design and manufacturing.

[0061] In some embodiments, the multi-stage signal transmission unit 30 includes at least one AND-OR logic circuit 31. The function of these logic circuits is to perform logical operations on the output signals of multiple signal output sources according to preset logic rules and then output them to the signal destination. Among them, the AND-OR logic circuit 31 is a basic logic circuit that can realize the functions of logical AND (AND) and logical OR (OR). The input end of each AND-OR logic circuit 31 is respectively connected to multiple signal output sources, which means that each AND-OR logic circuit 31 can simultaneously receive signals from multiple signal output sources as input. The output end of each AND-OR logic circuit 31 is connected to the signal destination accordingly. This means that after the AND-OR logic operation, the output of each AND-OR logic circuit 31 will be connected to the corresponding signal destination to meet the input signal requirements of the signal destination.

[0062] In some embodiments, when there is only one AND-OR logic circuit 31, in the multi-level signal transmission unit 30, the AND gate can be regarded as a first-level signal processing unit. The function of the AND gate is to perform a logical AND operation according to the states of multiple input signals. Only when all input signals are at a high level, the output of the AND gate is a high level. This is equivalent to the first-level screening and logical condition judgment. Only signals that meet specific conditions will continue to be passed to the next level (OR gate) for processing. In the multi-level signal transmission unit 30, the OR gate can be regarded as a second-level signal processing unit. The function of the OR gate is to perform a logical OR operation according to the states of multiple input signals. As long as one input signal is at a high level, the output of the OR gate is a high level. This is equivalent to the second-level merging and selection. According to the screening conditions of the previous level, the OR gate determines which signals will be output as the final signal destination.

[0063] In some embodiments, Figure 2As shown, when there are multiple AND / OR logic circuits 31, for example, when there are 16 AND / OR logic circuits 31, the corresponding Figure 2 As shown in the ×16AND-OR in the figure, it represents 16 AND-OR gate logic structures, and each AND-OR logic circuit is as shown in the structure of the front one in the figure. The 16 AND-OR gates here can be regarded as 16-level signal transmission units, and each level contains an AND-OR gate logic circuit. Each level of AND-OR gate logic circuit is connected to the signal input source respectively, among which the AND gate is responsible for screening and logical judgment according to the conditions of the input signal, and the OR gate is responsible for merging and selecting according to the results of the previous level of screening, and finally generating the input signal required by the signal destination. Therefore, such a design enables the signal transmission module 3 to have a more powerful logic processing capability, can handle complex signal conversion and matching, and can realize signal transmission between more signal input sources and fewer destinations, thereby improving the utilization rate of the signal and the flexibility of the signal output.

[0064] In some embodiments, the multi-stage signal transmission unit 30 includes a plurality of AND-OR logic circuits 31, and the number of the plurality of AND-OR logic circuits 31 is less than or equal to the number of signal destinations. This means that each signal destination can be processed by one or more AND-OR logic circuits 31, but there will not be a situation of excess logic circuits, thereby ensuring the integrity and correctness of the signal.

[0065] For example, assuming that there are N signal destinations, the number of AND-OR logic circuits 31 in the multi-stage signal transmission unit 30 is at most N. When the number of signal destinations is equal to the number of AND-OR logic circuits 31, each AND-OR logic circuit 31 can be responsible for the signal conversion logic of one signal destination, realizing one-to-one signal processing. If the number of signal destinations exceeds the number of AND-OR logic circuits 31, one logic circuit can be shared by multiple signal destinations to meet the needs of the signal destinations.

[0066] In some embodiments, each AND-OR logic circuit 31 includes at least one AND gate circuit group 310. Here, "group" refers to a collection of multiple AND gate circuits 3101, and each AND gate circuit group 310 includes multiple specific AND gate circuits 3101. Each AND gate circuit 3101 processes a specific bit of an input signal. Specifically, Figure 2 As shown, Figure 2 Each AND gate icon in the diagram can actually represent multiple AND gates, so they are referred to as a group here. For example, the first input 8 bits actually correspond to 8 AND gate circuits 3101, and each bit corresponds to an AND gate. Figure 2The combination of the 8-bit input AND gates in , actually constitutes an AND gate circuit group 310. Similarly, the 4-bit second input actually corresponds to 4 AND gate circuits 3101, the 8-bit third input actually corresponds to 8 AND gate circuits 3101, the 4-bit fourth input actually corresponds to 4 AND gate circuits 3101, and the 8-bit fifth input actually corresponds to 8 AND gate circuits 3101. Therefore, Figure 2 It is described that in an AND-OR logic circuit 31, there are 5 AND gate circuit groups 310, which can be said to have 28 specific AND gate circuits 3101, which also means that there are 28 signal output sources.

[0067] In some embodiments, the first input terminal of each AND gate circuit 3101 is connected to the corresponding signal output source, and the second input terminal of each AND gate circuit 3101 is connected to the control unit 40 for receiving a control signal. The output terminal of each AND gate circuit 3101 is used to output the output signal of the connected signal output source when the second input terminal of the AND gate circuit 3101 receives an output enable signal. Specifically, the control unit 40 configures and sends an output enable signal to the AND gate circuit group 310, indicating that the AND gate circuit group 310 can work. If the first input terminal of the first AND gate circuit 3101 receives a high level signal (indicating that the corresponding signal output source has a signal), and the second input terminal receives an output enable signal, the output terminal of the first AND gate circuit 3101 will output the signal. Other AND gate circuits 3101 also follow the same logic, which will not be repeated here.

[0068] In some embodiments, each AND-OR logic circuit 31 includes a plurality of AND gate circuit groups 310 for processing output signals of a plurality of signal output sources. The plurality of AND gate circuit groups 310 are connected in parallel in the same logic circuit module. This parallel connection method is actually to connect a plurality of AND gate circuit groups 310 side by side to form a large logic circuit unit.

[0069] like Figure 2As shown, there are 5 AND gate circuit groups 310 in the circuit, and each group contains multiple AND gate circuits 3101. These 5 AND gate circuit groups 310 are connected in parallel to form an integral logic circuit unit. This means that this logic unit can process the output signals of 5 different signal output sources at the same time and output corresponding results. The multiple AND gate circuits 3101 inside each AND gate circuit group 310 can process the output signals of multiple signal output sources respectively. The advantage of this structure is that multiple groups of signals can be processed in parallel, which improves the processing speed and efficiency. At the same time, this parallel connection design also makes the signal transmission module 3 more flexible, and the number and connection mode of the AND gate circuit groups 310 can be adjusted according to actual needs. Therefore, in the signal transmission module 3, the parallel connection of multiple AND gate circuit groups 310 and the multiple AND gate circuits 3101 inside each group work together to achieve flexible conversion and output of signals.

[0070] In some embodiments, each AND-OR logic circuit 31 further includes an OR gate circuit 311. The function of the OR gate circuit 311 is to perform a logical OR operation on the output signals of the multiple AND gate circuit groups 310 and output the result to the corresponding signal destination. Specifically, the input end of each OR gate circuit 311 is respectively connected to the output ends of the multiple AND gate circuit groups 310, so that the output signals of the multiple AND gate circuit groups 310 can be used as inputs to perform a logical OR operation. The output end of the OR gate circuit 311 is correspondingly connected to the signal destination, and is used to output the corresponding signal to the connected signal destination when any AND gate circuit group 310 has an output.

[0071] like Figure 2 As shown, OUT_MODULE can be regarded as a module, which has 28 output ports and can generate 28 output signal lines, and these signals need to be output to the 16 input ports of the signal destination. Figure 2 A combination of 16 AND-OR (AND-OR logic circuits 31) is used. The output end of each AND-OR (AND-OR logic circuit 31) is connected to a corresponding signal destination, and the function of the AND-OR logic circuit 31 is to select and combine signals from the 28 output ports of OUT_MODULE to generate an output signal, which is then output to the signal destination.

[0072] In some embodiments, Figure 2As shown, the OUT_SELij register 41 is used to control the selection of each group of AND-OR. Here, i can represent the serial number of the signal destination, and j represents the serial number of the output signal. By configuring the OUT_SELij register 41, it is possible to connect a specific output signal to a specific signal destination. Through the selection of the OUT_SELij register 41, the user can implement a variety of mapping methods. It can be a one-to-one mapping, outputting 28 output signal lines one-to-one to the signal destination. It can also be a many-to-one mapping, where multiple output signal lines are combined with the AND-OR logic circuit 31 and output to a certain input port of the signal destination.

[0073] Specifically, for each signal destination, the working principle of AND-OR is as follows: For the "AND" part, each of the 28 output signals is logically ANDed with the corresponding bit in the OUT_SELij register 41. Only when the corresponding bit in the OUT_SELij register 41 is 1, the corresponding output signal can pass. For the "OR" part, the output of the "AND" part is then subjected to a logical OR operation to obtain the final output signal. Such a design allows the 28 output signal lines to be flexibly output to the destination end one by one, and multiple output signal lines can also be output to the signal destination through AND-OR logic. As long as the source end selected in the OUT_SELij register 41 has a high level, the signal can be sent to the signal destination.

[0074] In some embodiments, Figure 2 Take 28 signal output lines and 16 groups of "AND-OR" logic circuits as an example, but the actual application is not limited to this number. This design is universal and scalable, and the number of output signals and logic gates can be increased or decreased according to specific system requirements to meet the mapping requirements of multiple output signals to signal destinations.

[0075] In some embodiments, the multi-stage signal transmission unit 30 includes a multi-stage multiplexer. The structure of such a multi-stage multiplexer plays a key role in the signal transmission module 3, and is used to convert the output signals of multiple signal output sources into the number of input signals corresponding to the signal destination. The input end of each stage of the multiplexer in the multi-stage multiplexer is connected to the output end of the multiplexer of the previous stage, wherein the input end of the first stage of the multiplexer in the multi-stage multiplexer is respectively connected to multiple signal output sources, and the output end of the last stage of the multiplexer in the multi-stage multiplexer is connected to the signal destination.

[0076] Specifically, the working principle of this design is: first, each level of the multiplexer can use multiplexing technology to merge the output signals of multiple signal output sources into one signal through the input port of the multiplexer, and then output it to the output port of the multiplexer. In this way, the output signals of multiple signal output sources are converted into input signals corresponding to the number of signal destinations. This cascade design of multi-level multiplexers allows the signal to pass through multiple levels of multiplexers in sequence and finally reach the signal destination. By controlling the working state of each level of the multiplexer, the signal and path can be flexibly selected, thereby realizing flexible allocation and conversion of the signal.

[0077] Therefore, the key to this design lies in the cascade connection of multi-stage multiplexers, which allows the output signals of multiple signal output sources to be selected and transmitted in multiple levels of multiplexers. The first-stage multiplexer inputs the signals of multiple signal output sources, selects and converts them according to the control signal and logic rules, and then outputs them to the next-stage multiplexer. The next-stage multiplexer selects and converts again until it finally reaches the final multiplexer and outputs the signal to the signal destination. Such a design effectively reduces the number and complexity of lines in the signal transmission process and improves the utilization and flexibility of the signal.

[0078] In some embodiments, the first-stage multiplexer is disposed close to the signal output source. The purpose of this design is to reduce the wiring length between the signal output source and the input terminal of the multiplexer, thereby improving the efficiency and reliability of signal transmission.

[0079] Specifically, in actual integrated circuit design, the wiring length between the signal output source and the multiplexer has a direct impact on the performance of signal transmission. Placing the first-stage multiplexer close to the signal output source can physically shorten the transmission distance of the signal from the output source to the multiplexer. A shorter transmission distance means lower signal transmission delay and less signal attenuation, which is especially important for high-speed signals and long-distance transmission. In addition, a shorter wiring length can also reduce crosstalk and interference during signal transmission, further improving the reliability and stability of the signal.

[0080] Figure 3 is a schematic diagram of a 2-stage multiplexer output according to an embodiment of the present invention, such as Figure 3As shown, the multi-level signal transmission unit 30 includes at least one multiplexer group 32. Each multiplexer group 32 includes a plurality of first-level multiplexers 321, and the input end of each first-level multiplexer 321 is connected to a corresponding signal output source among a plurality of signal output sources, so that each first-level multiplexer 321 can receive signals from different signal output sources. The channel selection end of each first-level multiplexer 321 is connected to the control unit 40, and is used to output the output signal of the corresponding signal output source according to the first channel selection signal;

[0081] Specifically, first, the control unit 40 configures the first channel selection signal as needed, and the signal can be a binary code for selecting which signal output source to select the signal from. After the channel selection end of each first-level multiplexer 321 receives the first channel selection signal, it decides which signal output sources to receive the signal from according to the selection provided by the control unit 40. For example, if the first channel selection signal is binary "00", then the first-level multiplexer 321 can select the signal of the first signal output source connected to it. If the first channel selection signal is "01", then the first-level multiplexer 321 can select the signal of the second signal output source connected to it, and so on. Therefore, the control unit 40 can select signals from different signal output sources and output them to the multiplexer of the next level by changing the first channel selection signal.

[0082] In some embodiments, the multi-level signal transmission unit 30 also includes at least one second-level multiplexer 33, the input end of each second-level multiplexer 33 is connected to the output end of the corresponding first-level multiplexer 321 in each multiplexer group 32, the output end of each second-level multiplexer 33 is connected to the signal destination, and the channel selection end of each second-level multiplexer 33 is connected to the control unit 40 for outputting a signal according to a second channel selection signal.

[0083] like Figure 2As shown, the signal transmission module 3 includes two multiplexer groups 32, each multiplexer group 32 includes three first-stage multiplexers 321, and the two multiplexer groups 32 have a total of six first-stage multiplexers 321, and the second-stage multiplexers 33 have a total of three. For the first second-stage multiplexer 33, the first second-stage multiplexer 33 can receive the signal coded as "00" output by the first first-stage multiplexer 321 in the first multiplexer group 32. At the same time, it can also receive the signal coded as "10" output by the first first-stage multiplexer 321 in the second multiplexer group 32. When the control unit 40 sends the second channel selection signal as SEL0, the first second-stage multiplexer 33 can output the signal corresponding to the selection signal to the signal destination or the next-stage multiplexer.

[0084] For the second second-stage multiplexer 33, the second second-stage multiplexer 33 can receive the signal coded as "01" output by the second first-stage multiplexer 321 in the first multiplexer group 32. At the same time, it can also receive the signal coded as "11" output by the second first-stage multiplexer 321 in the second multiplexer group 32. When the control unit 40 sends the second channel selection signal SEL1, the second second-stage multiplexer 33 can output the signal corresponding to the selection signal to the signal destination or the next-stage multiplexer.

[0085] For the third second-stage multiplexer 33, the third second-stage multiplexer 33 can receive the signal coded as "02" output by the third first-stage multiplexer 321 in the first multiplexer group 32. At the same time, it can also receive the signal coded as "12" output by the third first-stage multiplexer 321 in the second multiplexer group 32. When the control unit 40 sends the second channel selection signal SEL2, the third second-stage multiplexer 33 can output the signal corresponding to the selection signal to the signal destination or the next-stage multiplexer.

[0086] In some embodiments, the multi-level signal transmission unit 30 includes M multiplexer groups 32. These multiplexer groups 32 may be located in an IP module inside the chip (eg, Figure 3 The multi-level signal transmission unit 30 is a multi-level signal transmission unit 31, and each module includes a multiplexer group 32. The purpose of this design is to realize hierarchical processing and management of signals, so that the multi-level signal transmission unit 30 can process signals from multiple signal output sources in a hierarchical manner. Each multiplexer group 32 can be regarded as an independent processing unit, which is responsible for receiving and processing signals from a specific number of signal output sources, thereby realizing parallel processing of multiple signal sources.

[0087] In some embodiments, each multiplexer group 32 includes N first-stage multiplexers 321. This means that there are multiple first-stage multiplexers 321 inside each multiplexer group 32, and each first-stage multiplexer 321 can select different signal output sources for processing. Specifically, each first-stage multiplexer 321 in each multiplexer group 32 is responsible for receiving signals from different signal output sources, and selecting and distributing them according to the control signal sent by the control unit 40. The control unit 40 sends specific control signals to each first-stage multiplexer 321, and each first-stage multiplexer 321 decides which signal source to select based on these control signals, and passes the selected signal to the next level of multiplexers or signal destinations.

[0088] In some embodiments, the number of multiplexer groups 32 is M≥2, and M can be selected from 2, 3, 5, 8, 10, 15, 20, 25, etc. The number of first-stage multiplexers 321 is N≥2, and N can be selected from 2, 4, 6, 8, 10, 12, 15, 20, etc. The numbers of M and N can be selected according to specific design requirements and system requirements, and are not specifically limited here.

[0089] In some embodiments, the first-stage multiplexer 321 includes N input ports and M output ports, wherein the N input ports may indicate that the first-stage multiplexer 321 may receive signal inputs from N different signal sources. The M output ports may indicate that the first-stage multiplexer 321 may route the selected signal to M different output ports, N ≥ M, and this design reflects the multiplexing function of the multiplexer. The function of the multiplexer is to select one or more of the multiple input signals to be output to the corresponding output ports, thereby realizing the combination, selection and distribution of signals. In this way, it is possible to output part or all of the output signals of multiple signal output sources to fewer output ports. This can reduce the number of signals that need to be processed by the next-stage multiplexer, thereby reducing the complexity of wiring.

[0090] In some embodiments, the multi-stage signal transmission unit 30 includes N second-stage multiplexers 33. Here, N represents the number of second-stage multiplexers 33, that is, the entire signal transmission module 3 includes N second-stage multiplexers 33. The function of these second-stage multiplexers 33 is to further process the output signal of the first-stage multiplexer 321 and route it to the corresponding signal destination or the multiplexer of the next stage.

[0091] In some embodiments, the input end of each second-stage multiplexer 33 is respectively connected to the output end of the i-th first-stage multiplexer 321 in each multiplexer group 32. Specifically, the input end of each second-stage multiplexer 33 can be respectively connected to the output end of the i-th first-stage multiplexer 321 in each multiplexer group 32. Here, i represents the sequence number of the first-stage multiplexer 321 in the multiplexer group 32, because each multiplexer group 32 includes multiple first-stage multiplexers 321. Such a connection method ensures that the second-stage multiplexer 33 can receive signals from the first-stage multiplexers 321 at the same position in different multiplexer groups 32.

[0092] Among them, 1≤i≤N. This condition indicates that the input end of the second-stage multiplexer 33 is connected to the output ends of all the first-stage multiplexers 321 in each multiplexer group 32. The range of i is from 1 to N, which ensures that each second-stage multiplexer 33 can receive the signals of the first-stage multiplexers 321 at all corresponding positions in each multiplexer group 32. Through such a design, the second-stage multiplexer 33 can receive signals from the first-stage multiplexers 321 at different positions in different multiplexer groups 32, and route these signals to the corresponding signal destination or the next-stage multiplexer according to its channel selection signal. This hierarchical multiplexer structure effectively organizes and manages the transmission path of the signal, so that the signal undergoes multiple levels of selection and routing from the input end to the output end, thereby improving the flexibility and efficiency of signal transmission.

[0093] In some embodiments, the second-stage multiplexer 33 includes P input ports and Q output ports, which means that the second-stage multiplexer 33 has a structure of P input ports and Q output ports. P represents the number of input signals, and Q represents the number of output signals. Therefore, the second-stage multiplexer 33 can receive P input signals at the same time, and select one or more of them to be routed to Q output ports. P≥Q, which means that the number of input ports P must be at least greater than or equal to the number of output ports Q. This design ensures that the second-stage multiplexer 33 can process more input signals, and therefore can meet different signal routing requirements. At the same time, in this way, it is possible to convert the signal output by the first-stage multiplexer 321 into the number of input signals corresponding to the signal destination, thereby improving the utilization rate of the signal and the flexibility of the signal output, while effectively reducing the number of lines in the signal transmission process and reducing the complexity of the wiring.

[0094] like Figure 4As shown, the multi-level signal transmission unit 30 further includes a third-level multiplexer 34. The input end of the third-level multiplexer 34 is respectively connected to the output ends of the plurality of second-level multiplexers 33, which means that the third-level multiplexer 34 can receive output signals from the plurality of second-level multiplexers 33. The output end of the third-level multiplexer 34 is connected to the signal destination, which means that the third-level multiplexer 34 will eventually route the selected signal to the signal destination. The channel selection end of the third-level multiplexer 34 is connected to the control unit 40. Through the third channel selection signal sent by the control unit 40, the third-level multiplexer 34 can decide from which input end to receive the signal according to this signal, and output the selected signal to the signal destination.

[0095] The function of the third-stage multiplexer 34 is to select a specific signal from the outputs of the plurality of second-stage multiplexers 33 and output it to the signal destination according to the third channel selection signal sent by the control unit 40. Such a design allows the signal to be selected and distributed at multiple levels to meet the requirements for signal routing and distribution in complex systems.

[0096] In some embodiments, Figure 3 As shown, MODUL0 and MODUL1 are introduced as examples of IP modules inside the chip, but in practical applications, they are not limited to two MODULEs. The present invention is illustrated by two MODULEs. Moreover, the signal output sources of the multiplexer are not limited to four, but can be two, three, four or more. In addition, the output level of the multiplexer is not limited to two, but can be one, two, three or more, without specific limitation. This shows that the technical solution is universal and scalable, and is applicable to integrated circuit designs of different scales and complexities.

[0097] In some embodiments, the signal output source to the signal destination only passes through the wire and the multiplexer, without passing through the trigger. This means that in the data transmission process, no clock control elements such as triggers are introduced, thereby avoiding the clock delay caused by the trigger.

[0098] In some embodiments, the control unit 40 includes a register 41. The register 41 in the control unit 40 is connected to the channel selection end of the first-stage multiplexer 321. The register 41 here is mainly used to store and manage configuration information, and the configuration information refers to the parameters used to control signal routing and selection. The configuration information stored in the register 41 can be pre-set or dynamically configured according to the needs of the system during operation. The control unit 40 can generate corresponding first channel selection signals based on these configuration information, and then send these signals to the channel selection end of the first-stage multiplexer 321. The first-stage multiplexer 321 routes specific signals to corresponding output ports based on the selection of these signals, thereby realizing the transmission and distribution of signals. When the system needs to change the routing and distribution of signals, it can be achieved by updating the configuration information in the register 41. Such a design makes the system flexible and configurable, and the transmission path and destination of the signal can be dynamically adjusted according to different needs.

[0099] In some embodiments, Figure 2 and Figure 3 As shown, the first-stage multiplexer 321 is a four-to-one multiplexer. A four-to-one multiplexer is a common type of multiplexer, which has four input ports and one output port. This multiplexer can select one of the four input signals and output the selected signal to the output port.

[0100] In some embodiments, the first channel selection signal is any one of the values ​​assigned to the four bit fields of the register 41. Here, the generation method of the first channel selection signal is described. There are four bit fields in the register 41, each of which corresponds to an input port. These bit fields can be set to different values, representing four different selections. When the control unit 40 needs to specify a specific input port, the values ​​of the four bit fields of the register 41 can be set as needed, and one of them can be selected as the first channel selection signal. In this way, the first-stage multiplexer 321 can pass the corresponding input signal to the output port according to the selection of this signal.

[0101] In some embodiments, specific configuration rules for assigning values ​​to the four bit fields of register 41 are shown in Table 1 below:

[0102] Table 1 Configuration rules for the assignment of the four bit fields of the register

[0103] Bitfield[3:0] Output Selection 0001 Select signal output source 0 as multiplexer output 0010 Select signal output source 1 as multiplexer output 0100 Select signal output source 2 as multiplexer output 1000 Select signal output source 3 as multiplexer output

[0104] As shown in Table 1, users can easily select the signal output source of the multiplexer through simple bit operations and register 41 configuration. For example, by left-shifting 0x01 (the number of bits shifted to the left is the output source sequence number) and then assigning a value to the bit field, the output source output can be selected. The main advantage of this method is that it is easy to configure. Users can select the signal output source by performing simple bit operations on register 41. This provides an intuitive and easy-to-understand configuration method.

[0105] However, this design also has some disadvantages. Since the user needs to manually configure the register 41 bit field, there is a certain risk of configuration error, for example, the bit field is mistakenly configured as 0110. In order to prevent this situation, some error prevention mechanisms need to be added. In addition, in order to support the configuration of multiple signal output sources, multiple register 41 bit fields need to be occupied, which may result in more occupied register 41 bit fields, thereby increasing the chip area.

[0106] Therefore, when the first-stage multiplexer 321 is a four-to-one multiplexer, the present invention also provides another register 41 configuration design method, that is, the first channel selection signal is any one of the values ​​assigned to the two bit fields of the register 41. Each bit field corresponds to two input ports. These bit fields can be set to different values, representing four different selection situations. When the control unit 40 needs to specify a specific input port, the values ​​of the two bit fields of the register 41 can be set as needed, and one of them can be selected as the first channel selection signal. In this way, the first-stage multiplexer 321 can pass the corresponding input signal to the output port according to the selection of this signal.

[0107] In some embodiments, specific configuration rules for assigning values ​​to the two bit fields of register 41 are shown in Table 2 below:

[0108] Table 2 Configuration rules for the assignment of two bit fields of registers

[0109] Bitfield[1:0] Output Selection 00 Select output source 0 as multiplexer output 01 Select output source 1 as multiplexer output 10 Select output source 2 as multiplexer output 11 Select output source 3 as multiplexer output

[0110] As shown in Table 2, the advantage of this register 41 configuration is that every configuration value is a valid output selection. Using two register 41 bit fields, four different configuration combinations can be represented, each corresponding to an output source. Compared to the previous design, this approach minimizes the possibility of configuration errors because every configuration value is meaningful and corresponds to a valid output.

[0111] In summary, this register 41 configuration design method provides a simpler solution with reduced possibility of configuration errors by cleverly utilizing two register 41 bit fields. Each configuration value is directly mapped to a valid output selection, which enhances the clarity and reliability of configuration.

[0112] Reference below Figure 5 An integrated circuit according to an embodiment of the invention is described.

[0113] Figure 5 is a block diagram of an integrated circuit according to an embodiment of the present invention, such as Figure 5 As shown, the integrated circuit 111 includes: a plurality of signal output sources 1, a signal destination 2 and the signal transmission module 3 described in the above embodiment.

[0114] In some embodiments, the signal output source 1 may be various types of signal sources, such as signals generated by electronic devices such as sensors, processors, and memories.

[0115] In some embodiments, the signal destination 2 includes at least one of a signal input source and a signal transmission port. The signal input source may refer to an input port of a functional module or an IP core inside the integrated circuit 111, which is used to receive signal inputs from other parts. It may also be an external signal, such as a sensor, a communication interface, etc. The signal transmission port may refer to a port or interface inside the integrated circuit 111 for transmitting signals. For example, an IO port, which may refer to an Input / Output port, is an interface for connecting an external device to the integrated circuit 111. In the integrated circuit 111, the IO port is used to exchange data with external devices, including receiving external input signals and sending output signals to the outside. These ports may be digital ports or analog ports, depending on the type of signal they process.

[0116] In some embodiments, the signal transmission module 3 is connected to multiple signal output sources 1 and signal destinations 2 respectively. By connecting multiple signal output sources 1, the signal transmission module 3 can receive signal inputs from different modules or devices, and process, convert, select, and perform other operations on these signals as needed. Then the processed signals are output to the signal destination 2. Such a connection method enables the integrated circuit 111 to have flexible input and output capabilities, and can communicate and exchange data with multiple signal output sources 1 and signal destinations 2, thereby improving the flexibility of the integrated circuit 111.

[0117] According to the integrated circuit 111 of the embodiment of the present invention, by connecting the signal transmission module 3 to the multiple signal output sources 1 and the signal destinations 2 respectively, the output signals of the multiple signal output sources 1 can be effectively converted into input signals corresponding to the number of signal destinations 2, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations. At the same time, the design effectively reduces the number of lines in the integrated circuit 111, reduces the complexity of wiring, and reduces the cost of design and manufacturing.

[0118] Reference below Figure 6 An electronic device according to an embodiment of the present invention is described.

[0119] Figure 6 is a block diagram of an electronic device according to an embodiment of the present invention, such as Figure 6 As shown, the electronic device 110 includes the integrated circuit 111 described in the above embodiment.

[0120] In some embodiments, the electronic device 110 may be any device capable of electronic processing, control and communication, such as a mobile phone, a computer, a smart home device, a smart car, a sensor device, an industrial control system, etc. The electronic device 110 can process and transmit various types of information, such as data, images, audio, video, etc.

[0121] According to the electronic device 110 of the embodiment of the present invention, by adopting the integrated circuit 111 described in the above embodiment, the output signals of multiple signal output sources 1 can be effectively converted into input signals corresponding to the number of signal destinations 2, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations, and at the same time effectively reducing the number of lines in the signal transmission process, reducing the complexity of wiring, thereby improving the stability and reliability of the electronic device 110.

[0122] Reference below Figure 7 A vehicle according to an embodiment of the present invention is described.

[0123] Figure 7 is a block diagram of a vehicle according to an embodiment of the present invention, such as Figure 7 As shown, the vehicle 100 includes the electronic device 110 described in the above embodiment. The application of the electronic device 110 enables the vehicle 100 to have a higher level of intelligence and automation, and improves the safety, comfort and convenience of driving. Through the electronic device 110, the vehicle 100 can realize automatic driving functions, intelligent navigation and route planning, remote monitoring and diagnosis, vehicle communication and Internet connection, etc.

[0124] In some embodiments, the vehicle 100 may include various types of transportation and motor vehicles, such as cars, buses, trains, vans, trucks, etc.

[0125] According to the vehicle 100 of the embodiment of the present invention, by adopting the electronic device 110 described in the above embodiment, the output signals of multiple signal output sources 1 can be effectively converted into input signals corresponding to the number of signal destinations 2, thereby solving the signal transmission problem when the number of signal output sources is greater than the number of signal destinations. At the same time, the number of lines in the signal transmission process is effectively reduced, the complexity of wiring is reduced, and the overall performance of the vehicle 100 is improved.

[0126] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0127] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A signal transmission module, characterized in that: include: A multi-stage signal transmission unit, wherein the input end of the multi-stage signal transmission unit is connected to a plurality of signal output sources, and the output end of the multi-stage signal transmission unit is connected to a signal destination, and is used to convert the output signals of the plurality of signal output sources into input signals corresponding to the number of the signal destinations, wherein the number of the signal output sources is greater than the number of the signal destinations; A control unit, wherein the control unit is connected to the multi-level signal transmission unit respectively, and is used to control the signal transmission state of the multi-level signal transmission unit according to configuration information.

2. The signal transmission module according to claim 1, characterized in that: The multi-stage signal transmission unit includes at least one AND-OR logic circuit; The input end of each of the AND-OR logic circuits is connected to the plurality of signal output sources respectively, and the output end of each of the AND-OR logic circuits is connected to the signal destination accordingly.

3. The signal transmission module according to claim 2, characterized in that: The multi-level signal transmission unit includes a plurality of the AND-OR logic circuits; The number of the plurality of AND-OR logic circuits is less than or equal to the number of the signal destinations.

4. The signal transmission module according to claim 2, characterized in that: Each of the AND-OR logic circuits comprises: At least one AND gate circuit group, each of the AND gate circuit groups includes a plurality of AND gate circuits, a first input end of each of the AND gate circuits is connected to the corresponding signal output source, a second input end of each of the AND gate circuits is connected to the control unit, and an output end of each of the AND gate circuits is used to output an output signal of the connected signal output source when the second input end of the AND gate circuit receives an output enable signal.

5. The signal transmission module according to claim 4, characterized in that: Each of the AND-OR logic circuits includes a plurality of AND gate circuit groups, and the plurality of AND gate circuit groups are connected in parallel.

6. The signal transmission module according to claim 5, characterized in that: Each of the AND-OR logic circuits further comprises: An OR gate circuit, wherein the input end of the OR gate circuit is respectively connected to the output ends of the plurality of AND gate circuit groups, and the output end of the OR gate circuit is correspondingly connected to the signal destination, for outputting a corresponding signal to the connected signal destination when any of the AND gate circuit groups has an output.

7. The signal transmission module according to claim 1, characterized in that: The multi-stage signal transmission unit includes a multi-stage multiplexer; The input end of each stage of the multiplexer in the multi-stage multiplexer is connected to the output end of the multiplexer in the previous stage, wherein the input end of the first stage of the multiplexer in the multi-stage multiplexer is respectively connected to the multiple signal output sources, and the output end of the last stage of the multiplexer in the multi-stage multiplexer is connected to the signal destination.

8. The signal transmission module according to claim 7, characterized in that: The first-stage multiplexer is arranged close to the signal output source.

9. The signal transmission module according to claim 7, characterized in that: The multi-stage signal transmission unit comprises: at least one multiplexer group, each of the multiplexer groups comprising a plurality of first-stage multiplexers, an input end of each of the first-stage multiplexers being connected to a corresponding signal output source among the plurality of signal output sources, and a channel selection end of each of the first-stage multiplexers being connected to the control unit for outputting an output signal of the corresponding signal output source according to a first channel selection signal; at least one second-stage multiplexer, the input end of each second-stage multiplexer is connected to the output end of the corresponding first-stage multiplexer in each multiplexer group, the output end of each second-stage multiplexer is connected to the signal destination, and the channel selection end of each second-stage multiplexer is connected to the control unit for outputting a signal according to a second channel selection signal.

10. The signal transmission module according to claim 9, characterized in that: The multi-stage signal transmission unit includes M multiplexer groups; Each of the multiplexer groups includes N first-stage multiplexers; Among them, M≥2, and N≥2.

11. The signal transmission module according to claim 10, characterized in that: The multi-stage signal transmission unit includes N second-stage multiplexers; The input terminal of each of the second-stage multiplexers is respectively connected to the output terminal of the i-th first-stage multiplexer in each of the multiplexer groups, where 1≤i≤N.

12. The signal transmission module according to claim 11, characterized in that: The multi-stage signal transmission unit further includes: A third-stage multiplexer, wherein the input end of the third-stage multiplexer is respectively connected to the output ends of the plurality of second-stage multiplexers, the output end of the third-stage multiplexer is connected to the signal destination, and the channel selection end of the third-stage multiplexer is connected to the control unit for outputting a signal according to a third channel selection signal.

13. The signal transmission module according to claim 9, characterized in that: The control unit comprises: A register is connected to the channel selection end of the first-stage multiplexer and is used to output the first channel selection signal to the channel selection end of the first-stage multiplexer according to configuration information.

14. The signal transmission module according to claim 13, characterized in that: The first-stage multiplexer is a four-to-one multiplexer; The first channel selection signal is any one of the values ​​assigned to the four bit fields of the register.

15. The signal transmission module according to claim 13, characterized in that: The first-stage multiplexer is a four-to-one multiplexer; The first channel selection signal is any one of the values ​​assigned to the two bit fields of the register.

16. An integrated circuit, characterized in that: include: Multiple signal output sources and signal destinations; The signal transmission module according to any one of claims 1 to 15, wherein the signal transmission module is connected to a plurality of the signal output sources and the signal destinations respectively.

17. The integrated circuit according to claim 16, characterized in that The signal destination includes at least one of a signal input source and a signal transmission port.

18. An electronic device, characterized in that: Comprising at least one integrated circuit as claimed in claim 16 or 17.

19. A vehicle, characterized in that: An electronic device comprising the electronic device described in claim 18.

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