Large-scale chip design method and device based on AI model

Abstract

The invention discloses a large-scale chip design method and device based on an AI model, and relates to the technical field of chip design. Comprising the steps of 1, generating an initial design scheme and a technical specification of a chip according to related data by using an AI model, 2, evaluating the initial design scheme according to an evaluation system, and dividing module circuits of the chip according to a final design scheme, and 3, generating digital design codes corresponding to the module circuits according to the module specification by using the AI model, the method comprises the following steps of: 1, automatically generating a test case by using an AI model, 2, collecting data of a verification process and an execution condition of the test case, identifying digital design defects, and modifying digital design codes of corresponding module circuits according to optimization suggestions, and 3, splicing the digital design codes of the module circuits into a digital design total code of a large-scale chip. The AI model is utilized, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

Description

Technical Field

[0001] The present invention discloses a large-scale chip design method and device based on an AI model, and relates to the technical field of chip design. Background Art

[0002] With the development of emerging technologies such as artificial intelligence and the Internet of Things, the market's requirements for chip computing power continue to increase, and the scale and design complexity of chips are growing exponentially. When conducting large-scale chip design and verification, existing chip design and verification methods mainly rely on manual experience and trial and error, and the design process is cumbersome and inefficient. Therefore, as the scale and complexity of chip design continue to increase, manual design and verification work becomes extremely time-consuming, and it is difficult to find hidden design errors, increasing the risk of chip tape-out failure. Summary of the invention

[0003] In view of the problems of the prior art, the present invention provides a large-scale chip design method and device based on an AI model. The AI ​​model is used to shorten the chip design cycle and reduce development costs to meet the needs of the rapid development of modern large-scale chips.

[0004] The specific scheme proposed by the present invention is: The present invention provides a large-scale chip design method based on an AI model, comprising: Step 1: Collect the chip’s design requirements, function definition information, and constraint information, and organize them into relevant data. Use the AI ​​model to generate the chip’s initial design plan and technical specifications based on the relevant data. Step 2: Evaluate the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. Adjust the initial design plan according to the evaluation results to form a final design plan. Divide the module circuit of the chip according to the final design plan. Step 3: Define the function of each module according to the module circuit, generate the module specification for each module, and use the AI ​​model to generate the digital design code for the corresponding module circuit according to the module specification. Step 4: Use the AI ​​model to automatically generate test cases to simulate various working modes of the chip in actual applications. The AI ​​model uses the boundary value analysis strategy to generate test cases, the equivalence class partitioning strategy to generate test cases, and the corresponding test cases for each abnormal situation. Verify the test cases, monitor the verification process and the execution of the test cases, Step 5: Collect data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data and provides optimization suggestions for the defects. The digital design code of the corresponding module circuit is modified according to the optimization suggestions. Step 6: Splice the digital design codes of each module circuit into the digital design master code of the large-scale chip. Check whether the interface definitions between the modules are consistent according to the technical specifications, check whether the timing of the signals matches, and check whether the data formats are compatible. If there are any problems, modify the corresponding positions in the digital design master code. If there are no problems, assemble and manufacture the chip according to the digital design master code.

[0005] Furthermore, in step 1 of the large-scale chip design method based on an AI model, a Chatgpt or Deepseek model is selected as the AI ​​model to generate an initial design plan and technical specification of the chip according to relevant data. The technical specification includes the basic functions of the chip, the performance indicators of the chip, a list of key parameters, a communication protocol and a clock frequency.

[0006] Furthermore, in step 2 of the large-scale chip design method based on the AI ​​model, an evaluation system is established according to the design goals and industry standards of the chip. The performance index evaluation in the evaluation system includes computing speed, data processing capability, and performance evaluation under different workloads. The area index evaluation includes the physical area of ​​the chip, the number of logic gates, and the occupancy of wiring resources. The power consumption index evaluation includes static power consumption and dynamic power consumption evaluation, which respectively evaluates the energy consumption of the chip in standby state and working state.

[0007] Furthermore, step 3 of the large-scale chip design method based on an AI model specifically includes: According to the module circuit, define the function of each module: for the processing module, clarify the instruction set, data processing accuracy, and cache capacity parameters of the processing module; for the IO module, determine the interface type, data transmission rate, and signal level standard supported by the IO module. Generate the module specification of each module according to the module circuit: the module specification includes functional requirements, performance indicators, timing requirements, power consumption limits and area constraints. The AI ​​model is used to generate digital design code for the corresponding module circuit according to the module specification, and the generated digital design code is reviewed. The review content includes the logical correctness of the code, syntax errors, and compliance with coding standards. The code review tool Synopsys's SpyGlass component is used to perform static analysis on the code to check whether there are potential logical errors and safety hazards.

[0008] Furthermore, in step 4 of the large-scale chip design method based on the AI ​​model, the generated test cases are prioritized according to their importance and risk level, and higher priority is given to test cases of modules with key functions in the chip, test cases involving security mechanisms, and test cases that affect the stability of the chip system. When verifying the test case, set different simulation accuracies and time steps, adjust the simulation parameters according to the complexity of the test case, record the output signal and internal state changes of the chip, and compare them with the expected results. If it is found that the output result does not meet the expectations, mark the test case as a failed case, and record the cause of the failure and related test data.

[0009] The present invention also provides a large-scale chip design device based on an AI model, including a demand understanding module, an evaluation module, a design module, a test case module, a verification result analysis module and an integration module. The demand understanding module collects the chip's design requirement information, function definition information, and constraint information, and organizes them into relevant data. It uses the AI ​​model to generate the chip's initial design plan and technical specifications based on the relevant data. The evaluation module evaluates the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. The initial design plan is adjusted according to the evaluation results to form a final design plan. The module circuit of the chip is divided according to the final design plan. The design module defines the function of each module according to the module circuit and generates the module specification for each module. The AI ​​model is used to generate the digital design code for the corresponding module circuit according to the module specification. The test case module uses AI models to automatically generate test cases and simulate various working modes of chips in actual applications. It uses AI models to generate test cases using boundary value analysis strategy, equivalence class partitioning strategy, and corresponding test cases for each abnormal situation. Verify the test cases, monitor the verification process and the execution of the test cases, The verification result analysis module collects data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data, provides optimization suggestions for the defects, and modifies the digital design code of the corresponding module circuit based on the optimization suggestions. The integration module splices the digital design codes of each module circuit into the digital design master code of the large-scale chip, checks whether the interface definitions between the modules are consistent according to the technical specifications, checks whether the timing of the signals matches, and checks whether the data formats are compatible. If there are any problems, the corresponding positions in the digital design master code are modified. If there are no problems, the chip is assembled and manufactured according to the digital design master code.

[0010] Furthermore, the demand understanding module of the large-scale chip design device based on the AI ​​model selects the Chatgpt or Deepseek model as the AI ​​model to generate an initial design plan and technical specification of the chip according to relevant data. The technical specification includes the basic functions of the chip, the performance indicators of the chip, a list of key parameters, communication protocols and clock frequencies.

[0011] Furthermore, the evaluation module of the large-scale chip design device based on the AI ​​model establishes an evaluation system according to the design goals and industry standards of the chip. The performance index evaluation in the evaluation system includes computing speed, data processing capability and performance evaluation under different workloads. The area index evaluation includes the physical area of ​​the chip, the number of logic gates and the occupancy of wiring resources. The power consumption index evaluation includes static power consumption and dynamic power consumption evaluation, which respectively evaluates the energy consumption of the chip in standby state and working state.

[0012] Furthermore, the design module of the large-scale chip design device based on the AI ​​model defines the function of each module according to the module circuit: for the processing module, the instruction set, data processing accuracy, and cache capacity parameters of the processing module are clarified; for the IO module, the interface type, data transmission rate, and signal level standard supported by the IO module are determined. The design module generates a module specification for each module based on the module circuit: the module specification includes functional requirements, performance indicators, timing requirements, power consumption limits and area constraints. The design module uses the AI ​​model to generate digital design code for the corresponding module circuit according to the module specification, and reviews the generated digital design code. The review content includes the logical correctness of the code, syntax errors, and compliance with coding standards. The code review tool Synopsys's SpyGlass component is used to perform static analysis on the code to check whether there are potential logical errors and safety hazards.

[0013] Furthermore, the test case module of the large-scale chip design device based on the AI ​​model prioritizes the generated test cases according to the importance and risk level of the test cases, and gives higher priority to the test cases of modules with key functions in the chip, the test cases involving security mechanisms, and the test cases affecting the stability of the chip system. When verifying the test case, set different simulation accuracies and time steps, adjust the simulation parameters according to the complexity of the test case, record the output signal and internal state changes of the chip, and compare them with the expected results. If it is found that the output result does not meet the expectations, mark the test case as a failed case, and record the cause of the failure and related test data.

[0014] The benefits of the present invention are: 1. The present invention can learn a large number of excellent chip design cases through the AI ​​model to automatically generate chip design solutions, and the generated design solutions have higher performance and reliability.

[0015] 2. The present invention utilizes AI models to generate more optimized chip architecture and design codes, which can significantly improve chip design efficiency and achieve a high level of automated design, greatly shortening the chip design cycle and reducing labor and time costs.

[0016] 3. The present invention utilizes AI models to automatically generate test cases and an efficient verification environment, covering various possible working states of the chip and improving the accuracy and comprehensiveness of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0019] Embodiment 1: The present invention provides a large-scale chip design method based on an AI model, comprising: Step 1: Collect the chip's design requirements, function definition information, and constraint information, and organize them into relevant data. Use the AI ​​model to generate the chip's initial design plan and technical specifications based on the relevant data. You can choose Chatgpt or Deepseek model as the AI ​​model to generate the chip's initial design plan and technical specifications based on the relevant data. The technical specifications include the chip's basic functions, chip performance indicators, key parameter lists, communication protocols, and clock frequencies. The AI ​​model can learn a large amount of chip design data and chip architecture.

[0020] Step 2: Evaluate the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. Adjust the initial design plan according to the evaluation results to form a final design plan, and divide the module circuit of the chip according to the final design plan. The evaluation system can be established according to the design goals and industry standards of the chip. The performance index evaluation in the evaluation system includes the evaluation of computing speed, data processing capability and performance under different workloads. The area index evaluation includes the physical area of ​​the chip, the number of logic gates and the occupancy of wiring resources. The power consumption index evaluation includes static power consumption and dynamic power consumption evaluation, which evaluates the energy consumption of the chip in standby state and working state respectively.

[0021] If the initial design does not meet the requirements in some indicators during the evaluation, find out the root cause of the problem. For example, if the performance indicators of the chip do not meet expectations, it may be due to unreasonable architecture design of the processor core or insufficient data transmission bandwidth.

[0022] Adjust the initial design plan based on the problems found, such as using a more efficient algorithm, reducing the number of logic layers, or adjusting the module layout, shortening the signal transmission path, reducing latency, etc. After the adjustment, evaluate again and repeat the process until the initial design plan achieves the optimal balance in terms of performance, area, power consumption, etc., forming the final design plan.

[0023] According to the final design plan, the large-scale chip is divided into multiple module circuits. The principle of division is to group the functional requirements according to the logical relationship and implementation method based on the independence of functions and the interaction between modules. At the same time, the coupling between modules is minimized as much as possible, and the complexity of signal interaction between modules is reduced. For example, by reasonably designing the interface between modules and adopting standardized communication protocols, the signal dependency is reduced. After the division is completed, the input and output interfaces and functional requirements are defined for each module to provide clear guidance for subsequent design work.

[0024] Step 3: Define the function of each module according to the module circuit, generate the module specification for each module, and use the AI ​​model to generate the digital design code for the corresponding module circuit according to the module specification.

[0025] Specifically, it may include: According to the module circuit, define the function of each module: for the processing module, clarify the instruction set, data processing accuracy, and cache capacity parameters of the processing module; for the IO module, determine the interface type, data transmission rate, and signal level standard supported by the IO module.

[0026] Generate a module specification for each module based on the module circuit: the module specification includes functional requirements, performance indicators, timing requirements, power consumption limits and area constraints. For example, for a high-speed data transmission module, the specification will specify the clock frequency, data frame format, transmission delay requirements, etc. of its data transmission.

[0027] The AI ​​model is used to generate digital design codes for the corresponding module circuits based on the module specifications. The appropriate logic circuit structure and algorithm implementation method are selected according to the functional requirements and timing requirements of the module. For example, for a multiplier module, the model may choose to implement it using an array multiplier or Booth multiplier structure. The generated digital design code has good readability and maintainability, and complies with industry standard coding specifications. The code will contain detailed comments to explain the functions and design ideas of each module, which will facilitate subsequent code review and modification.

[0028] The generated digital design code is reviewed for logical correctness, syntax errors, and compliance with coding standards. The code review tool Synopsys's SpyGlass component is used to perform static analysis on the code to check for potential logical errors and safety hazards. The structure and performance bottlenecks of the code are analyzed, and the performance and efficiency of the code are improved by adjusting the algorithm structure and optimizing logical expressions. For example, if a module is found to have a slow calculation speed, the AI ​​model can recommend the use of pipeline technology or parallel computing for optimization.

[0029] Step 4: Use the AI ​​model to automatically generate test cases to simulate various working modes of the chip in actual applications to ensure that the chip can work properly in different situations. For example, for a chip with multimedia processing function, test its functional correctness under different resolutions and different formats of video and audio files. The AI ​​model will adopt multiple test case generation strategies to ensure the comprehensiveness and effectiveness of the test cases.

[0030] The AI ​​model is used to generate test cases using boundary value analysis strategy, test cases are generated using equivalence class partitioning strategy, and corresponding test cases are generated for each abnormal situation.

[0031] If the boundary value analysis strategy is adopted, for each input parameter, its minimum value, maximum value, value slightly less than the minimum value, and value slightly greater than the maximum value are selected as the input of the test case. For example, if the input data range of a module is 0-255, then the input of the test case will include -1, 0, 1, 254, 255, 256, etc.

[0032] If the equivalence class partitioning strategy is adopted, the input data is divided into several equivalence classes, and the data in each equivalence class has the same impact on the processing results of the module. One or more representative values ​​are selected from each equivalence class as the input of the test case. For example, for the format requirement of an input data, it can be divided into two equivalence classes: legal format and illegal format, and representative values ​​are selected for testing respectively.

[0033] Corresponding test cases are also generated for each abnormal situation, such as incorrect format of input data, data overflow, power failure and other abnormal situations.

[0034] The generated test cases can also be prioritized according to their importance and risk level, giving higher priority to test cases of modules with key functions in the chip, test cases involving security mechanisms, and test cases that affect the stability of the chip system. For example, a test case for a security encryption module will be executed first to ensure the security of the chip.

[0035] In step 4, the test cases are verified, and the verification process and the execution of the test cases are monitored. When verifying the test cases, different simulation accuracies and time steps are set, and the simulation parameters are adjusted according to the complexity of the test cases. The output signals and internal state changes of the chip are recorded and compared with the expected results. If the output results are found to be inconsistent with expectations, the test cases are marked as failed cases, and the reasons for the failure and related test data are recorded. At the same time, the verification process is monitored to grasp the verification progress and the execution of the test cases in real time. If it is found that a test case takes too long to execute, it may be due to a dead loop or other performance problems in the code, and timely investigation and processing should be carried out.

[0036] Step 5: Collect data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data, provides optimization suggestions for the defects, and modifies the digital design code of the corresponding module circuit based on the optimization suggestions. The optimization suggestions may include modifying a certain logical expression, adjusting the parameters of a certain module, optimizing the wiring scheme, etc. For example, if it is found that the power consumption of a certain module is too high, the AI ​​model may recommend a low-power circuit structure or optimize the power management strategy; if it is found that the timing of a certain signal does not meet the requirements, it may recommend adjusting the layout of the logic circuit or adding a buffer to improve the signal delay. The optimization suggestions or error information generated by the AI ​​model can be displayed in the form of a detailed report.

[0037] Step 6: Splice the digital design codes of each module circuit into the digital design code of the large-scale chip, and check whether the interface definitions between modules are consistent according to the technical specifications, such as whether the signal name, signal type, signal width, signal timing, etc. are consistent. Check whether the timing of the signal matches, analyze the transmission delay and timing relationship of the signal between modules, and ensure that the signal can be correctly transmitted and synchronized between different modules; Check whether the data format is compatible. If there is a problem, modify the corresponding position in the digital design code. After the modification is completed, perform compatibility check again until the interfaces and signals between all modules can work together normally.

[0038] If there are no problems, the chip will be assembled and manufactured according to the digital design master code.

[0039] Embodiment 2: The present invention also provides a large-scale chip design device based on an AI model, comprising a demand understanding module, an evaluation module, a design module, a test case module, a verification result analysis module and an integration module. The demand understanding module collects the chip's design requirement information, function definition information, and constraint information, and organizes them into relevant data. It uses the AI ​​model to generate the chip's initial design plan and technical specifications based on the relevant data. The evaluation module evaluates the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. The initial design plan is adjusted according to the evaluation results to form a final design plan. The module circuit of the chip is divided according to the final design plan. The design module defines the function of each module according to the module circuit and generates the module specification for each module. The AI ​​model is used to generate the digital design code for the corresponding module circuit according to the module specification. The test case module uses AI models to automatically generate test cases and simulate various working modes of chips in actual applications. It uses AI models to generate test cases using boundary value analysis strategy, equivalence class partitioning strategy, and corresponding test cases for each abnormal situation. Verify the test cases, monitor the verification process and the execution of the test cases, The verification result analysis module collects data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data, provides optimization suggestions for the defects, and modifies the digital design code of the corresponding module circuit based on the optimization suggestions. The integration module splices the digital design codes of each module circuit into the digital design master code of the large-scale chip, checks whether the interface definitions between the modules are consistent according to the technical specifications, checks whether the timing of the signals matches, and checks whether the data formats are compatible. If there are any problems, the corresponding positions in the digital design master code are modified. If there are no problems, the chip is assembled and manufactured according to the digital design master code.

[0040] As the information interaction and execution process between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention, the specific contents can be found in the description of the embodiment of the method of the present invention and will not be repeated here.

[0041] Likewise, the benefits of the device of the present invention are: 1. The present invention can learn a large number of excellent chip design cases through the AI ​​model to automatically generate chip design solutions, and the generated design solutions have higher performance and reliability.

[0042] 2. The present invention utilizes AI models to generate more optimized chip architecture and design codes, which can significantly improve chip design efficiency and achieve a high level of automated design, greatly shortening the chip design cycle and reducing labor and time costs.

[0043] 3. The present invention utilizes AI models to automatically generate test cases and an efficient verification environment, covering various possible working states of the chip and improving the accuracy and comprehensiveness of verification.

[0044] It should be noted that not all steps and modules in the above-mentioned processes and device structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or some components in multiple independent devices may be implemented together.

[0045] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A large-scale chip design method based on AI model, characterized by include: Step 1: Collect the chip’s design requirements, function definition information, and constraint information, and organize them into relevant data. Use the AI ​​model to generate the chip’s initial design plan and technical specifications based on the relevant data. Step 2: Evaluate the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. Adjust the initial design plan according to the evaluation results to form a final design plan. Divide the module circuit of the chip according to the final design plan. Step 3: Define the function of each module according to the module circuit, generate the module specification for each module, and use the AI ​​model to generate the digital design code for the corresponding module circuit according to the module specification. Step 4: Use the AI ​​model to automatically generate test cases and simulate various working modes of the chip in actual applications. The AI ​​model uses the boundary value analysis strategy to generate test cases, the equivalence class partitioning strategy to generate test cases, and the corresponding test cases for each abnormal situation. The test cases are verified, and the verification process and the execution of the test cases are monitored. Step 5: Collect data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data and provides optimization suggestions for the defects. The digital design code of the corresponding module circuit is modified according to the optimization suggestions. Step 6: Splice the digital design codes of each module circuit into the digital design master code of the large-scale chip. Check whether the interface definitions between the modules are consistent according to the technical specifications, check whether the timing of the signals matches, and check whether the data formats are compatible. If there are any problems, modify the corresponding positions in the digital design master code. If there are no problems, assemble and manufacture the chip according to the digital design master code.

2. According to claim 1, a large-scale chip design method based on an AI model is characterized by: In step 1, select Chatgpt or Deepseek model as the AI ​​model to generate the initial design plan and technical specifications of the chip based on relevant data. The technical specifications include the basic functions of the chip, the performance indicators of the chip, a list of key parameters, communication protocols, and clock frequencies.

3. According to claim 1, a large-scale chip design method based on an AI model is characterized by: In step 2, an evaluation system is established based on the chip's design goals and industry standards. The performance indicators in the evaluation system include computing speed, data processing capability, and performance under different workloads. The area indicators include the physical area of ​​the chip, the number of logic gates, and the occupancy of wiring resources. The power consumption indicators include static power consumption and dynamic power consumption, which evaluate the energy consumption of the chip in standby and working states respectively.

4. The large-scale chip design method based on AI model according to claim 1 is characterized by: Step 3 specifically includes: According to the module circuit, define the function of each module: for the processing module, clarify the instruction set, data processing accuracy, and cache capacity parameters of the processing module; for the IO module, determine the interface type, data transmission rate, and signal level standard supported by the IO module. Generate the module specification of each module according to the module circuit: the module specification includes functional requirements, performance indicators, timing requirements, power consumption limits and area constraints. The AI ​​model is used to generate digital design code for the corresponding module circuit according to the module specification, and the generated digital design code is reviewed. The review content includes the logical correctness of the code, syntax errors, and compliance with coding standards. The code review tool Synopsys's SpyGlass component is used to perform static analysis on the code to check whether there are potential logical errors and safety hazards.

5. The large-scale chip design method based on AI model according to claim 1 is characterized by: In step 4, the generated test cases are prioritized according to their importance and risk level. Test cases of modules with key functions in the chip, test cases involving security mechanisms, and test cases that affect the stability of the chip system are given higher priority. When verifying the test case, set different simulation accuracies and time steps, adjust the simulation parameters according to the complexity of the test case, record the output signal and internal state changes of the chip, and compare them with the expected results. If it is found that the output result does not meet the expectations, mark the test case as a failed case, and record the cause of the failure and related test data.

6. A large-scale chip design device based on an AI model, characterized by It includes requirement understanding module, evaluation module, design module, test case module, verification result analysis module and integration module. The demand understanding module collects the chip's design requirement information, function definition information, and constraint information, and organizes them into relevant data. It uses the AI ​​model to generate the chip's initial design plan and technical specifications based on the relevant data. The evaluation module evaluates the initial design plan according to the evaluation system, which includes performance index evaluation, area index evaluation and power consumption index evaluation. The initial design plan is adjusted according to the evaluation results to form a final design plan. The module circuit of the chip is divided according to the final design plan. The design module defines the function of each module according to the module circuit and generates the module specification for each module. The AI ​​model is used to generate the digital design code for the corresponding module circuit according to the module specification. The test case module uses AI models to automatically generate test cases and simulate various working modes of chips in actual applications. It uses AI models to generate test cases using boundary value analysis strategy, equivalence class partitioning strategy, and corresponding test cases for each abnormal situation. Verify the test cases, monitor the verification process and the execution of the test cases, The verification result analysis module collects data on the verification process and test case execution. The AI ​​model identifies digital design defects based on the collected data, provides optimization suggestions for the defects, and modifies the digital design code of the corresponding module circuit based on the optimization suggestions. The integration module splices the digital design codes of each module circuit into the digital design master code of the large-scale chip, checks whether the interface definitions between the modules are consistent according to the technical specifications, checks whether the timing of the signals matches, and checks whether the data formats are compatible. If there are any problems, the corresponding positions in the digital design master code are modified. If there are no problems, the chip is assembled and manufactured according to the digital design master code.

7. A large-scale chip design device based on an AI model according to claim 6, characterized in that the requirement The understanding module selects the Chatgpt or Deepseek model as the AI ​​model to generate the initial design plan and technical specifications of the chip based on the relevant data. The technical specifications include the basic functions of the chip, the performance indicators of the chip, a list of key parameters, communication protocols and clock frequencies.

8. The large-scale chip design device based on AI model according to claim 6, characterized in that The evaluation module establishes an evaluation system based on the chip's design goals and industry standards. The performance indicators in the evaluation system include computing speed, data processing capability, and performance under different workloads. The area indicator evaluation includes the chip's physical area, number of logic gates, and wiring resource occupancy. The power consumption indicator evaluation includes static power consumption and dynamic power consumption, which respectively evaluate the chip's energy consumption in standby and working states.

9. The large-scale chip design device based on AI model according to claim 6, characterized in that Design modules define the functions of each module according to the module circuit: for the processing module, clarify the instruction set, data processing accuracy, and cache capacity parameters of the processing module; for the IO module, determine the interface type, data transmission rate, and signal level standard supported by the IO module. The design module generates a module specification for each module based on the module circuit: the module specification includes functional requirements, performance indicators, timing requirements, power consumption limits and area constraints. The design module uses the AI ​​model to generate digital design code for the corresponding module circuit according to the module specification, and reviews the generated digital design code. The review content includes the logical correctness of the code, syntax errors, and compliance with coding standards. The code review tool Synopsys's SpyGlass component is used to perform static analysis on the code to check whether there are potential logical errors and safety hazards.

10. The large-scale chip design device based on AI model according to claim 6, characterized in that The test case module prioritizes the generated test cases according to their importance and risk level, and gives higher priority to test cases of modules with key functions in the chip, test cases involving security mechanisms, and test cases that affect the stability of the chip system. When verifying the test case, set different simulation accuracies and time steps, adjust the simulation parameters according to the complexity of the test case, record the output signal and internal state changes of the chip, and compare them with the expected results. If it is found that the output result does not meet the expectations, mark the test case as a failed case, and record the cause of the failure and related test data.

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